qcom,gcc-msm8994.h 5.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179
  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2016, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef _DT_BINDINGS_CLK_MSM_GCC_8994_H
  6. #define _DT_BINDINGS_CLK_MSM_GCC_8994_H
  7. #define GPLL0_EARLY 0
  8. #define GPLL0 1
  9. #define GPLL4_EARLY 2
  10. #define GPLL4 3
  11. #define UFS_AXI_CLK_SRC 4
  12. #define USB30_MASTER_CLK_SRC 5
  13. #define BLSP1_QUP1_I2C_APPS_CLK_SRC 6
  14. #define BLSP1_QUP1_SPI_APPS_CLK_SRC 7
  15. #define BLSP1_QUP2_I2C_APPS_CLK_SRC 8
  16. #define BLSP1_QUP2_SPI_APPS_CLK_SRC 9
  17. #define BLSP1_QUP3_I2C_APPS_CLK_SRC 10
  18. #define BLSP1_QUP3_SPI_APPS_CLK_SRC 11
  19. #define BLSP1_QUP4_I2C_APPS_CLK_SRC 12
  20. #define BLSP1_QUP4_SPI_APPS_CLK_SRC 13
  21. #define BLSP1_QUP5_I2C_APPS_CLK_SRC 14
  22. #define BLSP1_QUP5_SPI_APPS_CLK_SRC 15
  23. #define BLSP1_QUP6_I2C_APPS_CLK_SRC 16
  24. #define BLSP1_QUP6_SPI_APPS_CLK_SRC 17
  25. #define BLSP1_UART1_APPS_CLK_SRC 18
  26. #define BLSP1_UART2_APPS_CLK_SRC 19
  27. #define BLSP1_UART3_APPS_CLK_SRC 20
  28. #define BLSP1_UART4_APPS_CLK_SRC 21
  29. #define BLSP1_UART5_APPS_CLK_SRC 22
  30. #define BLSP1_UART6_APPS_CLK_SRC 23
  31. #define BLSP2_QUP1_I2C_APPS_CLK_SRC 24
  32. #define BLSP2_QUP1_SPI_APPS_CLK_SRC 25
  33. #define BLSP2_QUP2_I2C_APPS_CLK_SRC 26
  34. #define BLSP2_QUP2_SPI_APPS_CLK_SRC 27
  35. #define BLSP2_QUP3_I2C_APPS_CLK_SRC 28
  36. #define BLSP2_QUP3_SPI_APPS_CLK_SRC 29
  37. #define BLSP2_QUP4_I2C_APPS_CLK_SRC 30
  38. #define BLSP2_QUP4_SPI_APPS_CLK_SRC 31
  39. #define BLSP2_QUP5_I2C_APPS_CLK_SRC 32
  40. #define BLSP2_QUP5_SPI_APPS_CLK_SRC 33
  41. #define BLSP2_QUP6_I2C_APPS_CLK_SRC 34
  42. #define BLSP2_QUP6_SPI_APPS_CLK_SRC 35
  43. #define BLSP2_UART1_APPS_CLK_SRC 36
  44. #define BLSP2_UART2_APPS_CLK_SRC 37
  45. #define BLSP2_UART3_APPS_CLK_SRC 38
  46. #define BLSP2_UART4_APPS_CLK_SRC 39
  47. #define BLSP2_UART5_APPS_CLK_SRC 40
  48. #define BLSP2_UART6_APPS_CLK_SRC 41
  49. #define GP1_CLK_SRC 42
  50. #define GP2_CLK_SRC 43
  51. #define GP3_CLK_SRC 44
  52. #define PCIE_0_AUX_CLK_SRC 45
  53. #define PCIE_0_PIPE_CLK_SRC 46
  54. #define PCIE_1_AUX_CLK_SRC 47
  55. #define PCIE_1_PIPE_CLK_SRC 48
  56. #define PDM2_CLK_SRC 49
  57. #define SDCC1_APPS_CLK_SRC 50
  58. #define SDCC2_APPS_CLK_SRC 51
  59. #define SDCC3_APPS_CLK_SRC 52
  60. #define SDCC4_APPS_CLK_SRC 53
  61. #define TSIF_REF_CLK_SRC 54
  62. #define USB30_MOCK_UTMI_CLK_SRC 55
  63. #define USB3_PHY_AUX_CLK_SRC 56
  64. #define USB_HS_SYSTEM_CLK_SRC 57
  65. #define GCC_BLSP1_AHB_CLK 58
  66. #define GCC_BLSP1_QUP1_I2C_APPS_CLK 59
  67. #define GCC_BLSP1_QUP1_SPI_APPS_CLK 60
  68. #define GCC_BLSP1_QUP2_I2C_APPS_CLK 61
  69. #define GCC_BLSP1_QUP2_SPI_APPS_CLK 62
  70. #define GCC_BLSP1_QUP3_I2C_APPS_CLK 63
  71. #define GCC_BLSP1_QUP3_SPI_APPS_CLK 64
  72. #define GCC_BLSP1_QUP4_I2C_APPS_CLK 65
  73. #define GCC_BLSP1_QUP4_SPI_APPS_CLK 66
  74. #define GCC_BLSP1_QUP5_I2C_APPS_CLK 67
  75. #define GCC_BLSP1_QUP5_SPI_APPS_CLK 68
  76. #define GCC_BLSP1_QUP6_I2C_APPS_CLK 69
  77. #define GCC_BLSP1_QUP6_SPI_APPS_CLK 70
  78. #define GCC_BLSP1_UART1_APPS_CLK 71
  79. #define GCC_BLSP1_UART2_APPS_CLK 72
  80. #define GCC_BLSP1_UART3_APPS_CLK 73
  81. #define GCC_BLSP1_UART4_APPS_CLK 74
  82. #define GCC_BLSP1_UART5_APPS_CLK 75
  83. #define GCC_BLSP1_UART6_APPS_CLK 76
  84. #define GCC_BLSP2_AHB_CLK 77
  85. #define GCC_BLSP2_QUP1_I2C_APPS_CLK 78
  86. #define GCC_BLSP2_QUP1_SPI_APPS_CLK 79
  87. #define GCC_BLSP2_QUP2_I2C_APPS_CLK 80
  88. #define GCC_BLSP2_QUP2_SPI_APPS_CLK 81
  89. #define GCC_BLSP2_QUP3_I2C_APPS_CLK 82
  90. #define GCC_BLSP2_QUP3_SPI_APPS_CLK 83
  91. #define GCC_BLSP2_QUP4_I2C_APPS_CLK 84
  92. #define GCC_BLSP2_QUP4_SPI_APPS_CLK 85
  93. #define GCC_BLSP2_QUP5_I2C_APPS_CLK 86
  94. #define GCC_BLSP2_QUP5_SPI_APPS_CLK 87
  95. #define GCC_BLSP2_QUP6_I2C_APPS_CLK 88
  96. #define GCC_BLSP2_QUP6_SPI_APPS_CLK 89
  97. #define GCC_BLSP2_UART1_APPS_CLK 90
  98. #define GCC_BLSP2_UART2_APPS_CLK 91
  99. #define GCC_BLSP2_UART3_APPS_CLK 92
  100. #define GCC_BLSP2_UART4_APPS_CLK 93
  101. #define GCC_BLSP2_UART5_APPS_CLK 94
  102. #define GCC_BLSP2_UART6_APPS_CLK 95
  103. #define GCC_GP1_CLK 96
  104. #define GCC_GP2_CLK 97
  105. #define GCC_GP3_CLK 98
  106. #define GCC_PCIE_0_AUX_CLK 99
  107. #define GCC_PCIE_0_PIPE_CLK 100
  108. #define GCC_PCIE_1_AUX_CLK 101
  109. #define GCC_PCIE_1_PIPE_CLK 102
  110. #define GCC_PDM2_CLK 103
  111. #define GCC_SDCC1_APPS_CLK 104
  112. #define GCC_SDCC2_APPS_CLK 105
  113. #define GCC_SDCC3_APPS_CLK 106
  114. #define GCC_SDCC4_APPS_CLK 107
  115. #define GCC_SYS_NOC_UFS_AXI_CLK 108
  116. #define GCC_SYS_NOC_USB3_AXI_CLK 109
  117. #define GCC_TSIF_REF_CLK 110
  118. #define GCC_UFS_AXI_CLK 111
  119. #define GCC_UFS_RX_CFG_CLK 112
  120. #define GCC_UFS_TX_CFG_CLK 113
  121. #define GCC_USB30_MASTER_CLK 114
  122. #define GCC_USB30_MOCK_UTMI_CLK 115
  123. #define GCC_USB3_PHY_AUX_CLK 116
  124. #define GCC_USB_HS_SYSTEM_CLK 117
  125. #define GCC_SDCC1_AHB_CLK 118
  126. #define GCC_LPASS_Q6_AXI_CLK 119
  127. #define GCC_MSS_Q6_BIMC_AXI_CLK 120
  128. #define GCC_PCIE_0_CFG_AHB_CLK 121
  129. #define GCC_PCIE_0_MSTR_AXI_CLK 122
  130. #define GCC_PCIE_0_SLV_AXI_CLK 123
  131. #define GCC_PCIE_1_CFG_AHB_CLK 124
  132. #define GCC_PCIE_1_MSTR_AXI_CLK 125
  133. #define GCC_PCIE_1_SLV_AXI_CLK 126
  134. #define GCC_PDM_AHB_CLK 127
  135. #define GCC_SDCC2_AHB_CLK 128
  136. #define GCC_SDCC3_AHB_CLK 129
  137. #define GCC_SDCC4_AHB_CLK 130
  138. #define GCC_TSIF_AHB_CLK 131
  139. #define GCC_UFS_AHB_CLK 132
  140. #define GCC_UFS_RX_SYMBOL_0_CLK 133
  141. #define GCC_UFS_RX_SYMBOL_1_CLK 134
  142. #define GCC_UFS_TX_SYMBOL_0_CLK 135
  143. #define GCC_UFS_TX_SYMBOL_1_CLK 136
  144. #define GCC_USB2_HS_PHY_SLEEP_CLK 137
  145. #define GCC_USB30_SLEEP_CLK 138
  146. #define GCC_USB_HS_AHB_CLK 139
  147. #define GCC_USB_PHY_CFG_AHB2PHY_CLK 140
  148. #define CONFIG_NOC_CLK_SRC 141
  149. #define PERIPH_NOC_CLK_SRC 142
  150. #define SYSTEM_NOC_CLK_SRC 143
  151. #define GPLL0_OUT_MMSSCC 144
  152. #define GPLL0_OUT_MSSCC 145
  153. #define PCIE_0_PHY_LDO 146
  154. #define PCIE_1_PHY_LDO 147
  155. #define UFS_PHY_LDO 148
  156. #define USB_SS_PHY_LDO 149
  157. #define GCC_BOOT_ROM_AHB_CLK 150
  158. #define GCC_PRNG_AHB_CLK 151
  159. #define GCC_USB3_PHY_PIPE_CLK 152
  160. /* GDSCs */
  161. #define PCIE_GDSC 0
  162. #define PCIE_0_GDSC 1
  163. #define PCIE_1_GDSC 2
  164. #define USB30_GDSC 3
  165. #define UFS_GDSC 4
  166. /* Resets */
  167. #define USB3_PHY_RESET 0
  168. #define USB3PHY_PHY_RESET 1
  169. #define PCIE_PHY_0_RESET 2
  170. #define PCIE_PHY_1_RESET 3
  171. #define QUSB2_PHY_RESET 4
  172. #define MSS_RESET 5
  173. #endif