qcom,gcc-msm8976.h 7.7 KB

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  1. /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
  2. /*
  3. * Copyright (C) 2016, The Linux Foundation. All rights reserved.
  4. * Copyright (C) 2016-2021, AngeloGioacchino Del Regno
  5. * <[email protected]>
  6. */
  7. #ifndef _DT_BINDINGS_CLK_MSM_GCC_8976_H
  8. #define _DT_BINDINGS_CLK_MSM_GCC_8976_H
  9. #define GPLL0 0
  10. #define GPLL2 1
  11. #define GPLL3 2
  12. #define GPLL4 3
  13. #define GPLL6 4
  14. #define GPLL0_CLK_SRC 5
  15. #define GPLL2_CLK_SRC 6
  16. #define GPLL3_CLK_SRC 7
  17. #define GPLL4_CLK_SRC 8
  18. #define GPLL6_CLK_SRC 9
  19. #define GCC_BLSP1_QUP1_SPI_APPS_CLK 10
  20. #define GCC_BLSP1_QUP1_I2C_APPS_CLK 11
  21. #define GCC_BLSP1_QUP2_I2C_APPS_CLK 12
  22. #define GCC_BLSP1_QUP2_SPI_APPS_CLK 13
  23. #define GCC_BLSP1_QUP3_I2C_APPS_CLK 14
  24. #define GCC_BLSP1_QUP3_SPI_APPS_CLK 15
  25. #define GCC_BLSP1_QUP4_I2C_APPS_CLK 16
  26. #define GCC_BLSP1_QUP4_SPI_APPS_CLK 17
  27. #define GCC_BLSP1_UART1_APPS_CLK 18
  28. #define GCC_BLSP1_UART2_APPS_CLK 19
  29. #define GCC_BLSP2_QUP1_I2C_APPS_CLK 20
  30. #define GCC_BLSP2_QUP1_SPI_APPS_CLK 21
  31. #define GCC_BLSP2_QUP2_I2C_APPS_CLK 22
  32. #define GCC_BLSP2_QUP2_SPI_APPS_CLK 23
  33. #define GCC_BLSP2_QUP3_I2C_APPS_CLK 24
  34. #define GCC_BLSP2_QUP3_SPI_APPS_CLK 25
  35. #define GCC_BLSP2_QUP4_I2C_APPS_CLK 26
  36. #define GCC_BLSP2_QUP4_SPI_APPS_CLK 27
  37. #define GCC_BLSP2_UART1_APPS_CLK 28
  38. #define GCC_BLSP2_UART2_APPS_CLK 29
  39. #define GCC_CAMSS_CCI_AHB_CLK 30
  40. #define GCC_CAMSS_CCI_CLK 31
  41. #define GCC_CAMSS_CPP_AHB_CLK 32
  42. #define GCC_CAMSS_CPP_AXI_CLK 33
  43. #define GCC_CAMSS_CPP_CLK 34
  44. #define GCC_CAMSS_CSI0_AHB_CLK 35
  45. #define GCC_CAMSS_CSI0_CLK 36
  46. #define GCC_CAMSS_CSI0PHY_CLK 37
  47. #define GCC_CAMSS_CSI0PIX_CLK 38
  48. #define GCC_CAMSS_CSI0RDI_CLK 39
  49. #define GCC_CAMSS_CSI1_AHB_CLK 40
  50. #define GCC_CAMSS_CSI1_CLK 41
  51. #define GCC_CAMSS_CSI1PHY_CLK 42
  52. #define GCC_CAMSS_CSI1PIX_CLK 43
  53. #define GCC_CAMSS_CSI1RDI_CLK 44
  54. #define GCC_CAMSS_CSI2_AHB_CLK 45
  55. #define GCC_CAMSS_CSI2_CLK 46
  56. #define GCC_CAMSS_CSI2PHY_CLK 47
  57. #define GCC_CAMSS_CSI2PIX_CLK 48
  58. #define GCC_CAMSS_CSI2RDI_CLK 49
  59. #define GCC_CAMSS_CSI_VFE0_CLK 50
  60. #define GCC_CAMSS_CSI_VFE1_CLK 51
  61. #define GCC_CAMSS_GP0_CLK 52
  62. #define GCC_CAMSS_GP1_CLK 53
  63. #define GCC_CAMSS_ISPIF_AHB_CLK 54
  64. #define GCC_CAMSS_JPEG0_CLK 55
  65. #define GCC_CAMSS_JPEG_AHB_CLK 56
  66. #define GCC_CAMSS_JPEG_AXI_CLK 57
  67. #define GCC_CAMSS_MCLK0_CLK 58
  68. #define GCC_CAMSS_MCLK1_CLK 59
  69. #define GCC_CAMSS_MCLK2_CLK 60
  70. #define GCC_CAMSS_MICRO_AHB_CLK 61
  71. #define GCC_CAMSS_CSI0PHYTIMER_CLK 62
  72. #define GCC_CAMSS_CSI1PHYTIMER_CLK 63
  73. #define GCC_CAMSS_AHB_CLK 64
  74. #define GCC_CAMSS_TOP_AHB_CLK 65
  75. #define GCC_CAMSS_VFE0_CLK 66
  76. #define GCC_CAMSS_VFE_AHB_CLK 67
  77. #define GCC_CAMSS_VFE_AXI_CLK 68
  78. #define GCC_CAMSS_VFE1_AHB_CLK 69
  79. #define GCC_CAMSS_VFE1_AXI_CLK 70
  80. #define GCC_CAMSS_VFE1_CLK 71
  81. #define GCC_DCC_CLK 72
  82. #define GCC_GP1_CLK 73
  83. #define GCC_GP2_CLK 74
  84. #define GCC_GP3_CLK 75
  85. #define GCC_MDSS_AHB_CLK 76
  86. #define GCC_MDSS_AXI_CLK 77
  87. #define GCC_MDSS_ESC0_CLK 78
  88. #define GCC_MDSS_ESC1_CLK 79
  89. #define GCC_MDSS_MDP_CLK 80
  90. #define GCC_MDSS_VSYNC_CLK 81
  91. #define GCC_MSS_CFG_AHB_CLK 82
  92. #define GCC_MSS_Q6_BIMC_AXI_CLK 83
  93. #define GCC_PDM2_CLK 84
  94. #define GCC_PRNG_AHB_CLK 85
  95. #define GCC_PDM_AHB_CLK 86
  96. #define GCC_RBCPR_GFX_AHB_CLK 87
  97. #define GCC_RBCPR_GFX_CLK 88
  98. #define GCC_SDCC1_AHB_CLK 89
  99. #define GCC_SDCC1_APPS_CLK 90
  100. #define GCC_SDCC1_ICE_CORE_CLK 91
  101. #define GCC_SDCC2_AHB_CLK 92
  102. #define GCC_SDCC2_APPS_CLK 93
  103. #define GCC_SDCC3_AHB_CLK 94
  104. #define GCC_SDCC3_APPS_CLK 95
  105. #define GCC_USB2A_PHY_SLEEP_CLK 96
  106. #define GCC_USB_HS_PHY_CFG_AHB_CLK 97
  107. #define GCC_USB_FS_AHB_CLK 98
  108. #define GCC_USB_FS_IC_CLK 99
  109. #define GCC_USB_FS_SYSTEM_CLK 100
  110. #define GCC_USB_HS_AHB_CLK 101
  111. #define GCC_USB_HS_SYSTEM_CLK 102
  112. #define GCC_VENUS0_AHB_CLK 103
  113. #define GCC_VENUS0_AXI_CLK 104
  114. #define GCC_VENUS0_CORE0_VCODEC0_CLK 105
  115. #define GCC_VENUS0_CORE1_VCODEC0_CLK 106
  116. #define GCC_VENUS0_VCODEC0_CLK 107
  117. #define GCC_APSS_AHB_CLK 108
  118. #define GCC_APSS_AXI_CLK 109
  119. #define GCC_BLSP1_AHB_CLK 110
  120. #define GCC_BLSP2_AHB_CLK 111
  121. #define GCC_BOOT_ROM_AHB_CLK 112
  122. #define GCC_CRYPTO_AHB_CLK 113
  123. #define GCC_CRYPTO_AXI_CLK 114
  124. #define GCC_CRYPTO_CLK 115
  125. #define GCC_CPP_TBU_CLK 116
  126. #define GCC_APSS_TCU_CLK 117
  127. #define GCC_JPEG_TBU_CLK 118
  128. #define GCC_MDP_RT_TBU_CLK 119
  129. #define GCC_MDP_TBU_CLK 120
  130. #define GCC_SMMU_CFG_CLK 121
  131. #define GCC_VENUS_1_TBU_CLK 122
  132. #define GCC_VENUS_TBU_CLK 123
  133. #define GCC_VFE1_TBU_CLK 124
  134. #define GCC_VFE_TBU_CLK 125
  135. #define GCC_APS_0_CLK 126
  136. #define GCC_APS_1_CLK 127
  137. #define APS_0_CLK_SRC 128
  138. #define APS_1_CLK_SRC 129
  139. #define APSS_AHB_CLK_SRC 130
  140. #define BLSP1_QUP1_I2C_APPS_CLK_SRC 131
  141. #define BLSP1_QUP1_SPI_APPS_CLK_SRC 132
  142. #define BLSP1_QUP2_I2C_APPS_CLK_SRC 133
  143. #define BLSP1_QUP2_SPI_APPS_CLK_SRC 134
  144. #define BLSP1_QUP3_I2C_APPS_CLK_SRC 135
  145. #define BLSP1_QUP3_SPI_APPS_CLK_SRC 136
  146. #define BLSP1_QUP4_I2C_APPS_CLK_SRC 137
  147. #define BLSP1_QUP4_SPI_APPS_CLK_SRC 138
  148. #define BLSP1_UART1_APPS_CLK_SRC 139
  149. #define BLSP1_UART2_APPS_CLK_SRC 140
  150. #define BLSP2_QUP1_I2C_APPS_CLK_SRC 141
  151. #define BLSP2_QUP1_SPI_APPS_CLK_SRC 142
  152. #define BLSP2_QUP2_I2C_APPS_CLK_SRC 143
  153. #define BLSP2_QUP2_SPI_APPS_CLK_SRC 144
  154. #define BLSP2_QUP3_I2C_APPS_CLK_SRC 145
  155. #define BLSP2_QUP3_SPI_APPS_CLK_SRC 146
  156. #define BLSP2_QUP4_I2C_APPS_CLK_SRC 147
  157. #define BLSP2_QUP4_SPI_APPS_CLK_SRC 148
  158. #define BLSP2_UART1_APPS_CLK_SRC 149
  159. #define BLSP2_UART2_APPS_CLK_SRC 150
  160. #define CCI_CLK_SRC 151
  161. #define CPP_CLK_SRC 152
  162. #define CSI0_CLK_SRC 153
  163. #define CSI1_CLK_SRC 154
  164. #define CSI2_CLK_SRC 155
  165. #define CAMSS_GP0_CLK_SRC 156
  166. #define CAMSS_GP1_CLK_SRC 157
  167. #define JPEG0_CLK_SRC 158
  168. #define MCLK0_CLK_SRC 159
  169. #define MCLK1_CLK_SRC 160
  170. #define MCLK2_CLK_SRC 161
  171. #define CSI0PHYTIMER_CLK_SRC 162
  172. #define CSI1PHYTIMER_CLK_SRC 163
  173. #define CAMSS_TOP_AHB_CLK_SRC 164
  174. #define VFE0_CLK_SRC 165
  175. #define VFE1_CLK_SRC 166
  176. #define CRYPTO_CLK_SRC 167
  177. #define GP1_CLK_SRC 168
  178. #define GP2_CLK_SRC 169
  179. #define GP3_CLK_SRC 170
  180. #define ESC0_CLK_SRC 171
  181. #define ESC1_CLK_SRC 172
  182. #define MDP_CLK_SRC 173
  183. #define VSYNC_CLK_SRC 174
  184. #define PDM2_CLK_SRC 175
  185. #define RBCPR_GFX_CLK_SRC 176
  186. #define SDCC1_APPS_CLK_SRC 177
  187. #define SDCC1_ICE_CORE_CLK_SRC 178
  188. #define SDCC2_APPS_CLK_SRC 179
  189. #define SDCC3_APPS_CLK_SRC 180
  190. #define USB_FS_IC_CLK_SRC 181
  191. #define USB_FS_SYSTEM_CLK_SRC 182
  192. #define USB_HS_SYSTEM_CLK_SRC 183
  193. #define VCODEC0_CLK_SRC 184
  194. #define GCC_MDSS_BYTE0_CLK_SRC 185
  195. #define GCC_MDSS_BYTE1_CLK_SRC 186
  196. #define GCC_MDSS_BYTE0_CLK 187
  197. #define GCC_MDSS_BYTE1_CLK 188
  198. #define GCC_MDSS_PCLK0_CLK_SRC 189
  199. #define GCC_MDSS_PCLK1_CLK_SRC 190
  200. #define GCC_MDSS_PCLK0_CLK 191
  201. #define GCC_MDSS_PCLK1_CLK 192
  202. #define GCC_GFX3D_CLK_SRC 193
  203. #define GCC_GFX3D_OXILI_CLK 194
  204. #define GCC_GFX3D_BIMC_CLK 195
  205. #define GCC_GFX3D_OXILI_AHB_CLK 196
  206. #define GCC_GFX3D_OXILI_AON_CLK 197
  207. #define GCC_GFX3D_OXILI_GMEM_CLK 198
  208. #define GCC_GFX3D_OXILI_TIMER_CLK 199
  209. #define GCC_GFX3D_TBU0_CLK 200
  210. #define GCC_GFX3D_TBU1_CLK 201
  211. #define GCC_GFX3D_TCU_CLK 202
  212. #define GCC_GFX3D_GTCU_AHB_CLK 203
  213. /* GCC block resets */
  214. #define RST_CAMSS_MICRO_BCR 0
  215. #define RST_USB_HS_BCR 1
  216. #define RST_QUSB2_PHY_BCR 2
  217. #define RST_USB2_HS_PHY_ONLY_BCR 3
  218. #define RST_USB_HS_PHY_CFG_AHB_BCR 4
  219. #define RST_USB_FS_BCR 5
  220. #define RST_CAMSS_CSI1PIX_BCR 6
  221. #define RST_CAMSS_CSI_VFE1_BCR 7
  222. #define RST_CAMSS_VFE1_BCR 8
  223. #define RST_CAMSS_CPP_BCR 9
  224. #define RST_MSS_BCR 10
  225. /* GDSCs */
  226. #define VENUS_GDSC 0
  227. #define VENUS_CORE0_GDSC 1
  228. #define VENUS_CORE1_GDSC 2
  229. #define MDSS_GDSC 3
  230. #define JPEG_GDSC 4
  231. #define VFE0_GDSC 5
  232. #define VFE1_GDSC 6
  233. #define CPP_GDSC 7
  234. #define OXILI_GX_GDSC 8
  235. #define OXILI_CX_GDSC 9
  236. #endif /* _DT_BINDINGS_CLK_MSM_GCC_8976_H */