qcom,dispcc-sc7280.h 1.9 KB

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  1. /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
  2. /*
  3. * Copyright (c) 2021, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7280_H
  6. #define _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7280_H
  7. /* DISP_CC clocks */
  8. #define DISP_CC_PLL0 0
  9. #define DISP_CC_MDSS_AHB_CLK 1
  10. #define DISP_CC_MDSS_AHB_CLK_SRC 2
  11. #define DISP_CC_MDSS_BYTE0_CLK 3
  12. #define DISP_CC_MDSS_BYTE0_CLK_SRC 4
  13. #define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5
  14. #define DISP_CC_MDSS_BYTE0_INTF_CLK 6
  15. #define DISP_CC_MDSS_DP_AUX_CLK 7
  16. #define DISP_CC_MDSS_DP_AUX_CLK_SRC 8
  17. #define DISP_CC_MDSS_DP_CRYPTO_CLK 9
  18. #define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 10
  19. #define DISP_CC_MDSS_DP_LINK_CLK 11
  20. #define DISP_CC_MDSS_DP_LINK_CLK_SRC 12
  21. #define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 13
  22. #define DISP_CC_MDSS_DP_LINK_INTF_CLK 14
  23. #define DISP_CC_MDSS_DP_PIXEL_CLK 15
  24. #define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 16
  25. #define DISP_CC_MDSS_EDP_AUX_CLK 17
  26. #define DISP_CC_MDSS_EDP_AUX_CLK_SRC 18
  27. #define DISP_CC_MDSS_EDP_LINK_CLK 19
  28. #define DISP_CC_MDSS_EDP_LINK_CLK_SRC 20
  29. #define DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC 21
  30. #define DISP_CC_MDSS_EDP_LINK_INTF_CLK 22
  31. #define DISP_CC_MDSS_EDP_PIXEL_CLK 23
  32. #define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC 24
  33. #define DISP_CC_MDSS_ESC0_CLK 25
  34. #define DISP_CC_MDSS_ESC0_CLK_SRC 26
  35. #define DISP_CC_MDSS_MDP_CLK 27
  36. #define DISP_CC_MDSS_MDP_CLK_SRC 28
  37. #define DISP_CC_MDSS_MDP_LUT_CLK 29
  38. #define DISP_CC_MDSS_NON_GDSC_AHB_CLK 30
  39. #define DISP_CC_MDSS_PCLK0_CLK 31
  40. #define DISP_CC_MDSS_PCLK0_CLK_SRC 32
  41. #define DISP_CC_MDSS_ROT_CLK 33
  42. #define DISP_CC_MDSS_ROT_CLK_SRC 34
  43. #define DISP_CC_MDSS_RSCC_AHB_CLK 35
  44. #define DISP_CC_MDSS_RSCC_VSYNC_CLK 36
  45. #define DISP_CC_MDSS_VSYNC_CLK 37
  46. #define DISP_CC_MDSS_VSYNC_CLK_SRC 38
  47. #define DISP_CC_SLEEP_CLK 39
  48. #define DISP_CC_XO_CLK 40
  49. /* DISP_CC power domains */
  50. #define DISP_CC_MDSS_CORE_GDSC 0
  51. #endif