w1_io.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (c) 2004 Evgeniy Polyakov <[email protected]>
  4. */
  5. #include <asm/io.h>
  6. #include <linux/delay.h>
  7. #include <linux/moduleparam.h>
  8. #include <linux/module.h>
  9. #include "w1_internal.h"
  10. static int w1_delay_parm = 1;
  11. module_param_named(delay_coef, w1_delay_parm, int, 0);
  12. static int w1_disable_irqs = 0;
  13. module_param_named(disable_irqs, w1_disable_irqs, int, 0);
  14. static u8 w1_crc8_table[] = {
  15. 0, 94, 188, 226, 97, 63, 221, 131, 194, 156, 126, 32, 163, 253, 31, 65,
  16. 157, 195, 33, 127, 252, 162, 64, 30, 95, 1, 227, 189, 62, 96, 130, 220,
  17. 35, 125, 159, 193, 66, 28, 254, 160, 225, 191, 93, 3, 128, 222, 60, 98,
  18. 190, 224, 2, 92, 223, 129, 99, 61, 124, 34, 192, 158, 29, 67, 161, 255,
  19. 70, 24, 250, 164, 39, 121, 155, 197, 132, 218, 56, 102, 229, 187, 89, 7,
  20. 219, 133, 103, 57, 186, 228, 6, 88, 25, 71, 165, 251, 120, 38, 196, 154,
  21. 101, 59, 217, 135, 4, 90, 184, 230, 167, 249, 27, 69, 198, 152, 122, 36,
  22. 248, 166, 68, 26, 153, 199, 37, 123, 58, 100, 134, 216, 91, 5, 231, 185,
  23. 140, 210, 48, 110, 237, 179, 81, 15, 78, 16, 242, 172, 47, 113, 147, 205,
  24. 17, 79, 173, 243, 112, 46, 204, 146, 211, 141, 111, 49, 178, 236, 14, 80,
  25. 175, 241, 19, 77, 206, 144, 114, 44, 109, 51, 209, 143, 12, 82, 176, 238,
  26. 50, 108, 142, 208, 83, 13, 239, 177, 240, 174, 76, 18, 145, 207, 45, 115,
  27. 202, 148, 118, 40, 171, 245, 23, 73, 8, 86, 180, 234, 105, 55, 213, 139,
  28. 87, 9, 235, 181, 54, 104, 138, 212, 149, 203, 41, 119, 244, 170, 72, 22,
  29. 233, 183, 85, 11, 136, 214, 52, 106, 43, 117, 151, 201, 74, 20, 246, 168,
  30. 116, 42, 200, 150, 21, 75, 169, 247, 182, 232, 10, 84, 215, 137, 107, 53
  31. };
  32. static void w1_delay(unsigned long tm)
  33. {
  34. udelay(tm * w1_delay_parm);
  35. }
  36. static void w1_write_bit(struct w1_master *dev, int bit);
  37. static u8 w1_read_bit(struct w1_master *dev);
  38. /**
  39. * w1_touch_bit() - Generates a write-0 or write-1 cycle and samples the level.
  40. * @dev: the master device
  41. * @bit: 0 - write a 0, 1 - write a 0 read the level
  42. */
  43. u8 w1_touch_bit(struct w1_master *dev, int bit)
  44. {
  45. if (dev->bus_master->touch_bit)
  46. return dev->bus_master->touch_bit(dev->bus_master->data, bit);
  47. else if (bit)
  48. return w1_read_bit(dev);
  49. else {
  50. w1_write_bit(dev, 0);
  51. return 0;
  52. }
  53. }
  54. EXPORT_SYMBOL_GPL(w1_touch_bit);
  55. /**
  56. * w1_write_bit() - Generates a write-0 or write-1 cycle.
  57. * @dev: the master device
  58. * @bit: bit to write
  59. *
  60. * Only call if dev->bus_master->touch_bit is NULL
  61. */
  62. static void w1_write_bit(struct w1_master *dev, int bit)
  63. {
  64. unsigned long flags = 0;
  65. if(w1_disable_irqs) local_irq_save(flags);
  66. if (bit) {
  67. dev->bus_master->write_bit(dev->bus_master->data, 0);
  68. w1_delay(6);
  69. dev->bus_master->write_bit(dev->bus_master->data, 1);
  70. w1_delay(64);
  71. } else {
  72. dev->bus_master->write_bit(dev->bus_master->data, 0);
  73. w1_delay(60);
  74. dev->bus_master->write_bit(dev->bus_master->data, 1);
  75. w1_delay(10);
  76. }
  77. if(w1_disable_irqs) local_irq_restore(flags);
  78. }
  79. /**
  80. * w1_pre_write() - pre-write operations
  81. * @dev: the master device
  82. *
  83. * Pre-write operation, currently only supporting strong pullups.
  84. * Program the hardware for a strong pullup, if one has been requested and
  85. * the hardware supports it.
  86. */
  87. static void w1_pre_write(struct w1_master *dev)
  88. {
  89. if (dev->pullup_duration &&
  90. dev->enable_pullup && dev->bus_master->set_pullup) {
  91. dev->bus_master->set_pullup(dev->bus_master->data,
  92. dev->pullup_duration);
  93. }
  94. }
  95. /**
  96. * w1_post_write() - post-write options
  97. * @dev: the master device
  98. *
  99. * Post-write operation, currently only supporting strong pullups.
  100. * If a strong pullup was requested, clear it if the hardware supports
  101. * them, or execute the delay otherwise, in either case clear the request.
  102. */
  103. static void w1_post_write(struct w1_master *dev)
  104. {
  105. if (dev->pullup_duration) {
  106. if (dev->enable_pullup && dev->bus_master->set_pullup)
  107. dev->bus_master->set_pullup(dev->bus_master->data, 0);
  108. else
  109. msleep(dev->pullup_duration);
  110. dev->pullup_duration = 0;
  111. }
  112. }
  113. /**
  114. * w1_write_8() - Writes 8 bits.
  115. * @dev: the master device
  116. * @byte: the byte to write
  117. */
  118. void w1_write_8(struct w1_master *dev, u8 byte)
  119. {
  120. int i;
  121. if (dev->bus_master->write_byte) {
  122. w1_pre_write(dev);
  123. dev->bus_master->write_byte(dev->bus_master->data, byte);
  124. }
  125. else
  126. for (i = 0; i < 8; ++i) {
  127. if (i == 7)
  128. w1_pre_write(dev);
  129. w1_touch_bit(dev, (byte >> i) & 0x1);
  130. }
  131. w1_post_write(dev);
  132. }
  133. EXPORT_SYMBOL_GPL(w1_write_8);
  134. /**
  135. * w1_read_bit() - Generates a write-1 cycle and samples the level.
  136. * @dev: the master device
  137. *
  138. * Only call if dev->bus_master->touch_bit is NULL
  139. */
  140. static u8 w1_read_bit(struct w1_master *dev)
  141. {
  142. int result;
  143. unsigned long flags = 0;
  144. /* sample timing is critical here */
  145. local_irq_save(flags);
  146. dev->bus_master->write_bit(dev->bus_master->data, 0);
  147. w1_delay(6);
  148. dev->bus_master->write_bit(dev->bus_master->data, 1);
  149. w1_delay(9);
  150. result = dev->bus_master->read_bit(dev->bus_master->data);
  151. local_irq_restore(flags);
  152. w1_delay(55);
  153. return result & 0x1;
  154. }
  155. /**
  156. * w1_triplet() - * Does a triplet - used for searching ROM addresses.
  157. * @dev: the master device
  158. * @bdir: the bit to write if both id_bit and comp_bit are 0
  159. *
  160. * Return bits:
  161. * bit 0 = id_bit
  162. * bit 1 = comp_bit
  163. * bit 2 = dir_taken
  164. *
  165. * If both bits 0 & 1 are set, the search should be restarted.
  166. *
  167. * Return: bit fields - see above
  168. */
  169. u8 w1_triplet(struct w1_master *dev, int bdir)
  170. {
  171. if (dev->bus_master->triplet)
  172. return dev->bus_master->triplet(dev->bus_master->data, bdir);
  173. else {
  174. u8 id_bit = w1_touch_bit(dev, 1);
  175. u8 comp_bit = w1_touch_bit(dev, 1);
  176. u8 retval;
  177. if (id_bit && comp_bit)
  178. return 0x03; /* error */
  179. if (!id_bit && !comp_bit) {
  180. /* Both bits are valid, take the direction given */
  181. retval = bdir ? 0x04 : 0;
  182. } else {
  183. /* Only one bit is valid, take that direction */
  184. bdir = id_bit;
  185. retval = id_bit ? 0x05 : 0x02;
  186. }
  187. if (dev->bus_master->touch_bit)
  188. w1_touch_bit(dev, bdir);
  189. else
  190. w1_write_bit(dev, bdir);
  191. return retval;
  192. }
  193. }
  194. EXPORT_SYMBOL_GPL(w1_triplet);
  195. /**
  196. * w1_read_8() - Reads 8 bits.
  197. * @dev: the master device
  198. *
  199. * Return: the byte read
  200. */
  201. u8 w1_read_8(struct w1_master *dev)
  202. {
  203. int i;
  204. u8 res = 0;
  205. if (dev->bus_master->read_byte)
  206. res = dev->bus_master->read_byte(dev->bus_master->data);
  207. else
  208. for (i = 0; i < 8; ++i)
  209. res |= (w1_touch_bit(dev,1) << i);
  210. return res;
  211. }
  212. EXPORT_SYMBOL_GPL(w1_read_8);
  213. /**
  214. * w1_write_block() - Writes a series of bytes.
  215. * @dev: the master device
  216. * @buf: pointer to the data to write
  217. * @len: the number of bytes to write
  218. */
  219. void w1_write_block(struct w1_master *dev, const u8 *buf, int len)
  220. {
  221. int i;
  222. if (dev->bus_master->write_block) {
  223. w1_pre_write(dev);
  224. dev->bus_master->write_block(dev->bus_master->data, buf, len);
  225. }
  226. else
  227. for (i = 0; i < len; ++i)
  228. w1_write_8(dev, buf[i]); /* calls w1_pre_write */
  229. w1_post_write(dev);
  230. }
  231. EXPORT_SYMBOL_GPL(w1_write_block);
  232. /**
  233. * w1_touch_block() - Touches a series of bytes.
  234. * @dev: the master device
  235. * @buf: pointer to the data to write
  236. * @len: the number of bytes to write
  237. */
  238. void w1_touch_block(struct w1_master *dev, u8 *buf, int len)
  239. {
  240. int i, j;
  241. u8 tmp;
  242. for (i = 0; i < len; ++i) {
  243. tmp = 0;
  244. for (j = 0; j < 8; ++j) {
  245. if (j == 7)
  246. w1_pre_write(dev);
  247. tmp |= w1_touch_bit(dev, (buf[i] >> j) & 0x1) << j;
  248. }
  249. buf[i] = tmp;
  250. }
  251. }
  252. EXPORT_SYMBOL_GPL(w1_touch_block);
  253. /**
  254. * w1_read_block() - Reads a series of bytes.
  255. * @dev: the master device
  256. * @buf: pointer to the buffer to fill
  257. * @len: the number of bytes to read
  258. * Return: the number of bytes read
  259. */
  260. u8 w1_read_block(struct w1_master *dev, u8 *buf, int len)
  261. {
  262. int i;
  263. u8 ret;
  264. if (dev->bus_master->read_block)
  265. ret = dev->bus_master->read_block(dev->bus_master->data, buf, len);
  266. else {
  267. for (i = 0; i < len; ++i)
  268. buf[i] = w1_read_8(dev);
  269. ret = len;
  270. }
  271. return ret;
  272. }
  273. EXPORT_SYMBOL_GPL(w1_read_block);
  274. /**
  275. * w1_reset_bus() - Issues a reset bus sequence.
  276. * @dev: the master device
  277. * Return: 0=Device present, 1=No device present or error
  278. */
  279. int w1_reset_bus(struct w1_master *dev)
  280. {
  281. int result;
  282. unsigned long flags = 0;
  283. if(w1_disable_irqs) local_irq_save(flags);
  284. if (dev->bus_master->reset_bus)
  285. result = dev->bus_master->reset_bus(dev->bus_master->data) & 0x1;
  286. else {
  287. dev->bus_master->write_bit(dev->bus_master->data, 0);
  288. /* minimum 480, max ? us
  289. * be nice and sleep, except 18b20 spec lists 960us maximum,
  290. * so until we can sleep with microsecond accuracy, spin.
  291. * Feel free to come up with some other way to give up the
  292. * cpu for such a short amount of time AND get it back in
  293. * the maximum amount of time.
  294. */
  295. w1_delay(500);
  296. dev->bus_master->write_bit(dev->bus_master->data, 1);
  297. w1_delay(70);
  298. result = dev->bus_master->read_bit(dev->bus_master->data) & 0x1;
  299. /* minimum 70 (above) + 430 = 500 us
  300. * There aren't any timing requirements between a reset and
  301. * the following transactions. Sleeping is safe here.
  302. */
  303. /* w1_delay(430); min required time */
  304. msleep(1);
  305. }
  306. if(w1_disable_irqs) local_irq_restore(flags);
  307. return result;
  308. }
  309. EXPORT_SYMBOL_GPL(w1_reset_bus);
  310. u8 w1_calc_crc8(u8 * data, int len)
  311. {
  312. u8 crc = 0;
  313. while (len--)
  314. crc = w1_crc8_table[crc ^ *data++];
  315. return crc;
  316. }
  317. EXPORT_SYMBOL_GPL(w1_calc_crc8);
  318. void w1_search_devices(struct w1_master *dev, u8 search_type, w1_slave_found_callback cb)
  319. {
  320. dev->attempts++;
  321. if (dev->bus_master->search)
  322. dev->bus_master->search(dev->bus_master->data, dev,
  323. search_type, cb);
  324. else
  325. w1_search(dev, search_type, cb);
  326. }
  327. /**
  328. * w1_reset_select_slave() - reset and select a slave
  329. * @sl: the slave to select
  330. *
  331. * Resets the bus and then selects the slave by sending either a skip rom
  332. * or a rom match. A skip rom is issued if there is only one device
  333. * registered on the bus.
  334. * The w1 master lock must be held.
  335. *
  336. * Return: 0=success, anything else=error
  337. */
  338. int w1_reset_select_slave(struct w1_slave *sl)
  339. {
  340. if (w1_reset_bus(sl->master))
  341. return -1;
  342. if (sl->master->slave_count == 1)
  343. w1_write_8(sl->master, W1_SKIP_ROM);
  344. else {
  345. u8 match[9] = {W1_MATCH_ROM, };
  346. u64 rn = le64_to_cpu(*((u64*)&sl->reg_num));
  347. memcpy(&match[1], &rn, 8);
  348. w1_write_block(sl->master, match, 9);
  349. }
  350. return 0;
  351. }
  352. EXPORT_SYMBOL_GPL(w1_reset_select_slave);
  353. /**
  354. * w1_reset_resume_command() - resume instead of another match ROM
  355. * @dev: the master device
  356. *
  357. * When the workflow with a slave amongst many requires several
  358. * successive commands a reset between each, this function is similar
  359. * to doing a reset then a match ROM for the last matched ROM. The
  360. * advantage being that the matched ROM step is skipped in favor of the
  361. * resume command. The slave must support the command of course.
  362. *
  363. * If the bus has only one slave, traditionnaly the match ROM is skipped
  364. * and a "SKIP ROM" is done for efficiency. On multi-slave busses, this
  365. * doesn't work of course, but the resume command is the next best thing.
  366. *
  367. * The w1 master lock must be held.
  368. */
  369. int w1_reset_resume_command(struct w1_master *dev)
  370. {
  371. if (w1_reset_bus(dev))
  372. return -1;
  373. w1_write_8(dev, dev->slave_count > 1 ? W1_RESUME_CMD : W1_SKIP_ROM);
  374. return 0;
  375. }
  376. EXPORT_SYMBOL_GPL(w1_reset_resume_command);
  377. /**
  378. * w1_next_pullup() - register for a strong pullup
  379. * @dev: the master device
  380. * @delay: time in milliseconds
  381. *
  382. * Put out a strong pull-up of the specified duration after the next write
  383. * operation. Not all hardware supports strong pullups. Hardware that
  384. * doesn't support strong pullups will sleep for the given time after the
  385. * write operation without a strong pullup. This is a one shot request for
  386. * the next write, specifying zero will clear a previous request.
  387. * The w1 master lock must be held.
  388. *
  389. * Return: 0=success, anything else=error
  390. */
  391. void w1_next_pullup(struct w1_master *dev, int delay)
  392. {
  393. dev->pullup_duration = delay;
  394. }
  395. EXPORT_SYMBOL_GPL(w1_next_pullup);