mpfs.c 6.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * PolarFire SoC (MPFS) MUSB Glue Layer
  4. *
  5. * Copyright (c) 2020-2022 Microchip Corporation. All rights reserved.
  6. * Based on {omap2430,tusb6010,ux500}.c
  7. *
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/dma-mapping.h>
  11. #include <linux/err.h>
  12. #include <linux/io.h>
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/usb/usb_phy_generic.h>
  17. #include "musb_core.h"
  18. #include "musb_dma.h"
  19. #define MPFS_MUSB_MAX_EP_NUM 8
  20. #define MPFS_MUSB_RAM_BITS 12
  21. struct mpfs_glue {
  22. struct device *dev;
  23. struct platform_device *musb;
  24. struct platform_device *phy;
  25. struct clk *clk;
  26. };
  27. static struct musb_fifo_cfg mpfs_musb_mode_cfg[] = {
  28. { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
  29. { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
  30. { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
  31. { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
  32. { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
  33. { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
  34. { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 1024, },
  35. { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 4096, },
  36. };
  37. static const struct musb_hdrc_config mpfs_musb_hdrc_config = {
  38. .fifo_cfg = mpfs_musb_mode_cfg,
  39. .fifo_cfg_size = ARRAY_SIZE(mpfs_musb_mode_cfg),
  40. .multipoint = true,
  41. .dyn_fifo = true,
  42. .num_eps = MPFS_MUSB_MAX_EP_NUM,
  43. .ram_bits = MPFS_MUSB_RAM_BITS,
  44. };
  45. static irqreturn_t mpfs_musb_interrupt(int irq, void *__hci)
  46. {
  47. unsigned long flags;
  48. irqreturn_t ret = IRQ_NONE;
  49. struct musb *musb = __hci;
  50. spin_lock_irqsave(&musb->lock, flags);
  51. musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
  52. musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
  53. musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
  54. if (musb->int_usb || musb->int_tx || musb->int_rx) {
  55. musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
  56. musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
  57. musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
  58. ret = musb_interrupt(musb);
  59. }
  60. spin_unlock_irqrestore(&musb->lock, flags);
  61. return ret;
  62. }
  63. static void mpfs_musb_set_vbus(struct musb *musb, int is_on)
  64. {
  65. u8 devctl;
  66. /*
  67. * HDRC controls CPEN, but beware current surges during device
  68. * connect. They can trigger transient overcurrent conditions
  69. * that must be ignored.
  70. */
  71. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  72. if (is_on) {
  73. musb->is_active = 1;
  74. musb->xceiv->otg->default_a = 1;
  75. musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
  76. devctl |= MUSB_DEVCTL_SESSION;
  77. MUSB_HST_MODE(musb);
  78. } else {
  79. musb->is_active = 0;
  80. /*
  81. * NOTE: skipping A_WAIT_VFALL -> A_IDLE and
  82. * jumping right to B_IDLE...
  83. */
  84. musb->xceiv->otg->default_a = 0;
  85. musb->xceiv->otg->state = OTG_STATE_B_IDLE;
  86. devctl &= ~MUSB_DEVCTL_SESSION;
  87. MUSB_DEV_MODE(musb);
  88. }
  89. musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
  90. dev_dbg(musb->controller, "VBUS %s, devctl %02x\n",
  91. usb_otg_state_string(musb->xceiv->otg->state),
  92. musb_readb(musb->mregs, MUSB_DEVCTL));
  93. }
  94. static int mpfs_musb_init(struct musb *musb)
  95. {
  96. struct device *dev = musb->controller;
  97. musb->xceiv = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
  98. if (IS_ERR(musb->xceiv)) {
  99. dev_err(dev, "HS UDC: no transceiver configured\n");
  100. return PTR_ERR(musb->xceiv);
  101. }
  102. musb->dyn_fifo = true;
  103. musb->isr = mpfs_musb_interrupt;
  104. musb_platform_set_vbus(musb, 1);
  105. return 0;
  106. }
  107. static const struct musb_platform_ops mpfs_ops = {
  108. .quirks = MUSB_DMA_INVENTRA,
  109. .init = mpfs_musb_init,
  110. .fifo_mode = 2,
  111. #ifdef CONFIG_USB_INVENTRA_DMA
  112. .dma_init = musbhs_dma_controller_create,
  113. .dma_exit = musbhs_dma_controller_destroy,
  114. #endif
  115. .set_vbus = mpfs_musb_set_vbus
  116. };
  117. static int mpfs_probe(struct platform_device *pdev)
  118. {
  119. struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev);
  120. struct mpfs_glue *glue;
  121. struct platform_device *musb_pdev;
  122. struct device *dev = &pdev->dev;
  123. struct clk *clk;
  124. int ret;
  125. glue = devm_kzalloc(dev, sizeof(*glue), GFP_KERNEL);
  126. if (!glue)
  127. return -ENOMEM;
  128. musb_pdev = platform_device_alloc("musb-hdrc", PLATFORM_DEVID_AUTO);
  129. if (!musb_pdev) {
  130. dev_err(dev, "failed to allocate musb device\n");
  131. return -ENOMEM;
  132. }
  133. clk = devm_clk_get(&pdev->dev, NULL);
  134. if (IS_ERR(clk)) {
  135. dev_err(&pdev->dev, "failed to get clock\n");
  136. ret = PTR_ERR(clk);
  137. goto err_phy_release;
  138. }
  139. ret = clk_prepare_enable(clk);
  140. if (ret) {
  141. dev_err(&pdev->dev, "failed to enable clock\n");
  142. goto err_phy_release;
  143. }
  144. musb_pdev->dev.parent = dev;
  145. musb_pdev->dev.coherent_dma_mask = DMA_BIT_MASK(39);
  146. musb_pdev->dev.dma_mask = &musb_pdev->dev.coherent_dma_mask;
  147. device_set_of_node_from_dev(&musb_pdev->dev, dev);
  148. glue->dev = dev;
  149. glue->musb = musb_pdev;
  150. glue->clk = clk;
  151. pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
  152. if (!pdata) {
  153. ret = -ENOMEM;
  154. goto err_clk_disable;
  155. }
  156. pdata->config = &mpfs_musb_hdrc_config;
  157. pdata->platform_ops = &mpfs_ops;
  158. pdata->mode = usb_get_dr_mode(dev);
  159. if (pdata->mode == USB_DR_MODE_UNKNOWN) {
  160. dev_info(dev, "No dr_mode property found, defaulting to otg\n");
  161. pdata->mode = USB_DR_MODE_OTG;
  162. }
  163. glue->phy = usb_phy_generic_register();
  164. if (IS_ERR(glue->phy)) {
  165. dev_err(dev, "failed to register usb-phy %ld\n",
  166. PTR_ERR(glue->phy));
  167. ret = PTR_ERR(glue->phy);
  168. goto err_clk_disable;
  169. }
  170. platform_set_drvdata(pdev, glue);
  171. ret = platform_device_add_resources(musb_pdev, pdev->resource, pdev->num_resources);
  172. if (ret) {
  173. dev_err(dev, "failed to add resources\n");
  174. goto err_clk_disable;
  175. }
  176. ret = platform_device_add_data(musb_pdev, pdata, sizeof(*pdata));
  177. if (ret) {
  178. dev_err(dev, "failed to add platform_data\n");
  179. goto err_clk_disable;
  180. }
  181. ret = platform_device_add(musb_pdev);
  182. if (ret) {
  183. dev_err(dev, "failed to register musb device\n");
  184. goto err_clk_disable;
  185. }
  186. dev_info(&pdev->dev, "Registered MPFS MUSB driver\n");
  187. return 0;
  188. err_clk_disable:
  189. clk_disable_unprepare(clk);
  190. err_phy_release:
  191. usb_phy_generic_unregister(glue->phy);
  192. platform_device_put(musb_pdev);
  193. return ret;
  194. }
  195. static int mpfs_remove(struct platform_device *pdev)
  196. {
  197. struct mpfs_glue *glue = platform_get_drvdata(pdev);
  198. clk_disable_unprepare(glue->clk);
  199. platform_device_unregister(glue->musb);
  200. usb_phy_generic_unregister(pdev);
  201. return 0;
  202. }
  203. #ifdef CONFIG_OF
  204. static const struct of_device_id mpfs_id_table[] = {
  205. { .compatible = "microchip,mpfs-musb" },
  206. { }
  207. };
  208. MODULE_DEVICE_TABLE(of, mpfs_id_table);
  209. #endif
  210. static struct platform_driver mpfs_musb_driver = {
  211. .probe = mpfs_probe,
  212. .remove = mpfs_remove,
  213. .driver = {
  214. .name = "mpfs-musb",
  215. .of_match_table = of_match_ptr(mpfs_id_table)
  216. },
  217. };
  218. module_platform_driver(mpfs_musb_driver);
  219. MODULE_DESCRIPTION("PolarFire SoC MUSB Glue Layer");
  220. MODULE_LICENSE("GPL");