mediatek.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2019 MediaTek Inc.
  4. *
  5. * Author:
  6. * Min Guo <[email protected]>
  7. * Yonglong Wu <[email protected]>
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/dma-mapping.h>
  11. #include <linux/module.h>
  12. #include <linux/of_platform.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/usb/role.h>
  15. #include <linux/usb/usb_phy_generic.h>
  16. #include "musb_core.h"
  17. #include "musb_dma.h"
  18. #define USB_L1INTS 0x00a0
  19. #define USB_L1INTM 0x00a4
  20. #define MTK_MUSB_TXFUNCADDR 0x0480
  21. /* MediaTek controller toggle enable and status reg */
  22. #define MUSB_RXTOG 0x80
  23. #define MUSB_RXTOGEN 0x82
  24. #define MUSB_TXTOG 0x84
  25. #define MUSB_TXTOGEN 0x86
  26. #define MTK_TOGGLE_EN GENMASK(15, 0)
  27. #define TX_INT_STATUS BIT(0)
  28. #define RX_INT_STATUS BIT(1)
  29. #define USBCOM_INT_STATUS BIT(2)
  30. #define DMA_INT_STATUS BIT(3)
  31. #define DMA_INTR_STATUS_MSK GENMASK(7, 0)
  32. #define DMA_INTR_UNMASK_SET_MSK GENMASK(31, 24)
  33. #define MTK_MUSB_CLKS_NUM 3
  34. struct mtk_glue {
  35. struct device *dev;
  36. struct musb *musb;
  37. struct platform_device *musb_pdev;
  38. struct platform_device *usb_phy;
  39. struct phy *phy;
  40. struct usb_phy *xceiv;
  41. enum phy_mode phy_mode;
  42. struct clk_bulk_data clks[MTK_MUSB_CLKS_NUM];
  43. enum usb_role role;
  44. struct usb_role_switch *role_sw;
  45. };
  46. static int mtk_musb_clks_get(struct mtk_glue *glue)
  47. {
  48. struct device *dev = glue->dev;
  49. glue->clks[0].id = "main";
  50. glue->clks[1].id = "mcu";
  51. glue->clks[2].id = "univpll";
  52. return devm_clk_bulk_get(dev, MTK_MUSB_CLKS_NUM, glue->clks);
  53. }
  54. static int mtk_otg_switch_set(struct mtk_glue *glue, enum usb_role role)
  55. {
  56. struct musb *musb = glue->musb;
  57. u8 devctl = readb(musb->mregs + MUSB_DEVCTL);
  58. enum usb_role new_role;
  59. if (role == glue->role)
  60. return 0;
  61. switch (role) {
  62. case USB_ROLE_HOST:
  63. musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
  64. glue->phy_mode = PHY_MODE_USB_HOST;
  65. new_role = USB_ROLE_HOST;
  66. if (glue->role == USB_ROLE_NONE)
  67. phy_power_on(glue->phy);
  68. devctl |= MUSB_DEVCTL_SESSION;
  69. musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
  70. MUSB_HST_MODE(musb);
  71. break;
  72. case USB_ROLE_DEVICE:
  73. musb->xceiv->otg->state = OTG_STATE_B_IDLE;
  74. glue->phy_mode = PHY_MODE_USB_DEVICE;
  75. new_role = USB_ROLE_DEVICE;
  76. devctl &= ~MUSB_DEVCTL_SESSION;
  77. musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
  78. if (glue->role == USB_ROLE_NONE)
  79. phy_power_on(glue->phy);
  80. MUSB_DEV_MODE(musb);
  81. break;
  82. case USB_ROLE_NONE:
  83. glue->phy_mode = PHY_MODE_USB_OTG;
  84. new_role = USB_ROLE_NONE;
  85. devctl &= ~MUSB_DEVCTL_SESSION;
  86. musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
  87. if (glue->role != USB_ROLE_NONE)
  88. phy_power_off(glue->phy);
  89. break;
  90. default:
  91. dev_err(glue->dev, "Invalid State\n");
  92. return -EINVAL;
  93. }
  94. glue->role = new_role;
  95. phy_set_mode(glue->phy, glue->phy_mode);
  96. return 0;
  97. }
  98. static int musb_usb_role_sx_set(struct usb_role_switch *sw, enum usb_role role)
  99. {
  100. return mtk_otg_switch_set(usb_role_switch_get_drvdata(sw), role);
  101. }
  102. static enum usb_role musb_usb_role_sx_get(struct usb_role_switch *sw)
  103. {
  104. struct mtk_glue *glue = usb_role_switch_get_drvdata(sw);
  105. return glue->role;
  106. }
  107. static int mtk_otg_switch_init(struct mtk_glue *glue)
  108. {
  109. struct usb_role_switch_desc role_sx_desc = { 0 };
  110. role_sx_desc.set = musb_usb_role_sx_set;
  111. role_sx_desc.get = musb_usb_role_sx_get;
  112. role_sx_desc.allow_userspace_control = true;
  113. role_sx_desc.fwnode = dev_fwnode(glue->dev);
  114. role_sx_desc.driver_data = glue;
  115. glue->role_sw = usb_role_switch_register(glue->dev, &role_sx_desc);
  116. return PTR_ERR_OR_ZERO(glue->role_sw);
  117. }
  118. static void mtk_otg_switch_exit(struct mtk_glue *glue)
  119. {
  120. return usb_role_switch_unregister(glue->role_sw);
  121. }
  122. static irqreturn_t generic_interrupt(int irq, void *__hci)
  123. {
  124. unsigned long flags;
  125. irqreturn_t retval = IRQ_NONE;
  126. struct musb *musb = __hci;
  127. spin_lock_irqsave(&musb->lock, flags);
  128. musb->int_usb = musb_clearb(musb->mregs, MUSB_INTRUSB);
  129. musb->int_rx = musb_clearw(musb->mregs, MUSB_INTRRX);
  130. musb->int_tx = musb_clearw(musb->mregs, MUSB_INTRTX);
  131. if ((musb->int_usb & MUSB_INTR_RESET) && !is_host_active(musb)) {
  132. /* ep0 FADDR must be 0 when (re)entering peripheral mode */
  133. musb_ep_select(musb->mregs, 0);
  134. musb_writeb(musb->mregs, MUSB_FADDR, 0);
  135. }
  136. if (musb->int_usb || musb->int_tx || musb->int_rx)
  137. retval = musb_interrupt(musb);
  138. spin_unlock_irqrestore(&musb->lock, flags);
  139. return retval;
  140. }
  141. static irqreturn_t mtk_musb_interrupt(int irq, void *dev_id)
  142. {
  143. irqreturn_t retval = IRQ_NONE;
  144. struct musb *musb = (struct musb *)dev_id;
  145. u32 l1_ints;
  146. l1_ints = musb_readl(musb->mregs, USB_L1INTS) &
  147. musb_readl(musb->mregs, USB_L1INTM);
  148. if (l1_ints & (TX_INT_STATUS | RX_INT_STATUS | USBCOM_INT_STATUS))
  149. retval = generic_interrupt(irq, musb);
  150. #if defined(CONFIG_USB_INVENTRA_DMA)
  151. if (l1_ints & DMA_INT_STATUS)
  152. retval = dma_controller_irq(irq, musb->dma_controller);
  153. #endif
  154. return retval;
  155. }
  156. static u32 mtk_musb_busctl_offset(u8 epnum, u16 offset)
  157. {
  158. return MTK_MUSB_TXFUNCADDR + offset + 8 * epnum;
  159. }
  160. static u8 mtk_musb_clearb(void __iomem *addr, unsigned int offset)
  161. {
  162. u8 data;
  163. /* W1C */
  164. data = musb_readb(addr, offset);
  165. musb_writeb(addr, offset, data);
  166. return data;
  167. }
  168. static u16 mtk_musb_clearw(void __iomem *addr, unsigned int offset)
  169. {
  170. u16 data;
  171. /* W1C */
  172. data = musb_readw(addr, offset);
  173. musb_writew(addr, offset, data);
  174. return data;
  175. }
  176. static int mtk_musb_set_mode(struct musb *musb, u8 mode)
  177. {
  178. struct device *dev = musb->controller;
  179. struct mtk_glue *glue = dev_get_drvdata(dev->parent);
  180. enum phy_mode new_mode;
  181. enum usb_role new_role;
  182. switch (mode) {
  183. case MUSB_HOST:
  184. new_mode = PHY_MODE_USB_HOST;
  185. new_role = USB_ROLE_HOST;
  186. break;
  187. case MUSB_PERIPHERAL:
  188. new_mode = PHY_MODE_USB_DEVICE;
  189. new_role = USB_ROLE_DEVICE;
  190. break;
  191. case MUSB_OTG:
  192. new_mode = PHY_MODE_USB_OTG;
  193. new_role = USB_ROLE_NONE;
  194. break;
  195. default:
  196. dev_err(glue->dev, "Invalid mode request\n");
  197. return -EINVAL;
  198. }
  199. if (glue->phy_mode == new_mode)
  200. return 0;
  201. if (musb->port_mode != MUSB_OTG) {
  202. dev_err(glue->dev, "Does not support changing modes\n");
  203. return -EINVAL;
  204. }
  205. mtk_otg_switch_set(glue, new_role);
  206. return 0;
  207. }
  208. static int mtk_musb_init(struct musb *musb)
  209. {
  210. struct device *dev = musb->controller;
  211. struct mtk_glue *glue = dev_get_drvdata(dev->parent);
  212. int ret;
  213. glue->musb = musb;
  214. musb->phy = glue->phy;
  215. musb->xceiv = glue->xceiv;
  216. musb->is_host = false;
  217. musb->isr = mtk_musb_interrupt;
  218. /* Set TX/RX toggle enable */
  219. musb_writew(musb->mregs, MUSB_TXTOGEN, MTK_TOGGLE_EN);
  220. musb_writew(musb->mregs, MUSB_RXTOGEN, MTK_TOGGLE_EN);
  221. if (musb->port_mode == MUSB_OTG) {
  222. ret = mtk_otg_switch_init(glue);
  223. if (ret)
  224. return ret;
  225. }
  226. ret = phy_init(glue->phy);
  227. if (ret)
  228. goto err_phy_init;
  229. ret = phy_power_on(glue->phy);
  230. if (ret)
  231. goto err_phy_power_on;
  232. phy_set_mode(glue->phy, glue->phy_mode);
  233. #if defined(CONFIG_USB_INVENTRA_DMA)
  234. musb_writel(musb->mregs, MUSB_HSDMA_INTR,
  235. DMA_INTR_STATUS_MSK | DMA_INTR_UNMASK_SET_MSK);
  236. #endif
  237. musb_writel(musb->mregs, USB_L1INTM, TX_INT_STATUS | RX_INT_STATUS |
  238. USBCOM_INT_STATUS | DMA_INT_STATUS);
  239. return 0;
  240. err_phy_power_on:
  241. phy_exit(glue->phy);
  242. err_phy_init:
  243. if (musb->port_mode == MUSB_OTG)
  244. mtk_otg_switch_exit(glue);
  245. return ret;
  246. }
  247. static u16 mtk_musb_get_toggle(struct musb_qh *qh, int is_out)
  248. {
  249. struct musb *musb = qh->hw_ep->musb;
  250. u8 epnum = qh->hw_ep->epnum;
  251. u16 toggle;
  252. toggle = musb_readw(musb->mregs, is_out ? MUSB_TXTOG : MUSB_RXTOG);
  253. return toggle & (1 << epnum);
  254. }
  255. static u16 mtk_musb_set_toggle(struct musb_qh *qh, int is_out, struct urb *urb)
  256. {
  257. struct musb *musb = qh->hw_ep->musb;
  258. u8 epnum = qh->hw_ep->epnum;
  259. u16 value, toggle;
  260. toggle = usb_gettoggle(urb->dev, qh->epnum, is_out);
  261. if (is_out) {
  262. value = musb_readw(musb->mregs, MUSB_TXTOG);
  263. value |= toggle << epnum;
  264. musb_writew(musb->mregs, MUSB_TXTOG, value);
  265. } else {
  266. value = musb_readw(musb->mregs, MUSB_RXTOG);
  267. value |= toggle << epnum;
  268. musb_writew(musb->mregs, MUSB_RXTOG, value);
  269. }
  270. return 0;
  271. }
  272. static int mtk_musb_exit(struct musb *musb)
  273. {
  274. struct device *dev = musb->controller;
  275. struct mtk_glue *glue = dev_get_drvdata(dev->parent);
  276. mtk_otg_switch_exit(glue);
  277. phy_power_off(glue->phy);
  278. phy_exit(glue->phy);
  279. clk_bulk_disable_unprepare(MTK_MUSB_CLKS_NUM, glue->clks);
  280. pm_runtime_put_sync(dev);
  281. pm_runtime_disable(dev);
  282. return 0;
  283. }
  284. static const struct musb_platform_ops mtk_musb_ops = {
  285. .quirks = MUSB_DMA_INVENTRA,
  286. .init = mtk_musb_init,
  287. .get_toggle = mtk_musb_get_toggle,
  288. .set_toggle = mtk_musb_set_toggle,
  289. .exit = mtk_musb_exit,
  290. #ifdef CONFIG_USB_INVENTRA_DMA
  291. .dma_init = musbhs_dma_controller_create_noirq,
  292. .dma_exit = musbhs_dma_controller_destroy,
  293. #endif
  294. .clearb = mtk_musb_clearb,
  295. .clearw = mtk_musb_clearw,
  296. .busctl_offset = mtk_musb_busctl_offset,
  297. .set_mode = mtk_musb_set_mode,
  298. };
  299. #define MTK_MUSB_MAX_EP_NUM 8
  300. #define MTK_MUSB_RAM_BITS 11
  301. static struct musb_fifo_cfg mtk_musb_mode_cfg[] = {
  302. { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
  303. { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
  304. { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
  305. { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
  306. { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
  307. { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
  308. { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
  309. { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
  310. { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
  311. { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
  312. { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 1024, },
  313. { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 1024, },
  314. { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
  315. { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 64, },
  316. };
  317. static const struct musb_hdrc_config mtk_musb_hdrc_config = {
  318. .fifo_cfg = mtk_musb_mode_cfg,
  319. .fifo_cfg_size = ARRAY_SIZE(mtk_musb_mode_cfg),
  320. .multipoint = true,
  321. .dyn_fifo = true,
  322. .num_eps = MTK_MUSB_MAX_EP_NUM,
  323. .ram_bits = MTK_MUSB_RAM_BITS,
  324. };
  325. static const struct platform_device_info mtk_dev_info = {
  326. .name = "musb-hdrc",
  327. .id = PLATFORM_DEVID_AUTO,
  328. .dma_mask = DMA_BIT_MASK(32),
  329. };
  330. static int mtk_musb_probe(struct platform_device *pdev)
  331. {
  332. struct musb_hdrc_platform_data *pdata;
  333. struct mtk_glue *glue;
  334. struct platform_device_info pinfo;
  335. struct device *dev = &pdev->dev;
  336. struct device_node *np = dev->of_node;
  337. int ret;
  338. glue = devm_kzalloc(dev, sizeof(*glue), GFP_KERNEL);
  339. if (!glue)
  340. return -ENOMEM;
  341. glue->dev = dev;
  342. pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
  343. if (!pdata)
  344. return -ENOMEM;
  345. ret = of_platform_populate(np, NULL, NULL, dev);
  346. if (ret) {
  347. dev_err(dev, "failed to create child devices at %p\n", np);
  348. return ret;
  349. }
  350. ret = mtk_musb_clks_get(glue);
  351. if (ret)
  352. return ret;
  353. pdata->config = &mtk_musb_hdrc_config;
  354. pdata->platform_ops = &mtk_musb_ops;
  355. pdata->mode = usb_get_dr_mode(dev);
  356. if (IS_ENABLED(CONFIG_USB_MUSB_HOST))
  357. pdata->mode = USB_DR_MODE_HOST;
  358. else if (IS_ENABLED(CONFIG_USB_MUSB_GADGET))
  359. pdata->mode = USB_DR_MODE_PERIPHERAL;
  360. switch (pdata->mode) {
  361. case USB_DR_MODE_HOST:
  362. glue->phy_mode = PHY_MODE_USB_HOST;
  363. glue->role = USB_ROLE_HOST;
  364. break;
  365. case USB_DR_MODE_PERIPHERAL:
  366. glue->phy_mode = PHY_MODE_USB_DEVICE;
  367. glue->role = USB_ROLE_DEVICE;
  368. break;
  369. case USB_DR_MODE_OTG:
  370. glue->phy_mode = PHY_MODE_USB_OTG;
  371. glue->role = USB_ROLE_NONE;
  372. break;
  373. default:
  374. dev_err(&pdev->dev, "Error 'dr_mode' property\n");
  375. return -EINVAL;
  376. }
  377. glue->phy = devm_of_phy_get_by_index(dev, np, 0);
  378. if (IS_ERR(glue->phy)) {
  379. dev_err(dev, "fail to getting phy %ld\n",
  380. PTR_ERR(glue->phy));
  381. return PTR_ERR(glue->phy);
  382. }
  383. glue->usb_phy = usb_phy_generic_register();
  384. if (IS_ERR(glue->usb_phy)) {
  385. dev_err(dev, "fail to registering usb-phy %ld\n",
  386. PTR_ERR(glue->usb_phy));
  387. return PTR_ERR(glue->usb_phy);
  388. }
  389. glue->xceiv = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
  390. if (IS_ERR(glue->xceiv)) {
  391. ret = PTR_ERR(glue->xceiv);
  392. dev_err(dev, "fail to getting usb-phy %d\n", ret);
  393. goto err_unregister_usb_phy;
  394. }
  395. platform_set_drvdata(pdev, glue);
  396. pm_runtime_enable(dev);
  397. pm_runtime_get_sync(dev);
  398. ret = clk_bulk_prepare_enable(MTK_MUSB_CLKS_NUM, glue->clks);
  399. if (ret)
  400. goto err_enable_clk;
  401. pinfo = mtk_dev_info;
  402. pinfo.parent = dev;
  403. pinfo.res = pdev->resource;
  404. pinfo.num_res = pdev->num_resources;
  405. pinfo.data = pdata;
  406. pinfo.size_data = sizeof(*pdata);
  407. pinfo.fwnode = of_fwnode_handle(np);
  408. pinfo.of_node_reused = true;
  409. glue->musb_pdev = platform_device_register_full(&pinfo);
  410. if (IS_ERR(glue->musb_pdev)) {
  411. ret = PTR_ERR(glue->musb_pdev);
  412. dev_err(dev, "failed to register musb device: %d\n", ret);
  413. goto err_device_register;
  414. }
  415. return 0;
  416. err_device_register:
  417. clk_bulk_disable_unprepare(MTK_MUSB_CLKS_NUM, glue->clks);
  418. err_enable_clk:
  419. pm_runtime_put_sync(dev);
  420. pm_runtime_disable(dev);
  421. err_unregister_usb_phy:
  422. usb_phy_generic_unregister(glue->usb_phy);
  423. return ret;
  424. }
  425. static int mtk_musb_remove(struct platform_device *pdev)
  426. {
  427. struct mtk_glue *glue = platform_get_drvdata(pdev);
  428. struct platform_device *usb_phy = glue->usb_phy;
  429. platform_device_unregister(glue->musb_pdev);
  430. usb_phy_generic_unregister(usb_phy);
  431. return 0;
  432. }
  433. #ifdef CONFIG_OF
  434. static const struct of_device_id mtk_musb_match[] = {
  435. {.compatible = "mediatek,mtk-musb",},
  436. {},
  437. };
  438. MODULE_DEVICE_TABLE(of, mtk_musb_match);
  439. #endif
  440. static struct platform_driver mtk_musb_driver = {
  441. .probe = mtk_musb_probe,
  442. .remove = mtk_musb_remove,
  443. .driver = {
  444. .name = "musb-mtk",
  445. .of_match_table = of_match_ptr(mtk_musb_match),
  446. },
  447. };
  448. module_platform_driver(mtk_musb_driver);
  449. MODULE_DESCRIPTION("MediaTek MUSB Glue Layer");
  450. MODULE_AUTHOR("Min Guo <[email protected]>");
  451. MODULE_LICENSE("GPL v2");