mtu3_plat.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2016 MediaTek Inc.
  4. *
  5. * Author: Chunfeng Yun <[email protected]>
  6. */
  7. #include <linux/dma-mapping.h>
  8. #include <linux/iopoll.h>
  9. #include <linux/kernel.h>
  10. #include <linux/module.h>
  11. #include <linux/of_address.h>
  12. #include <linux/of_irq.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/pm_wakeirq.h>
  15. #include <linux/reset.h>
  16. #include "mtu3.h"
  17. #include "mtu3_dr.h"
  18. #include "mtu3_debug.h"
  19. /* u2-port0 should be powered on and enabled; */
  20. int ssusb_check_clocks(struct ssusb_mtk *ssusb, u32 ex_clks)
  21. {
  22. void __iomem *ibase = ssusb->ippc_base;
  23. u32 value, check_val;
  24. int ret;
  25. check_val = ex_clks | SSUSB_SYS125_RST_B_STS | SSUSB_SYSPLL_STABLE |
  26. SSUSB_REF_RST_B_STS;
  27. ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS1, value,
  28. (check_val == (value & check_val)), 100, 20000);
  29. if (ret) {
  30. dev_err(ssusb->dev, "clks of sts1 are not stable!\n");
  31. return ret;
  32. }
  33. ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS2, value,
  34. (value & SSUSB_U2_MAC_SYS_RST_B_STS), 100, 10000);
  35. if (ret) {
  36. dev_err(ssusb->dev, "mac2 clock is not stable\n");
  37. return ret;
  38. }
  39. return 0;
  40. }
  41. static int wait_for_ip_sleep(struct ssusb_mtk *ssusb)
  42. {
  43. bool sleep_check = true;
  44. u32 value;
  45. int ret;
  46. if (!ssusb->is_host)
  47. sleep_check = ssusb_gadget_ip_sleep_check(ssusb);
  48. if (!sleep_check)
  49. return 0;
  50. /* wait for ip enter sleep mode */
  51. ret = readl_poll_timeout(ssusb->ippc_base + U3D_SSUSB_IP_PW_STS1, value,
  52. (value & SSUSB_IP_SLEEP_STS), 100, 100000);
  53. if (ret) {
  54. dev_err(ssusb->dev, "ip sleep failed!!!\n");
  55. ret = -EBUSY;
  56. } else {
  57. /* workaround: avoid wrong wakeup signal latch for some soc */
  58. usleep_range(100, 200);
  59. }
  60. return ret;
  61. }
  62. static int ssusb_phy_init(struct ssusb_mtk *ssusb)
  63. {
  64. int i;
  65. int ret;
  66. for (i = 0; i < ssusb->num_phys; i++) {
  67. ret = phy_init(ssusb->phys[i]);
  68. if (ret)
  69. goto exit_phy;
  70. }
  71. return 0;
  72. exit_phy:
  73. for (; i > 0; i--)
  74. phy_exit(ssusb->phys[i - 1]);
  75. return ret;
  76. }
  77. static int ssusb_phy_exit(struct ssusb_mtk *ssusb)
  78. {
  79. int i;
  80. for (i = 0; i < ssusb->num_phys; i++)
  81. phy_exit(ssusb->phys[i]);
  82. return 0;
  83. }
  84. static int ssusb_phy_power_on(struct ssusb_mtk *ssusb)
  85. {
  86. int i;
  87. int ret;
  88. for (i = 0; i < ssusb->num_phys; i++) {
  89. ret = phy_power_on(ssusb->phys[i]);
  90. if (ret)
  91. goto power_off_phy;
  92. }
  93. return 0;
  94. power_off_phy:
  95. for (; i > 0; i--)
  96. phy_power_off(ssusb->phys[i - 1]);
  97. return ret;
  98. }
  99. static void ssusb_phy_power_off(struct ssusb_mtk *ssusb)
  100. {
  101. unsigned int i;
  102. for (i = 0; i < ssusb->num_phys; i++)
  103. phy_power_off(ssusb->phys[i]);
  104. }
  105. static int ssusb_rscs_init(struct ssusb_mtk *ssusb)
  106. {
  107. int ret = 0;
  108. ret = regulator_enable(ssusb->vusb33);
  109. if (ret) {
  110. dev_err(ssusb->dev, "failed to enable vusb33\n");
  111. goto vusb33_err;
  112. }
  113. ret = clk_bulk_prepare_enable(BULK_CLKS_CNT, ssusb->clks);
  114. if (ret)
  115. goto clks_err;
  116. ret = ssusb_phy_init(ssusb);
  117. if (ret) {
  118. dev_err(ssusb->dev, "failed to init phy\n");
  119. goto phy_init_err;
  120. }
  121. ret = ssusb_phy_power_on(ssusb);
  122. if (ret) {
  123. dev_err(ssusb->dev, "failed to power on phy\n");
  124. goto phy_err;
  125. }
  126. return 0;
  127. phy_err:
  128. ssusb_phy_exit(ssusb);
  129. phy_init_err:
  130. clk_bulk_disable_unprepare(BULK_CLKS_CNT, ssusb->clks);
  131. clks_err:
  132. regulator_disable(ssusb->vusb33);
  133. vusb33_err:
  134. return ret;
  135. }
  136. static void ssusb_rscs_exit(struct ssusb_mtk *ssusb)
  137. {
  138. clk_bulk_disable_unprepare(BULK_CLKS_CNT, ssusb->clks);
  139. regulator_disable(ssusb->vusb33);
  140. ssusb_phy_power_off(ssusb);
  141. ssusb_phy_exit(ssusb);
  142. }
  143. static void ssusb_ip_sw_reset(struct ssusb_mtk *ssusb)
  144. {
  145. /* reset whole ip (xhci & u3d) */
  146. mtu3_setbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST);
  147. udelay(1);
  148. mtu3_clrbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST);
  149. /*
  150. * device ip may be powered on in firmware/BROM stage before entering
  151. * kernel stage;
  152. * power down device ip, otherwise ip-sleep will fail when working as
  153. * host only mode
  154. */
  155. mtu3_setbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
  156. }
  157. static void ssusb_u3_drd_check(struct ssusb_mtk *ssusb)
  158. {
  159. struct otg_switch_mtk *otg_sx = &ssusb->otg_switch;
  160. u32 dev_u3p_num;
  161. u32 host_u3p_num;
  162. u32 value;
  163. /* u3 port0 is disabled */
  164. if (ssusb->u3p_dis_msk & BIT(0)) {
  165. otg_sx->is_u3_drd = false;
  166. goto out;
  167. }
  168. value = mtu3_readl(ssusb->ippc_base, U3D_SSUSB_IP_DEV_CAP);
  169. dev_u3p_num = SSUSB_IP_DEV_U3_PORT_NUM(value);
  170. value = mtu3_readl(ssusb->ippc_base, U3D_SSUSB_IP_XHCI_CAP);
  171. host_u3p_num = SSUSB_IP_XHCI_U3_PORT_NUM(value);
  172. otg_sx->is_u3_drd = !!(dev_u3p_num && host_u3p_num);
  173. out:
  174. dev_info(ssusb->dev, "usb3-drd: %d\n", otg_sx->is_u3_drd);
  175. }
  176. static int get_ssusb_rscs(struct platform_device *pdev, struct ssusb_mtk *ssusb)
  177. {
  178. struct device_node *node = pdev->dev.of_node;
  179. struct otg_switch_mtk *otg_sx = &ssusb->otg_switch;
  180. struct clk_bulk_data *clks = ssusb->clks;
  181. struct device *dev = &pdev->dev;
  182. int i;
  183. int ret;
  184. ssusb->vusb33 = devm_regulator_get(dev, "vusb33");
  185. if (IS_ERR(ssusb->vusb33)) {
  186. dev_err(dev, "failed to get vusb33\n");
  187. return PTR_ERR(ssusb->vusb33);
  188. }
  189. clks[0].id = "sys_ck";
  190. clks[1].id = "ref_ck";
  191. clks[2].id = "mcu_ck";
  192. clks[3].id = "dma_ck";
  193. ret = devm_clk_bulk_get_optional(dev, BULK_CLKS_CNT, clks);
  194. if (ret)
  195. return ret;
  196. ssusb->num_phys = of_count_phandle_with_args(node,
  197. "phys", "#phy-cells");
  198. if (ssusb->num_phys > 0) {
  199. ssusb->phys = devm_kcalloc(dev, ssusb->num_phys,
  200. sizeof(*ssusb->phys), GFP_KERNEL);
  201. if (!ssusb->phys)
  202. return -ENOMEM;
  203. } else {
  204. ssusb->num_phys = 0;
  205. }
  206. for (i = 0; i < ssusb->num_phys; i++) {
  207. ssusb->phys[i] = devm_of_phy_get_by_index(dev, node, i);
  208. if (IS_ERR(ssusb->phys[i])) {
  209. dev_err(dev, "failed to get phy-%d\n", i);
  210. return PTR_ERR(ssusb->phys[i]);
  211. }
  212. }
  213. ssusb->ippc_base = devm_platform_ioremap_resource_byname(pdev, "ippc");
  214. if (IS_ERR(ssusb->ippc_base))
  215. return PTR_ERR(ssusb->ippc_base);
  216. ssusb->wakeup_irq = platform_get_irq_byname_optional(pdev, "wakeup");
  217. if (ssusb->wakeup_irq == -EPROBE_DEFER)
  218. return ssusb->wakeup_irq;
  219. ssusb->dr_mode = usb_get_dr_mode(dev);
  220. if (ssusb->dr_mode == USB_DR_MODE_UNKNOWN)
  221. ssusb->dr_mode = USB_DR_MODE_OTG;
  222. of_property_read_u32(node, "mediatek,u3p-dis-msk", &ssusb->u3p_dis_msk);
  223. if (ssusb->dr_mode == USB_DR_MODE_PERIPHERAL)
  224. goto out;
  225. /* if host role is supported */
  226. ret = ssusb_wakeup_of_property_parse(ssusb, node);
  227. if (ret) {
  228. dev_err(dev, "failed to parse uwk property\n");
  229. return ret;
  230. }
  231. /* optional property, ignore the error if it does not exist */
  232. of_property_read_u32(node, "mediatek,u2p-dis-msk",
  233. &ssusb->u2p_dis_msk);
  234. otg_sx->vbus = devm_regulator_get(dev, "vbus");
  235. if (IS_ERR(otg_sx->vbus)) {
  236. dev_err(dev, "failed to get vbus\n");
  237. return PTR_ERR(otg_sx->vbus);
  238. }
  239. if (ssusb->dr_mode == USB_DR_MODE_HOST)
  240. goto out;
  241. /* if dual-role mode is supported */
  242. otg_sx->manual_drd_enabled =
  243. of_property_read_bool(node, "enable-manual-drd");
  244. otg_sx->role_sw_used = of_property_read_bool(node, "usb-role-switch");
  245. /* can't disable port0 when use dual-role mode */
  246. ssusb->u2p_dis_msk &= ~0x1;
  247. if (otg_sx->role_sw_used || otg_sx->manual_drd_enabled)
  248. goto out;
  249. if (of_property_read_bool(node, "extcon")) {
  250. otg_sx->edev = extcon_get_edev_by_phandle(ssusb->dev, 0);
  251. if (IS_ERR(otg_sx->edev)) {
  252. return dev_err_probe(dev, PTR_ERR(otg_sx->edev),
  253. "couldn't get extcon device\n");
  254. }
  255. }
  256. out:
  257. dev_info(dev, "dr_mode: %d, drd: %s\n", ssusb->dr_mode,
  258. otg_sx->manual_drd_enabled ? "manual" : "auto");
  259. dev_info(dev, "u2p_dis_msk: %x, u3p_dis_msk: %x\n",
  260. ssusb->u2p_dis_msk, ssusb->u3p_dis_msk);
  261. return 0;
  262. }
  263. static int mtu3_probe(struct platform_device *pdev)
  264. {
  265. struct device_node *node = pdev->dev.of_node;
  266. struct device *dev = &pdev->dev;
  267. struct ssusb_mtk *ssusb;
  268. int ret = -ENOMEM;
  269. /* all elements are set to ZERO as default value */
  270. ssusb = devm_kzalloc(dev, sizeof(*ssusb), GFP_KERNEL);
  271. if (!ssusb)
  272. return -ENOMEM;
  273. ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
  274. if (ret) {
  275. dev_err(dev, "No suitable DMA config available\n");
  276. return -ENOTSUPP;
  277. }
  278. platform_set_drvdata(pdev, ssusb);
  279. ssusb->dev = dev;
  280. ret = get_ssusb_rscs(pdev, ssusb);
  281. if (ret)
  282. return ret;
  283. ssusb_debugfs_create_root(ssusb);
  284. /* enable power domain */
  285. pm_runtime_set_active(dev);
  286. pm_runtime_use_autosuspend(dev);
  287. pm_runtime_set_autosuspend_delay(dev, 4000);
  288. pm_runtime_enable(dev);
  289. pm_runtime_get_sync(dev);
  290. device_init_wakeup(dev, true);
  291. ret = ssusb_rscs_init(ssusb);
  292. if (ret)
  293. goto comm_init_err;
  294. if (ssusb->wakeup_irq > 0) {
  295. ret = dev_pm_set_dedicated_wake_irq_reverse(dev, ssusb->wakeup_irq);
  296. if (ret) {
  297. dev_err(dev, "failed to set wakeup irq %d\n", ssusb->wakeup_irq);
  298. goto comm_exit;
  299. }
  300. dev_info(dev, "wakeup irq %d\n", ssusb->wakeup_irq);
  301. }
  302. ret = device_reset_optional(dev);
  303. if (ret) {
  304. dev_err_probe(dev, ret, "failed to reset controller\n");
  305. goto comm_exit;
  306. }
  307. ssusb_ip_sw_reset(ssusb);
  308. ssusb_u3_drd_check(ssusb);
  309. if (IS_ENABLED(CONFIG_USB_MTU3_HOST))
  310. ssusb->dr_mode = USB_DR_MODE_HOST;
  311. else if (IS_ENABLED(CONFIG_USB_MTU3_GADGET))
  312. ssusb->dr_mode = USB_DR_MODE_PERIPHERAL;
  313. /* default as host */
  314. ssusb->is_host = !(ssusb->dr_mode == USB_DR_MODE_PERIPHERAL);
  315. switch (ssusb->dr_mode) {
  316. case USB_DR_MODE_PERIPHERAL:
  317. ret = ssusb_gadget_init(ssusb);
  318. if (ret) {
  319. dev_err(dev, "failed to initialize gadget\n");
  320. goto comm_exit;
  321. }
  322. break;
  323. case USB_DR_MODE_HOST:
  324. ret = ssusb_host_init(ssusb, node);
  325. if (ret) {
  326. dev_err(dev, "failed to initialize host\n");
  327. goto comm_exit;
  328. }
  329. break;
  330. case USB_DR_MODE_OTG:
  331. ret = ssusb_gadget_init(ssusb);
  332. if (ret) {
  333. dev_err(dev, "failed to initialize gadget\n");
  334. goto comm_exit;
  335. }
  336. ret = ssusb_host_init(ssusb, node);
  337. if (ret) {
  338. dev_err(dev, "failed to initialize host\n");
  339. goto gadget_exit;
  340. }
  341. ret = ssusb_otg_switch_init(ssusb);
  342. if (ret) {
  343. dev_err(dev, "failed to initialize switch\n");
  344. goto host_exit;
  345. }
  346. break;
  347. default:
  348. dev_err(dev, "unsupported mode: %d\n", ssusb->dr_mode);
  349. ret = -EINVAL;
  350. goto comm_exit;
  351. }
  352. device_enable_async_suspend(dev);
  353. pm_runtime_mark_last_busy(dev);
  354. pm_runtime_put_autosuspend(dev);
  355. pm_runtime_forbid(dev);
  356. return 0;
  357. host_exit:
  358. ssusb_host_exit(ssusb);
  359. gadget_exit:
  360. ssusb_gadget_exit(ssusb);
  361. comm_exit:
  362. ssusb_rscs_exit(ssusb);
  363. comm_init_err:
  364. pm_runtime_put_noidle(dev);
  365. pm_runtime_disable(dev);
  366. ssusb_debugfs_remove_root(ssusb);
  367. return ret;
  368. }
  369. static int mtu3_remove(struct platform_device *pdev)
  370. {
  371. struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);
  372. pm_runtime_get_sync(&pdev->dev);
  373. switch (ssusb->dr_mode) {
  374. case USB_DR_MODE_PERIPHERAL:
  375. ssusb_gadget_exit(ssusb);
  376. break;
  377. case USB_DR_MODE_HOST:
  378. ssusb_host_exit(ssusb);
  379. break;
  380. case USB_DR_MODE_OTG:
  381. ssusb_otg_switch_exit(ssusb);
  382. ssusb_gadget_exit(ssusb);
  383. ssusb_host_exit(ssusb);
  384. break;
  385. default:
  386. return -EINVAL;
  387. }
  388. ssusb_rscs_exit(ssusb);
  389. ssusb_debugfs_remove_root(ssusb);
  390. pm_runtime_disable(&pdev->dev);
  391. pm_runtime_put_noidle(&pdev->dev);
  392. pm_runtime_set_suspended(&pdev->dev);
  393. return 0;
  394. }
  395. static int resume_ip_and_ports(struct ssusb_mtk *ssusb, pm_message_t msg)
  396. {
  397. switch (ssusb->dr_mode) {
  398. case USB_DR_MODE_PERIPHERAL:
  399. ssusb_gadget_resume(ssusb, msg);
  400. break;
  401. case USB_DR_MODE_HOST:
  402. ssusb_host_resume(ssusb, false);
  403. break;
  404. case USB_DR_MODE_OTG:
  405. ssusb_host_resume(ssusb, !ssusb->is_host);
  406. if (!ssusb->is_host)
  407. ssusb_gadget_resume(ssusb, msg);
  408. break;
  409. default:
  410. return -EINVAL;
  411. }
  412. return 0;
  413. }
  414. static int mtu3_suspend_common(struct device *dev, pm_message_t msg)
  415. {
  416. struct ssusb_mtk *ssusb = dev_get_drvdata(dev);
  417. int ret = 0;
  418. dev_dbg(dev, "%s\n", __func__);
  419. switch (ssusb->dr_mode) {
  420. case USB_DR_MODE_PERIPHERAL:
  421. ret = ssusb_gadget_suspend(ssusb, msg);
  422. if (ret)
  423. goto err;
  424. break;
  425. case USB_DR_MODE_HOST:
  426. ssusb_host_suspend(ssusb);
  427. break;
  428. case USB_DR_MODE_OTG:
  429. if (!ssusb->is_host) {
  430. ret = ssusb_gadget_suspend(ssusb, msg);
  431. if (ret)
  432. goto err;
  433. }
  434. ssusb_host_suspend(ssusb);
  435. break;
  436. default:
  437. return -EINVAL;
  438. }
  439. ret = wait_for_ip_sleep(ssusb);
  440. if (ret)
  441. goto sleep_err;
  442. ssusb_phy_power_off(ssusb);
  443. clk_bulk_disable_unprepare(BULK_CLKS_CNT, ssusb->clks);
  444. ssusb_wakeup_set(ssusb, true);
  445. return 0;
  446. sleep_err:
  447. resume_ip_and_ports(ssusb, msg);
  448. err:
  449. return ret;
  450. }
  451. static int mtu3_resume_common(struct device *dev, pm_message_t msg)
  452. {
  453. struct ssusb_mtk *ssusb = dev_get_drvdata(dev);
  454. int ret;
  455. dev_dbg(dev, "%s\n", __func__);
  456. ssusb_wakeup_set(ssusb, false);
  457. ret = clk_bulk_prepare_enable(BULK_CLKS_CNT, ssusb->clks);
  458. if (ret)
  459. goto clks_err;
  460. ret = ssusb_phy_power_on(ssusb);
  461. if (ret)
  462. goto phy_err;
  463. return resume_ip_and_ports(ssusb, msg);
  464. phy_err:
  465. clk_bulk_disable_unprepare(BULK_CLKS_CNT, ssusb->clks);
  466. clks_err:
  467. return ret;
  468. }
  469. static int __maybe_unused mtu3_suspend(struct device *dev)
  470. {
  471. return mtu3_suspend_common(dev, PMSG_SUSPEND);
  472. }
  473. static int __maybe_unused mtu3_resume(struct device *dev)
  474. {
  475. return mtu3_resume_common(dev, PMSG_SUSPEND);
  476. }
  477. static int __maybe_unused mtu3_runtime_suspend(struct device *dev)
  478. {
  479. if (!device_may_wakeup(dev))
  480. return 0;
  481. return mtu3_suspend_common(dev, PMSG_AUTO_SUSPEND);
  482. }
  483. static int __maybe_unused mtu3_runtime_resume(struct device *dev)
  484. {
  485. if (!device_may_wakeup(dev))
  486. return 0;
  487. return mtu3_resume_common(dev, PMSG_AUTO_SUSPEND);
  488. }
  489. static const struct dev_pm_ops mtu3_pm_ops = {
  490. SET_SYSTEM_SLEEP_PM_OPS(mtu3_suspend, mtu3_resume)
  491. SET_RUNTIME_PM_OPS(mtu3_runtime_suspend,
  492. mtu3_runtime_resume, NULL)
  493. };
  494. #define DEV_PM_OPS (IS_ENABLED(CONFIG_PM) ? &mtu3_pm_ops : NULL)
  495. static const struct of_device_id mtu3_of_match[] = {
  496. {.compatible = "mediatek,mt8173-mtu3",},
  497. {.compatible = "mediatek,mtu3",},
  498. {},
  499. };
  500. MODULE_DEVICE_TABLE(of, mtu3_of_match);
  501. static struct platform_driver mtu3_driver = {
  502. .probe = mtu3_probe,
  503. .remove = mtu3_remove,
  504. .driver = {
  505. .name = MTU3_DRIVER_NAME,
  506. .pm = DEV_PM_OPS,
  507. .of_match_table = mtu3_of_match,
  508. },
  509. };
  510. module_platform_driver(mtu3_driver);
  511. MODULE_AUTHOR("Chunfeng Yun <[email protected]>");
  512. MODULE_LICENSE("GPL v2");
  513. MODULE_DESCRIPTION("MediaTek USB3 DRD Controller Driver");