s3c2410_udc.c 46 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * linux/drivers/usb/gadget/s3c2410_udc.c
  4. *
  5. * Samsung S3C24xx series on-chip full speed USB device controllers
  6. *
  7. * Copyright (C) 2004-2007 Herbert Pötzl - Arnaud Patard
  8. * Additional cleanups by Ben Dooks <[email protected]>
  9. */
  10. #define pr_fmt(fmt) "s3c2410_udc: " fmt
  11. #include <linux/module.h>
  12. #include <linux/kernel.h>
  13. #include <linux/delay.h>
  14. #include <linux/ioport.h>
  15. #include <linux/sched.h>
  16. #include <linux/slab.h>
  17. #include <linux/errno.h>
  18. #include <linux/init.h>
  19. #include <linux/timer.h>
  20. #include <linux/list.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/clk.h>
  24. #include <linux/gpio/consumer.h>
  25. #include <linux/prefetch.h>
  26. #include <linux/io.h>
  27. #include <linux/debugfs.h>
  28. #include <linux/seq_file.h>
  29. #include <linux/usb.h>
  30. #include <linux/usb/gadget.h>
  31. #include <asm/byteorder.h>
  32. #include <asm/irq.h>
  33. #include <asm/unaligned.h>
  34. #include <linux/platform_data/usb-s3c2410_udc.h>
  35. #include "s3c2410_udc.h"
  36. #include "s3c2410_udc_regs.h"
  37. #define DRIVER_DESC "S3C2410 USB Device Controller Gadget"
  38. #define DRIVER_AUTHOR "Herbert Pötzl <[email protected]>, " \
  39. "Arnaud Patard <[email protected]>"
  40. static const char gadget_name[] = "s3c2410_udc";
  41. static const char driver_desc[] = DRIVER_DESC;
  42. static struct s3c2410_udc *the_controller;
  43. static struct clk *udc_clock;
  44. static struct clk *usb_bus_clock;
  45. static void __iomem *base_addr;
  46. static int irq_usbd;
  47. static struct dentry *s3c2410_udc_debugfs_root;
  48. static inline u32 udc_read(u32 reg)
  49. {
  50. return readb(base_addr + reg);
  51. }
  52. static inline void udc_write(u32 value, u32 reg)
  53. {
  54. writeb(value, base_addr + reg);
  55. }
  56. static inline void udc_writeb(void __iomem *base, u32 value, u32 reg)
  57. {
  58. writeb(value, base + reg);
  59. }
  60. static struct s3c2410_udc_mach_info *udc_info;
  61. /*************************** DEBUG FUNCTION ***************************/
  62. #define DEBUG_NORMAL 1
  63. #define DEBUG_VERBOSE 2
  64. #ifdef CONFIG_USB_S3C2410_DEBUG
  65. #define USB_S3C2410_DEBUG_LEVEL 0
  66. static uint32_t s3c2410_ticks = 0;
  67. __printf(2, 3)
  68. static void dprintk(int level, const char *fmt, ...)
  69. {
  70. static long prevticks;
  71. static int invocation;
  72. struct va_format vaf;
  73. va_list args;
  74. if (level > USB_S3C2410_DEBUG_LEVEL)
  75. return;
  76. va_start(args, fmt);
  77. vaf.fmt = fmt;
  78. vaf.va = &args;
  79. if (s3c2410_ticks != prevticks) {
  80. prevticks = s3c2410_ticks;
  81. invocation = 0;
  82. }
  83. pr_debug("%1lu.%02d USB: %pV", prevticks, invocation++, &vaf);
  84. va_end(args);
  85. }
  86. #else
  87. __printf(2, 3)
  88. static void dprintk(int level, const char *fmt, ...)
  89. {
  90. }
  91. #endif
  92. static int s3c2410_udc_debugfs_show(struct seq_file *m, void *p)
  93. {
  94. u32 addr_reg, pwr_reg, ep_int_reg, usb_int_reg;
  95. u32 ep_int_en_reg, usb_int_en_reg, ep0_csr;
  96. u32 ep1_i_csr1, ep1_i_csr2, ep1_o_csr1, ep1_o_csr2;
  97. u32 ep2_i_csr1, ep2_i_csr2, ep2_o_csr1, ep2_o_csr2;
  98. addr_reg = udc_read(S3C2410_UDC_FUNC_ADDR_REG);
  99. pwr_reg = udc_read(S3C2410_UDC_PWR_REG);
  100. ep_int_reg = udc_read(S3C2410_UDC_EP_INT_REG);
  101. usb_int_reg = udc_read(S3C2410_UDC_USB_INT_REG);
  102. ep_int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
  103. usb_int_en_reg = udc_read(S3C2410_UDC_USB_INT_EN_REG);
  104. udc_write(0, S3C2410_UDC_INDEX_REG);
  105. ep0_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  106. udc_write(1, S3C2410_UDC_INDEX_REG);
  107. ep1_i_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  108. ep1_i_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  109. ep1_o_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  110. ep1_o_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  111. udc_write(2, S3C2410_UDC_INDEX_REG);
  112. ep2_i_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  113. ep2_i_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  114. ep2_o_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  115. ep2_o_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  116. seq_printf(m, "FUNC_ADDR_REG : 0x%04X\n"
  117. "PWR_REG : 0x%04X\n"
  118. "EP_INT_REG : 0x%04X\n"
  119. "USB_INT_REG : 0x%04X\n"
  120. "EP_INT_EN_REG : 0x%04X\n"
  121. "USB_INT_EN_REG : 0x%04X\n"
  122. "EP0_CSR : 0x%04X\n"
  123. "EP1_I_CSR1 : 0x%04X\n"
  124. "EP1_I_CSR2 : 0x%04X\n"
  125. "EP1_O_CSR1 : 0x%04X\n"
  126. "EP1_O_CSR2 : 0x%04X\n"
  127. "EP2_I_CSR1 : 0x%04X\n"
  128. "EP2_I_CSR2 : 0x%04X\n"
  129. "EP2_O_CSR1 : 0x%04X\n"
  130. "EP2_O_CSR2 : 0x%04X\n",
  131. addr_reg, pwr_reg, ep_int_reg, usb_int_reg,
  132. ep_int_en_reg, usb_int_en_reg, ep0_csr,
  133. ep1_i_csr1, ep1_i_csr2, ep1_o_csr1, ep1_o_csr2,
  134. ep2_i_csr1, ep2_i_csr2, ep2_o_csr1, ep2_o_csr2
  135. );
  136. return 0;
  137. }
  138. DEFINE_SHOW_ATTRIBUTE(s3c2410_udc_debugfs);
  139. /* io macros */
  140. static inline void s3c2410_udc_clear_ep0_opr(void __iomem *base)
  141. {
  142. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  143. udc_writeb(base, S3C2410_UDC_EP0_CSR_SOPKTRDY,
  144. S3C2410_UDC_EP0_CSR_REG);
  145. }
  146. static inline void s3c2410_udc_clear_ep0_sst(void __iomem *base)
  147. {
  148. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  149. writeb(0x00, base + S3C2410_UDC_EP0_CSR_REG);
  150. }
  151. static inline void s3c2410_udc_clear_ep0_se(void __iomem *base)
  152. {
  153. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  154. udc_writeb(base, S3C2410_UDC_EP0_CSR_SSE, S3C2410_UDC_EP0_CSR_REG);
  155. }
  156. static inline void s3c2410_udc_set_ep0_ipr(void __iomem *base)
  157. {
  158. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  159. udc_writeb(base, S3C2410_UDC_EP0_CSR_IPKRDY, S3C2410_UDC_EP0_CSR_REG);
  160. }
  161. static inline void s3c2410_udc_set_ep0_de(void __iomem *base)
  162. {
  163. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  164. udc_writeb(base, S3C2410_UDC_EP0_CSR_DE, S3C2410_UDC_EP0_CSR_REG);
  165. }
  166. static inline void s3c2410_udc_set_ep0_ss(void __iomem *b)
  167. {
  168. udc_writeb(b, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  169. udc_writeb(b, S3C2410_UDC_EP0_CSR_SENDSTL, S3C2410_UDC_EP0_CSR_REG);
  170. }
  171. static inline void s3c2410_udc_set_ep0_de_out(void __iomem *base)
  172. {
  173. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  174. udc_writeb(base, (S3C2410_UDC_EP0_CSR_SOPKTRDY
  175. | S3C2410_UDC_EP0_CSR_DE),
  176. S3C2410_UDC_EP0_CSR_REG);
  177. }
  178. static inline void s3c2410_udc_set_ep0_de_in(void __iomem *base)
  179. {
  180. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  181. udc_writeb(base, (S3C2410_UDC_EP0_CSR_IPKRDY
  182. | S3C2410_UDC_EP0_CSR_DE),
  183. S3C2410_UDC_EP0_CSR_REG);
  184. }
  185. /*------------------------- I/O ----------------------------------*/
  186. /*
  187. * s3c2410_udc_done
  188. */
  189. static void s3c2410_udc_done(struct s3c2410_ep *ep,
  190. struct s3c2410_request *req, int status)
  191. {
  192. unsigned halted = ep->halted;
  193. list_del_init(&req->queue);
  194. if (likely(req->req.status == -EINPROGRESS))
  195. req->req.status = status;
  196. else
  197. status = req->req.status;
  198. ep->halted = 1;
  199. usb_gadget_giveback_request(&ep->ep, &req->req);
  200. ep->halted = halted;
  201. }
  202. static void s3c2410_udc_nuke(struct s3c2410_udc *udc,
  203. struct s3c2410_ep *ep, int status)
  204. {
  205. while (!list_empty(&ep->queue)) {
  206. struct s3c2410_request *req;
  207. req = list_entry(ep->queue.next, struct s3c2410_request,
  208. queue);
  209. s3c2410_udc_done(ep, req, status);
  210. }
  211. }
  212. static inline int s3c2410_udc_fifo_count_out(void)
  213. {
  214. int tmp;
  215. tmp = udc_read(S3C2410_UDC_OUT_FIFO_CNT2_REG) << 8;
  216. tmp |= udc_read(S3C2410_UDC_OUT_FIFO_CNT1_REG);
  217. return tmp;
  218. }
  219. /*
  220. * s3c2410_udc_write_packet
  221. */
  222. static inline int s3c2410_udc_write_packet(int fifo,
  223. struct s3c2410_request *req,
  224. unsigned max)
  225. {
  226. unsigned len = min(req->req.length - req->req.actual, max);
  227. u8 *buf = req->req.buf + req->req.actual;
  228. prefetch(buf);
  229. dprintk(DEBUG_VERBOSE, "%s %d %d %d %d\n", __func__,
  230. req->req.actual, req->req.length, len, req->req.actual + len);
  231. req->req.actual += len;
  232. udelay(5);
  233. writesb(base_addr + fifo, buf, len);
  234. return len;
  235. }
  236. /*
  237. * s3c2410_udc_write_fifo
  238. *
  239. * return: 0 = still running, 1 = completed, negative = errno
  240. */
  241. static int s3c2410_udc_write_fifo(struct s3c2410_ep *ep,
  242. struct s3c2410_request *req)
  243. {
  244. unsigned count;
  245. int is_last;
  246. u32 idx;
  247. int fifo_reg;
  248. u32 ep_csr;
  249. idx = ep->bEndpointAddress & 0x7F;
  250. switch (idx) {
  251. default:
  252. idx = 0;
  253. fallthrough;
  254. case 0:
  255. fifo_reg = S3C2410_UDC_EP0_FIFO_REG;
  256. break;
  257. case 1:
  258. fifo_reg = S3C2410_UDC_EP1_FIFO_REG;
  259. break;
  260. case 2:
  261. fifo_reg = S3C2410_UDC_EP2_FIFO_REG;
  262. break;
  263. case 3:
  264. fifo_reg = S3C2410_UDC_EP3_FIFO_REG;
  265. break;
  266. case 4:
  267. fifo_reg = S3C2410_UDC_EP4_FIFO_REG;
  268. break;
  269. }
  270. count = s3c2410_udc_write_packet(fifo_reg, req, ep->ep.maxpacket);
  271. /* last packet is often short (sometimes a zlp) */
  272. if (count != ep->ep.maxpacket)
  273. is_last = 1;
  274. else if (req->req.length != req->req.actual || req->req.zero)
  275. is_last = 0;
  276. else
  277. is_last = 2;
  278. /* Only ep0 debug messages are interesting */
  279. if (idx == 0)
  280. dprintk(DEBUG_NORMAL,
  281. "Written ep%d %d.%d of %d b [last %d,z %d]\n",
  282. idx, count, req->req.actual, req->req.length,
  283. is_last, req->req.zero);
  284. if (is_last) {
  285. /* The order is important. It prevents sending 2 packets
  286. * at the same time */
  287. if (idx == 0) {
  288. /* Reset signal => no need to say 'data sent' */
  289. if (!(udc_read(S3C2410_UDC_USB_INT_REG)
  290. & S3C2410_UDC_USBINT_RESET))
  291. s3c2410_udc_set_ep0_de_in(base_addr);
  292. ep->dev->ep0state = EP0_IDLE;
  293. } else {
  294. udc_write(idx, S3C2410_UDC_INDEX_REG);
  295. ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  296. udc_write(idx, S3C2410_UDC_INDEX_REG);
  297. udc_write(ep_csr | S3C2410_UDC_ICSR1_PKTRDY,
  298. S3C2410_UDC_IN_CSR1_REG);
  299. }
  300. s3c2410_udc_done(ep, req, 0);
  301. is_last = 1;
  302. } else {
  303. if (idx == 0) {
  304. /* Reset signal => no need to say 'data sent' */
  305. if (!(udc_read(S3C2410_UDC_USB_INT_REG)
  306. & S3C2410_UDC_USBINT_RESET))
  307. s3c2410_udc_set_ep0_ipr(base_addr);
  308. } else {
  309. udc_write(idx, S3C2410_UDC_INDEX_REG);
  310. ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  311. udc_write(idx, S3C2410_UDC_INDEX_REG);
  312. udc_write(ep_csr | S3C2410_UDC_ICSR1_PKTRDY,
  313. S3C2410_UDC_IN_CSR1_REG);
  314. }
  315. }
  316. return is_last;
  317. }
  318. static inline int s3c2410_udc_read_packet(int fifo, u8 *buf,
  319. struct s3c2410_request *req, unsigned avail)
  320. {
  321. unsigned len;
  322. len = min(req->req.length - req->req.actual, avail);
  323. req->req.actual += len;
  324. readsb(fifo + base_addr, buf, len);
  325. return len;
  326. }
  327. /*
  328. * return: 0 = still running, 1 = queue empty, negative = errno
  329. */
  330. static int s3c2410_udc_read_fifo(struct s3c2410_ep *ep,
  331. struct s3c2410_request *req)
  332. {
  333. u8 *buf;
  334. u32 ep_csr;
  335. unsigned bufferspace;
  336. int is_last = 1;
  337. unsigned avail;
  338. int fifo_count = 0;
  339. u32 idx;
  340. int fifo_reg;
  341. idx = ep->bEndpointAddress & 0x7F;
  342. switch (idx) {
  343. default:
  344. idx = 0;
  345. fallthrough;
  346. case 0:
  347. fifo_reg = S3C2410_UDC_EP0_FIFO_REG;
  348. break;
  349. case 1:
  350. fifo_reg = S3C2410_UDC_EP1_FIFO_REG;
  351. break;
  352. case 2:
  353. fifo_reg = S3C2410_UDC_EP2_FIFO_REG;
  354. break;
  355. case 3:
  356. fifo_reg = S3C2410_UDC_EP3_FIFO_REG;
  357. break;
  358. case 4:
  359. fifo_reg = S3C2410_UDC_EP4_FIFO_REG;
  360. break;
  361. }
  362. if (!req->req.length)
  363. return 1;
  364. buf = req->req.buf + req->req.actual;
  365. bufferspace = req->req.length - req->req.actual;
  366. if (!bufferspace) {
  367. dprintk(DEBUG_NORMAL, "%s: buffer full!\n", __func__);
  368. return -1;
  369. }
  370. udc_write(idx, S3C2410_UDC_INDEX_REG);
  371. fifo_count = s3c2410_udc_fifo_count_out();
  372. dprintk(DEBUG_NORMAL, "%s fifo count : %d\n", __func__, fifo_count);
  373. if (fifo_count > ep->ep.maxpacket)
  374. avail = ep->ep.maxpacket;
  375. else
  376. avail = fifo_count;
  377. fifo_count = s3c2410_udc_read_packet(fifo_reg, buf, req, avail);
  378. /* checking this with ep0 is not accurate as we already
  379. * read a control request
  380. **/
  381. if (idx != 0 && fifo_count < ep->ep.maxpacket) {
  382. is_last = 1;
  383. /* overflowed this request? flush extra data */
  384. if (fifo_count != avail)
  385. req->req.status = -EOVERFLOW;
  386. } else {
  387. is_last = (req->req.length <= req->req.actual) ? 1 : 0;
  388. }
  389. udc_write(idx, S3C2410_UDC_INDEX_REG);
  390. fifo_count = s3c2410_udc_fifo_count_out();
  391. /* Only ep0 debug messages are interesting */
  392. if (idx == 0)
  393. dprintk(DEBUG_VERBOSE, "%s fifo count : %d [last %d]\n",
  394. __func__, fifo_count, is_last);
  395. if (is_last) {
  396. if (idx == 0) {
  397. s3c2410_udc_set_ep0_de_out(base_addr);
  398. ep->dev->ep0state = EP0_IDLE;
  399. } else {
  400. udc_write(idx, S3C2410_UDC_INDEX_REG);
  401. ep_csr = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  402. udc_write(idx, S3C2410_UDC_INDEX_REG);
  403. udc_write(ep_csr & ~S3C2410_UDC_OCSR1_PKTRDY,
  404. S3C2410_UDC_OUT_CSR1_REG);
  405. }
  406. s3c2410_udc_done(ep, req, 0);
  407. } else {
  408. if (idx == 0) {
  409. s3c2410_udc_clear_ep0_opr(base_addr);
  410. } else {
  411. udc_write(idx, S3C2410_UDC_INDEX_REG);
  412. ep_csr = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  413. udc_write(idx, S3C2410_UDC_INDEX_REG);
  414. udc_write(ep_csr & ~S3C2410_UDC_OCSR1_PKTRDY,
  415. S3C2410_UDC_OUT_CSR1_REG);
  416. }
  417. }
  418. return is_last;
  419. }
  420. static int s3c2410_udc_read_fifo_crq(struct usb_ctrlrequest *crq)
  421. {
  422. unsigned char *outbuf = (unsigned char *)crq;
  423. int bytes_read = 0;
  424. udc_write(0, S3C2410_UDC_INDEX_REG);
  425. bytes_read = s3c2410_udc_fifo_count_out();
  426. dprintk(DEBUG_NORMAL, "%s: fifo_count=%d\n", __func__, bytes_read);
  427. if (bytes_read > sizeof(struct usb_ctrlrequest))
  428. bytes_read = sizeof(struct usb_ctrlrequest);
  429. readsb(S3C2410_UDC_EP0_FIFO_REG + base_addr, outbuf, bytes_read);
  430. dprintk(DEBUG_VERBOSE, "%s: len=%d %02x:%02x {%x,%x,%x}\n", __func__,
  431. bytes_read, crq->bRequest, crq->bRequestType,
  432. crq->wValue, crq->wIndex, crq->wLength);
  433. return bytes_read;
  434. }
  435. static int s3c2410_udc_get_status(struct s3c2410_udc *dev,
  436. struct usb_ctrlrequest *crq)
  437. {
  438. u16 status = 0;
  439. u8 ep_num = crq->wIndex & 0x7F;
  440. u8 is_in = crq->wIndex & USB_DIR_IN;
  441. switch (crq->bRequestType & USB_RECIP_MASK) {
  442. case USB_RECIP_INTERFACE:
  443. break;
  444. case USB_RECIP_DEVICE:
  445. status = dev->devstatus;
  446. break;
  447. case USB_RECIP_ENDPOINT:
  448. if (ep_num > 4 || crq->wLength > 2)
  449. return 1;
  450. if (ep_num == 0) {
  451. udc_write(0, S3C2410_UDC_INDEX_REG);
  452. status = udc_read(S3C2410_UDC_IN_CSR1_REG);
  453. status = status & S3C2410_UDC_EP0_CSR_SENDSTL;
  454. } else {
  455. udc_write(ep_num, S3C2410_UDC_INDEX_REG);
  456. if (is_in) {
  457. status = udc_read(S3C2410_UDC_IN_CSR1_REG);
  458. status = status & S3C2410_UDC_ICSR1_SENDSTL;
  459. } else {
  460. status = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  461. status = status & S3C2410_UDC_OCSR1_SENDSTL;
  462. }
  463. }
  464. status = status ? 1 : 0;
  465. break;
  466. default:
  467. return 1;
  468. }
  469. /* Seems to be needed to get it working. ouch :( */
  470. udelay(5);
  471. udc_write(status & 0xFF, S3C2410_UDC_EP0_FIFO_REG);
  472. udc_write(status >> 8, S3C2410_UDC_EP0_FIFO_REG);
  473. s3c2410_udc_set_ep0_de_in(base_addr);
  474. return 0;
  475. }
  476. /*------------------------- usb state machine -------------------------------*/
  477. static int s3c2410_udc_set_halt(struct usb_ep *_ep, int value);
  478. static void s3c2410_udc_handle_ep0_idle(struct s3c2410_udc *dev,
  479. struct s3c2410_ep *ep,
  480. struct usb_ctrlrequest *crq,
  481. u32 ep0csr)
  482. {
  483. int len, ret, tmp;
  484. /* start control request? */
  485. if (!(ep0csr & S3C2410_UDC_EP0_CSR_OPKRDY))
  486. return;
  487. s3c2410_udc_nuke(dev, ep, -EPROTO);
  488. len = s3c2410_udc_read_fifo_crq(crq);
  489. if (len != sizeof(*crq)) {
  490. dprintk(DEBUG_NORMAL, "setup begin: fifo READ ERROR"
  491. " wanted %d bytes got %d. Stalling out...\n",
  492. sizeof(*crq), len);
  493. s3c2410_udc_set_ep0_ss(base_addr);
  494. return;
  495. }
  496. dprintk(DEBUG_NORMAL, "bRequest = %d bRequestType %d wLength = %d\n",
  497. crq->bRequest, crq->bRequestType, crq->wLength);
  498. /* cope with automagic for some standard requests. */
  499. dev->req_std = (crq->bRequestType & USB_TYPE_MASK)
  500. == USB_TYPE_STANDARD;
  501. dev->req_config = 0;
  502. dev->req_pending = 1;
  503. switch (crq->bRequest) {
  504. case USB_REQ_SET_CONFIGURATION:
  505. dprintk(DEBUG_NORMAL, "USB_REQ_SET_CONFIGURATION ...\n");
  506. if (crq->bRequestType == USB_RECIP_DEVICE) {
  507. dev->req_config = 1;
  508. s3c2410_udc_set_ep0_de_out(base_addr);
  509. }
  510. break;
  511. case USB_REQ_SET_INTERFACE:
  512. dprintk(DEBUG_NORMAL, "USB_REQ_SET_INTERFACE ...\n");
  513. if (crq->bRequestType == USB_RECIP_INTERFACE) {
  514. dev->req_config = 1;
  515. s3c2410_udc_set_ep0_de_out(base_addr);
  516. }
  517. break;
  518. case USB_REQ_SET_ADDRESS:
  519. dprintk(DEBUG_NORMAL, "USB_REQ_SET_ADDRESS ...\n");
  520. if (crq->bRequestType == USB_RECIP_DEVICE) {
  521. tmp = crq->wValue & 0x7F;
  522. dev->address = tmp;
  523. udc_write((tmp | S3C2410_UDC_FUNCADDR_UPDATE),
  524. S3C2410_UDC_FUNC_ADDR_REG);
  525. s3c2410_udc_set_ep0_de_out(base_addr);
  526. return;
  527. }
  528. break;
  529. case USB_REQ_GET_STATUS:
  530. dprintk(DEBUG_NORMAL, "USB_REQ_GET_STATUS ...\n");
  531. s3c2410_udc_clear_ep0_opr(base_addr);
  532. if (dev->req_std) {
  533. if (!s3c2410_udc_get_status(dev, crq))
  534. return;
  535. }
  536. break;
  537. case USB_REQ_CLEAR_FEATURE:
  538. s3c2410_udc_clear_ep0_opr(base_addr);
  539. if (crq->bRequestType != USB_RECIP_ENDPOINT)
  540. break;
  541. if (crq->wValue != USB_ENDPOINT_HALT || crq->wLength != 0)
  542. break;
  543. s3c2410_udc_set_halt(&dev->ep[crq->wIndex & 0x7f].ep, 0);
  544. s3c2410_udc_set_ep0_de_out(base_addr);
  545. return;
  546. case USB_REQ_SET_FEATURE:
  547. s3c2410_udc_clear_ep0_opr(base_addr);
  548. if (crq->bRequestType != USB_RECIP_ENDPOINT)
  549. break;
  550. if (crq->wValue != USB_ENDPOINT_HALT || crq->wLength != 0)
  551. break;
  552. s3c2410_udc_set_halt(&dev->ep[crq->wIndex & 0x7f].ep, 1);
  553. s3c2410_udc_set_ep0_de_out(base_addr);
  554. return;
  555. default:
  556. s3c2410_udc_clear_ep0_opr(base_addr);
  557. break;
  558. }
  559. if (crq->bRequestType & USB_DIR_IN)
  560. dev->ep0state = EP0_IN_DATA_PHASE;
  561. else
  562. dev->ep0state = EP0_OUT_DATA_PHASE;
  563. if (!dev->driver)
  564. return;
  565. /* deliver the request to the gadget driver */
  566. ret = dev->driver->setup(&dev->gadget, crq);
  567. if (ret < 0) {
  568. if (dev->req_config) {
  569. dprintk(DEBUG_NORMAL, "config change %02x fail %d?\n",
  570. crq->bRequest, ret);
  571. return;
  572. }
  573. if (ret == -EOPNOTSUPP)
  574. dprintk(DEBUG_NORMAL, "Operation not supported\n");
  575. else
  576. dprintk(DEBUG_NORMAL,
  577. "dev->driver->setup failed. (%d)\n", ret);
  578. udelay(5);
  579. s3c2410_udc_set_ep0_ss(base_addr);
  580. s3c2410_udc_set_ep0_de_out(base_addr);
  581. dev->ep0state = EP0_IDLE;
  582. /* deferred i/o == no response yet */
  583. } else if (dev->req_pending) {
  584. dprintk(DEBUG_VERBOSE, "dev->req_pending... what now?\n");
  585. dev->req_pending = 0;
  586. }
  587. dprintk(DEBUG_VERBOSE, "ep0state %s\n", ep0states[dev->ep0state]);
  588. }
  589. static void s3c2410_udc_handle_ep0(struct s3c2410_udc *dev)
  590. {
  591. u32 ep0csr;
  592. struct s3c2410_ep *ep = &dev->ep[0];
  593. struct s3c2410_request *req;
  594. struct usb_ctrlrequest crq;
  595. if (list_empty(&ep->queue))
  596. req = NULL;
  597. else
  598. req = list_entry(ep->queue.next, struct s3c2410_request, queue);
  599. /* We make the assumption that S3C2410_UDC_IN_CSR1_REG equal to
  600. * S3C2410_UDC_EP0_CSR_REG when index is zero */
  601. udc_write(0, S3C2410_UDC_INDEX_REG);
  602. ep0csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  603. dprintk(DEBUG_NORMAL, "ep0csr %x ep0state %s\n",
  604. ep0csr, ep0states[dev->ep0state]);
  605. /* clear stall status */
  606. if (ep0csr & S3C2410_UDC_EP0_CSR_SENTSTL) {
  607. s3c2410_udc_nuke(dev, ep, -EPIPE);
  608. dprintk(DEBUG_NORMAL, "... clear SENT_STALL ...\n");
  609. s3c2410_udc_clear_ep0_sst(base_addr);
  610. dev->ep0state = EP0_IDLE;
  611. return;
  612. }
  613. /* clear setup end */
  614. if (ep0csr & S3C2410_UDC_EP0_CSR_SE) {
  615. dprintk(DEBUG_NORMAL, "... serviced SETUP_END ...\n");
  616. s3c2410_udc_nuke(dev, ep, 0);
  617. s3c2410_udc_clear_ep0_se(base_addr);
  618. dev->ep0state = EP0_IDLE;
  619. }
  620. switch (dev->ep0state) {
  621. case EP0_IDLE:
  622. s3c2410_udc_handle_ep0_idle(dev, ep, &crq, ep0csr);
  623. break;
  624. case EP0_IN_DATA_PHASE: /* GET_DESCRIPTOR etc */
  625. dprintk(DEBUG_NORMAL, "EP0_IN_DATA_PHASE ... what now?\n");
  626. if (!(ep0csr & S3C2410_UDC_EP0_CSR_IPKRDY) && req)
  627. s3c2410_udc_write_fifo(ep, req);
  628. break;
  629. case EP0_OUT_DATA_PHASE: /* SET_DESCRIPTOR etc */
  630. dprintk(DEBUG_NORMAL, "EP0_OUT_DATA_PHASE ... what now?\n");
  631. if ((ep0csr & S3C2410_UDC_EP0_CSR_OPKRDY) && req)
  632. s3c2410_udc_read_fifo(ep, req);
  633. break;
  634. case EP0_END_XFER:
  635. dprintk(DEBUG_NORMAL, "EP0_END_XFER ... what now?\n");
  636. dev->ep0state = EP0_IDLE;
  637. break;
  638. case EP0_STALL:
  639. dprintk(DEBUG_NORMAL, "EP0_STALL ... what now?\n");
  640. dev->ep0state = EP0_IDLE;
  641. break;
  642. }
  643. }
  644. /*
  645. * handle_ep - Manage I/O endpoints
  646. */
  647. static void s3c2410_udc_handle_ep(struct s3c2410_ep *ep)
  648. {
  649. struct s3c2410_request *req;
  650. int is_in = ep->bEndpointAddress & USB_DIR_IN;
  651. u32 ep_csr1;
  652. u32 idx;
  653. if (likely(!list_empty(&ep->queue)))
  654. req = list_entry(ep->queue.next,
  655. struct s3c2410_request, queue);
  656. else
  657. req = NULL;
  658. idx = ep->bEndpointAddress & 0x7F;
  659. if (is_in) {
  660. udc_write(idx, S3C2410_UDC_INDEX_REG);
  661. ep_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  662. dprintk(DEBUG_VERBOSE, "ep%01d write csr:%02x %d\n",
  663. idx, ep_csr1, req ? 1 : 0);
  664. if (ep_csr1 & S3C2410_UDC_ICSR1_SENTSTL) {
  665. dprintk(DEBUG_VERBOSE, "st\n");
  666. udc_write(idx, S3C2410_UDC_INDEX_REG);
  667. udc_write(ep_csr1 & ~S3C2410_UDC_ICSR1_SENTSTL,
  668. S3C2410_UDC_IN_CSR1_REG);
  669. return;
  670. }
  671. if (!(ep_csr1 & S3C2410_UDC_ICSR1_PKTRDY) && req)
  672. s3c2410_udc_write_fifo(ep, req);
  673. } else {
  674. udc_write(idx, S3C2410_UDC_INDEX_REG);
  675. ep_csr1 = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  676. dprintk(DEBUG_VERBOSE, "ep%01d rd csr:%02x\n", idx, ep_csr1);
  677. if (ep_csr1 & S3C2410_UDC_OCSR1_SENTSTL) {
  678. udc_write(idx, S3C2410_UDC_INDEX_REG);
  679. udc_write(ep_csr1 & ~S3C2410_UDC_OCSR1_SENTSTL,
  680. S3C2410_UDC_OUT_CSR1_REG);
  681. return;
  682. }
  683. if ((ep_csr1 & S3C2410_UDC_OCSR1_PKTRDY) && req)
  684. s3c2410_udc_read_fifo(ep, req);
  685. }
  686. }
  687. /*
  688. * s3c2410_udc_irq - interrupt handler
  689. */
  690. static irqreturn_t s3c2410_udc_irq(int dummy, void *_dev)
  691. {
  692. struct s3c2410_udc *dev = _dev;
  693. int usb_status;
  694. int usbd_status;
  695. int pwr_reg;
  696. int ep0csr;
  697. int i;
  698. u32 idx, idx2;
  699. unsigned long flags;
  700. spin_lock_irqsave(&dev->lock, flags);
  701. /* Driver connected ? */
  702. if (!dev->driver) {
  703. /* Clear interrupts */
  704. udc_write(udc_read(S3C2410_UDC_USB_INT_REG),
  705. S3C2410_UDC_USB_INT_REG);
  706. udc_write(udc_read(S3C2410_UDC_EP_INT_REG),
  707. S3C2410_UDC_EP_INT_REG);
  708. }
  709. /* Save index */
  710. idx = udc_read(S3C2410_UDC_INDEX_REG);
  711. /* Read status registers */
  712. usb_status = udc_read(S3C2410_UDC_USB_INT_REG);
  713. usbd_status = udc_read(S3C2410_UDC_EP_INT_REG);
  714. pwr_reg = udc_read(S3C2410_UDC_PWR_REG);
  715. udc_writeb(base_addr, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  716. ep0csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  717. dprintk(DEBUG_NORMAL, "usbs=%02x, usbds=%02x, pwr=%02x ep0csr=%02x\n",
  718. usb_status, usbd_status, pwr_reg, ep0csr);
  719. /*
  720. * Now, handle interrupts. There's two types :
  721. * - Reset, Resume, Suspend coming -> usb_int_reg
  722. * - EP -> ep_int_reg
  723. */
  724. /* RESET */
  725. if (usb_status & S3C2410_UDC_USBINT_RESET) {
  726. /* two kind of reset :
  727. * - reset start -> pwr reg = 8
  728. * - reset end -> pwr reg = 0
  729. **/
  730. dprintk(DEBUG_NORMAL, "USB reset csr %x pwr %x\n",
  731. ep0csr, pwr_reg);
  732. dev->gadget.speed = USB_SPEED_UNKNOWN;
  733. udc_write(0x00, S3C2410_UDC_INDEX_REG);
  734. udc_write((dev->ep[0].ep.maxpacket & 0x7ff) >> 3,
  735. S3C2410_UDC_MAXP_REG);
  736. dev->address = 0;
  737. dev->ep0state = EP0_IDLE;
  738. dev->gadget.speed = USB_SPEED_FULL;
  739. /* clear interrupt */
  740. udc_write(S3C2410_UDC_USBINT_RESET,
  741. S3C2410_UDC_USB_INT_REG);
  742. udc_write(idx, S3C2410_UDC_INDEX_REG);
  743. spin_unlock_irqrestore(&dev->lock, flags);
  744. return IRQ_HANDLED;
  745. }
  746. /* RESUME */
  747. if (usb_status & S3C2410_UDC_USBINT_RESUME) {
  748. dprintk(DEBUG_NORMAL, "USB resume\n");
  749. /* clear interrupt */
  750. udc_write(S3C2410_UDC_USBINT_RESUME,
  751. S3C2410_UDC_USB_INT_REG);
  752. if (dev->gadget.speed != USB_SPEED_UNKNOWN
  753. && dev->driver
  754. && dev->driver->resume)
  755. dev->driver->resume(&dev->gadget);
  756. }
  757. /* SUSPEND */
  758. if (usb_status & S3C2410_UDC_USBINT_SUSPEND) {
  759. dprintk(DEBUG_NORMAL, "USB suspend\n");
  760. /* clear interrupt */
  761. udc_write(S3C2410_UDC_USBINT_SUSPEND,
  762. S3C2410_UDC_USB_INT_REG);
  763. if (dev->gadget.speed != USB_SPEED_UNKNOWN
  764. && dev->driver
  765. && dev->driver->suspend)
  766. dev->driver->suspend(&dev->gadget);
  767. dev->ep0state = EP0_IDLE;
  768. }
  769. /* EP */
  770. /* control traffic */
  771. /* check on ep0csr != 0 is not a good idea as clearing in_pkt_ready
  772. * generate an interrupt
  773. */
  774. if (usbd_status & S3C2410_UDC_INT_EP0) {
  775. dprintk(DEBUG_VERBOSE, "USB ep0 irq\n");
  776. /* Clear the interrupt bit by setting it to 1 */
  777. udc_write(S3C2410_UDC_INT_EP0, S3C2410_UDC_EP_INT_REG);
  778. s3c2410_udc_handle_ep0(dev);
  779. }
  780. /* endpoint data transfers */
  781. for (i = 1; i < S3C2410_ENDPOINTS; i++) {
  782. u32 tmp = 1 << i;
  783. if (usbd_status & tmp) {
  784. dprintk(DEBUG_VERBOSE, "USB ep%d irq\n", i);
  785. /* Clear the interrupt bit by setting it to 1 */
  786. udc_write(tmp, S3C2410_UDC_EP_INT_REG);
  787. s3c2410_udc_handle_ep(&dev->ep[i]);
  788. }
  789. }
  790. /* what else causes this interrupt? a receive! who is it? */
  791. if (!usb_status && !usbd_status && !pwr_reg && !ep0csr) {
  792. for (i = 1; i < S3C2410_ENDPOINTS; i++) {
  793. idx2 = udc_read(S3C2410_UDC_INDEX_REG);
  794. udc_write(i, S3C2410_UDC_INDEX_REG);
  795. if (udc_read(S3C2410_UDC_OUT_CSR1_REG) & 0x1)
  796. s3c2410_udc_handle_ep(&dev->ep[i]);
  797. /* restore index */
  798. udc_write(idx2, S3C2410_UDC_INDEX_REG);
  799. }
  800. }
  801. dprintk(DEBUG_VERBOSE, "irq: %d s3c2410_udc_done.\n", irq_usbd);
  802. /* Restore old index */
  803. udc_write(idx, S3C2410_UDC_INDEX_REG);
  804. spin_unlock_irqrestore(&dev->lock, flags);
  805. return IRQ_HANDLED;
  806. }
  807. /*------------------------- s3c2410_ep_ops ----------------------------------*/
  808. static inline struct s3c2410_ep *to_s3c2410_ep(struct usb_ep *ep)
  809. {
  810. return container_of(ep, struct s3c2410_ep, ep);
  811. }
  812. static inline struct s3c2410_udc *to_s3c2410_udc(struct usb_gadget *gadget)
  813. {
  814. return container_of(gadget, struct s3c2410_udc, gadget);
  815. }
  816. static inline struct s3c2410_request *to_s3c2410_req(struct usb_request *req)
  817. {
  818. return container_of(req, struct s3c2410_request, req);
  819. }
  820. /*
  821. * s3c2410_udc_ep_enable
  822. */
  823. static int s3c2410_udc_ep_enable(struct usb_ep *_ep,
  824. const struct usb_endpoint_descriptor *desc)
  825. {
  826. struct s3c2410_udc *dev;
  827. struct s3c2410_ep *ep;
  828. u32 max, tmp;
  829. unsigned long flags;
  830. u32 csr1, csr2;
  831. u32 int_en_reg;
  832. ep = to_s3c2410_ep(_ep);
  833. if (!_ep || !desc
  834. || _ep->name == ep0name
  835. || desc->bDescriptorType != USB_DT_ENDPOINT)
  836. return -EINVAL;
  837. dev = ep->dev;
  838. if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
  839. return -ESHUTDOWN;
  840. max = usb_endpoint_maxp(desc);
  841. local_irq_save(flags);
  842. _ep->maxpacket = max;
  843. ep->ep.desc = desc;
  844. ep->halted = 0;
  845. ep->bEndpointAddress = desc->bEndpointAddress;
  846. /* set max packet */
  847. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  848. udc_write(max >> 3, S3C2410_UDC_MAXP_REG);
  849. /* set type, direction, address; reset fifo counters */
  850. if (desc->bEndpointAddress & USB_DIR_IN) {
  851. csr1 = S3C2410_UDC_ICSR1_FFLUSH|S3C2410_UDC_ICSR1_CLRDT;
  852. csr2 = S3C2410_UDC_ICSR2_MODEIN|S3C2410_UDC_ICSR2_DMAIEN;
  853. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  854. udc_write(csr1, S3C2410_UDC_IN_CSR1_REG);
  855. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  856. udc_write(csr2, S3C2410_UDC_IN_CSR2_REG);
  857. } else {
  858. /* don't flush in fifo or it will cause endpoint interrupt */
  859. csr1 = S3C2410_UDC_ICSR1_CLRDT;
  860. csr2 = S3C2410_UDC_ICSR2_DMAIEN;
  861. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  862. udc_write(csr1, S3C2410_UDC_IN_CSR1_REG);
  863. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  864. udc_write(csr2, S3C2410_UDC_IN_CSR2_REG);
  865. csr1 = S3C2410_UDC_OCSR1_FFLUSH | S3C2410_UDC_OCSR1_CLRDT;
  866. csr2 = S3C2410_UDC_OCSR2_DMAIEN;
  867. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  868. udc_write(csr1, S3C2410_UDC_OUT_CSR1_REG);
  869. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  870. udc_write(csr2, S3C2410_UDC_OUT_CSR2_REG);
  871. }
  872. /* enable irqs */
  873. int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
  874. udc_write(int_en_reg | (1 << ep->num), S3C2410_UDC_EP_INT_EN_REG);
  875. /* print some debug message */
  876. tmp = desc->bEndpointAddress;
  877. dprintk(DEBUG_NORMAL, "enable %s(%d) ep%x%s-blk max %02x\n",
  878. _ep->name, ep->num, tmp,
  879. desc->bEndpointAddress & USB_DIR_IN ? "in" : "out", max);
  880. local_irq_restore(flags);
  881. s3c2410_udc_set_halt(_ep, 0);
  882. return 0;
  883. }
  884. /*
  885. * s3c2410_udc_ep_disable
  886. */
  887. static int s3c2410_udc_ep_disable(struct usb_ep *_ep)
  888. {
  889. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  890. unsigned long flags;
  891. u32 int_en_reg;
  892. if (!_ep || !ep->ep.desc) {
  893. dprintk(DEBUG_NORMAL, "%s not enabled\n",
  894. _ep ? ep->ep.name : NULL);
  895. return -EINVAL;
  896. }
  897. local_irq_save(flags);
  898. dprintk(DEBUG_NORMAL, "ep_disable: %s\n", _ep->name);
  899. ep->ep.desc = NULL;
  900. ep->halted = 1;
  901. s3c2410_udc_nuke(ep->dev, ep, -ESHUTDOWN);
  902. /* disable irqs */
  903. int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
  904. udc_write(int_en_reg & ~(1<<ep->num), S3C2410_UDC_EP_INT_EN_REG);
  905. local_irq_restore(flags);
  906. dprintk(DEBUG_NORMAL, "%s disabled\n", _ep->name);
  907. return 0;
  908. }
  909. /*
  910. * s3c2410_udc_alloc_request
  911. */
  912. static struct usb_request *
  913. s3c2410_udc_alloc_request(struct usb_ep *_ep, gfp_t mem_flags)
  914. {
  915. struct s3c2410_request *req;
  916. dprintk(DEBUG_VERBOSE, "%s(%p,%d)\n", __func__, _ep, mem_flags);
  917. if (!_ep)
  918. return NULL;
  919. req = kzalloc(sizeof(struct s3c2410_request), mem_flags);
  920. if (!req)
  921. return NULL;
  922. INIT_LIST_HEAD(&req->queue);
  923. return &req->req;
  924. }
  925. /*
  926. * s3c2410_udc_free_request
  927. */
  928. static void
  929. s3c2410_udc_free_request(struct usb_ep *_ep, struct usb_request *_req)
  930. {
  931. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  932. struct s3c2410_request *req = to_s3c2410_req(_req);
  933. dprintk(DEBUG_VERBOSE, "%s(%p,%p)\n", __func__, _ep, _req);
  934. if (!ep || !_req || (!ep->ep.desc && _ep->name != ep0name))
  935. return;
  936. WARN_ON(!list_empty(&req->queue));
  937. kfree(req);
  938. }
  939. /*
  940. * s3c2410_udc_queue
  941. */
  942. static int s3c2410_udc_queue(struct usb_ep *_ep, struct usb_request *_req,
  943. gfp_t gfp_flags)
  944. {
  945. struct s3c2410_request *req = to_s3c2410_req(_req);
  946. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  947. struct s3c2410_udc *dev;
  948. u32 ep_csr = 0;
  949. int fifo_count = 0;
  950. unsigned long flags;
  951. if (unlikely(!_ep || (!ep->ep.desc && ep->ep.name != ep0name))) {
  952. dprintk(DEBUG_NORMAL, "%s: invalid args\n", __func__);
  953. return -EINVAL;
  954. }
  955. dev = ep->dev;
  956. if (unlikely(!dev->driver
  957. || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
  958. return -ESHUTDOWN;
  959. }
  960. local_irq_save(flags);
  961. if (unlikely(!_req || !_req->complete
  962. || !_req->buf || !list_empty(&req->queue))) {
  963. if (!_req)
  964. dprintk(DEBUG_NORMAL, "%s: 1 X X X\n", __func__);
  965. else {
  966. dprintk(DEBUG_NORMAL, "%s: 0 %01d %01d %01d\n",
  967. __func__, !_req->complete, !_req->buf,
  968. !list_empty(&req->queue));
  969. }
  970. local_irq_restore(flags);
  971. return -EINVAL;
  972. }
  973. _req->status = -EINPROGRESS;
  974. _req->actual = 0;
  975. dprintk(DEBUG_VERBOSE, "%s: ep%x len %d\n",
  976. __func__, ep->bEndpointAddress, _req->length);
  977. if (ep->bEndpointAddress) {
  978. udc_write(ep->bEndpointAddress & 0x7F, S3C2410_UDC_INDEX_REG);
  979. ep_csr = udc_read((ep->bEndpointAddress & USB_DIR_IN)
  980. ? S3C2410_UDC_IN_CSR1_REG
  981. : S3C2410_UDC_OUT_CSR1_REG);
  982. fifo_count = s3c2410_udc_fifo_count_out();
  983. } else {
  984. udc_write(0, S3C2410_UDC_INDEX_REG);
  985. ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  986. fifo_count = s3c2410_udc_fifo_count_out();
  987. }
  988. /* kickstart this i/o queue? */
  989. if (list_empty(&ep->queue) && !ep->halted) {
  990. if (ep->bEndpointAddress == 0 /* ep0 */) {
  991. switch (dev->ep0state) {
  992. case EP0_IN_DATA_PHASE:
  993. if (!(ep_csr&S3C2410_UDC_EP0_CSR_IPKRDY)
  994. && s3c2410_udc_write_fifo(ep,
  995. req)) {
  996. dev->ep0state = EP0_IDLE;
  997. req = NULL;
  998. }
  999. break;
  1000. case EP0_OUT_DATA_PHASE:
  1001. if ((!_req->length)
  1002. || ((ep_csr & S3C2410_UDC_OCSR1_PKTRDY)
  1003. && s3c2410_udc_read_fifo(ep,
  1004. req))) {
  1005. dev->ep0state = EP0_IDLE;
  1006. req = NULL;
  1007. }
  1008. break;
  1009. default:
  1010. local_irq_restore(flags);
  1011. return -EL2HLT;
  1012. }
  1013. } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0
  1014. && (!(ep_csr&S3C2410_UDC_OCSR1_PKTRDY))
  1015. && s3c2410_udc_write_fifo(ep, req)) {
  1016. req = NULL;
  1017. } else if ((ep_csr & S3C2410_UDC_OCSR1_PKTRDY)
  1018. && fifo_count
  1019. && s3c2410_udc_read_fifo(ep, req)) {
  1020. req = NULL;
  1021. }
  1022. }
  1023. /* pio or dma irq handler advances the queue. */
  1024. if (likely(req))
  1025. list_add_tail(&req->queue, &ep->queue);
  1026. local_irq_restore(flags);
  1027. dprintk(DEBUG_VERBOSE, "%s ok\n", __func__);
  1028. return 0;
  1029. }
  1030. /*
  1031. * s3c2410_udc_dequeue
  1032. */
  1033. static int s3c2410_udc_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  1034. {
  1035. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  1036. int retval = -EINVAL;
  1037. unsigned long flags;
  1038. struct s3c2410_request *req = NULL, *iter;
  1039. dprintk(DEBUG_VERBOSE, "%s(%p,%p)\n", __func__, _ep, _req);
  1040. if (!the_controller->driver)
  1041. return -ESHUTDOWN;
  1042. if (!_ep || !_req)
  1043. return retval;
  1044. local_irq_save(flags);
  1045. list_for_each_entry(iter, &ep->queue, queue) {
  1046. if (&iter->req != _req)
  1047. continue;
  1048. list_del_init(&iter->queue);
  1049. _req->status = -ECONNRESET;
  1050. req = iter;
  1051. retval = 0;
  1052. break;
  1053. }
  1054. if (retval == 0) {
  1055. dprintk(DEBUG_VERBOSE,
  1056. "dequeued req %p from %s, len %d buf %p\n",
  1057. req, _ep->name, _req->length, _req->buf);
  1058. s3c2410_udc_done(ep, req, -ECONNRESET);
  1059. }
  1060. local_irq_restore(flags);
  1061. return retval;
  1062. }
  1063. /*
  1064. * s3c2410_udc_set_halt
  1065. */
  1066. static int s3c2410_udc_set_halt(struct usb_ep *_ep, int value)
  1067. {
  1068. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  1069. u32 ep_csr = 0;
  1070. unsigned long flags;
  1071. u32 idx;
  1072. if (unlikely(!_ep || (!ep->ep.desc && ep->ep.name != ep0name))) {
  1073. dprintk(DEBUG_NORMAL, "%s: inval 2\n", __func__);
  1074. return -EINVAL;
  1075. }
  1076. local_irq_save(flags);
  1077. idx = ep->bEndpointAddress & 0x7F;
  1078. if (idx == 0) {
  1079. s3c2410_udc_set_ep0_ss(base_addr);
  1080. s3c2410_udc_set_ep0_de_out(base_addr);
  1081. } else {
  1082. udc_write(idx, S3C2410_UDC_INDEX_REG);
  1083. ep_csr = udc_read((ep->bEndpointAddress & USB_DIR_IN)
  1084. ? S3C2410_UDC_IN_CSR1_REG
  1085. : S3C2410_UDC_OUT_CSR1_REG);
  1086. if ((ep->bEndpointAddress & USB_DIR_IN) != 0) {
  1087. if (value)
  1088. udc_write(ep_csr | S3C2410_UDC_ICSR1_SENDSTL,
  1089. S3C2410_UDC_IN_CSR1_REG);
  1090. else {
  1091. ep_csr &= ~S3C2410_UDC_ICSR1_SENDSTL;
  1092. udc_write(ep_csr, S3C2410_UDC_IN_CSR1_REG);
  1093. ep_csr |= S3C2410_UDC_ICSR1_CLRDT;
  1094. udc_write(ep_csr, S3C2410_UDC_IN_CSR1_REG);
  1095. }
  1096. } else {
  1097. if (value)
  1098. udc_write(ep_csr | S3C2410_UDC_OCSR1_SENDSTL,
  1099. S3C2410_UDC_OUT_CSR1_REG);
  1100. else {
  1101. ep_csr &= ~S3C2410_UDC_OCSR1_SENDSTL;
  1102. udc_write(ep_csr, S3C2410_UDC_OUT_CSR1_REG);
  1103. ep_csr |= S3C2410_UDC_OCSR1_CLRDT;
  1104. udc_write(ep_csr, S3C2410_UDC_OUT_CSR1_REG);
  1105. }
  1106. }
  1107. }
  1108. ep->halted = value ? 1 : 0;
  1109. local_irq_restore(flags);
  1110. return 0;
  1111. }
  1112. static const struct usb_ep_ops s3c2410_ep_ops = {
  1113. .enable = s3c2410_udc_ep_enable,
  1114. .disable = s3c2410_udc_ep_disable,
  1115. .alloc_request = s3c2410_udc_alloc_request,
  1116. .free_request = s3c2410_udc_free_request,
  1117. .queue = s3c2410_udc_queue,
  1118. .dequeue = s3c2410_udc_dequeue,
  1119. .set_halt = s3c2410_udc_set_halt,
  1120. };
  1121. /*------------------------- usb_gadget_ops ----------------------------------*/
  1122. /*
  1123. * s3c2410_udc_get_frame
  1124. */
  1125. static int s3c2410_udc_get_frame(struct usb_gadget *_gadget)
  1126. {
  1127. int tmp;
  1128. dprintk(DEBUG_VERBOSE, "%s()\n", __func__);
  1129. tmp = udc_read(S3C2410_UDC_FRAME_NUM2_REG) << 8;
  1130. tmp |= udc_read(S3C2410_UDC_FRAME_NUM1_REG);
  1131. return tmp;
  1132. }
  1133. /*
  1134. * s3c2410_udc_wakeup
  1135. */
  1136. static int s3c2410_udc_wakeup(struct usb_gadget *_gadget)
  1137. {
  1138. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1139. return 0;
  1140. }
  1141. /*
  1142. * s3c2410_udc_set_selfpowered
  1143. */
  1144. static int s3c2410_udc_set_selfpowered(struct usb_gadget *gadget, int value)
  1145. {
  1146. struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
  1147. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1148. gadget->is_selfpowered = (value != 0);
  1149. if (value)
  1150. udc->devstatus |= (1 << USB_DEVICE_SELF_POWERED);
  1151. else
  1152. udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
  1153. return 0;
  1154. }
  1155. static void s3c2410_udc_disable(struct s3c2410_udc *dev);
  1156. static void s3c2410_udc_enable(struct s3c2410_udc *dev);
  1157. static int s3c2410_udc_set_pullup(struct s3c2410_udc *udc, int is_on)
  1158. {
  1159. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1160. if (udc_info && (udc_info->udc_command || udc->pullup_gpiod)) {
  1161. if (is_on)
  1162. s3c2410_udc_enable(udc);
  1163. else {
  1164. if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
  1165. if (udc->driver && udc->driver->disconnect)
  1166. udc->driver->disconnect(&udc->gadget);
  1167. }
  1168. s3c2410_udc_disable(udc);
  1169. }
  1170. } else {
  1171. return -EOPNOTSUPP;
  1172. }
  1173. return 0;
  1174. }
  1175. static int s3c2410_udc_vbus_session(struct usb_gadget *gadget, int is_active)
  1176. {
  1177. struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
  1178. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1179. udc->vbus = (is_active != 0);
  1180. s3c2410_udc_set_pullup(udc, is_active);
  1181. return 0;
  1182. }
  1183. static int s3c2410_udc_pullup(struct usb_gadget *gadget, int is_on)
  1184. {
  1185. struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
  1186. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1187. s3c2410_udc_set_pullup(udc, is_on);
  1188. return 0;
  1189. }
  1190. static irqreturn_t s3c2410_udc_vbus_irq(int irq, void *_dev)
  1191. {
  1192. struct s3c2410_udc *dev = _dev;
  1193. unsigned int value;
  1194. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1195. value = gpiod_get_value(dev->vbus_gpiod);
  1196. if (value != dev->vbus)
  1197. s3c2410_udc_vbus_session(&dev->gadget, value);
  1198. return IRQ_HANDLED;
  1199. }
  1200. static int s3c2410_vbus_draw(struct usb_gadget *_gadget, unsigned ma)
  1201. {
  1202. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1203. if (udc_info && udc_info->vbus_draw) {
  1204. udc_info->vbus_draw(ma);
  1205. return 0;
  1206. }
  1207. return -ENOTSUPP;
  1208. }
  1209. static int s3c2410_udc_start(struct usb_gadget *g,
  1210. struct usb_gadget_driver *driver);
  1211. static int s3c2410_udc_stop(struct usb_gadget *g);
  1212. static const struct usb_gadget_ops s3c2410_ops = {
  1213. .get_frame = s3c2410_udc_get_frame,
  1214. .wakeup = s3c2410_udc_wakeup,
  1215. .set_selfpowered = s3c2410_udc_set_selfpowered,
  1216. .pullup = s3c2410_udc_pullup,
  1217. .vbus_session = s3c2410_udc_vbus_session,
  1218. .vbus_draw = s3c2410_vbus_draw,
  1219. .udc_start = s3c2410_udc_start,
  1220. .udc_stop = s3c2410_udc_stop,
  1221. };
  1222. static void s3c2410_udc_command(struct s3c2410_udc *udc,
  1223. enum s3c2410_udc_cmd_e cmd)
  1224. {
  1225. if (!udc_info)
  1226. return;
  1227. if (udc_info->udc_command) {
  1228. udc_info->udc_command(cmd);
  1229. } else if (udc->pullup_gpiod) {
  1230. int value;
  1231. switch (cmd) {
  1232. case S3C2410_UDC_P_ENABLE:
  1233. value = 1;
  1234. break;
  1235. case S3C2410_UDC_P_DISABLE:
  1236. value = 0;
  1237. break;
  1238. default:
  1239. return;
  1240. }
  1241. gpiod_set_value(udc->pullup_gpiod, value);
  1242. }
  1243. }
  1244. /*------------------------- gadget driver handling---------------------------*/
  1245. /*
  1246. * s3c2410_udc_disable
  1247. */
  1248. static void s3c2410_udc_disable(struct s3c2410_udc *dev)
  1249. {
  1250. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1251. /* Disable all interrupts */
  1252. udc_write(0x00, S3C2410_UDC_USB_INT_EN_REG);
  1253. udc_write(0x00, S3C2410_UDC_EP_INT_EN_REG);
  1254. /* Clear the interrupt registers */
  1255. udc_write(S3C2410_UDC_USBINT_RESET
  1256. | S3C2410_UDC_USBINT_RESUME
  1257. | S3C2410_UDC_USBINT_SUSPEND,
  1258. S3C2410_UDC_USB_INT_REG);
  1259. udc_write(0x1F, S3C2410_UDC_EP_INT_REG);
  1260. /* Good bye, cruel world */
  1261. s3c2410_udc_command(dev, S3C2410_UDC_P_DISABLE);
  1262. /* Set speed to unknown */
  1263. dev->gadget.speed = USB_SPEED_UNKNOWN;
  1264. }
  1265. /*
  1266. * s3c2410_udc_reinit
  1267. */
  1268. static void s3c2410_udc_reinit(struct s3c2410_udc *dev)
  1269. {
  1270. u32 i;
  1271. /* device/ep0 records init */
  1272. INIT_LIST_HEAD(&dev->gadget.ep_list);
  1273. INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
  1274. dev->ep0state = EP0_IDLE;
  1275. for (i = 0; i < S3C2410_ENDPOINTS; i++) {
  1276. struct s3c2410_ep *ep = &dev->ep[i];
  1277. if (i != 0)
  1278. list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
  1279. ep->dev = dev;
  1280. ep->ep.desc = NULL;
  1281. ep->halted = 0;
  1282. INIT_LIST_HEAD(&ep->queue);
  1283. usb_ep_set_maxpacket_limit(&ep->ep, ep->ep.maxpacket);
  1284. }
  1285. }
  1286. /*
  1287. * s3c2410_udc_enable
  1288. */
  1289. static void s3c2410_udc_enable(struct s3c2410_udc *dev)
  1290. {
  1291. int i;
  1292. dprintk(DEBUG_NORMAL, "s3c2410_udc_enable called\n");
  1293. /* dev->gadget.speed = USB_SPEED_UNKNOWN; */
  1294. dev->gadget.speed = USB_SPEED_FULL;
  1295. /* Set MAXP for all endpoints */
  1296. for (i = 0; i < S3C2410_ENDPOINTS; i++) {
  1297. udc_write(i, S3C2410_UDC_INDEX_REG);
  1298. udc_write((dev->ep[i].ep.maxpacket & 0x7ff) >> 3,
  1299. S3C2410_UDC_MAXP_REG);
  1300. }
  1301. /* Set default power state */
  1302. udc_write(DEFAULT_POWER_STATE, S3C2410_UDC_PWR_REG);
  1303. /* Enable reset and suspend interrupt interrupts */
  1304. udc_write(S3C2410_UDC_USBINT_RESET | S3C2410_UDC_USBINT_SUSPEND,
  1305. S3C2410_UDC_USB_INT_EN_REG);
  1306. /* Enable ep0 interrupt */
  1307. udc_write(S3C2410_UDC_INT_EP0, S3C2410_UDC_EP_INT_EN_REG);
  1308. /* time to say "hello, world" */
  1309. s3c2410_udc_command(dev, S3C2410_UDC_P_ENABLE);
  1310. }
  1311. static int s3c2410_udc_start(struct usb_gadget *g,
  1312. struct usb_gadget_driver *driver)
  1313. {
  1314. struct s3c2410_udc *udc = to_s3c2410(g);
  1315. dprintk(DEBUG_NORMAL, "%s() '%s'\n", __func__, driver->driver.name);
  1316. /* Hook the driver */
  1317. udc->driver = driver;
  1318. /* Enable udc */
  1319. s3c2410_udc_enable(udc);
  1320. return 0;
  1321. }
  1322. static int s3c2410_udc_stop(struct usb_gadget *g)
  1323. {
  1324. struct s3c2410_udc *udc = to_s3c2410(g);
  1325. udc->driver = NULL;
  1326. /* Disable udc */
  1327. s3c2410_udc_disable(udc);
  1328. return 0;
  1329. }
  1330. /*---------------------------------------------------------------------------*/
  1331. static struct s3c2410_udc memory = {
  1332. .gadget = {
  1333. .ops = &s3c2410_ops,
  1334. .ep0 = &memory.ep[0].ep,
  1335. .name = gadget_name,
  1336. .dev = {
  1337. .init_name = "gadget",
  1338. },
  1339. },
  1340. /* control endpoint */
  1341. .ep[0] = {
  1342. .num = 0,
  1343. .ep = {
  1344. .name = ep0name,
  1345. .ops = &s3c2410_ep_ops,
  1346. .maxpacket = EP0_FIFO_SIZE,
  1347. .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL,
  1348. USB_EP_CAPS_DIR_ALL),
  1349. },
  1350. .dev = &memory,
  1351. },
  1352. /* first group of endpoints */
  1353. .ep[1] = {
  1354. .num = 1,
  1355. .ep = {
  1356. .name = "ep1-bulk",
  1357. .ops = &s3c2410_ep_ops,
  1358. .maxpacket = EP_FIFO_SIZE,
  1359. .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
  1360. USB_EP_CAPS_DIR_ALL),
  1361. },
  1362. .dev = &memory,
  1363. .fifo_size = EP_FIFO_SIZE,
  1364. .bEndpointAddress = 1,
  1365. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1366. },
  1367. .ep[2] = {
  1368. .num = 2,
  1369. .ep = {
  1370. .name = "ep2-bulk",
  1371. .ops = &s3c2410_ep_ops,
  1372. .maxpacket = EP_FIFO_SIZE,
  1373. .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
  1374. USB_EP_CAPS_DIR_ALL),
  1375. },
  1376. .dev = &memory,
  1377. .fifo_size = EP_FIFO_SIZE,
  1378. .bEndpointAddress = 2,
  1379. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1380. },
  1381. .ep[3] = {
  1382. .num = 3,
  1383. .ep = {
  1384. .name = "ep3-bulk",
  1385. .ops = &s3c2410_ep_ops,
  1386. .maxpacket = EP_FIFO_SIZE,
  1387. .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
  1388. USB_EP_CAPS_DIR_ALL),
  1389. },
  1390. .dev = &memory,
  1391. .fifo_size = EP_FIFO_SIZE,
  1392. .bEndpointAddress = 3,
  1393. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1394. },
  1395. .ep[4] = {
  1396. .num = 4,
  1397. .ep = {
  1398. .name = "ep4-bulk",
  1399. .ops = &s3c2410_ep_ops,
  1400. .maxpacket = EP_FIFO_SIZE,
  1401. .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
  1402. USB_EP_CAPS_DIR_ALL),
  1403. },
  1404. .dev = &memory,
  1405. .fifo_size = EP_FIFO_SIZE,
  1406. .bEndpointAddress = 4,
  1407. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1408. }
  1409. };
  1410. /*
  1411. * probe - binds to the platform device
  1412. */
  1413. static int s3c2410_udc_probe(struct platform_device *pdev)
  1414. {
  1415. struct s3c2410_udc *udc = &memory;
  1416. struct device *dev = &pdev->dev;
  1417. int retval;
  1418. int irq;
  1419. dev_dbg(dev, "%s()\n", __func__);
  1420. usb_bus_clock = clk_get(NULL, "usb-bus-gadget");
  1421. if (IS_ERR(usb_bus_clock)) {
  1422. dev_err(dev, "failed to get usb bus clock source\n");
  1423. return PTR_ERR(usb_bus_clock);
  1424. }
  1425. clk_prepare_enable(usb_bus_clock);
  1426. udc_clock = clk_get(NULL, "usb-device");
  1427. if (IS_ERR(udc_clock)) {
  1428. dev_err(dev, "failed to get udc clock source\n");
  1429. retval = PTR_ERR(udc_clock);
  1430. goto err_usb_bus_clk;
  1431. }
  1432. clk_prepare_enable(udc_clock);
  1433. mdelay(10);
  1434. dev_dbg(dev, "got and enabled clocks\n");
  1435. if (strncmp(pdev->name, "s3c2440", 7) == 0) {
  1436. dev_info(dev, "S3C2440: increasing FIFO to 128 bytes\n");
  1437. memory.ep[1].fifo_size = S3C2440_EP_FIFO_SIZE;
  1438. memory.ep[2].fifo_size = S3C2440_EP_FIFO_SIZE;
  1439. memory.ep[3].fifo_size = S3C2440_EP_FIFO_SIZE;
  1440. memory.ep[4].fifo_size = S3C2440_EP_FIFO_SIZE;
  1441. }
  1442. spin_lock_init(&udc->lock);
  1443. udc_info = dev_get_platdata(&pdev->dev);
  1444. base_addr = devm_platform_ioremap_resource(pdev, 0);
  1445. if (IS_ERR(base_addr)) {
  1446. retval = PTR_ERR(base_addr);
  1447. goto err_udc_clk;
  1448. }
  1449. the_controller = udc;
  1450. platform_set_drvdata(pdev, udc);
  1451. s3c2410_udc_disable(udc);
  1452. s3c2410_udc_reinit(udc);
  1453. irq_usbd = platform_get_irq(pdev, 0);
  1454. if (irq_usbd < 0) {
  1455. retval = irq_usbd;
  1456. goto err_udc_clk;
  1457. }
  1458. /* irq setup after old hardware state is cleaned up */
  1459. retval = request_irq(irq_usbd, s3c2410_udc_irq,
  1460. 0, gadget_name, udc);
  1461. if (retval != 0) {
  1462. dev_err(dev, "cannot get irq %i, err %d\n", irq_usbd, retval);
  1463. retval = -EBUSY;
  1464. goto err_udc_clk;
  1465. }
  1466. dev_dbg(dev, "got irq %i\n", irq_usbd);
  1467. udc->vbus_gpiod = gpiod_get_optional(dev, "vbus", GPIOD_IN);
  1468. if (IS_ERR(udc->vbus_gpiod)) {
  1469. retval = PTR_ERR(udc->vbus_gpiod);
  1470. goto err_int;
  1471. }
  1472. if (udc->vbus_gpiod) {
  1473. gpiod_set_consumer_name(udc->vbus_gpiod, "udc vbus");
  1474. irq = gpiod_to_irq(udc->vbus_gpiod);
  1475. if (irq < 0) {
  1476. dev_err(dev, "no irq for gpio vbus pin\n");
  1477. retval = irq;
  1478. goto err_gpio_claim;
  1479. }
  1480. retval = request_irq(irq, s3c2410_udc_vbus_irq,
  1481. IRQF_TRIGGER_RISING
  1482. | IRQF_TRIGGER_FALLING | IRQF_SHARED,
  1483. gadget_name, udc);
  1484. if (retval != 0) {
  1485. dev_err(dev, "can't get vbus irq %d, err %d\n",
  1486. irq, retval);
  1487. retval = -EBUSY;
  1488. goto err_gpio_claim;
  1489. }
  1490. dev_dbg(dev, "got irq %i\n", irq);
  1491. } else {
  1492. udc->vbus = 1;
  1493. }
  1494. udc->pullup_gpiod = gpiod_get_optional(dev, "pullup", GPIOD_OUT_LOW);
  1495. if (IS_ERR(udc->pullup_gpiod)) {
  1496. retval = PTR_ERR(udc->pullup_gpiod);
  1497. goto err_vbus_irq;
  1498. }
  1499. gpiod_set_consumer_name(udc->pullup_gpiod, "udc pullup");
  1500. retval = usb_add_gadget_udc(&pdev->dev, &udc->gadget);
  1501. if (retval)
  1502. goto err_add_udc;
  1503. debugfs_create_file("registers", S_IRUGO, s3c2410_udc_debugfs_root, udc,
  1504. &s3c2410_udc_debugfs_fops);
  1505. dev_dbg(dev, "probe ok\n");
  1506. return 0;
  1507. err_add_udc:
  1508. err_vbus_irq:
  1509. if (udc->vbus_gpiod)
  1510. free_irq(gpiod_to_irq(udc->vbus_gpiod), udc);
  1511. err_gpio_claim:
  1512. err_int:
  1513. free_irq(irq_usbd, udc);
  1514. err_udc_clk:
  1515. clk_disable_unprepare(udc_clock);
  1516. clk_put(udc_clock);
  1517. udc_clock = NULL;
  1518. err_usb_bus_clk:
  1519. clk_disable_unprepare(usb_bus_clock);
  1520. clk_put(usb_bus_clock);
  1521. usb_bus_clock = NULL;
  1522. return retval;
  1523. }
  1524. /*
  1525. * s3c2410_udc_remove
  1526. */
  1527. static int s3c2410_udc_remove(struct platform_device *pdev)
  1528. {
  1529. struct s3c2410_udc *udc = platform_get_drvdata(pdev);
  1530. dev_dbg(&pdev->dev, "%s()\n", __func__);
  1531. if (udc->driver)
  1532. return -EBUSY;
  1533. usb_del_gadget_udc(&udc->gadget);
  1534. debugfs_remove(debugfs_lookup("registers", s3c2410_udc_debugfs_root));
  1535. if (udc->vbus_gpiod)
  1536. free_irq(gpiod_to_irq(udc->vbus_gpiod), udc);
  1537. free_irq(irq_usbd, udc);
  1538. if (!IS_ERR(udc_clock) && udc_clock != NULL) {
  1539. clk_disable_unprepare(udc_clock);
  1540. clk_put(udc_clock);
  1541. udc_clock = NULL;
  1542. }
  1543. if (!IS_ERR(usb_bus_clock) && usb_bus_clock != NULL) {
  1544. clk_disable_unprepare(usb_bus_clock);
  1545. clk_put(usb_bus_clock);
  1546. usb_bus_clock = NULL;
  1547. }
  1548. dev_dbg(&pdev->dev, "%s: remove ok\n", __func__);
  1549. return 0;
  1550. }
  1551. #ifdef CONFIG_PM
  1552. static int
  1553. s3c2410_udc_suspend(struct platform_device *pdev, pm_message_t message)
  1554. {
  1555. struct s3c2410_udc *udc = platform_get_drvdata(pdev);
  1556. s3c2410_udc_command(udc, S3C2410_UDC_P_DISABLE);
  1557. return 0;
  1558. }
  1559. static int s3c2410_udc_resume(struct platform_device *pdev)
  1560. {
  1561. struct s3c2410_udc *udc = platform_get_drvdata(pdev);
  1562. s3c2410_udc_command(udc, S3C2410_UDC_P_ENABLE);
  1563. return 0;
  1564. }
  1565. #else
  1566. #define s3c2410_udc_suspend NULL
  1567. #define s3c2410_udc_resume NULL
  1568. #endif
  1569. static const struct platform_device_id s3c_udc_ids[] = {
  1570. { "s3c2410-usbgadget", },
  1571. { "s3c2440-usbgadget", },
  1572. { }
  1573. };
  1574. MODULE_DEVICE_TABLE(platform, s3c_udc_ids);
  1575. static struct platform_driver udc_driver_24x0 = {
  1576. .driver = {
  1577. .name = "s3c24x0-usbgadget",
  1578. },
  1579. .probe = s3c2410_udc_probe,
  1580. .remove = s3c2410_udc_remove,
  1581. .suspend = s3c2410_udc_suspend,
  1582. .resume = s3c2410_udc_resume,
  1583. .id_table = s3c_udc_ids,
  1584. };
  1585. static int __init udc_init(void)
  1586. {
  1587. int retval;
  1588. dprintk(DEBUG_NORMAL, "%s\n", gadget_name);
  1589. s3c2410_udc_debugfs_root = debugfs_create_dir(gadget_name,
  1590. usb_debug_root);
  1591. retval = platform_driver_register(&udc_driver_24x0);
  1592. if (retval)
  1593. goto err;
  1594. return 0;
  1595. err:
  1596. debugfs_remove(s3c2410_udc_debugfs_root);
  1597. return retval;
  1598. }
  1599. static void __exit udc_exit(void)
  1600. {
  1601. platform_driver_unregister(&udc_driver_24x0);
  1602. debugfs_remove_recursive(s3c2410_udc_debugfs_root);
  1603. }
  1604. module_init(udc_init);
  1605. module_exit(udc_exit);
  1606. MODULE_AUTHOR(DRIVER_AUTHOR);
  1607. MODULE_DESCRIPTION(DRIVER_DESC);
  1608. MODULE_LICENSE("GPL");