pxa25x_udc.h 6.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Intel PXA25x on-chip full speed USB device controller
  4. *
  5. * Copyright (C) 2003 Robert Schwebel <[email protected]>, Pengutronix
  6. * Copyright (C) 2003 David Brownell
  7. */
  8. #ifndef __LINUX_USB_GADGET_PXA25X_H
  9. #define __LINUX_USB_GADGET_PXA25X_H
  10. #include <linux/types.h>
  11. /*-------------------------------------------------------------------------*/
  12. /* pxa25x has this (move to include/asm-arm/arch-pxa/pxa-regs.h) */
  13. #define UFNRH_SIR (1 << 7) /* SOF interrupt request */
  14. #define UFNRH_SIM (1 << 6) /* SOF interrupt mask */
  15. #define UFNRH_IPE14 (1 << 5) /* ISO packet error, ep14 */
  16. #define UFNRH_IPE9 (1 << 4) /* ISO packet error, ep9 */
  17. #define UFNRH_IPE4 (1 << 3) /* ISO packet error, ep4 */
  18. /* pxa255 has this (move to include/asm-arm/arch-pxa/pxa-regs.h) */
  19. #define UDCCFR UDC_RES2 /* UDC Control Function Register */
  20. #define UDCCFR_AREN (1 << 7) /* ACK response enable (now) */
  21. #define UDCCFR_ACM (1 << 2) /* ACK control mode (wait for AREN) */
  22. /* latest pxa255 errata define new "must be one" bits in UDCCFR */
  23. #define UDCCFR_MB1 (0xff & ~(UDCCFR_AREN|UDCCFR_ACM))
  24. /*-------------------------------------------------------------------------*/
  25. struct pxa25x_udc;
  26. struct pxa25x_ep {
  27. struct usb_ep ep;
  28. struct pxa25x_udc *dev;
  29. struct list_head queue;
  30. unsigned long pio_irqs;
  31. unsigned short fifo_size;
  32. u8 bEndpointAddress;
  33. u8 bmAttributes;
  34. unsigned stopped : 1;
  35. unsigned dma_fixup : 1;
  36. /* UDCCS = UDC Control/Status for this EP
  37. * UBCR = UDC Byte Count Remaining (contents of OUT fifo)
  38. * UDDR = UDC Endpoint Data Register (the fifo)
  39. * DRCM = DMA Request Channel Map
  40. */
  41. u32 regoff_udccs;
  42. u32 regoff_ubcr;
  43. u32 regoff_uddr;
  44. };
  45. struct pxa25x_request {
  46. struct usb_request req;
  47. struct list_head queue;
  48. };
  49. enum ep0_state {
  50. EP0_IDLE,
  51. EP0_IN_DATA_PHASE,
  52. EP0_OUT_DATA_PHASE,
  53. EP0_END_XFER,
  54. EP0_STALL,
  55. };
  56. #define EP0_FIFO_SIZE ((unsigned)16)
  57. #define BULK_FIFO_SIZE ((unsigned)64)
  58. #define ISO_FIFO_SIZE ((unsigned)256)
  59. #define INT_FIFO_SIZE ((unsigned)8)
  60. struct udc_stats {
  61. struct ep0stats {
  62. unsigned long ops;
  63. unsigned long bytes;
  64. } read, write;
  65. unsigned long irqs;
  66. };
  67. #ifdef CONFIG_USB_PXA25X_SMALL
  68. /* when memory's tight, SMALL config saves code+data. */
  69. #define PXA_UDC_NUM_ENDPOINTS 3
  70. #endif
  71. #ifndef PXA_UDC_NUM_ENDPOINTS
  72. #define PXA_UDC_NUM_ENDPOINTS 16
  73. #endif
  74. struct pxa25x_udc {
  75. struct usb_gadget gadget;
  76. struct usb_gadget_driver *driver;
  77. enum ep0_state ep0state;
  78. struct udc_stats stats;
  79. unsigned got_irq : 1,
  80. vbus : 1,
  81. pullup : 1,
  82. has_cfr : 1,
  83. req_pending : 1,
  84. req_std : 1,
  85. req_config : 1,
  86. suspended : 1,
  87. active : 1;
  88. #define start_watchdog(dev) mod_timer(&dev->timer, jiffies + (HZ/200))
  89. struct timer_list timer;
  90. struct device *dev;
  91. struct clk *clk;
  92. struct pxa2xx_udc_mach_info *mach;
  93. struct usb_phy *transceiver;
  94. u64 dma_mask;
  95. struct pxa25x_ep ep [PXA_UDC_NUM_ENDPOINTS];
  96. void __iomem *regs;
  97. int usb_irq;
  98. int usb_disc_irq;
  99. };
  100. #define to_pxa25x(g) (container_of((g), struct pxa25x_udc, gadget))
  101. /*-------------------------------------------------------------------------*/
  102. static struct pxa25x_udc *the_controller;
  103. /*-------------------------------------------------------------------------*/
  104. /*
  105. * Debugging support vanishes in non-debug builds. DBG_NORMAL should be
  106. * mostly silent during normal use/testing, with no timing side-effects.
  107. */
  108. #define DBG_NORMAL 1 /* error paths, device state transitions */
  109. #define DBG_VERBOSE 2 /* add some success path trace info */
  110. #define DBG_NOISY 3 /* ... even more: request level */
  111. #define DBG_VERY_NOISY 4 /* ... even more: packet level */
  112. #define DMSG(stuff...) pr_debug("udc: " stuff)
  113. #ifdef DEBUG
  114. static const char *state_name[] = {
  115. "EP0_IDLE",
  116. "EP0_IN_DATA_PHASE", "EP0_OUT_DATA_PHASE",
  117. "EP0_END_XFER", "EP0_STALL"
  118. };
  119. #ifdef VERBOSE_DEBUG
  120. # define UDC_DEBUG DBG_VERBOSE
  121. #else
  122. # define UDC_DEBUG DBG_NORMAL
  123. #endif
  124. static void __maybe_unused
  125. dump_udccr(const char *label)
  126. {
  127. u32 udccr = UDCCR;
  128. DMSG("%s %02X =%s%s%s%s%s%s%s%s\n",
  129. label, udccr,
  130. (udccr & UDCCR_REM) ? " rem" : "",
  131. (udccr & UDCCR_RSTIR) ? " rstir" : "",
  132. (udccr & UDCCR_SRM) ? " srm" : "",
  133. (udccr & UDCCR_SUSIR) ? " susir" : "",
  134. (udccr & UDCCR_RESIR) ? " resir" : "",
  135. (udccr & UDCCR_RSM) ? " rsm" : "",
  136. (udccr & UDCCR_UDA) ? " uda" : "",
  137. (udccr & UDCCR_UDE) ? " ude" : "");
  138. }
  139. static void __maybe_unused
  140. dump_udccs0(const char *label)
  141. {
  142. u32 udccs0 = UDCCS0;
  143. DMSG("%s %s %02X =%s%s%s%s%s%s%s%s\n",
  144. label, state_name[the_controller->ep0state], udccs0,
  145. (udccs0 & UDCCS0_SA) ? " sa" : "",
  146. (udccs0 & UDCCS0_RNE) ? " rne" : "",
  147. (udccs0 & UDCCS0_FST) ? " fst" : "",
  148. (udccs0 & UDCCS0_SST) ? " sst" : "",
  149. (udccs0 & UDCCS0_DRWF) ? " dwrf" : "",
  150. (udccs0 & UDCCS0_FTF) ? " ftf" : "",
  151. (udccs0 & UDCCS0_IPR) ? " ipr" : "",
  152. (udccs0 & UDCCS0_OPR) ? " opr" : "");
  153. }
  154. static inline u32 udc_ep_get_UDCCS(struct pxa25x_ep *);
  155. static void __maybe_unused
  156. dump_state(struct pxa25x_udc *dev)
  157. {
  158. u32 tmp;
  159. unsigned i;
  160. DMSG("%s, uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n",
  161. state_name[dev->ep0state],
  162. UICR1, UICR0, USIR1, USIR0, UFNRH, UFNRL);
  163. dump_udccr("udccr");
  164. if (dev->has_cfr) {
  165. tmp = UDCCFR;
  166. DMSG("udccfr %02X =%s%s\n", tmp,
  167. (tmp & UDCCFR_AREN) ? " aren" : "",
  168. (tmp & UDCCFR_ACM) ? " acm" : "");
  169. }
  170. if (!dev->driver) {
  171. DMSG("no gadget driver bound\n");
  172. return;
  173. } else
  174. DMSG("ep0 driver '%s'\n", dev->driver->driver.name);
  175. dump_udccs0 ("udccs0");
  176. DMSG("ep0 IN %lu/%lu, OUT %lu/%lu\n",
  177. dev->stats.write.bytes, dev->stats.write.ops,
  178. dev->stats.read.bytes, dev->stats.read.ops);
  179. for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++) {
  180. if (dev->ep[i].ep.desc == NULL)
  181. continue;
  182. DMSG ("udccs%d = %02x\n", i, udc_ep_get_UDCCS(&dev->ep[i]));
  183. }
  184. }
  185. #else
  186. #define dump_udccr(x) do{}while(0)
  187. #define dump_udccs0(x) do{}while(0)
  188. #define dump_state(x) do{}while(0)
  189. #define UDC_DEBUG ((unsigned)0)
  190. #endif
  191. #define DBG(lvl, stuff...) do{if ((lvl) <= UDC_DEBUG) DMSG(stuff);}while(0)
  192. #define ERR(stuff...) pr_err("udc: " stuff)
  193. #define WARNING(stuff...) pr_warn("udc: " stuff)
  194. #define INFO(stuff...) pr_info("udc: " stuff)
  195. #endif /* __LINUX_USB_GADGET_PXA25X_H */