max3420_udc.c 30 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * MAX3420 Device Controller driver for USB.
  4. *
  5. * Author: Jaswinder Singh Brar <[email protected]>
  6. * (C) Copyright 2019-2020 Linaro Ltd
  7. *
  8. * Based on:
  9. * o MAX3420E datasheet
  10. * https://datasheets.maximintegrated.com/en/ds/MAX3420E.pdf
  11. * o MAX342{0,1}E Programming Guides
  12. * https://pdfserv.maximintegrated.com/en/an/AN3598.pdf
  13. * https://pdfserv.maximintegrated.com/en/an/AN3785.pdf
  14. */
  15. #include <linux/delay.h>
  16. #include <linux/device.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/io.h>
  19. #include <linux/module.h>
  20. #include <linux/bitfield.h>
  21. #include <linux/of_address.h>
  22. #include <linux/of_device.h>
  23. #include <linux/of_platform.h>
  24. #include <linux/of_irq.h>
  25. #include <linux/prefetch.h>
  26. #include <linux/usb/ch9.h>
  27. #include <linux/usb/gadget.h>
  28. #include <linux/spi/spi.h>
  29. #include <linux/gpio/consumer.h>
  30. #define MAX3420_MAX_EPS 4
  31. #define MAX3420_EP_MAX_PACKET 64 /* Same for all Endpoints */
  32. #define MAX3420_EPNAME_SIZE 16 /* Buffer size for endpoint name */
  33. #define MAX3420_ACKSTAT BIT(0)
  34. #define MAX3420_SPI_DIR_RD 0 /* read register from MAX3420 */
  35. #define MAX3420_SPI_DIR_WR 1 /* write register to MAX3420 */
  36. /* SPI commands: */
  37. #define MAX3420_SPI_DIR_SHIFT 1
  38. #define MAX3420_SPI_REG_SHIFT 3
  39. #define MAX3420_REG_EP0FIFO 0
  40. #define MAX3420_REG_EP1FIFO 1
  41. #define MAX3420_REG_EP2FIFO 2
  42. #define MAX3420_REG_EP3FIFO 3
  43. #define MAX3420_REG_SUDFIFO 4
  44. #define MAX3420_REG_EP0BC 5
  45. #define MAX3420_REG_EP1BC 6
  46. #define MAX3420_REG_EP2BC 7
  47. #define MAX3420_REG_EP3BC 8
  48. #define MAX3420_REG_EPSTALLS 9
  49. #define ACKSTAT BIT(6)
  50. #define STLSTAT BIT(5)
  51. #define STLEP3IN BIT(4)
  52. #define STLEP2IN BIT(3)
  53. #define STLEP1OUT BIT(2)
  54. #define STLEP0OUT BIT(1)
  55. #define STLEP0IN BIT(0)
  56. #define MAX3420_REG_CLRTOGS 10
  57. #define EP3DISAB BIT(7)
  58. #define EP2DISAB BIT(6)
  59. #define EP1DISAB BIT(5)
  60. #define CTGEP3IN BIT(4)
  61. #define CTGEP2IN BIT(3)
  62. #define CTGEP1OUT BIT(2)
  63. #define MAX3420_REG_EPIRQ 11
  64. #define MAX3420_REG_EPIEN 12
  65. #define SUDAVIRQ BIT(5)
  66. #define IN3BAVIRQ BIT(4)
  67. #define IN2BAVIRQ BIT(3)
  68. #define OUT1DAVIRQ BIT(2)
  69. #define OUT0DAVIRQ BIT(1)
  70. #define IN0BAVIRQ BIT(0)
  71. #define MAX3420_REG_USBIRQ 13
  72. #define MAX3420_REG_USBIEN 14
  73. #define OSCOKIRQ BIT(0)
  74. #define RWUDNIRQ BIT(1)
  75. #define BUSACTIRQ BIT(2)
  76. #define URESIRQ BIT(3)
  77. #define SUSPIRQ BIT(4)
  78. #define NOVBUSIRQ BIT(5)
  79. #define VBUSIRQ BIT(6)
  80. #define URESDNIRQ BIT(7)
  81. #define MAX3420_REG_USBCTL 15
  82. #define HOSCSTEN BIT(7)
  83. #define VBGATE BIT(6)
  84. #define CHIPRES BIT(5)
  85. #define PWRDOWN BIT(4)
  86. #define CONNECT BIT(3)
  87. #define SIGRWU BIT(2)
  88. #define MAX3420_REG_CPUCTL 16
  89. #define IE BIT(0)
  90. #define MAX3420_REG_PINCTL 17
  91. #define EP3INAK BIT(7)
  92. #define EP2INAK BIT(6)
  93. #define EP0INAK BIT(5)
  94. #define FDUPSPI BIT(4)
  95. #define INTLEVEL BIT(3)
  96. #define POSINT BIT(2)
  97. #define GPXB BIT(1)
  98. #define GPXA BIT(0)
  99. #define MAX3420_REG_REVISION 18
  100. #define MAX3420_REG_FNADDR 19
  101. #define FNADDR_MASK 0x7f
  102. #define MAX3420_REG_IOPINS 20
  103. #define MAX3420_REG_IOPINS2 21
  104. #define MAX3420_REG_GPINIRQ 22
  105. #define MAX3420_REG_GPINIEN 23
  106. #define MAX3420_REG_GPINPOL 24
  107. #define MAX3420_REG_HIRQ 25
  108. #define MAX3420_REG_HIEN 26
  109. #define MAX3420_REG_MODE 27
  110. #define MAX3420_REG_PERADDR 28
  111. #define MAX3420_REG_HCTL 29
  112. #define MAX3420_REG_HXFR 30
  113. #define MAX3420_REG_HRSL 31
  114. #define ENABLE_IRQ BIT(0)
  115. #define IOPIN_UPDATE BIT(1)
  116. #define REMOTE_WAKEUP BIT(2)
  117. #define CONNECT_HOST GENMASK(4, 3)
  118. #define HCONNECT (1 << 3)
  119. #define HDISCONNECT (3 << 3)
  120. #define UDC_START GENMASK(6, 5)
  121. #define START (1 << 5)
  122. #define STOP (3 << 5)
  123. #define ENABLE_EP GENMASK(8, 7)
  124. #define ENABLE (1 << 7)
  125. #define DISABLE (3 << 7)
  126. #define STALL_EP GENMASK(10, 9)
  127. #define STALL (1 << 9)
  128. #define UNSTALL (3 << 9)
  129. #define MAX3420_CMD(c) FIELD_PREP(GENMASK(7, 3), c)
  130. #define MAX3420_SPI_CMD_RD(c) (MAX3420_CMD(c) | (0 << 1))
  131. #define MAX3420_SPI_CMD_WR(c) (MAX3420_CMD(c) | (1 << 1))
  132. struct max3420_req {
  133. struct usb_request usb_req;
  134. struct list_head queue;
  135. struct max3420_ep *ep;
  136. };
  137. struct max3420_ep {
  138. struct usb_ep ep_usb;
  139. struct max3420_udc *udc;
  140. struct list_head queue;
  141. char name[MAX3420_EPNAME_SIZE];
  142. unsigned int maxpacket;
  143. spinlock_t lock;
  144. int halted;
  145. u32 todo;
  146. int id;
  147. };
  148. struct max3420_udc {
  149. struct usb_gadget gadget;
  150. struct max3420_ep ep[MAX3420_MAX_EPS];
  151. struct usb_gadget_driver *driver;
  152. struct task_struct *thread_task;
  153. int remote_wkp, is_selfpowered;
  154. bool vbus_active, softconnect;
  155. struct usb_ctrlrequest setup;
  156. struct mutex spi_bus_mutex;
  157. struct max3420_req ep0req;
  158. struct spi_device *spi;
  159. struct device *dev;
  160. spinlock_t lock;
  161. bool suspended;
  162. u8 ep0buf[64];
  163. u32 todo;
  164. };
  165. #define to_max3420_req(r) container_of((r), struct max3420_req, usb_req)
  166. #define to_max3420_ep(e) container_of((e), struct max3420_ep, ep_usb)
  167. #define to_udc(g) container_of((g), struct max3420_udc, gadget)
  168. #define DRIVER_DESC "MAX3420 USB Device-Mode Driver"
  169. static const char driver_name[] = "max3420-udc";
  170. /* Control endpoint configuration.*/
  171. static const struct usb_endpoint_descriptor ep0_desc = {
  172. .bEndpointAddress = USB_DIR_OUT,
  173. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  174. .wMaxPacketSize = cpu_to_le16(MAX3420_EP_MAX_PACKET),
  175. };
  176. static void spi_ack_ctrl(struct max3420_udc *udc)
  177. {
  178. struct spi_device *spi = udc->spi;
  179. struct spi_transfer transfer;
  180. struct spi_message msg;
  181. u8 txdata[1];
  182. memset(&transfer, 0, sizeof(transfer));
  183. spi_message_init(&msg);
  184. txdata[0] = MAX3420_ACKSTAT;
  185. transfer.tx_buf = txdata;
  186. transfer.len = 1;
  187. spi_message_add_tail(&transfer, &msg);
  188. spi_sync(spi, &msg);
  189. }
  190. static u8 spi_rd8_ack(struct max3420_udc *udc, u8 reg, int actstat)
  191. {
  192. struct spi_device *spi = udc->spi;
  193. struct spi_transfer transfer;
  194. struct spi_message msg;
  195. u8 txdata[2], rxdata[2];
  196. memset(&transfer, 0, sizeof(transfer));
  197. spi_message_init(&msg);
  198. txdata[0] = MAX3420_SPI_CMD_RD(reg) | (actstat ? MAX3420_ACKSTAT : 0);
  199. transfer.tx_buf = txdata;
  200. transfer.rx_buf = rxdata;
  201. transfer.len = 2;
  202. spi_message_add_tail(&transfer, &msg);
  203. spi_sync(spi, &msg);
  204. return rxdata[1];
  205. }
  206. static u8 spi_rd8(struct max3420_udc *udc, u8 reg)
  207. {
  208. return spi_rd8_ack(udc, reg, 0);
  209. }
  210. static void spi_wr8_ack(struct max3420_udc *udc, u8 reg, u8 val, int actstat)
  211. {
  212. struct spi_device *spi = udc->spi;
  213. struct spi_transfer transfer;
  214. struct spi_message msg;
  215. u8 txdata[2];
  216. memset(&transfer, 0, sizeof(transfer));
  217. spi_message_init(&msg);
  218. txdata[0] = MAX3420_SPI_CMD_WR(reg) | (actstat ? MAX3420_ACKSTAT : 0);
  219. txdata[1] = val;
  220. transfer.tx_buf = txdata;
  221. transfer.len = 2;
  222. spi_message_add_tail(&transfer, &msg);
  223. spi_sync(spi, &msg);
  224. }
  225. static void spi_wr8(struct max3420_udc *udc, u8 reg, u8 val)
  226. {
  227. spi_wr8_ack(udc, reg, val, 0);
  228. }
  229. static void spi_rd_buf(struct max3420_udc *udc, u8 reg, void *buf, u8 len)
  230. {
  231. struct spi_device *spi = udc->spi;
  232. struct spi_transfer transfer;
  233. struct spi_message msg;
  234. u8 local_buf[MAX3420_EP_MAX_PACKET + 1] = {};
  235. memset(&transfer, 0, sizeof(transfer));
  236. spi_message_init(&msg);
  237. local_buf[0] = MAX3420_SPI_CMD_RD(reg);
  238. transfer.tx_buf = &local_buf[0];
  239. transfer.rx_buf = &local_buf[0];
  240. transfer.len = len + 1;
  241. spi_message_add_tail(&transfer, &msg);
  242. spi_sync(spi, &msg);
  243. memcpy(buf, &local_buf[1], len);
  244. }
  245. static void spi_wr_buf(struct max3420_udc *udc, u8 reg, void *buf, u8 len)
  246. {
  247. struct spi_device *spi = udc->spi;
  248. struct spi_transfer transfer;
  249. struct spi_message msg;
  250. u8 local_buf[MAX3420_EP_MAX_PACKET + 1] = {};
  251. memset(&transfer, 0, sizeof(transfer));
  252. spi_message_init(&msg);
  253. local_buf[0] = MAX3420_SPI_CMD_WR(reg);
  254. memcpy(&local_buf[1], buf, len);
  255. transfer.tx_buf = local_buf;
  256. transfer.len = len + 1;
  257. spi_message_add_tail(&transfer, &msg);
  258. spi_sync(spi, &msg);
  259. }
  260. static int spi_max3420_enable(struct max3420_ep *ep)
  261. {
  262. struct max3420_udc *udc = ep->udc;
  263. unsigned long flags;
  264. u8 epdis, epien;
  265. int todo;
  266. spin_lock_irqsave(&ep->lock, flags);
  267. todo = ep->todo & ENABLE_EP;
  268. ep->todo &= ~ENABLE_EP;
  269. spin_unlock_irqrestore(&ep->lock, flags);
  270. if (!todo || ep->id == 0)
  271. return false;
  272. epien = spi_rd8(udc, MAX3420_REG_EPIEN);
  273. epdis = spi_rd8(udc, MAX3420_REG_CLRTOGS);
  274. if (todo == ENABLE) {
  275. epdis &= ~BIT(ep->id + 4);
  276. epien |= BIT(ep->id + 1);
  277. } else {
  278. epdis |= BIT(ep->id + 4);
  279. epien &= ~BIT(ep->id + 1);
  280. }
  281. spi_wr8(udc, MAX3420_REG_CLRTOGS, epdis);
  282. spi_wr8(udc, MAX3420_REG_EPIEN, epien);
  283. return true;
  284. }
  285. static int spi_max3420_stall(struct max3420_ep *ep)
  286. {
  287. struct max3420_udc *udc = ep->udc;
  288. unsigned long flags;
  289. u8 epstalls;
  290. int todo;
  291. spin_lock_irqsave(&ep->lock, flags);
  292. todo = ep->todo & STALL_EP;
  293. ep->todo &= ~STALL_EP;
  294. spin_unlock_irqrestore(&ep->lock, flags);
  295. if (!todo || ep->id == 0)
  296. return false;
  297. epstalls = spi_rd8(udc, MAX3420_REG_EPSTALLS);
  298. if (todo == STALL) {
  299. ep->halted = 1;
  300. epstalls |= BIT(ep->id + 1);
  301. } else {
  302. u8 clrtogs;
  303. ep->halted = 0;
  304. epstalls &= ~BIT(ep->id + 1);
  305. clrtogs = spi_rd8(udc, MAX3420_REG_CLRTOGS);
  306. clrtogs |= BIT(ep->id + 1);
  307. spi_wr8(udc, MAX3420_REG_CLRTOGS, clrtogs);
  308. }
  309. spi_wr8(udc, MAX3420_REG_EPSTALLS, epstalls | ACKSTAT);
  310. return true;
  311. }
  312. static int spi_max3420_rwkup(struct max3420_udc *udc)
  313. {
  314. unsigned long flags;
  315. int wake_remote;
  316. u8 usbctl;
  317. spin_lock_irqsave(&udc->lock, flags);
  318. wake_remote = udc->todo & REMOTE_WAKEUP;
  319. udc->todo &= ~REMOTE_WAKEUP;
  320. spin_unlock_irqrestore(&udc->lock, flags);
  321. if (!wake_remote || !udc->suspended)
  322. return false;
  323. /* Set Remote-WkUp Signal*/
  324. usbctl = spi_rd8(udc, MAX3420_REG_USBCTL);
  325. usbctl |= SIGRWU;
  326. spi_wr8(udc, MAX3420_REG_USBCTL, usbctl);
  327. msleep_interruptible(5);
  328. /* Clear Remote-WkUp Signal*/
  329. usbctl = spi_rd8(udc, MAX3420_REG_USBCTL);
  330. usbctl &= ~SIGRWU;
  331. spi_wr8(udc, MAX3420_REG_USBCTL, usbctl);
  332. udc->suspended = false;
  333. return true;
  334. }
  335. static void max3420_nuke(struct max3420_ep *ep, int status);
  336. static void __max3420_stop(struct max3420_udc *udc)
  337. {
  338. u8 val;
  339. int i;
  340. /* clear all pending requests */
  341. for (i = 1; i < MAX3420_MAX_EPS; i++)
  342. max3420_nuke(&udc->ep[i], -ECONNRESET);
  343. /* Disable IRQ to CPU */
  344. spi_wr8(udc, MAX3420_REG_CPUCTL, 0);
  345. val = spi_rd8(udc, MAX3420_REG_USBCTL);
  346. val |= PWRDOWN;
  347. if (udc->is_selfpowered)
  348. val &= ~HOSCSTEN;
  349. else
  350. val |= HOSCSTEN;
  351. spi_wr8(udc, MAX3420_REG_USBCTL, val);
  352. }
  353. static void __max3420_start(struct max3420_udc *udc)
  354. {
  355. u8 val;
  356. /* Need this delay if bus-powered,
  357. * but even for self-powered it helps stability
  358. */
  359. msleep_interruptible(250);
  360. /* configure SPI */
  361. spi_wr8(udc, MAX3420_REG_PINCTL, FDUPSPI);
  362. /* Chip Reset */
  363. spi_wr8(udc, MAX3420_REG_USBCTL, CHIPRES);
  364. msleep_interruptible(5);
  365. spi_wr8(udc, MAX3420_REG_USBCTL, 0);
  366. /* Poll for OSC to stabilize */
  367. while (1) {
  368. val = spi_rd8(udc, MAX3420_REG_USBIRQ);
  369. if (val & OSCOKIRQ)
  370. break;
  371. cond_resched();
  372. }
  373. /* Enable PULL-UP only when Vbus detected */
  374. val = spi_rd8(udc, MAX3420_REG_USBCTL);
  375. val |= VBGATE | CONNECT;
  376. spi_wr8(udc, MAX3420_REG_USBCTL, val);
  377. val = URESDNIRQ | URESIRQ;
  378. if (udc->is_selfpowered)
  379. val |= NOVBUSIRQ;
  380. spi_wr8(udc, MAX3420_REG_USBIEN, val);
  381. /* Enable only EP0 interrupts */
  382. val = IN0BAVIRQ | OUT0DAVIRQ | SUDAVIRQ;
  383. spi_wr8(udc, MAX3420_REG_EPIEN, val);
  384. /* Enable IRQ to CPU */
  385. spi_wr8(udc, MAX3420_REG_CPUCTL, IE);
  386. }
  387. static int max3420_start(struct max3420_udc *udc)
  388. {
  389. unsigned long flags;
  390. int todo;
  391. spin_lock_irqsave(&udc->lock, flags);
  392. todo = udc->todo & UDC_START;
  393. udc->todo &= ~UDC_START;
  394. spin_unlock_irqrestore(&udc->lock, flags);
  395. if (!todo)
  396. return false;
  397. if (udc->vbus_active && udc->softconnect)
  398. __max3420_start(udc);
  399. else
  400. __max3420_stop(udc);
  401. return true;
  402. }
  403. static irqreturn_t max3420_vbus_handler(int irq, void *dev_id)
  404. {
  405. struct max3420_udc *udc = dev_id;
  406. unsigned long flags;
  407. spin_lock_irqsave(&udc->lock, flags);
  408. /* its a vbus change interrupt */
  409. udc->vbus_active = !udc->vbus_active;
  410. udc->todo |= UDC_START;
  411. usb_udc_vbus_handler(&udc->gadget, udc->vbus_active);
  412. usb_gadget_set_state(&udc->gadget, udc->vbus_active
  413. ? USB_STATE_POWERED : USB_STATE_NOTATTACHED);
  414. spin_unlock_irqrestore(&udc->lock, flags);
  415. if (udc->thread_task)
  416. wake_up_process(udc->thread_task);
  417. return IRQ_HANDLED;
  418. }
  419. static irqreturn_t max3420_irq_handler(int irq, void *dev_id)
  420. {
  421. struct max3420_udc *udc = dev_id;
  422. struct spi_device *spi = udc->spi;
  423. unsigned long flags;
  424. spin_lock_irqsave(&udc->lock, flags);
  425. if ((udc->todo & ENABLE_IRQ) == 0) {
  426. disable_irq_nosync(spi->irq);
  427. udc->todo |= ENABLE_IRQ;
  428. }
  429. spin_unlock_irqrestore(&udc->lock, flags);
  430. if (udc->thread_task)
  431. wake_up_process(udc->thread_task);
  432. return IRQ_HANDLED;
  433. }
  434. static void max3420_getstatus(struct max3420_udc *udc)
  435. {
  436. struct max3420_ep *ep;
  437. u16 status = 0;
  438. switch (udc->setup.bRequestType & USB_RECIP_MASK) {
  439. case USB_RECIP_DEVICE:
  440. /* Get device status */
  441. status = udc->gadget.is_selfpowered << USB_DEVICE_SELF_POWERED;
  442. status |= (udc->remote_wkp << USB_DEVICE_REMOTE_WAKEUP);
  443. break;
  444. case USB_RECIP_INTERFACE:
  445. if (udc->driver->setup(&udc->gadget, &udc->setup) < 0)
  446. goto stall;
  447. break;
  448. case USB_RECIP_ENDPOINT:
  449. ep = &udc->ep[udc->setup.wIndex & USB_ENDPOINT_NUMBER_MASK];
  450. if (udc->setup.wIndex & USB_DIR_IN) {
  451. if (!ep->ep_usb.caps.dir_in)
  452. goto stall;
  453. } else {
  454. if (!ep->ep_usb.caps.dir_out)
  455. goto stall;
  456. }
  457. if (ep->halted)
  458. status = 1 << USB_ENDPOINT_HALT;
  459. break;
  460. default:
  461. goto stall;
  462. }
  463. status = cpu_to_le16(status);
  464. spi_wr_buf(udc, MAX3420_REG_EP0FIFO, &status, 2);
  465. spi_wr8_ack(udc, MAX3420_REG_EP0BC, 2, 1);
  466. return;
  467. stall:
  468. dev_err(udc->dev, "Can't respond to getstatus request\n");
  469. spi_wr8(udc, MAX3420_REG_EPSTALLS, STLEP0IN | STLEP0OUT | STLSTAT);
  470. }
  471. static void max3420_set_clear_feature(struct max3420_udc *udc)
  472. {
  473. struct max3420_ep *ep;
  474. int set = udc->setup.bRequest == USB_REQ_SET_FEATURE;
  475. unsigned long flags;
  476. int id;
  477. switch (udc->setup.bRequestType) {
  478. case USB_RECIP_DEVICE:
  479. if (udc->setup.wValue != USB_DEVICE_REMOTE_WAKEUP)
  480. break;
  481. if (udc->setup.bRequest == USB_REQ_SET_FEATURE)
  482. udc->remote_wkp = 1;
  483. else
  484. udc->remote_wkp = 0;
  485. return spi_ack_ctrl(udc);
  486. case USB_RECIP_ENDPOINT:
  487. if (udc->setup.wValue != USB_ENDPOINT_HALT)
  488. break;
  489. id = udc->setup.wIndex & USB_ENDPOINT_NUMBER_MASK;
  490. ep = &udc->ep[id];
  491. spin_lock_irqsave(&ep->lock, flags);
  492. ep->todo &= ~STALL_EP;
  493. if (set)
  494. ep->todo |= STALL;
  495. else
  496. ep->todo |= UNSTALL;
  497. spin_unlock_irqrestore(&ep->lock, flags);
  498. spi_max3420_stall(ep);
  499. return;
  500. default:
  501. break;
  502. }
  503. dev_err(udc->dev, "Can't respond to SET/CLEAR FEATURE\n");
  504. spi_wr8(udc, MAX3420_REG_EPSTALLS, STLEP0IN | STLEP0OUT | STLSTAT);
  505. }
  506. static void max3420_handle_setup(struct max3420_udc *udc)
  507. {
  508. struct usb_ctrlrequest setup;
  509. spi_rd_buf(udc, MAX3420_REG_SUDFIFO, (void *)&setup, 8);
  510. udc->setup = setup;
  511. udc->setup.wValue = cpu_to_le16(setup.wValue);
  512. udc->setup.wIndex = cpu_to_le16(setup.wIndex);
  513. udc->setup.wLength = cpu_to_le16(setup.wLength);
  514. switch (udc->setup.bRequest) {
  515. case USB_REQ_GET_STATUS:
  516. /* Data+Status phase form udc */
  517. if ((udc->setup.bRequestType &
  518. (USB_DIR_IN | USB_TYPE_MASK)) !=
  519. (USB_DIR_IN | USB_TYPE_STANDARD)) {
  520. break;
  521. }
  522. return max3420_getstatus(udc);
  523. case USB_REQ_SET_ADDRESS:
  524. /* Status phase from udc */
  525. if (udc->setup.bRequestType != (USB_DIR_OUT |
  526. USB_TYPE_STANDARD | USB_RECIP_DEVICE)) {
  527. break;
  528. }
  529. spi_rd8_ack(udc, MAX3420_REG_FNADDR, 1);
  530. dev_dbg(udc->dev, "Assigned Address=%d\n", udc->setup.wValue);
  531. return;
  532. case USB_REQ_CLEAR_FEATURE:
  533. case USB_REQ_SET_FEATURE:
  534. /* Requests with no data phase, status phase from udc */
  535. if ((udc->setup.bRequestType & USB_TYPE_MASK)
  536. != USB_TYPE_STANDARD)
  537. break;
  538. return max3420_set_clear_feature(udc);
  539. default:
  540. break;
  541. }
  542. if (udc->driver->setup(&udc->gadget, &setup) < 0) {
  543. /* Stall EP0 */
  544. spi_wr8(udc, MAX3420_REG_EPSTALLS,
  545. STLEP0IN | STLEP0OUT | STLSTAT);
  546. }
  547. }
  548. static void max3420_req_done(struct max3420_req *req, int status)
  549. {
  550. struct max3420_ep *ep = req->ep;
  551. struct max3420_udc *udc = ep->udc;
  552. if (req->usb_req.status == -EINPROGRESS)
  553. req->usb_req.status = status;
  554. else
  555. status = req->usb_req.status;
  556. if (status && status != -ESHUTDOWN)
  557. dev_err(udc->dev, "%s done %p, status %d\n",
  558. ep->ep_usb.name, req, status);
  559. if (req->usb_req.complete)
  560. req->usb_req.complete(&ep->ep_usb, &req->usb_req);
  561. }
  562. static int max3420_do_data(struct max3420_udc *udc, int ep_id, int in)
  563. {
  564. struct max3420_ep *ep = &udc->ep[ep_id];
  565. struct max3420_req *req;
  566. int done, length, psz;
  567. void *buf;
  568. if (list_empty(&ep->queue))
  569. return false;
  570. req = list_first_entry(&ep->queue, struct max3420_req, queue);
  571. buf = req->usb_req.buf + req->usb_req.actual;
  572. psz = ep->ep_usb.maxpacket;
  573. length = req->usb_req.length - req->usb_req.actual;
  574. length = min(length, psz);
  575. if (length == 0) {
  576. done = 1;
  577. goto xfer_done;
  578. }
  579. done = 0;
  580. if (in) {
  581. prefetch(buf);
  582. spi_wr_buf(udc, MAX3420_REG_EP0FIFO + ep_id, buf, length);
  583. spi_wr8(udc, MAX3420_REG_EP0BC + ep_id, length);
  584. if (length < psz)
  585. done = 1;
  586. } else {
  587. psz = spi_rd8(udc, MAX3420_REG_EP0BC + ep_id);
  588. length = min(length, psz);
  589. prefetchw(buf);
  590. spi_rd_buf(udc, MAX3420_REG_EP0FIFO + ep_id, buf, length);
  591. if (length < ep->ep_usb.maxpacket)
  592. done = 1;
  593. }
  594. req->usb_req.actual += length;
  595. if (req->usb_req.actual == req->usb_req.length)
  596. done = 1;
  597. xfer_done:
  598. if (done) {
  599. unsigned long flags;
  600. spin_lock_irqsave(&ep->lock, flags);
  601. list_del_init(&req->queue);
  602. spin_unlock_irqrestore(&ep->lock, flags);
  603. if (ep_id == 0)
  604. spi_ack_ctrl(udc);
  605. max3420_req_done(req, 0);
  606. }
  607. return true;
  608. }
  609. static int max3420_handle_irqs(struct max3420_udc *udc)
  610. {
  611. u8 epien, epirq, usbirq, usbien, reg[4];
  612. bool ret = false;
  613. spi_rd_buf(udc, MAX3420_REG_EPIRQ, reg, 4);
  614. epirq = reg[0];
  615. epien = reg[1];
  616. usbirq = reg[2];
  617. usbien = reg[3];
  618. usbirq &= usbien;
  619. epirq &= epien;
  620. if (epirq & SUDAVIRQ) {
  621. spi_wr8(udc, MAX3420_REG_EPIRQ, SUDAVIRQ);
  622. max3420_handle_setup(udc);
  623. return true;
  624. }
  625. if (usbirq & VBUSIRQ) {
  626. spi_wr8(udc, MAX3420_REG_USBIRQ, VBUSIRQ);
  627. dev_dbg(udc->dev, "Cable plugged in\n");
  628. return true;
  629. }
  630. if (usbirq & NOVBUSIRQ) {
  631. spi_wr8(udc, MAX3420_REG_USBIRQ, NOVBUSIRQ);
  632. dev_dbg(udc->dev, "Cable pulled out\n");
  633. return true;
  634. }
  635. if (usbirq & URESIRQ) {
  636. spi_wr8(udc, MAX3420_REG_USBIRQ, URESIRQ);
  637. dev_dbg(udc->dev, "USB Reset - Start\n");
  638. return true;
  639. }
  640. if (usbirq & URESDNIRQ) {
  641. spi_wr8(udc, MAX3420_REG_USBIRQ, URESDNIRQ);
  642. dev_dbg(udc->dev, "USB Reset - END\n");
  643. spi_wr8(udc, MAX3420_REG_USBIEN, URESDNIRQ | URESIRQ);
  644. spi_wr8(udc, MAX3420_REG_EPIEN, SUDAVIRQ | IN0BAVIRQ
  645. | OUT0DAVIRQ);
  646. return true;
  647. }
  648. if (usbirq & SUSPIRQ) {
  649. spi_wr8(udc, MAX3420_REG_USBIRQ, SUSPIRQ);
  650. dev_dbg(udc->dev, "USB Suspend - Enter\n");
  651. udc->suspended = true;
  652. return true;
  653. }
  654. if (usbirq & BUSACTIRQ) {
  655. spi_wr8(udc, MAX3420_REG_USBIRQ, BUSACTIRQ);
  656. dev_dbg(udc->dev, "USB Suspend - Exit\n");
  657. udc->suspended = false;
  658. return true;
  659. }
  660. if (usbirq & RWUDNIRQ) {
  661. spi_wr8(udc, MAX3420_REG_USBIRQ, RWUDNIRQ);
  662. dev_dbg(udc->dev, "Asked Host to wakeup\n");
  663. return true;
  664. }
  665. if (usbirq & OSCOKIRQ) {
  666. spi_wr8(udc, MAX3420_REG_USBIRQ, OSCOKIRQ);
  667. dev_dbg(udc->dev, "Osc stabilized, start work\n");
  668. return true;
  669. }
  670. if (epirq & OUT0DAVIRQ && max3420_do_data(udc, 0, 0)) {
  671. spi_wr8_ack(udc, MAX3420_REG_EPIRQ, OUT0DAVIRQ, 1);
  672. ret = true;
  673. }
  674. if (epirq & IN0BAVIRQ && max3420_do_data(udc, 0, 1))
  675. ret = true;
  676. if (epirq & OUT1DAVIRQ && max3420_do_data(udc, 1, 0)) {
  677. spi_wr8_ack(udc, MAX3420_REG_EPIRQ, OUT1DAVIRQ, 1);
  678. ret = true;
  679. }
  680. if (epirq & IN2BAVIRQ && max3420_do_data(udc, 2, 1))
  681. ret = true;
  682. if (epirq & IN3BAVIRQ && max3420_do_data(udc, 3, 1))
  683. ret = true;
  684. return ret;
  685. }
  686. static int max3420_thread(void *dev_id)
  687. {
  688. struct max3420_udc *udc = dev_id;
  689. struct spi_device *spi = udc->spi;
  690. int i, loop_again = 1;
  691. unsigned long flags;
  692. while (!kthread_should_stop()) {
  693. if (!loop_again) {
  694. ktime_t kt = ns_to_ktime(1000 * 1000 * 250); /* 250ms */
  695. set_current_state(TASK_INTERRUPTIBLE);
  696. spin_lock_irqsave(&udc->lock, flags);
  697. if (udc->todo & ENABLE_IRQ) {
  698. enable_irq(spi->irq);
  699. udc->todo &= ~ENABLE_IRQ;
  700. }
  701. spin_unlock_irqrestore(&udc->lock, flags);
  702. schedule_hrtimeout(&kt, HRTIMER_MODE_REL);
  703. }
  704. loop_again = 0;
  705. mutex_lock(&udc->spi_bus_mutex);
  706. /* If bus-vbus_active and disconnected */
  707. if (!udc->vbus_active || !udc->softconnect)
  708. goto loop;
  709. if (max3420_start(udc)) {
  710. loop_again = 1;
  711. goto loop;
  712. }
  713. if (max3420_handle_irqs(udc)) {
  714. loop_again = 1;
  715. goto loop;
  716. }
  717. if (spi_max3420_rwkup(udc)) {
  718. loop_again = 1;
  719. goto loop;
  720. }
  721. max3420_do_data(udc, 0, 1); /* get done with the EP0 ZLP */
  722. for (i = 1; i < MAX3420_MAX_EPS; i++) {
  723. struct max3420_ep *ep = &udc->ep[i];
  724. if (spi_max3420_enable(ep))
  725. loop_again = 1;
  726. if (spi_max3420_stall(ep))
  727. loop_again = 1;
  728. }
  729. loop:
  730. mutex_unlock(&udc->spi_bus_mutex);
  731. }
  732. set_current_state(TASK_RUNNING);
  733. dev_info(udc->dev, "SPI thread exiting\n");
  734. return 0;
  735. }
  736. static int max3420_ep_set_halt(struct usb_ep *_ep, int stall)
  737. {
  738. struct max3420_ep *ep = to_max3420_ep(_ep);
  739. struct max3420_udc *udc = ep->udc;
  740. unsigned long flags;
  741. spin_lock_irqsave(&ep->lock, flags);
  742. ep->todo &= ~STALL_EP;
  743. if (stall)
  744. ep->todo |= STALL;
  745. else
  746. ep->todo |= UNSTALL;
  747. spin_unlock_irqrestore(&ep->lock, flags);
  748. wake_up_process(udc->thread_task);
  749. dev_dbg(udc->dev, "%sStall %s\n", stall ? "" : "Un", ep->name);
  750. return 0;
  751. }
  752. static int __max3420_ep_enable(struct max3420_ep *ep,
  753. const struct usb_endpoint_descriptor *desc)
  754. {
  755. unsigned int maxp = usb_endpoint_maxp(desc);
  756. unsigned long flags;
  757. spin_lock_irqsave(&ep->lock, flags);
  758. ep->ep_usb.desc = desc;
  759. ep->ep_usb.maxpacket = maxp;
  760. ep->todo &= ~ENABLE_EP;
  761. ep->todo |= ENABLE;
  762. spin_unlock_irqrestore(&ep->lock, flags);
  763. return 0;
  764. }
  765. static int max3420_ep_enable(struct usb_ep *_ep,
  766. const struct usb_endpoint_descriptor *desc)
  767. {
  768. struct max3420_ep *ep = to_max3420_ep(_ep);
  769. struct max3420_udc *udc = ep->udc;
  770. __max3420_ep_enable(ep, desc);
  771. wake_up_process(udc->thread_task);
  772. return 0;
  773. }
  774. static void max3420_nuke(struct max3420_ep *ep, int status)
  775. {
  776. struct max3420_req *req, *r;
  777. unsigned long flags;
  778. spin_lock_irqsave(&ep->lock, flags);
  779. list_for_each_entry_safe(req, r, &ep->queue, queue) {
  780. list_del_init(&req->queue);
  781. spin_unlock_irqrestore(&ep->lock, flags);
  782. max3420_req_done(req, status);
  783. spin_lock_irqsave(&ep->lock, flags);
  784. }
  785. spin_unlock_irqrestore(&ep->lock, flags);
  786. }
  787. static void __max3420_ep_disable(struct max3420_ep *ep)
  788. {
  789. struct max3420_udc *udc = ep->udc;
  790. unsigned long flags;
  791. spin_lock_irqsave(&ep->lock, flags);
  792. ep->ep_usb.desc = NULL;
  793. ep->todo &= ~ENABLE_EP;
  794. ep->todo |= DISABLE;
  795. spin_unlock_irqrestore(&ep->lock, flags);
  796. dev_dbg(udc->dev, "Disabled %s\n", ep->name);
  797. }
  798. static int max3420_ep_disable(struct usb_ep *_ep)
  799. {
  800. struct max3420_ep *ep = to_max3420_ep(_ep);
  801. struct max3420_udc *udc = ep->udc;
  802. max3420_nuke(ep, -ESHUTDOWN);
  803. __max3420_ep_disable(ep);
  804. wake_up_process(udc->thread_task);
  805. return 0;
  806. }
  807. static struct usb_request *max3420_alloc_request(struct usb_ep *_ep,
  808. gfp_t gfp_flags)
  809. {
  810. struct max3420_ep *ep = to_max3420_ep(_ep);
  811. struct max3420_req *req;
  812. req = kzalloc(sizeof(*req), gfp_flags);
  813. if (!req)
  814. return NULL;
  815. req->ep = ep;
  816. return &req->usb_req;
  817. }
  818. static void max3420_free_request(struct usb_ep *_ep, struct usb_request *_req)
  819. {
  820. kfree(to_max3420_req(_req));
  821. }
  822. static int max3420_ep_queue(struct usb_ep *_ep, struct usb_request *_req,
  823. gfp_t ignored)
  824. {
  825. struct max3420_req *req = to_max3420_req(_req);
  826. struct max3420_ep *ep = to_max3420_ep(_ep);
  827. struct max3420_udc *udc = ep->udc;
  828. unsigned long flags;
  829. _req->status = -EINPROGRESS;
  830. _req->actual = 0;
  831. spin_lock_irqsave(&ep->lock, flags);
  832. list_add_tail(&req->queue, &ep->queue);
  833. spin_unlock_irqrestore(&ep->lock, flags);
  834. wake_up_process(udc->thread_task);
  835. return 0;
  836. }
  837. static int max3420_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  838. {
  839. struct max3420_req *t = NULL;
  840. struct max3420_req *req = to_max3420_req(_req);
  841. struct max3420_req *iter;
  842. struct max3420_ep *ep = to_max3420_ep(_ep);
  843. unsigned long flags;
  844. spin_lock_irqsave(&ep->lock, flags);
  845. /* Pluck the descriptor from queue */
  846. list_for_each_entry(iter, &ep->queue, queue) {
  847. if (iter != req)
  848. continue;
  849. list_del_init(&req->queue);
  850. t = iter;
  851. break;
  852. }
  853. spin_unlock_irqrestore(&ep->lock, flags);
  854. if (t)
  855. max3420_req_done(req, -ECONNRESET);
  856. return 0;
  857. }
  858. static const struct usb_ep_ops max3420_ep_ops = {
  859. .enable = max3420_ep_enable,
  860. .disable = max3420_ep_disable,
  861. .alloc_request = max3420_alloc_request,
  862. .free_request = max3420_free_request,
  863. .queue = max3420_ep_queue,
  864. .dequeue = max3420_ep_dequeue,
  865. .set_halt = max3420_ep_set_halt,
  866. };
  867. static int max3420_wakeup(struct usb_gadget *gadget)
  868. {
  869. struct max3420_udc *udc = to_udc(gadget);
  870. unsigned long flags;
  871. int ret = -EINVAL;
  872. spin_lock_irqsave(&udc->lock, flags);
  873. /* Only if wakeup allowed by host */
  874. if (udc->remote_wkp) {
  875. udc->todo |= REMOTE_WAKEUP;
  876. ret = 0;
  877. }
  878. spin_unlock_irqrestore(&udc->lock, flags);
  879. if (udc->thread_task)
  880. wake_up_process(udc->thread_task);
  881. return ret;
  882. }
  883. static int max3420_udc_start(struct usb_gadget *gadget,
  884. struct usb_gadget_driver *driver)
  885. {
  886. struct max3420_udc *udc = to_udc(gadget);
  887. unsigned long flags;
  888. spin_lock_irqsave(&udc->lock, flags);
  889. /* hook up the driver */
  890. udc->driver = driver;
  891. udc->gadget.speed = USB_SPEED_FULL;
  892. udc->gadget.is_selfpowered = udc->is_selfpowered;
  893. udc->remote_wkp = 0;
  894. udc->softconnect = true;
  895. udc->todo |= UDC_START;
  896. spin_unlock_irqrestore(&udc->lock, flags);
  897. if (udc->thread_task)
  898. wake_up_process(udc->thread_task);
  899. return 0;
  900. }
  901. static int max3420_udc_stop(struct usb_gadget *gadget)
  902. {
  903. struct max3420_udc *udc = to_udc(gadget);
  904. unsigned long flags;
  905. spin_lock_irqsave(&udc->lock, flags);
  906. udc->is_selfpowered = udc->gadget.is_selfpowered;
  907. udc->gadget.speed = USB_SPEED_UNKNOWN;
  908. udc->driver = NULL;
  909. udc->softconnect = false;
  910. udc->todo |= UDC_START;
  911. spin_unlock_irqrestore(&udc->lock, flags);
  912. if (udc->thread_task)
  913. wake_up_process(udc->thread_task);
  914. return 0;
  915. }
  916. static const struct usb_gadget_ops max3420_udc_ops = {
  917. .udc_start = max3420_udc_start,
  918. .udc_stop = max3420_udc_stop,
  919. .wakeup = max3420_wakeup,
  920. };
  921. static void max3420_eps_init(struct max3420_udc *udc)
  922. {
  923. int idx;
  924. INIT_LIST_HEAD(&udc->gadget.ep_list);
  925. for (idx = 0; idx < MAX3420_MAX_EPS; idx++) {
  926. struct max3420_ep *ep = &udc->ep[idx];
  927. spin_lock_init(&ep->lock);
  928. INIT_LIST_HEAD(&ep->queue);
  929. ep->udc = udc;
  930. ep->id = idx;
  931. ep->halted = 0;
  932. ep->maxpacket = 0;
  933. ep->ep_usb.name = ep->name;
  934. ep->ep_usb.ops = &max3420_ep_ops;
  935. usb_ep_set_maxpacket_limit(&ep->ep_usb, MAX3420_EP_MAX_PACKET);
  936. if (idx == 0) { /* For EP0 */
  937. ep->ep_usb.desc = &ep0_desc;
  938. ep->ep_usb.maxpacket = usb_endpoint_maxp(&ep0_desc);
  939. ep->ep_usb.caps.type_control = true;
  940. ep->ep_usb.caps.dir_in = true;
  941. ep->ep_usb.caps.dir_out = true;
  942. snprintf(ep->name, MAX3420_EPNAME_SIZE, "ep0");
  943. continue;
  944. }
  945. if (idx == 1) { /* EP1 is OUT */
  946. ep->ep_usb.caps.dir_in = false;
  947. ep->ep_usb.caps.dir_out = true;
  948. snprintf(ep->name, MAX3420_EPNAME_SIZE, "ep1-bulk-out");
  949. } else { /* EP2 & EP3 are IN */
  950. ep->ep_usb.caps.dir_in = true;
  951. ep->ep_usb.caps.dir_out = false;
  952. snprintf(ep->name, MAX3420_EPNAME_SIZE,
  953. "ep%d-bulk-in", idx);
  954. }
  955. ep->ep_usb.caps.type_iso = false;
  956. ep->ep_usb.caps.type_int = false;
  957. ep->ep_usb.caps.type_bulk = true;
  958. list_add_tail(&ep->ep_usb.ep_list,
  959. &udc->gadget.ep_list);
  960. }
  961. }
  962. static int max3420_probe(struct spi_device *spi)
  963. {
  964. struct max3420_udc *udc;
  965. int err, irq;
  966. u8 reg[8];
  967. if (spi->master->flags & SPI_MASTER_HALF_DUPLEX) {
  968. dev_err(&spi->dev, "UDC needs full duplex to work\n");
  969. return -EINVAL;
  970. }
  971. spi->mode = SPI_MODE_3;
  972. spi->bits_per_word = 8;
  973. err = spi_setup(spi);
  974. if (err) {
  975. dev_err(&spi->dev, "Unable to setup SPI bus\n");
  976. return -EFAULT;
  977. }
  978. udc = devm_kzalloc(&spi->dev, sizeof(*udc), GFP_KERNEL);
  979. if (!udc)
  980. return -ENOMEM;
  981. udc->spi = spi;
  982. udc->remote_wkp = 0;
  983. /* Setup gadget structure */
  984. udc->gadget.ops = &max3420_udc_ops;
  985. udc->gadget.max_speed = USB_SPEED_FULL;
  986. udc->gadget.speed = USB_SPEED_UNKNOWN;
  987. udc->gadget.ep0 = &udc->ep[0].ep_usb;
  988. udc->gadget.name = driver_name;
  989. spin_lock_init(&udc->lock);
  990. mutex_init(&udc->spi_bus_mutex);
  991. udc->ep0req.ep = &udc->ep[0];
  992. udc->ep0req.usb_req.buf = udc->ep0buf;
  993. INIT_LIST_HEAD(&udc->ep0req.queue);
  994. /* setup Endpoints */
  995. max3420_eps_init(udc);
  996. /* configure SPI */
  997. spi_rd_buf(udc, MAX3420_REG_EPIRQ, reg, 8);
  998. spi_wr8(udc, MAX3420_REG_PINCTL, FDUPSPI);
  999. err = usb_add_gadget_udc(&spi->dev, &udc->gadget);
  1000. if (err)
  1001. return err;
  1002. udc->dev = &udc->gadget.dev;
  1003. spi_set_drvdata(spi, udc);
  1004. irq = of_irq_get_byname(spi->dev.of_node, "udc");
  1005. err = devm_request_irq(&spi->dev, irq, max3420_irq_handler, 0,
  1006. "max3420", udc);
  1007. if (err < 0)
  1008. goto del_gadget;
  1009. udc->thread_task = kthread_create(max3420_thread, udc,
  1010. "max3420-thread");
  1011. if (IS_ERR(udc->thread_task)) {
  1012. err = PTR_ERR(udc->thread_task);
  1013. goto del_gadget;
  1014. }
  1015. irq = of_irq_get_byname(spi->dev.of_node, "vbus");
  1016. if (irq <= 0) { /* no vbus irq implies self-powered design */
  1017. udc->is_selfpowered = 1;
  1018. udc->vbus_active = true;
  1019. udc->todo |= UDC_START;
  1020. usb_udc_vbus_handler(&udc->gadget, udc->vbus_active);
  1021. usb_gadget_set_state(&udc->gadget, USB_STATE_POWERED);
  1022. max3420_start(udc);
  1023. } else {
  1024. udc->is_selfpowered = 0;
  1025. /* Detect current vbus status */
  1026. spi_rd_buf(udc, MAX3420_REG_EPIRQ, reg, 8);
  1027. if (reg[7] != 0xff)
  1028. udc->vbus_active = true;
  1029. err = devm_request_irq(&spi->dev, irq,
  1030. max3420_vbus_handler, 0, "vbus", udc);
  1031. if (err < 0)
  1032. goto del_gadget;
  1033. }
  1034. return 0;
  1035. del_gadget:
  1036. usb_del_gadget_udc(&udc->gadget);
  1037. return err;
  1038. }
  1039. static void max3420_remove(struct spi_device *spi)
  1040. {
  1041. struct max3420_udc *udc = spi_get_drvdata(spi);
  1042. unsigned long flags;
  1043. usb_del_gadget_udc(&udc->gadget);
  1044. spin_lock_irqsave(&udc->lock, flags);
  1045. kthread_stop(udc->thread_task);
  1046. spin_unlock_irqrestore(&udc->lock, flags);
  1047. }
  1048. static const struct of_device_id max3420_udc_of_match[] = {
  1049. { .compatible = "maxim,max3420-udc"},
  1050. { .compatible = "maxim,max3421-udc"},
  1051. {},
  1052. };
  1053. MODULE_DEVICE_TABLE(of, max3420_udc_of_match);
  1054. static struct spi_driver max3420_driver = {
  1055. .driver = {
  1056. .name = "max3420-udc",
  1057. .of_match_table = of_match_ptr(max3420_udc_of_match),
  1058. },
  1059. .probe = max3420_probe,
  1060. .remove = max3420_remove,
  1061. };
  1062. module_spi_driver(max3420_driver);
  1063. MODULE_DESCRIPTION(DRIVER_DESC);
  1064. MODULE_AUTHOR("Jassi Brar <[email protected]>");
  1065. MODULE_LICENSE("GPL");