m66592-udc.c 41 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * M66592 UDC (USB gadget)
  4. *
  5. * Copyright (C) 2006-2007 Renesas Solutions Corp.
  6. *
  7. * Author : Yoshihiro Shimoda <[email protected]>
  8. */
  9. #include <linux/module.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/delay.h>
  12. #include <linux/io.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/slab.h>
  15. #include <linux/err.h>
  16. #include <linux/usb/ch9.h>
  17. #include <linux/usb/gadget.h>
  18. #include "m66592-udc.h"
  19. MODULE_DESCRIPTION("M66592 USB gadget driver");
  20. MODULE_LICENSE("GPL");
  21. MODULE_AUTHOR("Yoshihiro Shimoda");
  22. MODULE_ALIAS("platform:m66592_udc");
  23. #define DRIVER_VERSION "21 July 2009"
  24. static const char udc_name[] = "m66592_udc";
  25. static const char *m66592_ep_name[] = {
  26. "ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7"
  27. };
  28. static void disable_controller(struct m66592 *m66592);
  29. static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req);
  30. static void irq_packet_write(struct m66592_ep *ep, struct m66592_request *req);
  31. static int m66592_queue(struct usb_ep *_ep, struct usb_request *_req,
  32. gfp_t gfp_flags);
  33. static void transfer_complete(struct m66592_ep *ep,
  34. struct m66592_request *req, int status);
  35. /*-------------------------------------------------------------------------*/
  36. static inline u16 get_usb_speed(struct m66592 *m66592)
  37. {
  38. return (m66592_read(m66592, M66592_DVSTCTR) & M66592_RHST);
  39. }
  40. static void enable_pipe_irq(struct m66592 *m66592, u16 pipenum,
  41. unsigned long reg)
  42. {
  43. u16 tmp;
  44. tmp = m66592_read(m66592, M66592_INTENB0);
  45. m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE,
  46. M66592_INTENB0);
  47. m66592_bset(m66592, (1 << pipenum), reg);
  48. m66592_write(m66592, tmp, M66592_INTENB0);
  49. }
  50. static void disable_pipe_irq(struct m66592 *m66592, u16 pipenum,
  51. unsigned long reg)
  52. {
  53. u16 tmp;
  54. tmp = m66592_read(m66592, M66592_INTENB0);
  55. m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE,
  56. M66592_INTENB0);
  57. m66592_bclr(m66592, (1 << pipenum), reg);
  58. m66592_write(m66592, tmp, M66592_INTENB0);
  59. }
  60. static void m66592_usb_connect(struct m66592 *m66592)
  61. {
  62. m66592_bset(m66592, M66592_CTRE, M66592_INTENB0);
  63. m66592_bset(m66592, M66592_WDST | M66592_RDST | M66592_CMPL,
  64. M66592_INTENB0);
  65. m66592_bset(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0);
  66. m66592_bset(m66592, M66592_DPRPU, M66592_SYSCFG);
  67. }
  68. static void m66592_usb_disconnect(struct m66592 *m66592)
  69. __releases(m66592->lock)
  70. __acquires(m66592->lock)
  71. {
  72. m66592_bclr(m66592, M66592_CTRE, M66592_INTENB0);
  73. m66592_bclr(m66592, M66592_WDST | M66592_RDST | M66592_CMPL,
  74. M66592_INTENB0);
  75. m66592_bclr(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0);
  76. m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
  77. m66592->gadget.speed = USB_SPEED_UNKNOWN;
  78. spin_unlock(&m66592->lock);
  79. m66592->driver->disconnect(&m66592->gadget);
  80. spin_lock(&m66592->lock);
  81. disable_controller(m66592);
  82. INIT_LIST_HEAD(&m66592->ep[0].queue);
  83. }
  84. static inline u16 control_reg_get_pid(struct m66592 *m66592, u16 pipenum)
  85. {
  86. u16 pid = 0;
  87. unsigned long offset;
  88. if (pipenum == 0)
  89. pid = m66592_read(m66592, M66592_DCPCTR) & M66592_PID;
  90. else if (pipenum < M66592_MAX_NUM_PIPE) {
  91. offset = get_pipectr_addr(pipenum);
  92. pid = m66592_read(m66592, offset) & M66592_PID;
  93. } else
  94. pr_err("unexpect pipe num (%d)\n", pipenum);
  95. return pid;
  96. }
  97. static inline void control_reg_set_pid(struct m66592 *m66592, u16 pipenum,
  98. u16 pid)
  99. {
  100. unsigned long offset;
  101. if (pipenum == 0)
  102. m66592_mdfy(m66592, pid, M66592_PID, M66592_DCPCTR);
  103. else if (pipenum < M66592_MAX_NUM_PIPE) {
  104. offset = get_pipectr_addr(pipenum);
  105. m66592_mdfy(m66592, pid, M66592_PID, offset);
  106. } else
  107. pr_err("unexpect pipe num (%d)\n", pipenum);
  108. }
  109. static inline void pipe_start(struct m66592 *m66592, u16 pipenum)
  110. {
  111. control_reg_set_pid(m66592, pipenum, M66592_PID_BUF);
  112. }
  113. static inline void pipe_stop(struct m66592 *m66592, u16 pipenum)
  114. {
  115. control_reg_set_pid(m66592, pipenum, M66592_PID_NAK);
  116. }
  117. static inline void pipe_stall(struct m66592 *m66592, u16 pipenum)
  118. {
  119. control_reg_set_pid(m66592, pipenum, M66592_PID_STALL);
  120. }
  121. static inline u16 control_reg_get(struct m66592 *m66592, u16 pipenum)
  122. {
  123. u16 ret = 0;
  124. unsigned long offset;
  125. if (pipenum == 0)
  126. ret = m66592_read(m66592, M66592_DCPCTR);
  127. else if (pipenum < M66592_MAX_NUM_PIPE) {
  128. offset = get_pipectr_addr(pipenum);
  129. ret = m66592_read(m66592, offset);
  130. } else
  131. pr_err("unexpect pipe num (%d)\n", pipenum);
  132. return ret;
  133. }
  134. static inline void control_reg_sqclr(struct m66592 *m66592, u16 pipenum)
  135. {
  136. unsigned long offset;
  137. pipe_stop(m66592, pipenum);
  138. if (pipenum == 0)
  139. m66592_bset(m66592, M66592_SQCLR, M66592_DCPCTR);
  140. else if (pipenum < M66592_MAX_NUM_PIPE) {
  141. offset = get_pipectr_addr(pipenum);
  142. m66592_bset(m66592, M66592_SQCLR, offset);
  143. } else
  144. pr_err("unexpect pipe num(%d)\n", pipenum);
  145. }
  146. static inline int get_buffer_size(struct m66592 *m66592, u16 pipenum)
  147. {
  148. u16 tmp;
  149. int size;
  150. if (pipenum == 0) {
  151. tmp = m66592_read(m66592, M66592_DCPCFG);
  152. if ((tmp & M66592_CNTMD) != 0)
  153. size = 256;
  154. else {
  155. tmp = m66592_read(m66592, M66592_DCPMAXP);
  156. size = tmp & M66592_MAXP;
  157. }
  158. } else {
  159. m66592_write(m66592, pipenum, M66592_PIPESEL);
  160. tmp = m66592_read(m66592, M66592_PIPECFG);
  161. if ((tmp & M66592_CNTMD) != 0) {
  162. tmp = m66592_read(m66592, M66592_PIPEBUF);
  163. size = ((tmp >> 10) + 1) * 64;
  164. } else {
  165. tmp = m66592_read(m66592, M66592_PIPEMAXP);
  166. size = tmp & M66592_MXPS;
  167. }
  168. }
  169. return size;
  170. }
  171. static inline void pipe_change(struct m66592 *m66592, u16 pipenum)
  172. {
  173. struct m66592_ep *ep = m66592->pipenum2ep[pipenum];
  174. unsigned short mbw;
  175. if (ep->use_dma)
  176. return;
  177. m66592_mdfy(m66592, pipenum, M66592_CURPIPE, ep->fifosel);
  178. ndelay(450);
  179. if (m66592->pdata->on_chip)
  180. mbw = M66592_MBW_32;
  181. else
  182. mbw = M66592_MBW_16;
  183. m66592_bset(m66592, mbw, ep->fifosel);
  184. }
  185. static int pipe_buffer_setting(struct m66592 *m66592,
  186. struct m66592_pipe_info *info)
  187. {
  188. u16 bufnum = 0, buf_bsize = 0;
  189. u16 pipecfg = 0;
  190. if (info->pipe == 0)
  191. return -EINVAL;
  192. m66592_write(m66592, info->pipe, M66592_PIPESEL);
  193. if (info->dir_in)
  194. pipecfg |= M66592_DIR;
  195. pipecfg |= info->type;
  196. pipecfg |= info->epnum;
  197. switch (info->type) {
  198. case M66592_INT:
  199. bufnum = 4 + (info->pipe - M66592_BASE_PIPENUM_INT);
  200. buf_bsize = 0;
  201. break;
  202. case M66592_BULK:
  203. /* isochronous pipes may be used as bulk pipes */
  204. if (info->pipe >= M66592_BASE_PIPENUM_BULK)
  205. bufnum = info->pipe - M66592_BASE_PIPENUM_BULK;
  206. else
  207. bufnum = info->pipe - M66592_BASE_PIPENUM_ISOC;
  208. bufnum = M66592_BASE_BUFNUM + (bufnum * 16);
  209. buf_bsize = 7;
  210. pipecfg |= M66592_DBLB;
  211. if (!info->dir_in)
  212. pipecfg |= M66592_SHTNAK;
  213. break;
  214. case M66592_ISO:
  215. bufnum = M66592_BASE_BUFNUM +
  216. (info->pipe - M66592_BASE_PIPENUM_ISOC) * 16;
  217. buf_bsize = 7;
  218. break;
  219. }
  220. if (buf_bsize && ((bufnum + 16) >= M66592_MAX_BUFNUM)) {
  221. pr_err("m66592 pipe memory is insufficient\n");
  222. return -ENOMEM;
  223. }
  224. m66592_write(m66592, pipecfg, M66592_PIPECFG);
  225. m66592_write(m66592, (buf_bsize << 10) | (bufnum), M66592_PIPEBUF);
  226. m66592_write(m66592, info->maxpacket, M66592_PIPEMAXP);
  227. if (info->interval)
  228. info->interval--;
  229. m66592_write(m66592, info->interval, M66592_PIPEPERI);
  230. return 0;
  231. }
  232. static void pipe_buffer_release(struct m66592 *m66592,
  233. struct m66592_pipe_info *info)
  234. {
  235. if (info->pipe == 0)
  236. return;
  237. if (is_bulk_pipe(info->pipe)) {
  238. m66592->bulk--;
  239. } else if (is_interrupt_pipe(info->pipe))
  240. m66592->interrupt--;
  241. else if (is_isoc_pipe(info->pipe)) {
  242. m66592->isochronous--;
  243. if (info->type == M66592_BULK)
  244. m66592->bulk--;
  245. } else
  246. pr_err("ep_release: unexpect pipenum (%d)\n",
  247. info->pipe);
  248. }
  249. static void pipe_initialize(struct m66592_ep *ep)
  250. {
  251. struct m66592 *m66592 = ep->m66592;
  252. unsigned short mbw;
  253. m66592_mdfy(m66592, 0, M66592_CURPIPE, ep->fifosel);
  254. m66592_write(m66592, M66592_ACLRM, ep->pipectr);
  255. m66592_write(m66592, 0, ep->pipectr);
  256. m66592_write(m66592, M66592_SQCLR, ep->pipectr);
  257. if (ep->use_dma) {
  258. m66592_mdfy(m66592, ep->pipenum, M66592_CURPIPE, ep->fifosel);
  259. ndelay(450);
  260. if (m66592->pdata->on_chip)
  261. mbw = M66592_MBW_32;
  262. else
  263. mbw = M66592_MBW_16;
  264. m66592_bset(m66592, mbw, ep->fifosel);
  265. }
  266. }
  267. static void m66592_ep_setting(struct m66592 *m66592, struct m66592_ep *ep,
  268. const struct usb_endpoint_descriptor *desc,
  269. u16 pipenum, int dma)
  270. {
  271. if ((pipenum != 0) && dma) {
  272. if (m66592->num_dma == 0) {
  273. m66592->num_dma++;
  274. ep->use_dma = 1;
  275. ep->fifoaddr = M66592_D0FIFO;
  276. ep->fifosel = M66592_D0FIFOSEL;
  277. ep->fifoctr = M66592_D0FIFOCTR;
  278. ep->fifotrn = M66592_D0FIFOTRN;
  279. } else if (!m66592->pdata->on_chip && m66592->num_dma == 1) {
  280. m66592->num_dma++;
  281. ep->use_dma = 1;
  282. ep->fifoaddr = M66592_D1FIFO;
  283. ep->fifosel = M66592_D1FIFOSEL;
  284. ep->fifoctr = M66592_D1FIFOCTR;
  285. ep->fifotrn = M66592_D1FIFOTRN;
  286. } else {
  287. ep->use_dma = 0;
  288. ep->fifoaddr = M66592_CFIFO;
  289. ep->fifosel = M66592_CFIFOSEL;
  290. ep->fifoctr = M66592_CFIFOCTR;
  291. ep->fifotrn = 0;
  292. }
  293. } else {
  294. ep->use_dma = 0;
  295. ep->fifoaddr = M66592_CFIFO;
  296. ep->fifosel = M66592_CFIFOSEL;
  297. ep->fifoctr = M66592_CFIFOCTR;
  298. ep->fifotrn = 0;
  299. }
  300. ep->pipectr = get_pipectr_addr(pipenum);
  301. ep->pipenum = pipenum;
  302. ep->ep.maxpacket = usb_endpoint_maxp(desc);
  303. m66592->pipenum2ep[pipenum] = ep;
  304. m66592->epaddr2ep[desc->bEndpointAddress&USB_ENDPOINT_NUMBER_MASK] = ep;
  305. INIT_LIST_HEAD(&ep->queue);
  306. }
  307. static void m66592_ep_release(struct m66592_ep *ep)
  308. {
  309. struct m66592 *m66592 = ep->m66592;
  310. u16 pipenum = ep->pipenum;
  311. if (pipenum == 0)
  312. return;
  313. if (ep->use_dma)
  314. m66592->num_dma--;
  315. ep->pipenum = 0;
  316. ep->busy = 0;
  317. ep->use_dma = 0;
  318. }
  319. static int alloc_pipe_config(struct m66592_ep *ep,
  320. const struct usb_endpoint_descriptor *desc)
  321. {
  322. struct m66592 *m66592 = ep->m66592;
  323. struct m66592_pipe_info info;
  324. int dma = 0;
  325. int *counter;
  326. int ret;
  327. ep->ep.desc = desc;
  328. BUG_ON(ep->pipenum);
  329. switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
  330. case USB_ENDPOINT_XFER_BULK:
  331. if (m66592->bulk >= M66592_MAX_NUM_BULK) {
  332. if (m66592->isochronous >= M66592_MAX_NUM_ISOC) {
  333. pr_err("bulk pipe is insufficient\n");
  334. return -ENODEV;
  335. } else {
  336. info.pipe = M66592_BASE_PIPENUM_ISOC
  337. + m66592->isochronous;
  338. counter = &m66592->isochronous;
  339. }
  340. } else {
  341. info.pipe = M66592_BASE_PIPENUM_BULK + m66592->bulk;
  342. counter = &m66592->bulk;
  343. }
  344. info.type = M66592_BULK;
  345. dma = 1;
  346. break;
  347. case USB_ENDPOINT_XFER_INT:
  348. if (m66592->interrupt >= M66592_MAX_NUM_INT) {
  349. pr_err("interrupt pipe is insufficient\n");
  350. return -ENODEV;
  351. }
  352. info.pipe = M66592_BASE_PIPENUM_INT + m66592->interrupt;
  353. info.type = M66592_INT;
  354. counter = &m66592->interrupt;
  355. break;
  356. case USB_ENDPOINT_XFER_ISOC:
  357. if (m66592->isochronous >= M66592_MAX_NUM_ISOC) {
  358. pr_err("isochronous pipe is insufficient\n");
  359. return -ENODEV;
  360. }
  361. info.pipe = M66592_BASE_PIPENUM_ISOC + m66592->isochronous;
  362. info.type = M66592_ISO;
  363. counter = &m66592->isochronous;
  364. break;
  365. default:
  366. pr_err("unexpect xfer type\n");
  367. return -EINVAL;
  368. }
  369. ep->type = info.type;
  370. info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
  371. info.maxpacket = usb_endpoint_maxp(desc);
  372. info.interval = desc->bInterval;
  373. if (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK)
  374. info.dir_in = 1;
  375. else
  376. info.dir_in = 0;
  377. ret = pipe_buffer_setting(m66592, &info);
  378. if (ret < 0) {
  379. pr_err("pipe_buffer_setting fail\n");
  380. return ret;
  381. }
  382. (*counter)++;
  383. if ((counter == &m66592->isochronous) && info.type == M66592_BULK)
  384. m66592->bulk++;
  385. m66592_ep_setting(m66592, ep, desc, info.pipe, dma);
  386. pipe_initialize(ep);
  387. return 0;
  388. }
  389. static int free_pipe_config(struct m66592_ep *ep)
  390. {
  391. struct m66592 *m66592 = ep->m66592;
  392. struct m66592_pipe_info info;
  393. info.pipe = ep->pipenum;
  394. info.type = ep->type;
  395. pipe_buffer_release(m66592, &info);
  396. m66592_ep_release(ep);
  397. return 0;
  398. }
  399. /*-------------------------------------------------------------------------*/
  400. static void pipe_irq_enable(struct m66592 *m66592, u16 pipenum)
  401. {
  402. enable_irq_ready(m66592, pipenum);
  403. enable_irq_nrdy(m66592, pipenum);
  404. }
  405. static void pipe_irq_disable(struct m66592 *m66592, u16 pipenum)
  406. {
  407. disable_irq_ready(m66592, pipenum);
  408. disable_irq_nrdy(m66592, pipenum);
  409. }
  410. /* if complete is true, gadget driver complete function is not call */
  411. static void control_end(struct m66592 *m66592, unsigned ccpl)
  412. {
  413. m66592->ep[0].internal_ccpl = ccpl;
  414. pipe_start(m66592, 0);
  415. m66592_bset(m66592, M66592_CCPL, M66592_DCPCTR);
  416. }
  417. static void start_ep0_write(struct m66592_ep *ep, struct m66592_request *req)
  418. {
  419. struct m66592 *m66592 = ep->m66592;
  420. pipe_change(m66592, ep->pipenum);
  421. m66592_mdfy(m66592, M66592_ISEL | M66592_PIPE0,
  422. (M66592_ISEL | M66592_CURPIPE),
  423. M66592_CFIFOSEL);
  424. m66592_write(m66592, M66592_BCLR, ep->fifoctr);
  425. if (req->req.length == 0) {
  426. m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
  427. pipe_start(m66592, 0);
  428. transfer_complete(ep, req, 0);
  429. } else {
  430. m66592_write(m66592, ~M66592_BEMP0, M66592_BEMPSTS);
  431. irq_ep0_write(ep, req);
  432. }
  433. }
  434. static void start_packet_write(struct m66592_ep *ep, struct m66592_request *req)
  435. {
  436. struct m66592 *m66592 = ep->m66592;
  437. u16 tmp;
  438. pipe_change(m66592, ep->pipenum);
  439. disable_irq_empty(m66592, ep->pipenum);
  440. pipe_start(m66592, ep->pipenum);
  441. tmp = m66592_read(m66592, ep->fifoctr);
  442. if (unlikely((tmp & M66592_FRDY) == 0))
  443. pipe_irq_enable(m66592, ep->pipenum);
  444. else
  445. irq_packet_write(ep, req);
  446. }
  447. static void start_packet_read(struct m66592_ep *ep, struct m66592_request *req)
  448. {
  449. struct m66592 *m66592 = ep->m66592;
  450. u16 pipenum = ep->pipenum;
  451. if (ep->pipenum == 0) {
  452. m66592_mdfy(m66592, M66592_PIPE0,
  453. (M66592_ISEL | M66592_CURPIPE),
  454. M66592_CFIFOSEL);
  455. m66592_write(m66592, M66592_BCLR, ep->fifoctr);
  456. pipe_start(m66592, pipenum);
  457. pipe_irq_enable(m66592, pipenum);
  458. } else {
  459. if (ep->use_dma) {
  460. m66592_bset(m66592, M66592_TRCLR, ep->fifosel);
  461. pipe_change(m66592, pipenum);
  462. m66592_bset(m66592, M66592_TRENB, ep->fifosel);
  463. m66592_write(m66592,
  464. (req->req.length + ep->ep.maxpacket - 1)
  465. / ep->ep.maxpacket,
  466. ep->fifotrn);
  467. }
  468. pipe_start(m66592, pipenum); /* trigger once */
  469. pipe_irq_enable(m66592, pipenum);
  470. }
  471. }
  472. static void start_packet(struct m66592_ep *ep, struct m66592_request *req)
  473. {
  474. if (ep->ep.desc->bEndpointAddress & USB_DIR_IN)
  475. start_packet_write(ep, req);
  476. else
  477. start_packet_read(ep, req);
  478. }
  479. static void start_ep0(struct m66592_ep *ep, struct m66592_request *req)
  480. {
  481. u16 ctsq;
  482. ctsq = m66592_read(ep->m66592, M66592_INTSTS0) & M66592_CTSQ;
  483. switch (ctsq) {
  484. case M66592_CS_RDDS:
  485. start_ep0_write(ep, req);
  486. break;
  487. case M66592_CS_WRDS:
  488. start_packet_read(ep, req);
  489. break;
  490. case M66592_CS_WRND:
  491. control_end(ep->m66592, 0);
  492. break;
  493. default:
  494. pr_err("start_ep0: unexpect ctsq(%x)\n", ctsq);
  495. break;
  496. }
  497. }
  498. static void init_controller(struct m66592 *m66592)
  499. {
  500. unsigned int endian;
  501. if (m66592->pdata->on_chip) {
  502. if (m66592->pdata->endian)
  503. endian = 0; /* big endian */
  504. else
  505. endian = M66592_LITTLE; /* little endian */
  506. m66592_bset(m66592, M66592_HSE, M66592_SYSCFG); /* High spd */
  507. m66592_bclr(m66592, M66592_USBE, M66592_SYSCFG);
  508. m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
  509. m66592_bset(m66592, M66592_USBE, M66592_SYSCFG);
  510. /* This is a workaound for SH7722 2nd cut */
  511. m66592_bset(m66592, 0x8000, M66592_DVSTCTR);
  512. m66592_bset(m66592, 0x1000, M66592_TESTMODE);
  513. m66592_bclr(m66592, 0x8000, M66592_DVSTCTR);
  514. m66592_bset(m66592, M66592_INTL, M66592_INTENB1);
  515. m66592_write(m66592, 0, M66592_CFBCFG);
  516. m66592_write(m66592, 0, M66592_D0FBCFG);
  517. m66592_bset(m66592, endian, M66592_CFBCFG);
  518. m66592_bset(m66592, endian, M66592_D0FBCFG);
  519. } else {
  520. unsigned int clock, vif, irq_sense;
  521. if (m66592->pdata->endian)
  522. endian = M66592_BIGEND; /* big endian */
  523. else
  524. endian = 0; /* little endian */
  525. if (m66592->pdata->vif)
  526. vif = M66592_LDRV; /* 3.3v */
  527. else
  528. vif = 0; /* 1.5v */
  529. switch (m66592->pdata->xtal) {
  530. case M66592_PLATDATA_XTAL_12MHZ:
  531. clock = M66592_XTAL12;
  532. break;
  533. case M66592_PLATDATA_XTAL_24MHZ:
  534. clock = M66592_XTAL24;
  535. break;
  536. case M66592_PLATDATA_XTAL_48MHZ:
  537. clock = M66592_XTAL48;
  538. break;
  539. default:
  540. pr_warn("m66592-udc: xtal configuration error\n");
  541. clock = 0;
  542. }
  543. switch (m66592->irq_trigger) {
  544. case IRQF_TRIGGER_LOW:
  545. irq_sense = M66592_INTL;
  546. break;
  547. case IRQF_TRIGGER_FALLING:
  548. irq_sense = 0;
  549. break;
  550. default:
  551. pr_warn("m66592-udc: irq trigger config error\n");
  552. irq_sense = 0;
  553. }
  554. m66592_bset(m66592,
  555. (vif & M66592_LDRV) | (endian & M66592_BIGEND),
  556. M66592_PINCFG);
  557. m66592_bset(m66592, M66592_HSE, M66592_SYSCFG); /* High spd */
  558. m66592_mdfy(m66592, clock & M66592_XTAL, M66592_XTAL,
  559. M66592_SYSCFG);
  560. m66592_bclr(m66592, M66592_USBE, M66592_SYSCFG);
  561. m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
  562. m66592_bset(m66592, M66592_USBE, M66592_SYSCFG);
  563. m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG);
  564. msleep(3);
  565. m66592_bset(m66592, M66592_RCKE | M66592_PLLC, M66592_SYSCFG);
  566. msleep(1);
  567. m66592_bset(m66592, M66592_SCKE, M66592_SYSCFG);
  568. m66592_bset(m66592, irq_sense & M66592_INTL, M66592_INTENB1);
  569. m66592_write(m66592, M66592_BURST | M66592_CPU_ADR_RD_WR,
  570. M66592_DMA0CFG);
  571. }
  572. }
  573. static void disable_controller(struct m66592 *m66592)
  574. {
  575. m66592_bclr(m66592, M66592_UTST, M66592_TESTMODE);
  576. if (!m66592->pdata->on_chip) {
  577. m66592_bclr(m66592, M66592_SCKE, M66592_SYSCFG);
  578. udelay(1);
  579. m66592_bclr(m66592, M66592_PLLC, M66592_SYSCFG);
  580. udelay(1);
  581. m66592_bclr(m66592, M66592_RCKE, M66592_SYSCFG);
  582. udelay(1);
  583. m66592_bclr(m66592, M66592_XCKE, M66592_SYSCFG);
  584. }
  585. }
  586. static void m66592_start_xclock(struct m66592 *m66592)
  587. {
  588. u16 tmp;
  589. if (!m66592->pdata->on_chip) {
  590. tmp = m66592_read(m66592, M66592_SYSCFG);
  591. if (!(tmp & M66592_XCKE))
  592. m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG);
  593. }
  594. }
  595. /*-------------------------------------------------------------------------*/
  596. static void transfer_complete(struct m66592_ep *ep,
  597. struct m66592_request *req, int status)
  598. __releases(m66592->lock)
  599. __acquires(m66592->lock)
  600. {
  601. int restart = 0;
  602. if (unlikely(ep->pipenum == 0)) {
  603. if (ep->internal_ccpl) {
  604. ep->internal_ccpl = 0;
  605. return;
  606. }
  607. }
  608. list_del_init(&req->queue);
  609. if (ep->m66592->gadget.speed == USB_SPEED_UNKNOWN)
  610. req->req.status = -ESHUTDOWN;
  611. else
  612. req->req.status = status;
  613. if (!list_empty(&ep->queue))
  614. restart = 1;
  615. spin_unlock(&ep->m66592->lock);
  616. usb_gadget_giveback_request(&ep->ep, &req->req);
  617. spin_lock(&ep->m66592->lock);
  618. if (restart) {
  619. req = list_entry(ep->queue.next, struct m66592_request, queue);
  620. if (ep->ep.desc)
  621. start_packet(ep, req);
  622. }
  623. }
  624. static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req)
  625. {
  626. int i;
  627. u16 tmp;
  628. unsigned bufsize;
  629. size_t size;
  630. void *buf;
  631. u16 pipenum = ep->pipenum;
  632. struct m66592 *m66592 = ep->m66592;
  633. pipe_change(m66592, pipenum);
  634. m66592_bset(m66592, M66592_ISEL, ep->fifosel);
  635. i = 0;
  636. do {
  637. tmp = m66592_read(m66592, ep->fifoctr);
  638. if (i++ > 100000) {
  639. pr_err("pipe0 is busy. maybe cpu i/o bus "
  640. "conflict. please power off this controller.");
  641. return;
  642. }
  643. ndelay(1);
  644. } while ((tmp & M66592_FRDY) == 0);
  645. /* prepare parameters */
  646. bufsize = get_buffer_size(m66592, pipenum);
  647. buf = req->req.buf + req->req.actual;
  648. size = min(bufsize, req->req.length - req->req.actual);
  649. /* write fifo */
  650. if (req->req.buf) {
  651. if (size > 0)
  652. m66592_write_fifo(m66592, ep, buf, size);
  653. if ((size == 0) || ((size % ep->ep.maxpacket) != 0))
  654. m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
  655. }
  656. /* update parameters */
  657. req->req.actual += size;
  658. /* check transfer finish */
  659. if ((!req->req.zero && (req->req.actual == req->req.length))
  660. || (size % ep->ep.maxpacket)
  661. || (size == 0)) {
  662. disable_irq_ready(m66592, pipenum);
  663. disable_irq_empty(m66592, pipenum);
  664. } else {
  665. disable_irq_ready(m66592, pipenum);
  666. enable_irq_empty(m66592, pipenum);
  667. }
  668. pipe_start(m66592, pipenum);
  669. }
  670. static void irq_packet_write(struct m66592_ep *ep, struct m66592_request *req)
  671. {
  672. u16 tmp;
  673. unsigned bufsize;
  674. size_t size;
  675. void *buf;
  676. u16 pipenum = ep->pipenum;
  677. struct m66592 *m66592 = ep->m66592;
  678. pipe_change(m66592, pipenum);
  679. tmp = m66592_read(m66592, ep->fifoctr);
  680. if (unlikely((tmp & M66592_FRDY) == 0)) {
  681. pipe_stop(m66592, pipenum);
  682. pipe_irq_disable(m66592, pipenum);
  683. pr_err("write fifo not ready. pipnum=%d\n", pipenum);
  684. return;
  685. }
  686. /* prepare parameters */
  687. bufsize = get_buffer_size(m66592, pipenum);
  688. buf = req->req.buf + req->req.actual;
  689. size = min(bufsize, req->req.length - req->req.actual);
  690. /* write fifo */
  691. if (req->req.buf) {
  692. m66592_write_fifo(m66592, ep, buf, size);
  693. if ((size == 0)
  694. || ((size % ep->ep.maxpacket) != 0)
  695. || ((bufsize != ep->ep.maxpacket)
  696. && (bufsize > size)))
  697. m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
  698. }
  699. /* update parameters */
  700. req->req.actual += size;
  701. /* check transfer finish */
  702. if ((!req->req.zero && (req->req.actual == req->req.length))
  703. || (size % ep->ep.maxpacket)
  704. || (size == 0)) {
  705. disable_irq_ready(m66592, pipenum);
  706. enable_irq_empty(m66592, pipenum);
  707. } else {
  708. disable_irq_empty(m66592, pipenum);
  709. pipe_irq_enable(m66592, pipenum);
  710. }
  711. }
  712. static void irq_packet_read(struct m66592_ep *ep, struct m66592_request *req)
  713. {
  714. u16 tmp;
  715. int rcv_len, bufsize, req_len;
  716. int size;
  717. void *buf;
  718. u16 pipenum = ep->pipenum;
  719. struct m66592 *m66592 = ep->m66592;
  720. int finish = 0;
  721. pipe_change(m66592, pipenum);
  722. tmp = m66592_read(m66592, ep->fifoctr);
  723. if (unlikely((tmp & M66592_FRDY) == 0)) {
  724. req->req.status = -EPIPE;
  725. pipe_stop(m66592, pipenum);
  726. pipe_irq_disable(m66592, pipenum);
  727. pr_err("read fifo not ready");
  728. return;
  729. }
  730. /* prepare parameters */
  731. rcv_len = tmp & M66592_DTLN;
  732. bufsize = get_buffer_size(m66592, pipenum);
  733. buf = req->req.buf + req->req.actual;
  734. req_len = req->req.length - req->req.actual;
  735. if (rcv_len < bufsize)
  736. size = min(rcv_len, req_len);
  737. else
  738. size = min(bufsize, req_len);
  739. /* update parameters */
  740. req->req.actual += size;
  741. /* check transfer finish */
  742. if ((!req->req.zero && (req->req.actual == req->req.length))
  743. || (size % ep->ep.maxpacket)
  744. || (size == 0)) {
  745. pipe_stop(m66592, pipenum);
  746. pipe_irq_disable(m66592, pipenum);
  747. finish = 1;
  748. }
  749. /* read fifo */
  750. if (req->req.buf) {
  751. if (size == 0)
  752. m66592_write(m66592, M66592_BCLR, ep->fifoctr);
  753. else
  754. m66592_read_fifo(m66592, ep->fifoaddr, buf, size);
  755. }
  756. if ((ep->pipenum != 0) && finish)
  757. transfer_complete(ep, req, 0);
  758. }
  759. static void irq_pipe_ready(struct m66592 *m66592, u16 status, u16 enb)
  760. {
  761. u16 check;
  762. u16 pipenum;
  763. struct m66592_ep *ep;
  764. struct m66592_request *req;
  765. if ((status & M66592_BRDY0) && (enb & M66592_BRDY0)) {
  766. m66592_write(m66592, ~M66592_BRDY0, M66592_BRDYSTS);
  767. m66592_mdfy(m66592, M66592_PIPE0, M66592_CURPIPE,
  768. M66592_CFIFOSEL);
  769. ep = &m66592->ep[0];
  770. req = list_entry(ep->queue.next, struct m66592_request, queue);
  771. irq_packet_read(ep, req);
  772. } else {
  773. for (pipenum = 1; pipenum < M66592_MAX_NUM_PIPE; pipenum++) {
  774. check = 1 << pipenum;
  775. if ((status & check) && (enb & check)) {
  776. m66592_write(m66592, ~check, M66592_BRDYSTS);
  777. ep = m66592->pipenum2ep[pipenum];
  778. req = list_entry(ep->queue.next,
  779. struct m66592_request, queue);
  780. if (ep->ep.desc->bEndpointAddress & USB_DIR_IN)
  781. irq_packet_write(ep, req);
  782. else
  783. irq_packet_read(ep, req);
  784. }
  785. }
  786. }
  787. }
  788. static void irq_pipe_empty(struct m66592 *m66592, u16 status, u16 enb)
  789. {
  790. u16 tmp;
  791. u16 check;
  792. u16 pipenum;
  793. struct m66592_ep *ep;
  794. struct m66592_request *req;
  795. if ((status & M66592_BEMP0) && (enb & M66592_BEMP0)) {
  796. m66592_write(m66592, ~M66592_BEMP0, M66592_BEMPSTS);
  797. ep = &m66592->ep[0];
  798. req = list_entry(ep->queue.next, struct m66592_request, queue);
  799. irq_ep0_write(ep, req);
  800. } else {
  801. for (pipenum = 1; pipenum < M66592_MAX_NUM_PIPE; pipenum++) {
  802. check = 1 << pipenum;
  803. if ((status & check) && (enb & check)) {
  804. m66592_write(m66592, ~check, M66592_BEMPSTS);
  805. tmp = control_reg_get(m66592, pipenum);
  806. if ((tmp & M66592_INBUFM) == 0) {
  807. disable_irq_empty(m66592, pipenum);
  808. pipe_irq_disable(m66592, pipenum);
  809. pipe_stop(m66592, pipenum);
  810. ep = m66592->pipenum2ep[pipenum];
  811. req = list_entry(ep->queue.next,
  812. struct m66592_request,
  813. queue);
  814. if (!list_empty(&ep->queue))
  815. transfer_complete(ep, req, 0);
  816. }
  817. }
  818. }
  819. }
  820. }
  821. static void get_status(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
  822. __releases(m66592->lock)
  823. __acquires(m66592->lock)
  824. {
  825. struct m66592_ep *ep;
  826. u16 pid;
  827. u16 status = 0;
  828. u16 w_index = le16_to_cpu(ctrl->wIndex);
  829. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  830. case USB_RECIP_DEVICE:
  831. status = 1 << USB_DEVICE_SELF_POWERED;
  832. break;
  833. case USB_RECIP_INTERFACE:
  834. status = 0;
  835. break;
  836. case USB_RECIP_ENDPOINT:
  837. ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  838. pid = control_reg_get_pid(m66592, ep->pipenum);
  839. if (pid == M66592_PID_STALL)
  840. status = 1 << USB_ENDPOINT_HALT;
  841. else
  842. status = 0;
  843. break;
  844. default:
  845. pipe_stall(m66592, 0);
  846. return; /* exit */
  847. }
  848. m66592->ep0_data = cpu_to_le16(status);
  849. m66592->ep0_req->buf = &m66592->ep0_data;
  850. m66592->ep0_req->length = 2;
  851. /* AV: what happens if we get called again before that gets through? */
  852. spin_unlock(&m66592->lock);
  853. m66592_queue(m66592->gadget.ep0, m66592->ep0_req, GFP_KERNEL);
  854. spin_lock(&m66592->lock);
  855. }
  856. static void clear_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
  857. {
  858. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  859. case USB_RECIP_DEVICE:
  860. control_end(m66592, 1);
  861. break;
  862. case USB_RECIP_INTERFACE:
  863. control_end(m66592, 1);
  864. break;
  865. case USB_RECIP_ENDPOINT: {
  866. struct m66592_ep *ep;
  867. struct m66592_request *req;
  868. u16 w_index = le16_to_cpu(ctrl->wIndex);
  869. ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  870. pipe_stop(m66592, ep->pipenum);
  871. control_reg_sqclr(m66592, ep->pipenum);
  872. control_end(m66592, 1);
  873. req = list_entry(ep->queue.next,
  874. struct m66592_request, queue);
  875. if (ep->busy) {
  876. ep->busy = 0;
  877. if (list_empty(&ep->queue))
  878. break;
  879. start_packet(ep, req);
  880. } else if (!list_empty(&ep->queue))
  881. pipe_start(m66592, ep->pipenum);
  882. }
  883. break;
  884. default:
  885. pipe_stall(m66592, 0);
  886. break;
  887. }
  888. }
  889. static void set_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
  890. {
  891. u16 tmp;
  892. int timeout = 3000;
  893. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  894. case USB_RECIP_DEVICE:
  895. switch (le16_to_cpu(ctrl->wValue)) {
  896. case USB_DEVICE_TEST_MODE:
  897. control_end(m66592, 1);
  898. /* Wait for the completion of status stage */
  899. do {
  900. tmp = m66592_read(m66592, M66592_INTSTS0) &
  901. M66592_CTSQ;
  902. udelay(1);
  903. } while (tmp != M66592_CS_IDST && timeout-- > 0);
  904. if (tmp == M66592_CS_IDST)
  905. m66592_bset(m66592,
  906. le16_to_cpu(ctrl->wIndex >> 8),
  907. M66592_TESTMODE);
  908. break;
  909. default:
  910. pipe_stall(m66592, 0);
  911. break;
  912. }
  913. break;
  914. case USB_RECIP_INTERFACE:
  915. control_end(m66592, 1);
  916. break;
  917. case USB_RECIP_ENDPOINT: {
  918. struct m66592_ep *ep;
  919. u16 w_index = le16_to_cpu(ctrl->wIndex);
  920. ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  921. pipe_stall(m66592, ep->pipenum);
  922. control_end(m66592, 1);
  923. }
  924. break;
  925. default:
  926. pipe_stall(m66592, 0);
  927. break;
  928. }
  929. }
  930. /* if return value is true, call class driver's setup() */
  931. static int setup_packet(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
  932. {
  933. u16 *p = (u16 *)ctrl;
  934. unsigned long offset = M66592_USBREQ;
  935. int i, ret = 0;
  936. /* read fifo */
  937. m66592_write(m66592, ~M66592_VALID, M66592_INTSTS0);
  938. for (i = 0; i < 4; i++)
  939. p[i] = m66592_read(m66592, offset + i*2);
  940. /* check request */
  941. if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
  942. switch (ctrl->bRequest) {
  943. case USB_REQ_GET_STATUS:
  944. get_status(m66592, ctrl);
  945. break;
  946. case USB_REQ_CLEAR_FEATURE:
  947. clear_feature(m66592, ctrl);
  948. break;
  949. case USB_REQ_SET_FEATURE:
  950. set_feature(m66592, ctrl);
  951. break;
  952. default:
  953. ret = 1;
  954. break;
  955. }
  956. } else
  957. ret = 1;
  958. return ret;
  959. }
  960. static void m66592_update_usb_speed(struct m66592 *m66592)
  961. {
  962. u16 speed = get_usb_speed(m66592);
  963. switch (speed) {
  964. case M66592_HSMODE:
  965. m66592->gadget.speed = USB_SPEED_HIGH;
  966. break;
  967. case M66592_FSMODE:
  968. m66592->gadget.speed = USB_SPEED_FULL;
  969. break;
  970. default:
  971. m66592->gadget.speed = USB_SPEED_UNKNOWN;
  972. pr_err("USB speed unknown\n");
  973. }
  974. }
  975. static void irq_device_state(struct m66592 *m66592)
  976. {
  977. u16 dvsq;
  978. dvsq = m66592_read(m66592, M66592_INTSTS0) & M66592_DVSQ;
  979. m66592_write(m66592, ~M66592_DVST, M66592_INTSTS0);
  980. if (dvsq == M66592_DS_DFLT) { /* bus reset */
  981. usb_gadget_udc_reset(&m66592->gadget, m66592->driver);
  982. m66592_update_usb_speed(m66592);
  983. }
  984. if (m66592->old_dvsq == M66592_DS_CNFG && dvsq != M66592_DS_CNFG)
  985. m66592_update_usb_speed(m66592);
  986. if ((dvsq == M66592_DS_CNFG || dvsq == M66592_DS_ADDS)
  987. && m66592->gadget.speed == USB_SPEED_UNKNOWN)
  988. m66592_update_usb_speed(m66592);
  989. m66592->old_dvsq = dvsq;
  990. }
  991. static void irq_control_stage(struct m66592 *m66592)
  992. __releases(m66592->lock)
  993. __acquires(m66592->lock)
  994. {
  995. struct usb_ctrlrequest ctrl;
  996. u16 ctsq;
  997. ctsq = m66592_read(m66592, M66592_INTSTS0) & M66592_CTSQ;
  998. m66592_write(m66592, ~M66592_CTRT, M66592_INTSTS0);
  999. switch (ctsq) {
  1000. case M66592_CS_IDST: {
  1001. struct m66592_ep *ep;
  1002. struct m66592_request *req;
  1003. ep = &m66592->ep[0];
  1004. req = list_entry(ep->queue.next, struct m66592_request, queue);
  1005. transfer_complete(ep, req, 0);
  1006. }
  1007. break;
  1008. case M66592_CS_RDDS:
  1009. case M66592_CS_WRDS:
  1010. case M66592_CS_WRND:
  1011. if (setup_packet(m66592, &ctrl)) {
  1012. spin_unlock(&m66592->lock);
  1013. if (m66592->driver->setup(&m66592->gadget, &ctrl) < 0)
  1014. pipe_stall(m66592, 0);
  1015. spin_lock(&m66592->lock);
  1016. }
  1017. break;
  1018. case M66592_CS_RDSS:
  1019. case M66592_CS_WRSS:
  1020. control_end(m66592, 0);
  1021. break;
  1022. default:
  1023. pr_err("ctrl_stage: unexpect ctsq(%x)\n", ctsq);
  1024. break;
  1025. }
  1026. }
  1027. static irqreturn_t m66592_irq(int irq, void *_m66592)
  1028. {
  1029. struct m66592 *m66592 = _m66592;
  1030. u16 intsts0;
  1031. u16 intenb0;
  1032. u16 savepipe;
  1033. u16 mask0;
  1034. spin_lock(&m66592->lock);
  1035. intsts0 = m66592_read(m66592, M66592_INTSTS0);
  1036. intenb0 = m66592_read(m66592, M66592_INTENB0);
  1037. if (m66592->pdata->on_chip && !intsts0 && !intenb0) {
  1038. /*
  1039. * When USB clock stops, it cannot read register. Even if a
  1040. * clock stops, the interrupt occurs. So this driver turn on
  1041. * a clock by this timing and do re-reading of register.
  1042. */
  1043. m66592_start_xclock(m66592);
  1044. intsts0 = m66592_read(m66592, M66592_INTSTS0);
  1045. intenb0 = m66592_read(m66592, M66592_INTENB0);
  1046. }
  1047. savepipe = m66592_read(m66592, M66592_CFIFOSEL);
  1048. mask0 = intsts0 & intenb0;
  1049. if (mask0) {
  1050. u16 brdysts = m66592_read(m66592, M66592_BRDYSTS);
  1051. u16 bempsts = m66592_read(m66592, M66592_BEMPSTS);
  1052. u16 brdyenb = m66592_read(m66592, M66592_BRDYENB);
  1053. u16 bempenb = m66592_read(m66592, M66592_BEMPENB);
  1054. if (mask0 & M66592_VBINT) {
  1055. m66592_write(m66592, 0xffff & ~M66592_VBINT,
  1056. M66592_INTSTS0);
  1057. m66592_start_xclock(m66592);
  1058. /* start vbus sampling */
  1059. m66592->old_vbus = m66592_read(m66592, M66592_INTSTS0)
  1060. & M66592_VBSTS;
  1061. m66592->scount = M66592_MAX_SAMPLING;
  1062. mod_timer(&m66592->timer,
  1063. jiffies + msecs_to_jiffies(50));
  1064. }
  1065. if (intsts0 & M66592_DVSQ)
  1066. irq_device_state(m66592);
  1067. if ((intsts0 & M66592_BRDY) && (intenb0 & M66592_BRDYE)
  1068. && (brdysts & brdyenb)) {
  1069. irq_pipe_ready(m66592, brdysts, brdyenb);
  1070. }
  1071. if ((intsts0 & M66592_BEMP) && (intenb0 & M66592_BEMPE)
  1072. && (bempsts & bempenb)) {
  1073. irq_pipe_empty(m66592, bempsts, bempenb);
  1074. }
  1075. if (intsts0 & M66592_CTRT)
  1076. irq_control_stage(m66592);
  1077. }
  1078. m66592_write(m66592, savepipe, M66592_CFIFOSEL);
  1079. spin_unlock(&m66592->lock);
  1080. return IRQ_HANDLED;
  1081. }
  1082. static void m66592_timer(struct timer_list *t)
  1083. {
  1084. struct m66592 *m66592 = from_timer(m66592, t, timer);
  1085. unsigned long flags;
  1086. u16 tmp;
  1087. spin_lock_irqsave(&m66592->lock, flags);
  1088. tmp = m66592_read(m66592, M66592_SYSCFG);
  1089. if (!(tmp & M66592_RCKE)) {
  1090. m66592_bset(m66592, M66592_RCKE | M66592_PLLC, M66592_SYSCFG);
  1091. udelay(10);
  1092. m66592_bset(m66592, M66592_SCKE, M66592_SYSCFG);
  1093. }
  1094. if (m66592->scount > 0) {
  1095. tmp = m66592_read(m66592, M66592_INTSTS0) & M66592_VBSTS;
  1096. if (tmp == m66592->old_vbus) {
  1097. m66592->scount--;
  1098. if (m66592->scount == 0) {
  1099. if (tmp == M66592_VBSTS)
  1100. m66592_usb_connect(m66592);
  1101. else
  1102. m66592_usb_disconnect(m66592);
  1103. } else {
  1104. mod_timer(&m66592->timer,
  1105. jiffies + msecs_to_jiffies(50));
  1106. }
  1107. } else {
  1108. m66592->scount = M66592_MAX_SAMPLING;
  1109. m66592->old_vbus = tmp;
  1110. mod_timer(&m66592->timer,
  1111. jiffies + msecs_to_jiffies(50));
  1112. }
  1113. }
  1114. spin_unlock_irqrestore(&m66592->lock, flags);
  1115. }
  1116. /*-------------------------------------------------------------------------*/
  1117. static int m66592_enable(struct usb_ep *_ep,
  1118. const struct usb_endpoint_descriptor *desc)
  1119. {
  1120. struct m66592_ep *ep;
  1121. ep = container_of(_ep, struct m66592_ep, ep);
  1122. return alloc_pipe_config(ep, desc);
  1123. }
  1124. static int m66592_disable(struct usb_ep *_ep)
  1125. {
  1126. struct m66592_ep *ep;
  1127. struct m66592_request *req;
  1128. unsigned long flags;
  1129. ep = container_of(_ep, struct m66592_ep, ep);
  1130. BUG_ON(!ep);
  1131. while (!list_empty(&ep->queue)) {
  1132. req = list_entry(ep->queue.next, struct m66592_request, queue);
  1133. spin_lock_irqsave(&ep->m66592->lock, flags);
  1134. transfer_complete(ep, req, -ECONNRESET);
  1135. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1136. }
  1137. pipe_irq_disable(ep->m66592, ep->pipenum);
  1138. return free_pipe_config(ep);
  1139. }
  1140. static struct usb_request *m66592_alloc_request(struct usb_ep *_ep,
  1141. gfp_t gfp_flags)
  1142. {
  1143. struct m66592_request *req;
  1144. req = kzalloc(sizeof(struct m66592_request), gfp_flags);
  1145. if (!req)
  1146. return NULL;
  1147. INIT_LIST_HEAD(&req->queue);
  1148. return &req->req;
  1149. }
  1150. static void m66592_free_request(struct usb_ep *_ep, struct usb_request *_req)
  1151. {
  1152. struct m66592_request *req;
  1153. req = container_of(_req, struct m66592_request, req);
  1154. kfree(req);
  1155. }
  1156. static int m66592_queue(struct usb_ep *_ep, struct usb_request *_req,
  1157. gfp_t gfp_flags)
  1158. {
  1159. struct m66592_ep *ep;
  1160. struct m66592_request *req;
  1161. unsigned long flags;
  1162. int request = 0;
  1163. ep = container_of(_ep, struct m66592_ep, ep);
  1164. req = container_of(_req, struct m66592_request, req);
  1165. if (ep->m66592->gadget.speed == USB_SPEED_UNKNOWN)
  1166. return -ESHUTDOWN;
  1167. spin_lock_irqsave(&ep->m66592->lock, flags);
  1168. if (list_empty(&ep->queue))
  1169. request = 1;
  1170. list_add_tail(&req->queue, &ep->queue);
  1171. req->req.actual = 0;
  1172. req->req.status = -EINPROGRESS;
  1173. if (ep->ep.desc == NULL) /* control */
  1174. start_ep0(ep, req);
  1175. else {
  1176. if (request && !ep->busy)
  1177. start_packet(ep, req);
  1178. }
  1179. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1180. return 0;
  1181. }
  1182. static int m66592_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  1183. {
  1184. struct m66592_ep *ep;
  1185. struct m66592_request *req;
  1186. unsigned long flags;
  1187. ep = container_of(_ep, struct m66592_ep, ep);
  1188. req = container_of(_req, struct m66592_request, req);
  1189. spin_lock_irqsave(&ep->m66592->lock, flags);
  1190. if (!list_empty(&ep->queue))
  1191. transfer_complete(ep, req, -ECONNRESET);
  1192. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1193. return 0;
  1194. }
  1195. static int m66592_set_halt(struct usb_ep *_ep, int value)
  1196. {
  1197. struct m66592_ep *ep = container_of(_ep, struct m66592_ep, ep);
  1198. unsigned long flags;
  1199. int ret = 0;
  1200. spin_lock_irqsave(&ep->m66592->lock, flags);
  1201. if (!list_empty(&ep->queue)) {
  1202. ret = -EAGAIN;
  1203. } else if (value) {
  1204. ep->busy = 1;
  1205. pipe_stall(ep->m66592, ep->pipenum);
  1206. } else {
  1207. ep->busy = 0;
  1208. pipe_stop(ep->m66592, ep->pipenum);
  1209. }
  1210. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1211. return ret;
  1212. }
  1213. static void m66592_fifo_flush(struct usb_ep *_ep)
  1214. {
  1215. struct m66592_ep *ep;
  1216. unsigned long flags;
  1217. ep = container_of(_ep, struct m66592_ep, ep);
  1218. spin_lock_irqsave(&ep->m66592->lock, flags);
  1219. if (list_empty(&ep->queue) && !ep->busy) {
  1220. pipe_stop(ep->m66592, ep->pipenum);
  1221. m66592_bclr(ep->m66592, M66592_BCLR, ep->fifoctr);
  1222. }
  1223. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1224. }
  1225. static const struct usb_ep_ops m66592_ep_ops = {
  1226. .enable = m66592_enable,
  1227. .disable = m66592_disable,
  1228. .alloc_request = m66592_alloc_request,
  1229. .free_request = m66592_free_request,
  1230. .queue = m66592_queue,
  1231. .dequeue = m66592_dequeue,
  1232. .set_halt = m66592_set_halt,
  1233. .fifo_flush = m66592_fifo_flush,
  1234. };
  1235. /*-------------------------------------------------------------------------*/
  1236. static int m66592_udc_start(struct usb_gadget *g,
  1237. struct usb_gadget_driver *driver)
  1238. {
  1239. struct m66592 *m66592 = to_m66592(g);
  1240. /* hook up the driver */
  1241. m66592->driver = driver;
  1242. m66592_bset(m66592, M66592_VBSE | M66592_URST, M66592_INTENB0);
  1243. if (m66592_read(m66592, M66592_INTSTS0) & M66592_VBSTS) {
  1244. m66592_start_xclock(m66592);
  1245. /* start vbus sampling */
  1246. m66592->old_vbus = m66592_read(m66592,
  1247. M66592_INTSTS0) & M66592_VBSTS;
  1248. m66592->scount = M66592_MAX_SAMPLING;
  1249. mod_timer(&m66592->timer, jiffies + msecs_to_jiffies(50));
  1250. }
  1251. return 0;
  1252. }
  1253. static int m66592_udc_stop(struct usb_gadget *g)
  1254. {
  1255. struct m66592 *m66592 = to_m66592(g);
  1256. m66592_bclr(m66592, M66592_VBSE | M66592_URST, M66592_INTENB0);
  1257. init_controller(m66592);
  1258. disable_controller(m66592);
  1259. m66592->driver = NULL;
  1260. return 0;
  1261. }
  1262. /*-------------------------------------------------------------------------*/
  1263. static int m66592_get_frame(struct usb_gadget *_gadget)
  1264. {
  1265. struct m66592 *m66592 = gadget_to_m66592(_gadget);
  1266. return m66592_read(m66592, M66592_FRMNUM) & 0x03FF;
  1267. }
  1268. static int m66592_pullup(struct usb_gadget *gadget, int is_on)
  1269. {
  1270. struct m66592 *m66592 = gadget_to_m66592(gadget);
  1271. unsigned long flags;
  1272. spin_lock_irqsave(&m66592->lock, flags);
  1273. if (is_on)
  1274. m66592_bset(m66592, M66592_DPRPU, M66592_SYSCFG);
  1275. else
  1276. m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
  1277. spin_unlock_irqrestore(&m66592->lock, flags);
  1278. return 0;
  1279. }
  1280. static const struct usb_gadget_ops m66592_gadget_ops = {
  1281. .get_frame = m66592_get_frame,
  1282. .udc_start = m66592_udc_start,
  1283. .udc_stop = m66592_udc_stop,
  1284. .pullup = m66592_pullup,
  1285. };
  1286. static int m66592_remove(struct platform_device *pdev)
  1287. {
  1288. struct m66592 *m66592 = platform_get_drvdata(pdev);
  1289. usb_del_gadget_udc(&m66592->gadget);
  1290. del_timer_sync(&m66592->timer);
  1291. iounmap(m66592->reg);
  1292. free_irq(platform_get_irq(pdev, 0), m66592);
  1293. m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
  1294. if (m66592->pdata->on_chip) {
  1295. clk_disable(m66592->clk);
  1296. clk_put(m66592->clk);
  1297. }
  1298. kfree(m66592);
  1299. return 0;
  1300. }
  1301. static void nop_completion(struct usb_ep *ep, struct usb_request *r)
  1302. {
  1303. }
  1304. static int m66592_probe(struct platform_device *pdev)
  1305. {
  1306. struct resource *res, *ires;
  1307. void __iomem *reg = NULL;
  1308. struct m66592 *m66592 = NULL;
  1309. char clk_name[8];
  1310. int ret = 0;
  1311. int i;
  1312. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1313. if (!res) {
  1314. ret = -ENODEV;
  1315. pr_err("platform_get_resource error.\n");
  1316. goto clean_up;
  1317. }
  1318. ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1319. if (!ires) {
  1320. ret = -ENODEV;
  1321. dev_err(&pdev->dev,
  1322. "platform_get_resource IORESOURCE_IRQ error.\n");
  1323. goto clean_up;
  1324. }
  1325. reg = ioremap(res->start, resource_size(res));
  1326. if (reg == NULL) {
  1327. ret = -ENOMEM;
  1328. pr_err("ioremap error.\n");
  1329. goto clean_up;
  1330. }
  1331. if (dev_get_platdata(&pdev->dev) == NULL) {
  1332. dev_err(&pdev->dev, "no platform data\n");
  1333. ret = -ENODEV;
  1334. goto clean_up;
  1335. }
  1336. /* initialize ucd */
  1337. m66592 = kzalloc(sizeof(struct m66592), GFP_KERNEL);
  1338. if (m66592 == NULL) {
  1339. ret = -ENOMEM;
  1340. goto clean_up;
  1341. }
  1342. m66592->pdata = dev_get_platdata(&pdev->dev);
  1343. m66592->irq_trigger = ires->flags & IRQF_TRIGGER_MASK;
  1344. spin_lock_init(&m66592->lock);
  1345. platform_set_drvdata(pdev, m66592);
  1346. m66592->gadget.ops = &m66592_gadget_ops;
  1347. m66592->gadget.max_speed = USB_SPEED_HIGH;
  1348. m66592->gadget.name = udc_name;
  1349. timer_setup(&m66592->timer, m66592_timer, 0);
  1350. m66592->reg = reg;
  1351. ret = request_irq(ires->start, m66592_irq, IRQF_SHARED,
  1352. udc_name, m66592);
  1353. if (ret < 0) {
  1354. pr_err("request_irq error (%d)\n", ret);
  1355. goto clean_up;
  1356. }
  1357. if (m66592->pdata->on_chip) {
  1358. snprintf(clk_name, sizeof(clk_name), "usbf%d", pdev->id);
  1359. m66592->clk = clk_get(&pdev->dev, clk_name);
  1360. if (IS_ERR(m66592->clk)) {
  1361. dev_err(&pdev->dev, "cannot get clock \"%s\"\n",
  1362. clk_name);
  1363. ret = PTR_ERR(m66592->clk);
  1364. goto clean_up2;
  1365. }
  1366. clk_enable(m66592->clk);
  1367. }
  1368. INIT_LIST_HEAD(&m66592->gadget.ep_list);
  1369. m66592->gadget.ep0 = &m66592->ep[0].ep;
  1370. INIT_LIST_HEAD(&m66592->gadget.ep0->ep_list);
  1371. for (i = 0; i < M66592_MAX_NUM_PIPE; i++) {
  1372. struct m66592_ep *ep = &m66592->ep[i];
  1373. if (i != 0) {
  1374. INIT_LIST_HEAD(&m66592->ep[i].ep.ep_list);
  1375. list_add_tail(&m66592->ep[i].ep.ep_list,
  1376. &m66592->gadget.ep_list);
  1377. }
  1378. ep->m66592 = m66592;
  1379. INIT_LIST_HEAD(&ep->queue);
  1380. ep->ep.name = m66592_ep_name[i];
  1381. ep->ep.ops = &m66592_ep_ops;
  1382. usb_ep_set_maxpacket_limit(&ep->ep, 512);
  1383. if (i == 0) {
  1384. ep->ep.caps.type_control = true;
  1385. } else {
  1386. ep->ep.caps.type_iso = true;
  1387. ep->ep.caps.type_bulk = true;
  1388. ep->ep.caps.type_int = true;
  1389. }
  1390. ep->ep.caps.dir_in = true;
  1391. ep->ep.caps.dir_out = true;
  1392. }
  1393. usb_ep_set_maxpacket_limit(&m66592->ep[0].ep, 64);
  1394. m66592->ep[0].pipenum = 0;
  1395. m66592->ep[0].fifoaddr = M66592_CFIFO;
  1396. m66592->ep[0].fifosel = M66592_CFIFOSEL;
  1397. m66592->ep[0].fifoctr = M66592_CFIFOCTR;
  1398. m66592->ep[0].fifotrn = 0;
  1399. m66592->ep[0].pipectr = get_pipectr_addr(0);
  1400. m66592->pipenum2ep[0] = &m66592->ep[0];
  1401. m66592->epaddr2ep[0] = &m66592->ep[0];
  1402. m66592->ep0_req = m66592_alloc_request(&m66592->ep[0].ep, GFP_KERNEL);
  1403. if (m66592->ep0_req == NULL) {
  1404. ret = -ENOMEM;
  1405. goto clean_up3;
  1406. }
  1407. m66592->ep0_req->complete = nop_completion;
  1408. init_controller(m66592);
  1409. ret = usb_add_gadget_udc(&pdev->dev, &m66592->gadget);
  1410. if (ret)
  1411. goto err_add_udc;
  1412. dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
  1413. return 0;
  1414. err_add_udc:
  1415. m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
  1416. m66592->ep0_req = NULL;
  1417. clean_up3:
  1418. if (m66592->pdata->on_chip) {
  1419. clk_disable(m66592->clk);
  1420. clk_put(m66592->clk);
  1421. }
  1422. clean_up2:
  1423. free_irq(ires->start, m66592);
  1424. clean_up:
  1425. if (m66592) {
  1426. if (m66592->ep0_req)
  1427. m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
  1428. kfree(m66592);
  1429. }
  1430. if (reg)
  1431. iounmap(reg);
  1432. return ret;
  1433. }
  1434. /*-------------------------------------------------------------------------*/
  1435. static struct platform_driver m66592_driver = {
  1436. .remove = m66592_remove,
  1437. .driver = {
  1438. .name = udc_name,
  1439. },
  1440. };
  1441. module_platform_driver_probe(m66592_driver, m66592_probe);