fusb300_udc.c 36 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Fusb300 UDC (USB gadget)
  4. *
  5. * Copyright (C) 2010 Faraday Technology Corp.
  6. *
  7. * Author : Yuan-hsin Chen <[email protected]>
  8. */
  9. #include <linux/dma-mapping.h>
  10. #include <linux/err.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/io.h>
  13. #include <linux/module.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/usb/ch9.h>
  16. #include <linux/usb/gadget.h>
  17. #include "fusb300_udc.h"
  18. MODULE_DESCRIPTION("FUSB300 USB gadget driver");
  19. MODULE_LICENSE("GPL");
  20. MODULE_AUTHOR("Yuan-Hsin Chen, Feng-Hsin Chiang <[email protected]>");
  21. MODULE_ALIAS("platform:fusb300_udc");
  22. #define DRIVER_VERSION "20 October 2010"
  23. static const char udc_name[] = "fusb300_udc";
  24. static const char * const fusb300_ep_name[] = {
  25. "ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7", "ep8", "ep9",
  26. "ep10", "ep11", "ep12", "ep13", "ep14", "ep15"
  27. };
  28. static void done(struct fusb300_ep *ep, struct fusb300_request *req,
  29. int status);
  30. static void fusb300_enable_bit(struct fusb300 *fusb300, u32 offset,
  31. u32 value)
  32. {
  33. u32 reg = ioread32(fusb300->reg + offset);
  34. reg |= value;
  35. iowrite32(reg, fusb300->reg + offset);
  36. }
  37. static void fusb300_disable_bit(struct fusb300 *fusb300, u32 offset,
  38. u32 value)
  39. {
  40. u32 reg = ioread32(fusb300->reg + offset);
  41. reg &= ~value;
  42. iowrite32(reg, fusb300->reg + offset);
  43. }
  44. static void fusb300_ep_setting(struct fusb300_ep *ep,
  45. struct fusb300_ep_info info)
  46. {
  47. ep->epnum = info.epnum;
  48. ep->type = info.type;
  49. }
  50. static int fusb300_ep_release(struct fusb300_ep *ep)
  51. {
  52. if (!ep->epnum)
  53. return 0;
  54. ep->epnum = 0;
  55. ep->stall = 0;
  56. ep->wedged = 0;
  57. return 0;
  58. }
  59. static void fusb300_set_fifo_entry(struct fusb300 *fusb300,
  60. u32 ep)
  61. {
  62. u32 val = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
  63. val &= ~FUSB300_EPSET1_FIFOENTRY_MSK;
  64. val |= FUSB300_EPSET1_FIFOENTRY(FUSB300_FIFO_ENTRY_NUM);
  65. iowrite32(val, fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
  66. }
  67. static void fusb300_set_start_entry(struct fusb300 *fusb300,
  68. u8 ep)
  69. {
  70. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
  71. u32 start_entry = fusb300->fifo_entry_num * FUSB300_FIFO_ENTRY_NUM;
  72. reg &= ~FUSB300_EPSET1_START_ENTRY_MSK ;
  73. reg |= FUSB300_EPSET1_START_ENTRY(start_entry);
  74. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
  75. if (fusb300->fifo_entry_num == FUSB300_MAX_FIFO_ENTRY) {
  76. fusb300->fifo_entry_num = 0;
  77. fusb300->addrofs = 0;
  78. pr_err("fifo entry is over the maximum number!\n");
  79. } else
  80. fusb300->fifo_entry_num++;
  81. }
  82. /* set fusb300_set_start_entry first before fusb300_set_epaddrofs */
  83. static void fusb300_set_epaddrofs(struct fusb300 *fusb300,
  84. struct fusb300_ep_info info)
  85. {
  86. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum));
  87. reg &= ~FUSB300_EPSET2_ADDROFS_MSK;
  88. reg |= FUSB300_EPSET2_ADDROFS(fusb300->addrofs);
  89. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum));
  90. fusb300->addrofs += (info.maxpacket + 7) / 8 * FUSB300_FIFO_ENTRY_NUM;
  91. }
  92. static void ep_fifo_setting(struct fusb300 *fusb300,
  93. struct fusb300_ep_info info)
  94. {
  95. fusb300_set_fifo_entry(fusb300, info.epnum);
  96. fusb300_set_start_entry(fusb300, info.epnum);
  97. fusb300_set_epaddrofs(fusb300, info);
  98. }
  99. static void fusb300_set_eptype(struct fusb300 *fusb300,
  100. struct fusb300_ep_info info)
  101. {
  102. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
  103. reg &= ~FUSB300_EPSET1_TYPE_MSK;
  104. reg |= FUSB300_EPSET1_TYPE(info.type);
  105. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
  106. }
  107. static void fusb300_set_epdir(struct fusb300 *fusb300,
  108. struct fusb300_ep_info info)
  109. {
  110. u32 reg;
  111. if (!info.dir_in)
  112. return;
  113. reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
  114. reg &= ~FUSB300_EPSET1_DIR_MSK;
  115. reg |= FUSB300_EPSET1_DIRIN;
  116. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
  117. }
  118. static void fusb300_set_ep_active(struct fusb300 *fusb300,
  119. u8 ep)
  120. {
  121. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
  122. reg |= FUSB300_EPSET1_ACTEN;
  123. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
  124. }
  125. static void fusb300_set_epmps(struct fusb300 *fusb300,
  126. struct fusb300_ep_info info)
  127. {
  128. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum));
  129. reg &= ~FUSB300_EPSET2_MPS_MSK;
  130. reg |= FUSB300_EPSET2_MPS(info.maxpacket);
  131. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum));
  132. }
  133. static void fusb300_set_interval(struct fusb300 *fusb300,
  134. struct fusb300_ep_info info)
  135. {
  136. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
  137. reg &= ~FUSB300_EPSET1_INTERVAL(0x7);
  138. reg |= FUSB300_EPSET1_INTERVAL(info.interval);
  139. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
  140. }
  141. static void fusb300_set_bwnum(struct fusb300 *fusb300,
  142. struct fusb300_ep_info info)
  143. {
  144. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
  145. reg &= ~FUSB300_EPSET1_BWNUM(0x3);
  146. reg |= FUSB300_EPSET1_BWNUM(info.bw_num);
  147. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
  148. }
  149. static void set_ep_reg(struct fusb300 *fusb300,
  150. struct fusb300_ep_info info)
  151. {
  152. fusb300_set_eptype(fusb300, info);
  153. fusb300_set_epdir(fusb300, info);
  154. fusb300_set_epmps(fusb300, info);
  155. if (info.interval)
  156. fusb300_set_interval(fusb300, info);
  157. if (info.bw_num)
  158. fusb300_set_bwnum(fusb300, info);
  159. fusb300_set_ep_active(fusb300, info.epnum);
  160. }
  161. static int config_ep(struct fusb300_ep *ep,
  162. const struct usb_endpoint_descriptor *desc)
  163. {
  164. struct fusb300 *fusb300 = ep->fusb300;
  165. struct fusb300_ep_info info;
  166. ep->ep.desc = desc;
  167. info.interval = 0;
  168. info.addrofs = 0;
  169. info.bw_num = 0;
  170. info.type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
  171. info.dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
  172. info.maxpacket = usb_endpoint_maxp(desc);
  173. info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
  174. if ((info.type == USB_ENDPOINT_XFER_INT) ||
  175. (info.type == USB_ENDPOINT_XFER_ISOC)) {
  176. info.interval = desc->bInterval;
  177. if (info.type == USB_ENDPOINT_XFER_ISOC)
  178. info.bw_num = usb_endpoint_maxp_mult(desc);
  179. }
  180. ep_fifo_setting(fusb300, info);
  181. set_ep_reg(fusb300, info);
  182. fusb300_ep_setting(ep, info);
  183. fusb300->ep[info.epnum] = ep;
  184. return 0;
  185. }
  186. static int fusb300_enable(struct usb_ep *_ep,
  187. const struct usb_endpoint_descriptor *desc)
  188. {
  189. struct fusb300_ep *ep;
  190. ep = container_of(_ep, struct fusb300_ep, ep);
  191. if (ep->fusb300->reenum) {
  192. ep->fusb300->fifo_entry_num = 0;
  193. ep->fusb300->addrofs = 0;
  194. ep->fusb300->reenum = 0;
  195. }
  196. return config_ep(ep, desc);
  197. }
  198. static int fusb300_disable(struct usb_ep *_ep)
  199. {
  200. struct fusb300_ep *ep;
  201. struct fusb300_request *req;
  202. unsigned long flags;
  203. ep = container_of(_ep, struct fusb300_ep, ep);
  204. BUG_ON(!ep);
  205. while (!list_empty(&ep->queue)) {
  206. req = list_entry(ep->queue.next, struct fusb300_request, queue);
  207. spin_lock_irqsave(&ep->fusb300->lock, flags);
  208. done(ep, req, -ECONNRESET);
  209. spin_unlock_irqrestore(&ep->fusb300->lock, flags);
  210. }
  211. return fusb300_ep_release(ep);
  212. }
  213. static struct usb_request *fusb300_alloc_request(struct usb_ep *_ep,
  214. gfp_t gfp_flags)
  215. {
  216. struct fusb300_request *req;
  217. req = kzalloc(sizeof(struct fusb300_request), gfp_flags);
  218. if (!req)
  219. return NULL;
  220. INIT_LIST_HEAD(&req->queue);
  221. return &req->req;
  222. }
  223. static void fusb300_free_request(struct usb_ep *_ep, struct usb_request *_req)
  224. {
  225. struct fusb300_request *req;
  226. req = container_of(_req, struct fusb300_request, req);
  227. kfree(req);
  228. }
  229. static int enable_fifo_int(struct fusb300_ep *ep)
  230. {
  231. struct fusb300 *fusb300 = ep->fusb300;
  232. if (ep->epnum) {
  233. fusb300_enable_bit(fusb300, FUSB300_OFFSET_IGER0,
  234. FUSB300_IGER0_EEPn_FIFO_INT(ep->epnum));
  235. } else {
  236. pr_err("can't enable_fifo_int ep0\n");
  237. return -EINVAL;
  238. }
  239. return 0;
  240. }
  241. static int disable_fifo_int(struct fusb300_ep *ep)
  242. {
  243. struct fusb300 *fusb300 = ep->fusb300;
  244. if (ep->epnum) {
  245. fusb300_disable_bit(fusb300, FUSB300_OFFSET_IGER0,
  246. FUSB300_IGER0_EEPn_FIFO_INT(ep->epnum));
  247. } else {
  248. pr_err("can't disable_fifo_int ep0\n");
  249. return -EINVAL;
  250. }
  251. return 0;
  252. }
  253. static void fusb300_set_cxlen(struct fusb300 *fusb300, u32 length)
  254. {
  255. u32 reg;
  256. reg = ioread32(fusb300->reg + FUSB300_OFFSET_CSR);
  257. reg &= ~FUSB300_CSR_LEN_MSK;
  258. reg |= FUSB300_CSR_LEN(length);
  259. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_CSR);
  260. }
  261. /* write data to cx fifo */
  262. static void fusb300_wrcxf(struct fusb300_ep *ep,
  263. struct fusb300_request *req)
  264. {
  265. int i = 0;
  266. u8 *tmp;
  267. u32 data;
  268. struct fusb300 *fusb300 = ep->fusb300;
  269. u32 length = req->req.length - req->req.actual;
  270. tmp = req->req.buf + req->req.actual;
  271. if (length > SS_CTL_MAX_PACKET_SIZE) {
  272. fusb300_set_cxlen(fusb300, SS_CTL_MAX_PACKET_SIZE);
  273. for (i = (SS_CTL_MAX_PACKET_SIZE >> 2); i > 0; i--) {
  274. data = *tmp | *(tmp + 1) << 8 | *(tmp + 2) << 16 |
  275. *(tmp + 3) << 24;
  276. iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT);
  277. tmp += 4;
  278. }
  279. req->req.actual += SS_CTL_MAX_PACKET_SIZE;
  280. } else { /* length is less than max packet size */
  281. fusb300_set_cxlen(fusb300, length);
  282. for (i = length >> 2; i > 0; i--) {
  283. data = *tmp | *(tmp + 1) << 8 | *(tmp + 2) << 16 |
  284. *(tmp + 3) << 24;
  285. printk(KERN_DEBUG " 0x%x\n", data);
  286. iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT);
  287. tmp = tmp + 4;
  288. }
  289. switch (length % 4) {
  290. case 1:
  291. data = *tmp;
  292. printk(KERN_DEBUG " 0x%x\n", data);
  293. iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT);
  294. break;
  295. case 2:
  296. data = *tmp | *(tmp + 1) << 8;
  297. printk(KERN_DEBUG " 0x%x\n", data);
  298. iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT);
  299. break;
  300. case 3:
  301. data = *tmp | *(tmp + 1) << 8 | *(tmp + 2) << 16;
  302. printk(KERN_DEBUG " 0x%x\n", data);
  303. iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT);
  304. break;
  305. default:
  306. break;
  307. }
  308. req->req.actual += length;
  309. }
  310. }
  311. static void fusb300_set_epnstall(struct fusb300 *fusb300, u8 ep)
  312. {
  313. fusb300_enable_bit(fusb300, FUSB300_OFFSET_EPSET0(ep),
  314. FUSB300_EPSET0_STL);
  315. }
  316. static void fusb300_clear_epnstall(struct fusb300 *fusb300, u8 ep)
  317. {
  318. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET0(ep));
  319. if (reg & FUSB300_EPSET0_STL) {
  320. printk(KERN_DEBUG "EP%d stall... Clear!!\n", ep);
  321. reg |= FUSB300_EPSET0_STL_CLR;
  322. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET0(ep));
  323. }
  324. }
  325. static void ep0_queue(struct fusb300_ep *ep, struct fusb300_request *req)
  326. {
  327. if (ep->fusb300->ep0_dir) { /* if IN */
  328. if (req->req.length) {
  329. fusb300_wrcxf(ep, req);
  330. } else
  331. printk(KERN_DEBUG "%s : req->req.length = 0x%x\n",
  332. __func__, req->req.length);
  333. if ((req->req.length == req->req.actual) ||
  334. (req->req.actual < ep->ep.maxpacket))
  335. done(ep, req, 0);
  336. } else { /* OUT */
  337. if (!req->req.length)
  338. done(ep, req, 0);
  339. else
  340. fusb300_enable_bit(ep->fusb300, FUSB300_OFFSET_IGER1,
  341. FUSB300_IGER1_CX_OUT_INT);
  342. }
  343. }
  344. static int fusb300_queue(struct usb_ep *_ep, struct usb_request *_req,
  345. gfp_t gfp_flags)
  346. {
  347. struct fusb300_ep *ep;
  348. struct fusb300_request *req;
  349. unsigned long flags;
  350. int request = 0;
  351. ep = container_of(_ep, struct fusb300_ep, ep);
  352. req = container_of(_req, struct fusb300_request, req);
  353. if (ep->fusb300->gadget.speed == USB_SPEED_UNKNOWN)
  354. return -ESHUTDOWN;
  355. spin_lock_irqsave(&ep->fusb300->lock, flags);
  356. if (list_empty(&ep->queue))
  357. request = 1;
  358. list_add_tail(&req->queue, &ep->queue);
  359. req->req.actual = 0;
  360. req->req.status = -EINPROGRESS;
  361. if (ep->ep.desc == NULL) /* ep0 */
  362. ep0_queue(ep, req);
  363. else if (request && !ep->stall)
  364. enable_fifo_int(ep);
  365. spin_unlock_irqrestore(&ep->fusb300->lock, flags);
  366. return 0;
  367. }
  368. static int fusb300_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  369. {
  370. struct fusb300_ep *ep;
  371. struct fusb300_request *req;
  372. unsigned long flags;
  373. ep = container_of(_ep, struct fusb300_ep, ep);
  374. req = container_of(_req, struct fusb300_request, req);
  375. spin_lock_irqsave(&ep->fusb300->lock, flags);
  376. if (!list_empty(&ep->queue))
  377. done(ep, req, -ECONNRESET);
  378. spin_unlock_irqrestore(&ep->fusb300->lock, flags);
  379. return 0;
  380. }
  381. static int fusb300_set_halt_and_wedge(struct usb_ep *_ep, int value, int wedge)
  382. {
  383. struct fusb300_ep *ep;
  384. struct fusb300 *fusb300;
  385. unsigned long flags;
  386. int ret = 0;
  387. ep = container_of(_ep, struct fusb300_ep, ep);
  388. fusb300 = ep->fusb300;
  389. spin_lock_irqsave(&ep->fusb300->lock, flags);
  390. if (!list_empty(&ep->queue)) {
  391. ret = -EAGAIN;
  392. goto out;
  393. }
  394. if (value) {
  395. fusb300_set_epnstall(fusb300, ep->epnum);
  396. ep->stall = 1;
  397. if (wedge)
  398. ep->wedged = 1;
  399. } else {
  400. fusb300_clear_epnstall(fusb300, ep->epnum);
  401. ep->stall = 0;
  402. ep->wedged = 0;
  403. }
  404. out:
  405. spin_unlock_irqrestore(&ep->fusb300->lock, flags);
  406. return ret;
  407. }
  408. static int fusb300_set_halt(struct usb_ep *_ep, int value)
  409. {
  410. return fusb300_set_halt_and_wedge(_ep, value, 0);
  411. }
  412. static int fusb300_set_wedge(struct usb_ep *_ep)
  413. {
  414. return fusb300_set_halt_and_wedge(_ep, 1, 1);
  415. }
  416. static void fusb300_fifo_flush(struct usb_ep *_ep)
  417. {
  418. }
  419. static const struct usb_ep_ops fusb300_ep_ops = {
  420. .enable = fusb300_enable,
  421. .disable = fusb300_disable,
  422. .alloc_request = fusb300_alloc_request,
  423. .free_request = fusb300_free_request,
  424. .queue = fusb300_queue,
  425. .dequeue = fusb300_dequeue,
  426. .set_halt = fusb300_set_halt,
  427. .fifo_flush = fusb300_fifo_flush,
  428. .set_wedge = fusb300_set_wedge,
  429. };
  430. /*****************************************************************************/
  431. static void fusb300_clear_int(struct fusb300 *fusb300, u32 offset,
  432. u32 value)
  433. {
  434. iowrite32(value, fusb300->reg + offset);
  435. }
  436. static void fusb300_reset(void)
  437. {
  438. }
  439. static void fusb300_set_cxstall(struct fusb300 *fusb300)
  440. {
  441. fusb300_enable_bit(fusb300, FUSB300_OFFSET_CSR,
  442. FUSB300_CSR_STL);
  443. }
  444. static void fusb300_set_cxdone(struct fusb300 *fusb300)
  445. {
  446. fusb300_enable_bit(fusb300, FUSB300_OFFSET_CSR,
  447. FUSB300_CSR_DONE);
  448. }
  449. /* read data from cx fifo */
  450. static void fusb300_rdcxf(struct fusb300 *fusb300,
  451. u8 *buffer, u32 length)
  452. {
  453. int i = 0;
  454. u8 *tmp;
  455. u32 data;
  456. tmp = buffer;
  457. for (i = (length >> 2); i > 0; i--) {
  458. data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT);
  459. printk(KERN_DEBUG " 0x%x\n", data);
  460. *tmp = data & 0xFF;
  461. *(tmp + 1) = (data >> 8) & 0xFF;
  462. *(tmp + 2) = (data >> 16) & 0xFF;
  463. *(tmp + 3) = (data >> 24) & 0xFF;
  464. tmp = tmp + 4;
  465. }
  466. switch (length % 4) {
  467. case 1:
  468. data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT);
  469. printk(KERN_DEBUG " 0x%x\n", data);
  470. *tmp = data & 0xFF;
  471. break;
  472. case 2:
  473. data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT);
  474. printk(KERN_DEBUG " 0x%x\n", data);
  475. *tmp = data & 0xFF;
  476. *(tmp + 1) = (data >> 8) & 0xFF;
  477. break;
  478. case 3:
  479. data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT);
  480. printk(KERN_DEBUG " 0x%x\n", data);
  481. *tmp = data & 0xFF;
  482. *(tmp + 1) = (data >> 8) & 0xFF;
  483. *(tmp + 2) = (data >> 16) & 0xFF;
  484. break;
  485. default:
  486. break;
  487. }
  488. }
  489. static void fusb300_rdfifo(struct fusb300_ep *ep,
  490. struct fusb300_request *req,
  491. u32 length)
  492. {
  493. int i = 0;
  494. u8 *tmp;
  495. u32 data, reg;
  496. struct fusb300 *fusb300 = ep->fusb300;
  497. tmp = req->req.buf + req->req.actual;
  498. req->req.actual += length;
  499. if (req->req.actual > req->req.length)
  500. printk(KERN_DEBUG "req->req.actual > req->req.length\n");
  501. for (i = (length >> 2); i > 0; i--) {
  502. data = ioread32(fusb300->reg +
  503. FUSB300_OFFSET_EPPORT(ep->epnum));
  504. *tmp = data & 0xFF;
  505. *(tmp + 1) = (data >> 8) & 0xFF;
  506. *(tmp + 2) = (data >> 16) & 0xFF;
  507. *(tmp + 3) = (data >> 24) & 0xFF;
  508. tmp = tmp + 4;
  509. }
  510. switch (length % 4) {
  511. case 1:
  512. data = ioread32(fusb300->reg +
  513. FUSB300_OFFSET_EPPORT(ep->epnum));
  514. *tmp = data & 0xFF;
  515. break;
  516. case 2:
  517. data = ioread32(fusb300->reg +
  518. FUSB300_OFFSET_EPPORT(ep->epnum));
  519. *tmp = data & 0xFF;
  520. *(tmp + 1) = (data >> 8) & 0xFF;
  521. break;
  522. case 3:
  523. data = ioread32(fusb300->reg +
  524. FUSB300_OFFSET_EPPORT(ep->epnum));
  525. *tmp = data & 0xFF;
  526. *(tmp + 1) = (data >> 8) & 0xFF;
  527. *(tmp + 2) = (data >> 16) & 0xFF;
  528. break;
  529. default:
  530. break;
  531. }
  532. do {
  533. reg = ioread32(fusb300->reg + FUSB300_OFFSET_IGR1);
  534. reg &= FUSB300_IGR1_SYNF0_EMPTY_INT;
  535. if (i)
  536. printk(KERN_INFO "sync fifo is not empty!\n");
  537. i++;
  538. } while (!reg);
  539. }
  540. static u8 fusb300_get_epnstall(struct fusb300 *fusb300, u8 ep)
  541. {
  542. u8 value;
  543. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET0(ep));
  544. value = reg & FUSB300_EPSET0_STL;
  545. return value;
  546. }
  547. static u8 fusb300_get_cxstall(struct fusb300 *fusb300)
  548. {
  549. u8 value;
  550. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_CSR);
  551. value = (reg & FUSB300_CSR_STL) >> 1;
  552. return value;
  553. }
  554. static void request_error(struct fusb300 *fusb300)
  555. {
  556. fusb300_set_cxstall(fusb300);
  557. printk(KERN_DEBUG "request error!!\n");
  558. }
  559. static void get_status(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl)
  560. __releases(fusb300->lock)
  561. __acquires(fusb300->lock)
  562. {
  563. u8 ep;
  564. u16 status = 0;
  565. u16 w_index = ctrl->wIndex;
  566. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  567. case USB_RECIP_DEVICE:
  568. status = 1 << USB_DEVICE_SELF_POWERED;
  569. break;
  570. case USB_RECIP_INTERFACE:
  571. status = 0;
  572. break;
  573. case USB_RECIP_ENDPOINT:
  574. ep = w_index & USB_ENDPOINT_NUMBER_MASK;
  575. if (ep) {
  576. if (fusb300_get_epnstall(fusb300, ep))
  577. status = 1 << USB_ENDPOINT_HALT;
  578. } else {
  579. if (fusb300_get_cxstall(fusb300))
  580. status = 0;
  581. }
  582. break;
  583. default:
  584. request_error(fusb300);
  585. return; /* exit */
  586. }
  587. fusb300->ep0_data = cpu_to_le16(status);
  588. fusb300->ep0_req->buf = &fusb300->ep0_data;
  589. fusb300->ep0_req->length = 2;
  590. spin_unlock(&fusb300->lock);
  591. fusb300_queue(fusb300->gadget.ep0, fusb300->ep0_req, GFP_KERNEL);
  592. spin_lock(&fusb300->lock);
  593. }
  594. static void set_feature(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl)
  595. {
  596. u8 ep;
  597. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  598. case USB_RECIP_DEVICE:
  599. fusb300_set_cxdone(fusb300);
  600. break;
  601. case USB_RECIP_INTERFACE:
  602. fusb300_set_cxdone(fusb300);
  603. break;
  604. case USB_RECIP_ENDPOINT: {
  605. u16 w_index = le16_to_cpu(ctrl->wIndex);
  606. ep = w_index & USB_ENDPOINT_NUMBER_MASK;
  607. if (ep)
  608. fusb300_set_epnstall(fusb300, ep);
  609. else
  610. fusb300_set_cxstall(fusb300);
  611. fusb300_set_cxdone(fusb300);
  612. }
  613. break;
  614. default:
  615. request_error(fusb300);
  616. break;
  617. }
  618. }
  619. static void fusb300_clear_seqnum(struct fusb300 *fusb300, u8 ep)
  620. {
  621. fusb300_enable_bit(fusb300, FUSB300_OFFSET_EPSET0(ep),
  622. FUSB300_EPSET0_CLRSEQNUM);
  623. }
  624. static void clear_feature(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl)
  625. {
  626. struct fusb300_ep *ep =
  627. fusb300->ep[ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK];
  628. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  629. case USB_RECIP_DEVICE:
  630. fusb300_set_cxdone(fusb300);
  631. break;
  632. case USB_RECIP_INTERFACE:
  633. fusb300_set_cxdone(fusb300);
  634. break;
  635. case USB_RECIP_ENDPOINT:
  636. if (ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK) {
  637. if (ep->wedged) {
  638. fusb300_set_cxdone(fusb300);
  639. break;
  640. }
  641. if (ep->stall) {
  642. ep->stall = 0;
  643. fusb300_clear_seqnum(fusb300, ep->epnum);
  644. fusb300_clear_epnstall(fusb300, ep->epnum);
  645. if (!list_empty(&ep->queue))
  646. enable_fifo_int(ep);
  647. }
  648. }
  649. fusb300_set_cxdone(fusb300);
  650. break;
  651. default:
  652. request_error(fusb300);
  653. break;
  654. }
  655. }
  656. static void fusb300_set_dev_addr(struct fusb300 *fusb300, u16 addr)
  657. {
  658. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_DAR);
  659. reg &= ~FUSB300_DAR_DRVADDR_MSK;
  660. reg |= FUSB300_DAR_DRVADDR(addr);
  661. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_DAR);
  662. }
  663. static void set_address(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl)
  664. {
  665. if (ctrl->wValue >= 0x0100)
  666. request_error(fusb300);
  667. else {
  668. fusb300_set_dev_addr(fusb300, ctrl->wValue);
  669. fusb300_set_cxdone(fusb300);
  670. }
  671. }
  672. #define UVC_COPY_DESCRIPTORS(mem, src) \
  673. do { \
  674. const struct usb_descriptor_header * const *__src; \
  675. for (__src = src; *__src; ++__src) { \
  676. memcpy(mem, *__src, (*__src)->bLength); \
  677. mem += (*__src)->bLength; \
  678. } \
  679. } while (0)
  680. static int setup_packet(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl)
  681. {
  682. u8 *p = (u8 *)ctrl;
  683. u8 ret = 0;
  684. u8 i = 0;
  685. fusb300_rdcxf(fusb300, p, 8);
  686. fusb300->ep0_dir = ctrl->bRequestType & USB_DIR_IN;
  687. fusb300->ep0_length = ctrl->wLength;
  688. /* check request */
  689. if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
  690. switch (ctrl->bRequest) {
  691. case USB_REQ_GET_STATUS:
  692. get_status(fusb300, ctrl);
  693. break;
  694. case USB_REQ_CLEAR_FEATURE:
  695. clear_feature(fusb300, ctrl);
  696. break;
  697. case USB_REQ_SET_FEATURE:
  698. set_feature(fusb300, ctrl);
  699. break;
  700. case USB_REQ_SET_ADDRESS:
  701. set_address(fusb300, ctrl);
  702. break;
  703. case USB_REQ_SET_CONFIGURATION:
  704. fusb300_enable_bit(fusb300, FUSB300_OFFSET_DAR,
  705. FUSB300_DAR_SETCONFG);
  706. /* clear sequence number */
  707. for (i = 1; i <= FUSB300_MAX_NUM_EP; i++)
  708. fusb300_clear_seqnum(fusb300, i);
  709. fusb300->reenum = 1;
  710. ret = 1;
  711. break;
  712. default:
  713. ret = 1;
  714. break;
  715. }
  716. } else
  717. ret = 1;
  718. return ret;
  719. }
  720. static void done(struct fusb300_ep *ep, struct fusb300_request *req,
  721. int status)
  722. {
  723. list_del_init(&req->queue);
  724. /* don't modify queue heads during completion callback */
  725. if (ep->fusb300->gadget.speed == USB_SPEED_UNKNOWN)
  726. req->req.status = -ESHUTDOWN;
  727. else
  728. req->req.status = status;
  729. spin_unlock(&ep->fusb300->lock);
  730. usb_gadget_giveback_request(&ep->ep, &req->req);
  731. spin_lock(&ep->fusb300->lock);
  732. if (ep->epnum) {
  733. disable_fifo_int(ep);
  734. if (!list_empty(&ep->queue))
  735. enable_fifo_int(ep);
  736. } else
  737. fusb300_set_cxdone(ep->fusb300);
  738. }
  739. static void fusb300_fill_idma_prdtbl(struct fusb300_ep *ep, dma_addr_t d,
  740. u32 len)
  741. {
  742. u32 value;
  743. u32 reg;
  744. /* wait SW owner */
  745. do {
  746. reg = ioread32(ep->fusb300->reg +
  747. FUSB300_OFFSET_EPPRD_W0(ep->epnum));
  748. reg &= FUSB300_EPPRD0_H;
  749. } while (reg);
  750. iowrite32(d, ep->fusb300->reg + FUSB300_OFFSET_EPPRD_W1(ep->epnum));
  751. value = FUSB300_EPPRD0_BTC(len) | FUSB300_EPPRD0_H |
  752. FUSB300_EPPRD0_F | FUSB300_EPPRD0_L | FUSB300_EPPRD0_I;
  753. iowrite32(value, ep->fusb300->reg + FUSB300_OFFSET_EPPRD_W0(ep->epnum));
  754. iowrite32(0x0, ep->fusb300->reg + FUSB300_OFFSET_EPPRD_W2(ep->epnum));
  755. fusb300_enable_bit(ep->fusb300, FUSB300_OFFSET_EPPRDRDY,
  756. FUSB300_EPPRDR_EP_PRD_RDY(ep->epnum));
  757. }
  758. static void fusb300_wait_idma_finished(struct fusb300_ep *ep)
  759. {
  760. u32 reg;
  761. do {
  762. reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_IGR1);
  763. if ((reg & FUSB300_IGR1_VBUS_CHG_INT) ||
  764. (reg & FUSB300_IGR1_WARM_RST_INT) ||
  765. (reg & FUSB300_IGR1_HOT_RST_INT) ||
  766. (reg & FUSB300_IGR1_USBRST_INT)
  767. )
  768. goto IDMA_RESET;
  769. reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_IGR0);
  770. reg &= FUSB300_IGR0_EPn_PRD_INT(ep->epnum);
  771. } while (!reg);
  772. fusb300_clear_int(ep->fusb300, FUSB300_OFFSET_IGR0,
  773. FUSB300_IGR0_EPn_PRD_INT(ep->epnum));
  774. return;
  775. IDMA_RESET:
  776. reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_IGER0);
  777. reg &= ~FUSB300_IGER0_EEPn_PRD_INT(ep->epnum);
  778. iowrite32(reg, ep->fusb300->reg + FUSB300_OFFSET_IGER0);
  779. }
  780. static void fusb300_set_idma(struct fusb300_ep *ep,
  781. struct fusb300_request *req)
  782. {
  783. int ret;
  784. ret = usb_gadget_map_request(&ep->fusb300->gadget,
  785. &req->req, DMA_TO_DEVICE);
  786. if (ret)
  787. return;
  788. fusb300_enable_bit(ep->fusb300, FUSB300_OFFSET_IGER0,
  789. FUSB300_IGER0_EEPn_PRD_INT(ep->epnum));
  790. fusb300_fill_idma_prdtbl(ep, req->req.dma, req->req.length);
  791. /* check idma is done */
  792. fusb300_wait_idma_finished(ep);
  793. usb_gadget_unmap_request(&ep->fusb300->gadget,
  794. &req->req, DMA_TO_DEVICE);
  795. }
  796. static void in_ep_fifo_handler(struct fusb300_ep *ep)
  797. {
  798. struct fusb300_request *req = list_entry(ep->queue.next,
  799. struct fusb300_request, queue);
  800. if (req->req.length)
  801. fusb300_set_idma(ep, req);
  802. done(ep, req, 0);
  803. }
  804. static void out_ep_fifo_handler(struct fusb300_ep *ep)
  805. {
  806. struct fusb300 *fusb300 = ep->fusb300;
  807. struct fusb300_request *req = list_entry(ep->queue.next,
  808. struct fusb300_request, queue);
  809. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPFFR(ep->epnum));
  810. u32 length = reg & FUSB300_FFR_BYCNT;
  811. fusb300_rdfifo(ep, req, length);
  812. /* finish out transfer */
  813. if ((req->req.length == req->req.actual) || (length < ep->ep.maxpacket))
  814. done(ep, req, 0);
  815. }
  816. static void check_device_mode(struct fusb300 *fusb300)
  817. {
  818. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_GCR);
  819. switch (reg & FUSB300_GCR_DEVEN_MSK) {
  820. case FUSB300_GCR_DEVEN_SS:
  821. fusb300->gadget.speed = USB_SPEED_SUPER;
  822. break;
  823. case FUSB300_GCR_DEVEN_HS:
  824. fusb300->gadget.speed = USB_SPEED_HIGH;
  825. break;
  826. case FUSB300_GCR_DEVEN_FS:
  827. fusb300->gadget.speed = USB_SPEED_FULL;
  828. break;
  829. default:
  830. fusb300->gadget.speed = USB_SPEED_UNKNOWN;
  831. break;
  832. }
  833. printk(KERN_INFO "dev_mode = %d\n", (reg & FUSB300_GCR_DEVEN_MSK));
  834. }
  835. static void fusb300_ep0out(struct fusb300 *fusb300)
  836. {
  837. struct fusb300_ep *ep = fusb300->ep[0];
  838. u32 reg;
  839. if (!list_empty(&ep->queue)) {
  840. struct fusb300_request *req;
  841. req = list_first_entry(&ep->queue,
  842. struct fusb300_request, queue);
  843. if (req->req.length)
  844. fusb300_rdcxf(ep->fusb300, req->req.buf,
  845. req->req.length);
  846. done(ep, req, 0);
  847. reg = ioread32(fusb300->reg + FUSB300_OFFSET_IGER1);
  848. reg &= ~FUSB300_IGER1_CX_OUT_INT;
  849. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_IGER1);
  850. } else
  851. pr_err("%s : empty queue\n", __func__);
  852. }
  853. static void fusb300_ep0in(struct fusb300 *fusb300)
  854. {
  855. struct fusb300_request *req;
  856. struct fusb300_ep *ep = fusb300->ep[0];
  857. if ((!list_empty(&ep->queue)) && (fusb300->ep0_dir)) {
  858. req = list_entry(ep->queue.next,
  859. struct fusb300_request, queue);
  860. if (req->req.length)
  861. fusb300_wrcxf(ep, req);
  862. if ((req->req.length - req->req.actual) < ep->ep.maxpacket)
  863. done(ep, req, 0);
  864. } else
  865. fusb300_set_cxdone(fusb300);
  866. }
  867. static void fusb300_grp2_handler(void)
  868. {
  869. }
  870. static void fusb300_grp3_handler(void)
  871. {
  872. }
  873. static void fusb300_grp4_handler(void)
  874. {
  875. }
  876. static void fusb300_grp5_handler(void)
  877. {
  878. }
  879. static irqreturn_t fusb300_irq(int irq, void *_fusb300)
  880. {
  881. struct fusb300 *fusb300 = _fusb300;
  882. u32 int_grp1 = ioread32(fusb300->reg + FUSB300_OFFSET_IGR1);
  883. u32 int_grp1_en = ioread32(fusb300->reg + FUSB300_OFFSET_IGER1);
  884. u32 int_grp0 = ioread32(fusb300->reg + FUSB300_OFFSET_IGR0);
  885. u32 int_grp0_en = ioread32(fusb300->reg + FUSB300_OFFSET_IGER0);
  886. struct usb_ctrlrequest ctrl;
  887. u8 in;
  888. u32 reg;
  889. int i;
  890. spin_lock(&fusb300->lock);
  891. int_grp1 &= int_grp1_en;
  892. int_grp0 &= int_grp0_en;
  893. if (int_grp1 & FUSB300_IGR1_WARM_RST_INT) {
  894. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  895. FUSB300_IGR1_WARM_RST_INT);
  896. printk(KERN_INFO"fusb300_warmreset\n");
  897. fusb300_reset();
  898. }
  899. if (int_grp1 & FUSB300_IGR1_HOT_RST_INT) {
  900. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  901. FUSB300_IGR1_HOT_RST_INT);
  902. printk(KERN_INFO"fusb300_hotreset\n");
  903. fusb300_reset();
  904. }
  905. if (int_grp1 & FUSB300_IGR1_USBRST_INT) {
  906. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  907. FUSB300_IGR1_USBRST_INT);
  908. fusb300_reset();
  909. }
  910. /* COMABT_INT has a highest priority */
  911. if (int_grp1 & FUSB300_IGR1_CX_COMABT_INT) {
  912. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  913. FUSB300_IGR1_CX_COMABT_INT);
  914. printk(KERN_INFO"fusb300_ep0abt\n");
  915. }
  916. if (int_grp1 & FUSB300_IGR1_VBUS_CHG_INT) {
  917. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  918. FUSB300_IGR1_VBUS_CHG_INT);
  919. printk(KERN_INFO"fusb300_vbus_change\n");
  920. }
  921. if (int_grp1 & FUSB300_IGR1_U3_EXIT_FAIL_INT) {
  922. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  923. FUSB300_IGR1_U3_EXIT_FAIL_INT);
  924. }
  925. if (int_grp1 & FUSB300_IGR1_U2_EXIT_FAIL_INT) {
  926. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  927. FUSB300_IGR1_U2_EXIT_FAIL_INT);
  928. }
  929. if (int_grp1 & FUSB300_IGR1_U1_EXIT_FAIL_INT) {
  930. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  931. FUSB300_IGR1_U1_EXIT_FAIL_INT);
  932. }
  933. if (int_grp1 & FUSB300_IGR1_U2_ENTRY_FAIL_INT) {
  934. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  935. FUSB300_IGR1_U2_ENTRY_FAIL_INT);
  936. }
  937. if (int_grp1 & FUSB300_IGR1_U1_ENTRY_FAIL_INT) {
  938. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  939. FUSB300_IGR1_U1_ENTRY_FAIL_INT);
  940. }
  941. if (int_grp1 & FUSB300_IGR1_U3_EXIT_INT) {
  942. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  943. FUSB300_IGR1_U3_EXIT_INT);
  944. printk(KERN_INFO "FUSB300_IGR1_U3_EXIT_INT\n");
  945. }
  946. if (int_grp1 & FUSB300_IGR1_U2_EXIT_INT) {
  947. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  948. FUSB300_IGR1_U2_EXIT_INT);
  949. printk(KERN_INFO "FUSB300_IGR1_U2_EXIT_INT\n");
  950. }
  951. if (int_grp1 & FUSB300_IGR1_U1_EXIT_INT) {
  952. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  953. FUSB300_IGR1_U1_EXIT_INT);
  954. printk(KERN_INFO "FUSB300_IGR1_U1_EXIT_INT\n");
  955. }
  956. if (int_grp1 & FUSB300_IGR1_U3_ENTRY_INT) {
  957. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  958. FUSB300_IGR1_U3_ENTRY_INT);
  959. printk(KERN_INFO "FUSB300_IGR1_U3_ENTRY_INT\n");
  960. fusb300_enable_bit(fusb300, FUSB300_OFFSET_SSCR1,
  961. FUSB300_SSCR1_GO_U3_DONE);
  962. }
  963. if (int_grp1 & FUSB300_IGR1_U2_ENTRY_INT) {
  964. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  965. FUSB300_IGR1_U2_ENTRY_INT);
  966. printk(KERN_INFO "FUSB300_IGR1_U2_ENTRY_INT\n");
  967. }
  968. if (int_grp1 & FUSB300_IGR1_U1_ENTRY_INT) {
  969. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  970. FUSB300_IGR1_U1_ENTRY_INT);
  971. printk(KERN_INFO "FUSB300_IGR1_U1_ENTRY_INT\n");
  972. }
  973. if (int_grp1 & FUSB300_IGR1_RESM_INT) {
  974. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  975. FUSB300_IGR1_RESM_INT);
  976. printk(KERN_INFO "fusb300_resume\n");
  977. }
  978. if (int_grp1 & FUSB300_IGR1_SUSP_INT) {
  979. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  980. FUSB300_IGR1_SUSP_INT);
  981. printk(KERN_INFO "fusb300_suspend\n");
  982. }
  983. if (int_grp1 & FUSB300_IGR1_HS_LPM_INT) {
  984. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  985. FUSB300_IGR1_HS_LPM_INT);
  986. printk(KERN_INFO "fusb300_HS_LPM_INT\n");
  987. }
  988. if (int_grp1 & FUSB300_IGR1_DEV_MODE_CHG_INT) {
  989. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  990. FUSB300_IGR1_DEV_MODE_CHG_INT);
  991. check_device_mode(fusb300);
  992. }
  993. if (int_grp1 & FUSB300_IGR1_CX_COMFAIL_INT) {
  994. fusb300_set_cxstall(fusb300);
  995. printk(KERN_INFO "fusb300_ep0fail\n");
  996. }
  997. if (int_grp1 & FUSB300_IGR1_CX_SETUP_INT) {
  998. printk(KERN_INFO "fusb300_ep0setup\n");
  999. if (setup_packet(fusb300, &ctrl)) {
  1000. spin_unlock(&fusb300->lock);
  1001. if (fusb300->driver->setup(&fusb300->gadget, &ctrl) < 0)
  1002. fusb300_set_cxstall(fusb300);
  1003. spin_lock(&fusb300->lock);
  1004. }
  1005. }
  1006. if (int_grp1 & FUSB300_IGR1_CX_CMDEND_INT)
  1007. printk(KERN_INFO "fusb300_cmdend\n");
  1008. if (int_grp1 & FUSB300_IGR1_CX_OUT_INT) {
  1009. printk(KERN_INFO "fusb300_cxout\n");
  1010. fusb300_ep0out(fusb300);
  1011. }
  1012. if (int_grp1 & FUSB300_IGR1_CX_IN_INT) {
  1013. printk(KERN_INFO "fusb300_cxin\n");
  1014. fusb300_ep0in(fusb300);
  1015. }
  1016. if (int_grp1 & FUSB300_IGR1_INTGRP5)
  1017. fusb300_grp5_handler();
  1018. if (int_grp1 & FUSB300_IGR1_INTGRP4)
  1019. fusb300_grp4_handler();
  1020. if (int_grp1 & FUSB300_IGR1_INTGRP3)
  1021. fusb300_grp3_handler();
  1022. if (int_grp1 & FUSB300_IGR1_INTGRP2)
  1023. fusb300_grp2_handler();
  1024. if (int_grp0) {
  1025. for (i = 1; i < FUSB300_MAX_NUM_EP; i++) {
  1026. if (int_grp0 & FUSB300_IGR0_EPn_FIFO_INT(i)) {
  1027. reg = ioread32(fusb300->reg +
  1028. FUSB300_OFFSET_EPSET1(i));
  1029. in = (reg & FUSB300_EPSET1_DIRIN) ? 1 : 0;
  1030. if (in)
  1031. in_ep_fifo_handler(fusb300->ep[i]);
  1032. else
  1033. out_ep_fifo_handler(fusb300->ep[i]);
  1034. }
  1035. }
  1036. }
  1037. spin_unlock(&fusb300->lock);
  1038. return IRQ_HANDLED;
  1039. }
  1040. static void fusb300_set_u2_timeout(struct fusb300 *fusb300,
  1041. u32 time)
  1042. {
  1043. u32 reg;
  1044. reg = ioread32(fusb300->reg + FUSB300_OFFSET_TT);
  1045. reg &= ~0xff;
  1046. reg |= FUSB300_SSCR2_U2TIMEOUT(time);
  1047. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_TT);
  1048. }
  1049. static void fusb300_set_u1_timeout(struct fusb300 *fusb300,
  1050. u32 time)
  1051. {
  1052. u32 reg;
  1053. reg = ioread32(fusb300->reg + FUSB300_OFFSET_TT);
  1054. reg &= ~(0xff << 8);
  1055. reg |= FUSB300_SSCR2_U1TIMEOUT(time);
  1056. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_TT);
  1057. }
  1058. static void init_controller(struct fusb300 *fusb300)
  1059. {
  1060. u32 reg;
  1061. u32 mask = 0;
  1062. u32 val = 0;
  1063. /* split on */
  1064. mask = val = FUSB300_AHBBCR_S0_SPLIT_ON | FUSB300_AHBBCR_S1_SPLIT_ON;
  1065. reg = ioread32(fusb300->reg + FUSB300_OFFSET_AHBCR);
  1066. reg &= ~mask;
  1067. reg |= val;
  1068. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_AHBCR);
  1069. /* enable high-speed LPM */
  1070. mask = val = FUSB300_HSCR_HS_LPM_PERMIT;
  1071. reg = ioread32(fusb300->reg + FUSB300_OFFSET_HSCR);
  1072. reg &= ~mask;
  1073. reg |= val;
  1074. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_HSCR);
  1075. /*set u1 u2 timmer*/
  1076. fusb300_set_u2_timeout(fusb300, 0xff);
  1077. fusb300_set_u1_timeout(fusb300, 0xff);
  1078. /* enable all grp1 interrupt */
  1079. iowrite32(0xcfffff9f, fusb300->reg + FUSB300_OFFSET_IGER1);
  1080. }
  1081. /*------------------------------------------------------------------------*/
  1082. static int fusb300_udc_start(struct usb_gadget *g,
  1083. struct usb_gadget_driver *driver)
  1084. {
  1085. struct fusb300 *fusb300 = to_fusb300(g);
  1086. /* hook up the driver */
  1087. fusb300->driver = driver;
  1088. return 0;
  1089. }
  1090. static int fusb300_udc_stop(struct usb_gadget *g)
  1091. {
  1092. struct fusb300 *fusb300 = to_fusb300(g);
  1093. init_controller(fusb300);
  1094. fusb300->driver = NULL;
  1095. return 0;
  1096. }
  1097. /*--------------------------------------------------------------------------*/
  1098. static int fusb300_udc_pullup(struct usb_gadget *_gadget, int is_active)
  1099. {
  1100. return 0;
  1101. }
  1102. static const struct usb_gadget_ops fusb300_gadget_ops = {
  1103. .pullup = fusb300_udc_pullup,
  1104. .udc_start = fusb300_udc_start,
  1105. .udc_stop = fusb300_udc_stop,
  1106. };
  1107. static int fusb300_remove(struct platform_device *pdev)
  1108. {
  1109. struct fusb300 *fusb300 = platform_get_drvdata(pdev);
  1110. int i;
  1111. usb_del_gadget_udc(&fusb300->gadget);
  1112. iounmap(fusb300->reg);
  1113. free_irq(platform_get_irq(pdev, 0), fusb300);
  1114. free_irq(platform_get_irq(pdev, 1), fusb300);
  1115. fusb300_free_request(&fusb300->ep[0]->ep, fusb300->ep0_req);
  1116. for (i = 0; i < FUSB300_MAX_NUM_EP; i++)
  1117. kfree(fusb300->ep[i]);
  1118. kfree(fusb300);
  1119. return 0;
  1120. }
  1121. static int fusb300_probe(struct platform_device *pdev)
  1122. {
  1123. struct resource *res, *ires, *ires1;
  1124. void __iomem *reg = NULL;
  1125. struct fusb300 *fusb300 = NULL;
  1126. struct fusb300_ep *_ep[FUSB300_MAX_NUM_EP];
  1127. int ret = 0;
  1128. int i;
  1129. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1130. if (!res) {
  1131. ret = -ENODEV;
  1132. pr_err("platform_get_resource error.\n");
  1133. goto clean_up;
  1134. }
  1135. ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1136. if (!ires) {
  1137. ret = -ENODEV;
  1138. dev_err(&pdev->dev,
  1139. "platform_get_resource IORESOURCE_IRQ error.\n");
  1140. goto clean_up;
  1141. }
  1142. ires1 = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
  1143. if (!ires1) {
  1144. ret = -ENODEV;
  1145. dev_err(&pdev->dev,
  1146. "platform_get_resource IORESOURCE_IRQ 1 error.\n");
  1147. goto clean_up;
  1148. }
  1149. reg = ioremap(res->start, resource_size(res));
  1150. if (reg == NULL) {
  1151. ret = -ENOMEM;
  1152. pr_err("ioremap error.\n");
  1153. goto clean_up;
  1154. }
  1155. /* initialize udc */
  1156. fusb300 = kzalloc(sizeof(struct fusb300), GFP_KERNEL);
  1157. if (fusb300 == NULL) {
  1158. ret = -ENOMEM;
  1159. goto clean_up;
  1160. }
  1161. for (i = 0; i < FUSB300_MAX_NUM_EP; i++) {
  1162. _ep[i] = kzalloc(sizeof(struct fusb300_ep), GFP_KERNEL);
  1163. if (_ep[i] == NULL) {
  1164. ret = -ENOMEM;
  1165. goto clean_up;
  1166. }
  1167. fusb300->ep[i] = _ep[i];
  1168. }
  1169. spin_lock_init(&fusb300->lock);
  1170. platform_set_drvdata(pdev, fusb300);
  1171. fusb300->gadget.ops = &fusb300_gadget_ops;
  1172. fusb300->gadget.max_speed = USB_SPEED_HIGH;
  1173. fusb300->gadget.name = udc_name;
  1174. fusb300->reg = reg;
  1175. ret = request_irq(ires->start, fusb300_irq, IRQF_SHARED,
  1176. udc_name, fusb300);
  1177. if (ret < 0) {
  1178. pr_err("request_irq error (%d)\n", ret);
  1179. goto clean_up;
  1180. }
  1181. ret = request_irq(ires1->start, fusb300_irq,
  1182. IRQF_SHARED, udc_name, fusb300);
  1183. if (ret < 0) {
  1184. pr_err("request_irq1 error (%d)\n", ret);
  1185. goto err_request_irq1;
  1186. }
  1187. INIT_LIST_HEAD(&fusb300->gadget.ep_list);
  1188. for (i = 0; i < FUSB300_MAX_NUM_EP ; i++) {
  1189. struct fusb300_ep *ep = fusb300->ep[i];
  1190. if (i != 0) {
  1191. INIT_LIST_HEAD(&fusb300->ep[i]->ep.ep_list);
  1192. list_add_tail(&fusb300->ep[i]->ep.ep_list,
  1193. &fusb300->gadget.ep_list);
  1194. }
  1195. ep->fusb300 = fusb300;
  1196. INIT_LIST_HEAD(&ep->queue);
  1197. ep->ep.name = fusb300_ep_name[i];
  1198. ep->ep.ops = &fusb300_ep_ops;
  1199. usb_ep_set_maxpacket_limit(&ep->ep, HS_BULK_MAX_PACKET_SIZE);
  1200. if (i == 0) {
  1201. ep->ep.caps.type_control = true;
  1202. } else {
  1203. ep->ep.caps.type_iso = true;
  1204. ep->ep.caps.type_bulk = true;
  1205. ep->ep.caps.type_int = true;
  1206. }
  1207. ep->ep.caps.dir_in = true;
  1208. ep->ep.caps.dir_out = true;
  1209. }
  1210. usb_ep_set_maxpacket_limit(&fusb300->ep[0]->ep, HS_CTL_MAX_PACKET_SIZE);
  1211. fusb300->ep[0]->epnum = 0;
  1212. fusb300->gadget.ep0 = &fusb300->ep[0]->ep;
  1213. INIT_LIST_HEAD(&fusb300->gadget.ep0->ep_list);
  1214. fusb300->ep0_req = fusb300_alloc_request(&fusb300->ep[0]->ep,
  1215. GFP_KERNEL);
  1216. if (fusb300->ep0_req == NULL) {
  1217. ret = -ENOMEM;
  1218. goto err_alloc_request;
  1219. }
  1220. init_controller(fusb300);
  1221. ret = usb_add_gadget_udc(&pdev->dev, &fusb300->gadget);
  1222. if (ret)
  1223. goto err_add_udc;
  1224. dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
  1225. return 0;
  1226. err_add_udc:
  1227. fusb300_free_request(&fusb300->ep[0]->ep, fusb300->ep0_req);
  1228. err_alloc_request:
  1229. free_irq(ires1->start, fusb300);
  1230. err_request_irq1:
  1231. free_irq(ires->start, fusb300);
  1232. clean_up:
  1233. if (fusb300) {
  1234. if (fusb300->ep0_req)
  1235. fusb300_free_request(&fusb300->ep[0]->ep,
  1236. fusb300->ep0_req);
  1237. for (i = 0; i < FUSB300_MAX_NUM_EP; i++)
  1238. kfree(fusb300->ep[i]);
  1239. kfree(fusb300);
  1240. }
  1241. if (reg)
  1242. iounmap(reg);
  1243. return ret;
  1244. }
  1245. static struct platform_driver fusb300_driver = {
  1246. .remove = fusb300_remove,
  1247. .driver = {
  1248. .name = udc_name,
  1249. },
  1250. };
  1251. module_platform_driver_probe(fusb300_driver, fusb300_probe);