dwc3-qcom.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /* Copyright (c) 2018, The Linux Foundation. All rights reserved.
  3. *
  4. * Inspired by dwc3-of-simple.c
  5. */
  6. #include <linux/acpi.h>
  7. #include <linux/io.h>
  8. #include <linux/of.h>
  9. #include <linux/clk.h>
  10. #include <linux/irq.h>
  11. #include <linux/of_clk.h>
  12. #include <linux/module.h>
  13. #include <linux/kernel.h>
  14. #include <linux/extcon.h>
  15. #include <linux/interconnect.h>
  16. #include <linux/of_platform.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/phy/phy.h>
  19. #include <linux/usb/of.h>
  20. #include <linux/reset.h>
  21. #include <linux/iopoll.h>
  22. #include <linux/usb/hcd.h>
  23. #include <linux/usb.h>
  24. #include "core.h"
  25. /* USB QSCRATCH Hardware registers */
  26. #define QSCRATCH_HS_PHY_CTRL 0x10
  27. #define UTMI_OTG_VBUS_VALID BIT(20)
  28. #define SW_SESSVLD_SEL BIT(28)
  29. #define QSCRATCH_SS_PHY_CTRL 0x30
  30. #define LANE0_PWR_PRESENT BIT(24)
  31. #define QSCRATCH_GENERAL_CFG 0x08
  32. #define PIPE_UTMI_CLK_SEL BIT(0)
  33. #define PIPE3_PHYSTATUS_SW BIT(3)
  34. #define PIPE_UTMI_CLK_DIS BIT(8)
  35. #define PWR_EVNT_IRQ_STAT_REG 0x58
  36. #define PWR_EVNT_LPM_IN_L2_MASK BIT(4)
  37. #define PWR_EVNT_LPM_OUT_L2_MASK BIT(5)
  38. #define SDM845_QSCRATCH_BASE_OFFSET 0xf8800
  39. #define SDM845_QSCRATCH_SIZE 0x400
  40. #define SDM845_DWC3_CORE_SIZE 0xcd00
  41. /* Interconnect path bandwidths in MBps */
  42. #define USB_MEMORY_AVG_HS_BW MBps_to_icc(240)
  43. #define USB_MEMORY_PEAK_HS_BW MBps_to_icc(700)
  44. #define USB_MEMORY_AVG_SS_BW MBps_to_icc(1000)
  45. #define USB_MEMORY_PEAK_SS_BW MBps_to_icc(2500)
  46. #define APPS_USB_AVG_BW 0
  47. #define APPS_USB_PEAK_BW MBps_to_icc(40)
  48. struct dwc3_acpi_pdata {
  49. u32 qscratch_base_offset;
  50. u32 qscratch_base_size;
  51. u32 dwc3_core_base_size;
  52. int hs_phy_irq_index;
  53. int dp_hs_phy_irq_index;
  54. int dm_hs_phy_irq_index;
  55. int ss_phy_irq_index;
  56. bool is_urs;
  57. };
  58. struct dwc3_qcom {
  59. struct device *dev;
  60. void __iomem *qscratch_base;
  61. struct platform_device *dwc3;
  62. struct platform_device *urs_usb;
  63. struct clk **clks;
  64. int num_clocks;
  65. struct reset_control *resets;
  66. int hs_phy_irq;
  67. int dp_hs_phy_irq;
  68. int dm_hs_phy_irq;
  69. int ss_phy_irq;
  70. enum usb_device_speed usb2_speed;
  71. struct extcon_dev *edev;
  72. struct extcon_dev *host_edev;
  73. struct notifier_block vbus_nb;
  74. struct notifier_block host_nb;
  75. const struct dwc3_acpi_pdata *acpi_pdata;
  76. enum usb_dr_mode mode;
  77. bool is_suspended;
  78. bool pm_suspended;
  79. struct icc_path *icc_path_ddr;
  80. struct icc_path *icc_path_apps;
  81. };
  82. static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val)
  83. {
  84. u32 reg;
  85. reg = readl(base + offset);
  86. reg |= val;
  87. writel(reg, base + offset);
  88. /* ensure that above write is through */
  89. readl(base + offset);
  90. }
  91. static inline void dwc3_qcom_clrbits(void __iomem *base, u32 offset, u32 val)
  92. {
  93. u32 reg;
  94. reg = readl(base + offset);
  95. reg &= ~val;
  96. writel(reg, base + offset);
  97. /* ensure that above write is through */
  98. readl(base + offset);
  99. }
  100. static void dwc3_qcom_vbus_override_enable(struct dwc3_qcom *qcom, bool enable)
  101. {
  102. if (enable) {
  103. dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL,
  104. LANE0_PWR_PRESENT);
  105. dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL,
  106. UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
  107. } else {
  108. dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL,
  109. LANE0_PWR_PRESENT);
  110. dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL,
  111. UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
  112. }
  113. }
  114. static int dwc3_qcom_vbus_notifier(struct notifier_block *nb,
  115. unsigned long event, void *ptr)
  116. {
  117. struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, vbus_nb);
  118. /* enable vbus override for device mode */
  119. dwc3_qcom_vbus_override_enable(qcom, event);
  120. qcom->mode = event ? USB_DR_MODE_PERIPHERAL : USB_DR_MODE_HOST;
  121. return NOTIFY_DONE;
  122. }
  123. static int dwc3_qcom_host_notifier(struct notifier_block *nb,
  124. unsigned long event, void *ptr)
  125. {
  126. struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, host_nb);
  127. /* disable vbus override in host mode */
  128. dwc3_qcom_vbus_override_enable(qcom, !event);
  129. qcom->mode = event ? USB_DR_MODE_HOST : USB_DR_MODE_PERIPHERAL;
  130. return NOTIFY_DONE;
  131. }
  132. static int dwc3_qcom_register_extcon(struct dwc3_qcom *qcom)
  133. {
  134. struct device *dev = qcom->dev;
  135. struct extcon_dev *host_edev;
  136. int ret;
  137. if (!of_property_read_bool(dev->of_node, "extcon"))
  138. return 0;
  139. qcom->edev = extcon_get_edev_by_phandle(dev, 0);
  140. if (IS_ERR(qcom->edev))
  141. return PTR_ERR(qcom->edev);
  142. qcom->vbus_nb.notifier_call = dwc3_qcom_vbus_notifier;
  143. qcom->host_edev = extcon_get_edev_by_phandle(dev, 1);
  144. if (IS_ERR(qcom->host_edev))
  145. qcom->host_edev = NULL;
  146. ret = devm_extcon_register_notifier(dev, qcom->edev, EXTCON_USB,
  147. &qcom->vbus_nb);
  148. if (ret < 0) {
  149. dev_err(dev, "VBUS notifier register failed\n");
  150. return ret;
  151. }
  152. if (qcom->host_edev)
  153. host_edev = qcom->host_edev;
  154. else
  155. host_edev = qcom->edev;
  156. qcom->host_nb.notifier_call = dwc3_qcom_host_notifier;
  157. ret = devm_extcon_register_notifier(dev, host_edev, EXTCON_USB_HOST,
  158. &qcom->host_nb);
  159. if (ret < 0) {
  160. dev_err(dev, "Host notifier register failed\n");
  161. return ret;
  162. }
  163. /* Update initial VBUS override based on extcon state */
  164. if (extcon_get_state(qcom->edev, EXTCON_USB) ||
  165. !extcon_get_state(host_edev, EXTCON_USB_HOST))
  166. dwc3_qcom_vbus_notifier(&qcom->vbus_nb, true, qcom->edev);
  167. else
  168. dwc3_qcom_vbus_notifier(&qcom->vbus_nb, false, qcom->edev);
  169. return 0;
  170. }
  171. static int dwc3_qcom_interconnect_enable(struct dwc3_qcom *qcom)
  172. {
  173. int ret;
  174. ret = icc_enable(qcom->icc_path_ddr);
  175. if (ret)
  176. return ret;
  177. ret = icc_enable(qcom->icc_path_apps);
  178. if (ret)
  179. icc_disable(qcom->icc_path_ddr);
  180. return ret;
  181. }
  182. static int dwc3_qcom_interconnect_disable(struct dwc3_qcom *qcom)
  183. {
  184. int ret;
  185. ret = icc_disable(qcom->icc_path_ddr);
  186. if (ret)
  187. return ret;
  188. ret = icc_disable(qcom->icc_path_apps);
  189. if (ret)
  190. icc_enable(qcom->icc_path_ddr);
  191. return ret;
  192. }
  193. /**
  194. * dwc3_qcom_interconnect_init() - Get interconnect path handles
  195. * and set bandwidth.
  196. * @qcom: Pointer to the concerned usb core.
  197. *
  198. */
  199. static int dwc3_qcom_interconnect_init(struct dwc3_qcom *qcom)
  200. {
  201. enum usb_device_speed max_speed;
  202. struct device *dev = qcom->dev;
  203. int ret;
  204. if (has_acpi_companion(dev))
  205. return 0;
  206. qcom->icc_path_ddr = of_icc_get(dev, "usb-ddr");
  207. if (IS_ERR(qcom->icc_path_ddr)) {
  208. dev_err(dev, "failed to get usb-ddr path: %ld\n",
  209. PTR_ERR(qcom->icc_path_ddr));
  210. return PTR_ERR(qcom->icc_path_ddr);
  211. }
  212. qcom->icc_path_apps = of_icc_get(dev, "apps-usb");
  213. if (IS_ERR(qcom->icc_path_apps)) {
  214. dev_err(dev, "failed to get apps-usb path: %ld\n",
  215. PTR_ERR(qcom->icc_path_apps));
  216. ret = PTR_ERR(qcom->icc_path_apps);
  217. goto put_path_ddr;
  218. }
  219. max_speed = usb_get_maximum_speed(&qcom->dwc3->dev);
  220. if (max_speed >= USB_SPEED_SUPER || max_speed == USB_SPEED_UNKNOWN) {
  221. ret = icc_set_bw(qcom->icc_path_ddr,
  222. USB_MEMORY_AVG_SS_BW, USB_MEMORY_PEAK_SS_BW);
  223. } else {
  224. ret = icc_set_bw(qcom->icc_path_ddr,
  225. USB_MEMORY_AVG_HS_BW, USB_MEMORY_PEAK_HS_BW);
  226. }
  227. if (ret) {
  228. dev_err(dev, "failed to set bandwidth for usb-ddr path: %d\n", ret);
  229. goto put_path_apps;
  230. }
  231. ret = icc_set_bw(qcom->icc_path_apps, APPS_USB_AVG_BW, APPS_USB_PEAK_BW);
  232. if (ret) {
  233. dev_err(dev, "failed to set bandwidth for apps-usb path: %d\n", ret);
  234. goto put_path_apps;
  235. }
  236. return 0;
  237. put_path_apps:
  238. icc_put(qcom->icc_path_apps);
  239. put_path_ddr:
  240. icc_put(qcom->icc_path_ddr);
  241. return ret;
  242. }
  243. /**
  244. * dwc3_qcom_interconnect_exit() - Release interconnect path handles
  245. * @qcom: Pointer to the concerned usb core.
  246. *
  247. * This function is used to release interconnect path handle.
  248. */
  249. static void dwc3_qcom_interconnect_exit(struct dwc3_qcom *qcom)
  250. {
  251. icc_put(qcom->icc_path_ddr);
  252. icc_put(qcom->icc_path_apps);
  253. }
  254. /* Only usable in contexts where the role can not change. */
  255. static bool dwc3_qcom_is_host(struct dwc3_qcom *qcom)
  256. {
  257. struct dwc3 *dwc;
  258. /*
  259. * FIXME: Fix this layering violation.
  260. */
  261. dwc = platform_get_drvdata(qcom->dwc3);
  262. /* Core driver may not have probed yet. */
  263. if (!dwc)
  264. return false;
  265. return dwc->xhci;
  266. }
  267. static enum usb_device_speed dwc3_qcom_read_usb2_speed(struct dwc3_qcom *qcom)
  268. {
  269. struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3);
  270. struct usb_device *udev;
  271. struct usb_hcd __maybe_unused *hcd;
  272. /*
  273. * FIXME: Fix this layering violation.
  274. */
  275. hcd = platform_get_drvdata(dwc->xhci);
  276. /*
  277. * It is possible to query the speed of all children of
  278. * USB2.0 root hub via usb_hub_for_each_child(). DWC3 code
  279. * currently supports only 1 port per controller. So
  280. * this is sufficient.
  281. */
  282. #ifdef CONFIG_USB
  283. udev = usb_hub_find_child(hcd->self.root_hub, 1);
  284. #else
  285. udev = NULL;
  286. #endif
  287. if (!udev)
  288. return USB_SPEED_UNKNOWN;
  289. return udev->speed;
  290. }
  291. static void dwc3_qcom_enable_wakeup_irq(int irq, unsigned int polarity)
  292. {
  293. if (!irq)
  294. return;
  295. if (polarity)
  296. irq_set_irq_type(irq, polarity);
  297. enable_irq(irq);
  298. enable_irq_wake(irq);
  299. }
  300. static void dwc3_qcom_disable_wakeup_irq(int irq)
  301. {
  302. if (!irq)
  303. return;
  304. disable_irq_wake(irq);
  305. disable_irq_nosync(irq);
  306. }
  307. static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom)
  308. {
  309. dwc3_qcom_disable_wakeup_irq(qcom->hs_phy_irq);
  310. if (qcom->usb2_speed == USB_SPEED_LOW) {
  311. dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq);
  312. } else if ((qcom->usb2_speed == USB_SPEED_HIGH) ||
  313. (qcom->usb2_speed == USB_SPEED_FULL)) {
  314. dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq);
  315. } else {
  316. dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq);
  317. dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq);
  318. }
  319. dwc3_qcom_disable_wakeup_irq(qcom->ss_phy_irq);
  320. }
  321. static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
  322. {
  323. dwc3_qcom_enable_wakeup_irq(qcom->hs_phy_irq, 0);
  324. /*
  325. * Configure DP/DM line interrupts based on the USB2 device attached to
  326. * the root hub port. When HS/FS device is connected, configure the DP line
  327. * as falling edge to detect both disconnect and remote wakeup scenarios. When
  328. * LS device is connected, configure DM line as falling edge to detect both
  329. * disconnect and remote wakeup. When no device is connected, configure both
  330. * DP and DM lines as rising edge to detect HS/HS/LS device connect scenario.
  331. */
  332. if (qcom->usb2_speed == USB_SPEED_LOW) {
  333. dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq,
  334. IRQ_TYPE_EDGE_FALLING);
  335. } else if ((qcom->usb2_speed == USB_SPEED_HIGH) ||
  336. (qcom->usb2_speed == USB_SPEED_FULL)) {
  337. dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq,
  338. IRQ_TYPE_EDGE_FALLING);
  339. } else {
  340. dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq,
  341. IRQ_TYPE_EDGE_RISING);
  342. dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq,
  343. IRQ_TYPE_EDGE_RISING);
  344. }
  345. dwc3_qcom_enable_wakeup_irq(qcom->ss_phy_irq, 0);
  346. }
  347. static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
  348. {
  349. u32 val;
  350. int i, ret;
  351. if (qcom->is_suspended)
  352. return 0;
  353. val = readl(qcom->qscratch_base + PWR_EVNT_IRQ_STAT_REG);
  354. if (!(val & PWR_EVNT_LPM_IN_L2_MASK))
  355. dev_err(qcom->dev, "HS-PHY not in L2\n");
  356. for (i = qcom->num_clocks - 1; i >= 0; i--)
  357. clk_disable_unprepare(qcom->clks[i]);
  358. ret = dwc3_qcom_interconnect_disable(qcom);
  359. if (ret)
  360. dev_warn(qcom->dev, "failed to disable interconnect: %d\n", ret);
  361. /*
  362. * The role is stable during suspend as role switching is done from a
  363. * freezable workqueue.
  364. */
  365. if (dwc3_qcom_is_host(qcom) && wakeup) {
  366. qcom->usb2_speed = dwc3_qcom_read_usb2_speed(qcom);
  367. dwc3_qcom_enable_interrupts(qcom);
  368. }
  369. qcom->is_suspended = true;
  370. return 0;
  371. }
  372. static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup)
  373. {
  374. int ret;
  375. int i;
  376. if (!qcom->is_suspended)
  377. return 0;
  378. if (dwc3_qcom_is_host(qcom) && wakeup)
  379. dwc3_qcom_disable_interrupts(qcom);
  380. for (i = 0; i < qcom->num_clocks; i++) {
  381. ret = clk_prepare_enable(qcom->clks[i]);
  382. if (ret < 0) {
  383. while (--i >= 0)
  384. clk_disable_unprepare(qcom->clks[i]);
  385. return ret;
  386. }
  387. }
  388. ret = dwc3_qcom_interconnect_enable(qcom);
  389. if (ret)
  390. dev_warn(qcom->dev, "failed to enable interconnect: %d\n", ret);
  391. /* Clear existing events from PHY related to L2 in/out */
  392. dwc3_qcom_setbits(qcom->qscratch_base, PWR_EVNT_IRQ_STAT_REG,
  393. PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK);
  394. qcom->is_suspended = false;
  395. return 0;
  396. }
  397. static irqreturn_t qcom_dwc3_resume_irq(int irq, void *data)
  398. {
  399. struct dwc3_qcom *qcom = data;
  400. struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3);
  401. /* If pm_suspended then let pm_resume take care of resuming h/w */
  402. if (qcom->pm_suspended)
  403. return IRQ_HANDLED;
  404. /*
  405. * This is safe as role switching is done from a freezable workqueue
  406. * and the wakeup interrupts are disabled as part of resume.
  407. */
  408. if (dwc3_qcom_is_host(qcom))
  409. pm_runtime_resume(&dwc->xhci->dev);
  410. return IRQ_HANDLED;
  411. }
  412. static void dwc3_qcom_select_utmi_clk(struct dwc3_qcom *qcom)
  413. {
  414. /* Configure dwc3 to use UTMI clock as PIPE clock not present */
  415. dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
  416. PIPE_UTMI_CLK_DIS);
  417. usleep_range(100, 1000);
  418. dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
  419. PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW);
  420. usleep_range(100, 1000);
  421. dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
  422. PIPE_UTMI_CLK_DIS);
  423. }
  424. static int dwc3_qcom_get_irq(struct platform_device *pdev,
  425. const char *name, int num)
  426. {
  427. struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
  428. struct platform_device *pdev_irq = qcom->urs_usb ? qcom->urs_usb : pdev;
  429. struct device_node *np = pdev->dev.of_node;
  430. int ret;
  431. if (np)
  432. ret = platform_get_irq_byname_optional(pdev_irq, name);
  433. else
  434. ret = platform_get_irq_optional(pdev_irq, num);
  435. return ret;
  436. }
  437. static int dwc3_qcom_setup_irq(struct platform_device *pdev)
  438. {
  439. struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
  440. const struct dwc3_acpi_pdata *pdata = qcom->acpi_pdata;
  441. int irq;
  442. int ret;
  443. irq = dwc3_qcom_get_irq(pdev, "hs_phy_irq",
  444. pdata ? pdata->hs_phy_irq_index : -1);
  445. if (irq > 0) {
  446. /* Keep wakeup interrupts disabled until suspend */
  447. irq_set_status_flags(irq, IRQ_NOAUTOEN);
  448. ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
  449. qcom_dwc3_resume_irq,
  450. IRQF_ONESHOT,
  451. "qcom_dwc3 HS", qcom);
  452. if (ret) {
  453. dev_err(qcom->dev, "hs_phy_irq failed: %d\n", ret);
  454. return ret;
  455. }
  456. qcom->hs_phy_irq = irq;
  457. }
  458. irq = dwc3_qcom_get_irq(pdev, "dp_hs_phy_irq",
  459. pdata ? pdata->dp_hs_phy_irq_index : -1);
  460. if (irq > 0) {
  461. irq_set_status_flags(irq, IRQ_NOAUTOEN);
  462. ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
  463. qcom_dwc3_resume_irq,
  464. IRQF_ONESHOT,
  465. "qcom_dwc3 DP_HS", qcom);
  466. if (ret) {
  467. dev_err(qcom->dev, "dp_hs_phy_irq failed: %d\n", ret);
  468. return ret;
  469. }
  470. qcom->dp_hs_phy_irq = irq;
  471. }
  472. irq = dwc3_qcom_get_irq(pdev, "dm_hs_phy_irq",
  473. pdata ? pdata->dm_hs_phy_irq_index : -1);
  474. if (irq > 0) {
  475. irq_set_status_flags(irq, IRQ_NOAUTOEN);
  476. ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
  477. qcom_dwc3_resume_irq,
  478. IRQF_ONESHOT,
  479. "qcom_dwc3 DM_HS", qcom);
  480. if (ret) {
  481. dev_err(qcom->dev, "dm_hs_phy_irq failed: %d\n", ret);
  482. return ret;
  483. }
  484. qcom->dm_hs_phy_irq = irq;
  485. }
  486. irq = dwc3_qcom_get_irq(pdev, "ss_phy_irq",
  487. pdata ? pdata->ss_phy_irq_index : -1);
  488. if (irq > 0) {
  489. irq_set_status_flags(irq, IRQ_NOAUTOEN);
  490. ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
  491. qcom_dwc3_resume_irq,
  492. IRQF_ONESHOT,
  493. "qcom_dwc3 SS", qcom);
  494. if (ret) {
  495. dev_err(qcom->dev, "ss_phy_irq failed: %d\n", ret);
  496. return ret;
  497. }
  498. qcom->ss_phy_irq = irq;
  499. }
  500. return 0;
  501. }
  502. static int dwc3_qcom_clk_init(struct dwc3_qcom *qcom, int count)
  503. {
  504. struct device *dev = qcom->dev;
  505. struct device_node *np = dev->of_node;
  506. int i;
  507. if (!np || !count)
  508. return 0;
  509. if (count < 0)
  510. return count;
  511. qcom->num_clocks = count;
  512. qcom->clks = devm_kcalloc(dev, qcom->num_clocks,
  513. sizeof(struct clk *), GFP_KERNEL);
  514. if (!qcom->clks)
  515. return -ENOMEM;
  516. for (i = 0; i < qcom->num_clocks; i++) {
  517. struct clk *clk;
  518. int ret;
  519. clk = of_clk_get(np, i);
  520. if (IS_ERR(clk)) {
  521. while (--i >= 0)
  522. clk_put(qcom->clks[i]);
  523. return PTR_ERR(clk);
  524. }
  525. ret = clk_prepare_enable(clk);
  526. if (ret < 0) {
  527. while (--i >= 0) {
  528. clk_disable_unprepare(qcom->clks[i]);
  529. clk_put(qcom->clks[i]);
  530. }
  531. clk_put(clk);
  532. return ret;
  533. }
  534. qcom->clks[i] = clk;
  535. }
  536. return 0;
  537. }
  538. static const struct property_entry dwc3_qcom_acpi_properties[] = {
  539. PROPERTY_ENTRY_STRING("dr_mode", "host"),
  540. {}
  541. };
  542. static const struct software_node dwc3_qcom_swnode = {
  543. .properties = dwc3_qcom_acpi_properties,
  544. };
  545. static int dwc3_qcom_acpi_register_core(struct platform_device *pdev)
  546. {
  547. struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
  548. struct device *dev = &pdev->dev;
  549. struct resource *res, *child_res = NULL;
  550. struct platform_device *pdev_irq = qcom->urs_usb ? qcom->urs_usb :
  551. pdev;
  552. int irq;
  553. int ret;
  554. qcom->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
  555. if (!qcom->dwc3)
  556. return -ENOMEM;
  557. qcom->dwc3->dev.parent = dev;
  558. qcom->dwc3->dev.type = dev->type;
  559. qcom->dwc3->dev.dma_mask = dev->dma_mask;
  560. qcom->dwc3->dev.dma_parms = dev->dma_parms;
  561. qcom->dwc3->dev.coherent_dma_mask = dev->coherent_dma_mask;
  562. child_res = kcalloc(2, sizeof(*child_res), GFP_KERNEL);
  563. if (!child_res) {
  564. platform_device_put(qcom->dwc3);
  565. return -ENOMEM;
  566. }
  567. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  568. if (!res) {
  569. dev_err(&pdev->dev, "failed to get memory resource\n");
  570. ret = -ENODEV;
  571. goto out;
  572. }
  573. child_res[0].flags = res->flags;
  574. child_res[0].start = res->start;
  575. child_res[0].end = child_res[0].start +
  576. qcom->acpi_pdata->dwc3_core_base_size;
  577. irq = platform_get_irq(pdev_irq, 0);
  578. if (irq < 0) {
  579. ret = irq;
  580. goto out;
  581. }
  582. child_res[1].flags = IORESOURCE_IRQ;
  583. child_res[1].start = child_res[1].end = irq;
  584. ret = platform_device_add_resources(qcom->dwc3, child_res, 2);
  585. if (ret) {
  586. dev_err(&pdev->dev, "failed to add resources\n");
  587. goto out;
  588. }
  589. ret = device_add_software_node(&qcom->dwc3->dev, &dwc3_qcom_swnode);
  590. if (ret < 0) {
  591. dev_err(&pdev->dev, "failed to add properties\n");
  592. goto out;
  593. }
  594. ret = platform_device_add(qcom->dwc3);
  595. if (ret) {
  596. dev_err(&pdev->dev, "failed to add device\n");
  597. device_remove_software_node(&qcom->dwc3->dev);
  598. goto out;
  599. }
  600. kfree(child_res);
  601. return 0;
  602. out:
  603. platform_device_put(qcom->dwc3);
  604. kfree(child_res);
  605. return ret;
  606. }
  607. static int dwc3_qcom_of_register_core(struct platform_device *pdev)
  608. {
  609. struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
  610. struct device_node *np = pdev->dev.of_node, *dwc3_np;
  611. struct device *dev = &pdev->dev;
  612. int ret;
  613. dwc3_np = of_get_compatible_child(np, "snps,dwc3");
  614. if (!dwc3_np) {
  615. dev_err(dev, "failed to find dwc3 core child\n");
  616. return -ENODEV;
  617. }
  618. ret = of_platform_populate(np, NULL, NULL, dev);
  619. if (ret) {
  620. dev_err(dev, "failed to register dwc3 core - %d\n", ret);
  621. goto node_put;
  622. }
  623. qcom->dwc3 = of_find_device_by_node(dwc3_np);
  624. if (!qcom->dwc3) {
  625. ret = -ENODEV;
  626. dev_err(dev, "failed to get dwc3 platform device\n");
  627. of_platform_depopulate(dev);
  628. }
  629. node_put:
  630. of_node_put(dwc3_np);
  631. return ret;
  632. }
  633. static struct platform_device *dwc3_qcom_create_urs_usb_platdev(struct device *dev)
  634. {
  635. struct platform_device *urs_usb = NULL;
  636. struct fwnode_handle *fwh;
  637. struct acpi_device *adev;
  638. char name[8];
  639. int ret;
  640. int id;
  641. /* Figure out device id */
  642. ret = sscanf(fwnode_get_name(dev->fwnode), "URS%d", &id);
  643. if (!ret)
  644. return NULL;
  645. /* Find the child using name */
  646. snprintf(name, sizeof(name), "USB%d", id);
  647. fwh = fwnode_get_named_child_node(dev->fwnode, name);
  648. if (!fwh)
  649. return NULL;
  650. adev = to_acpi_device_node(fwh);
  651. if (!adev)
  652. goto err_put_handle;
  653. urs_usb = acpi_create_platform_device(adev, NULL);
  654. if (IS_ERR_OR_NULL(urs_usb))
  655. goto err_put_handle;
  656. return urs_usb;
  657. err_put_handle:
  658. fwnode_handle_put(fwh);
  659. return urs_usb;
  660. }
  661. static void dwc3_qcom_destroy_urs_usb_platdev(struct platform_device *urs_usb)
  662. {
  663. struct fwnode_handle *fwh = urs_usb->dev.fwnode;
  664. platform_device_unregister(urs_usb);
  665. fwnode_handle_put(fwh);
  666. }
  667. static int dwc3_qcom_probe(struct platform_device *pdev)
  668. {
  669. struct device_node *np = pdev->dev.of_node;
  670. struct device *dev = &pdev->dev;
  671. struct dwc3_qcom *qcom;
  672. struct resource *res, *parent_res = NULL;
  673. struct resource local_res;
  674. int ret, i;
  675. bool ignore_pipe_clk;
  676. bool wakeup_source;
  677. qcom = devm_kzalloc(&pdev->dev, sizeof(*qcom), GFP_KERNEL);
  678. if (!qcom)
  679. return -ENOMEM;
  680. platform_set_drvdata(pdev, qcom);
  681. qcom->dev = &pdev->dev;
  682. if (has_acpi_companion(dev)) {
  683. qcom->acpi_pdata = acpi_device_get_match_data(dev);
  684. if (!qcom->acpi_pdata) {
  685. dev_err(&pdev->dev, "no supporting ACPI device data\n");
  686. return -EINVAL;
  687. }
  688. }
  689. qcom->resets = devm_reset_control_array_get_optional_exclusive(dev);
  690. if (IS_ERR(qcom->resets)) {
  691. ret = PTR_ERR(qcom->resets);
  692. dev_err(&pdev->dev, "failed to get resets, err=%d\n", ret);
  693. return ret;
  694. }
  695. ret = reset_control_assert(qcom->resets);
  696. if (ret) {
  697. dev_err(&pdev->dev, "failed to assert resets, err=%d\n", ret);
  698. return ret;
  699. }
  700. usleep_range(10, 1000);
  701. ret = reset_control_deassert(qcom->resets);
  702. if (ret) {
  703. dev_err(&pdev->dev, "failed to deassert resets, err=%d\n", ret);
  704. goto reset_assert;
  705. }
  706. ret = dwc3_qcom_clk_init(qcom, of_clk_get_parent_count(np));
  707. if (ret) {
  708. dev_err(dev, "failed to get clocks\n");
  709. goto reset_assert;
  710. }
  711. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  712. if (np) {
  713. parent_res = res;
  714. } else {
  715. memcpy(&local_res, res, sizeof(struct resource));
  716. parent_res = &local_res;
  717. parent_res->start = res->start +
  718. qcom->acpi_pdata->qscratch_base_offset;
  719. parent_res->end = parent_res->start +
  720. qcom->acpi_pdata->qscratch_base_size;
  721. if (qcom->acpi_pdata->is_urs) {
  722. qcom->urs_usb = dwc3_qcom_create_urs_usb_platdev(dev);
  723. if (IS_ERR_OR_NULL(qcom->urs_usb)) {
  724. dev_err(dev, "failed to create URS USB platdev\n");
  725. if (!qcom->urs_usb)
  726. ret = -ENODEV;
  727. else
  728. ret = PTR_ERR(qcom->urs_usb);
  729. goto clk_disable;
  730. }
  731. }
  732. }
  733. qcom->qscratch_base = devm_ioremap_resource(dev, parent_res);
  734. if (IS_ERR(qcom->qscratch_base)) {
  735. ret = PTR_ERR(qcom->qscratch_base);
  736. goto free_urs;
  737. }
  738. ret = dwc3_qcom_setup_irq(pdev);
  739. if (ret) {
  740. dev_err(dev, "failed to setup IRQs, err=%d\n", ret);
  741. goto free_urs;
  742. }
  743. /*
  744. * Disable pipe_clk requirement if specified. Used when dwc3
  745. * operates without SSPHY and only HS/FS/LS modes are supported.
  746. */
  747. ignore_pipe_clk = device_property_read_bool(dev,
  748. "qcom,select-utmi-as-pipe-clk");
  749. if (ignore_pipe_clk)
  750. dwc3_qcom_select_utmi_clk(qcom);
  751. if (np)
  752. ret = dwc3_qcom_of_register_core(pdev);
  753. else
  754. ret = dwc3_qcom_acpi_register_core(pdev);
  755. if (ret) {
  756. dev_err(dev, "failed to register DWC3 Core, err=%d\n", ret);
  757. goto free_urs;
  758. }
  759. ret = dwc3_qcom_interconnect_init(qcom);
  760. if (ret)
  761. goto depopulate;
  762. qcom->mode = usb_get_dr_mode(&qcom->dwc3->dev);
  763. /* enable vbus override for device mode */
  764. if (qcom->mode != USB_DR_MODE_HOST)
  765. dwc3_qcom_vbus_override_enable(qcom, true);
  766. /* register extcon to override sw_vbus on Vbus change later */
  767. ret = dwc3_qcom_register_extcon(qcom);
  768. if (ret)
  769. goto interconnect_exit;
  770. wakeup_source = of_property_read_bool(dev->of_node, "wakeup-source");
  771. device_init_wakeup(&pdev->dev, wakeup_source);
  772. device_init_wakeup(&qcom->dwc3->dev, wakeup_source);
  773. qcom->is_suspended = false;
  774. pm_runtime_set_active(dev);
  775. pm_runtime_enable(dev);
  776. pm_runtime_forbid(dev);
  777. return 0;
  778. interconnect_exit:
  779. dwc3_qcom_interconnect_exit(qcom);
  780. depopulate:
  781. if (np) {
  782. of_platform_depopulate(&pdev->dev);
  783. } else {
  784. device_remove_software_node(&qcom->dwc3->dev);
  785. platform_device_del(qcom->dwc3);
  786. }
  787. platform_device_put(qcom->dwc3);
  788. free_urs:
  789. if (qcom->urs_usb)
  790. dwc3_qcom_destroy_urs_usb_platdev(qcom->urs_usb);
  791. clk_disable:
  792. for (i = qcom->num_clocks - 1; i >= 0; i--) {
  793. clk_disable_unprepare(qcom->clks[i]);
  794. clk_put(qcom->clks[i]);
  795. }
  796. reset_assert:
  797. reset_control_assert(qcom->resets);
  798. return ret;
  799. }
  800. static int dwc3_qcom_remove(struct platform_device *pdev)
  801. {
  802. struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
  803. struct device_node *np = pdev->dev.of_node;
  804. struct device *dev = &pdev->dev;
  805. int i;
  806. if (np) {
  807. of_platform_depopulate(&pdev->dev);
  808. } else {
  809. device_remove_software_node(&qcom->dwc3->dev);
  810. platform_device_del(qcom->dwc3);
  811. }
  812. platform_device_put(qcom->dwc3);
  813. if (qcom->urs_usb)
  814. dwc3_qcom_destroy_urs_usb_platdev(qcom->urs_usb);
  815. for (i = qcom->num_clocks - 1; i >= 0; i--) {
  816. clk_disable_unprepare(qcom->clks[i]);
  817. clk_put(qcom->clks[i]);
  818. }
  819. qcom->num_clocks = 0;
  820. dwc3_qcom_interconnect_exit(qcom);
  821. reset_control_assert(qcom->resets);
  822. pm_runtime_allow(dev);
  823. pm_runtime_disable(dev);
  824. return 0;
  825. }
  826. static int __maybe_unused dwc3_qcom_pm_suspend(struct device *dev)
  827. {
  828. struct dwc3_qcom *qcom = dev_get_drvdata(dev);
  829. bool wakeup = device_may_wakeup(dev);
  830. int ret;
  831. ret = dwc3_qcom_suspend(qcom, wakeup);
  832. if (ret)
  833. return ret;
  834. qcom->pm_suspended = true;
  835. return 0;
  836. }
  837. static int __maybe_unused dwc3_qcom_pm_resume(struct device *dev)
  838. {
  839. struct dwc3_qcom *qcom = dev_get_drvdata(dev);
  840. bool wakeup = device_may_wakeup(dev);
  841. int ret;
  842. ret = dwc3_qcom_resume(qcom, wakeup);
  843. if (ret)
  844. return ret;
  845. qcom->pm_suspended = false;
  846. return 0;
  847. }
  848. static int __maybe_unused dwc3_qcom_runtime_suspend(struct device *dev)
  849. {
  850. struct dwc3_qcom *qcom = dev_get_drvdata(dev);
  851. return dwc3_qcom_suspend(qcom, true);
  852. }
  853. static int __maybe_unused dwc3_qcom_runtime_resume(struct device *dev)
  854. {
  855. struct dwc3_qcom *qcom = dev_get_drvdata(dev);
  856. return dwc3_qcom_resume(qcom, true);
  857. }
  858. static const struct dev_pm_ops dwc3_qcom_dev_pm_ops = {
  859. SET_SYSTEM_SLEEP_PM_OPS(dwc3_qcom_pm_suspend, dwc3_qcom_pm_resume)
  860. SET_RUNTIME_PM_OPS(dwc3_qcom_runtime_suspend, dwc3_qcom_runtime_resume,
  861. NULL)
  862. };
  863. static const struct of_device_id dwc3_qcom_of_match[] = {
  864. { .compatible = "qcom,dwc3" },
  865. { }
  866. };
  867. MODULE_DEVICE_TABLE(of, dwc3_qcom_of_match);
  868. #ifdef CONFIG_ACPI
  869. static const struct dwc3_acpi_pdata sdm845_acpi_pdata = {
  870. .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET,
  871. .qscratch_base_size = SDM845_QSCRATCH_SIZE,
  872. .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE,
  873. .hs_phy_irq_index = 1,
  874. .dp_hs_phy_irq_index = 4,
  875. .dm_hs_phy_irq_index = 3,
  876. .ss_phy_irq_index = 2
  877. };
  878. static const struct dwc3_acpi_pdata sdm845_acpi_urs_pdata = {
  879. .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET,
  880. .qscratch_base_size = SDM845_QSCRATCH_SIZE,
  881. .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE,
  882. .hs_phy_irq_index = 1,
  883. .dp_hs_phy_irq_index = 4,
  884. .dm_hs_phy_irq_index = 3,
  885. .ss_phy_irq_index = 2,
  886. .is_urs = true,
  887. };
  888. static const struct acpi_device_id dwc3_qcom_acpi_match[] = {
  889. { "QCOM2430", (unsigned long)&sdm845_acpi_pdata },
  890. { "QCOM0304", (unsigned long)&sdm845_acpi_urs_pdata },
  891. { "QCOM0497", (unsigned long)&sdm845_acpi_urs_pdata },
  892. { "QCOM04A6", (unsigned long)&sdm845_acpi_pdata },
  893. { },
  894. };
  895. MODULE_DEVICE_TABLE(acpi, dwc3_qcom_acpi_match);
  896. #endif
  897. static struct platform_driver dwc3_qcom_driver = {
  898. .probe = dwc3_qcom_probe,
  899. .remove = dwc3_qcom_remove,
  900. .driver = {
  901. .name = "dwc3-qcom",
  902. .pm = &dwc3_qcom_dev_pm_ops,
  903. .of_match_table = dwc3_qcom_of_match,
  904. .acpi_match_table = ACPI_PTR(dwc3_qcom_acpi_match),
  905. },
  906. };
  907. module_platform_driver(dwc3_qcom_driver);
  908. MODULE_LICENSE("GPL v2");
  909. MODULE_DESCRIPTION("DesignWare DWC3 QCOM Glue Driver");