platform.c 18 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
  2. /*
  3. * platform.c - DesignWare HS OTG Controller platform driver
  4. *
  5. * Copyright (C) Matthijs Kooijman <[email protected]>
  6. */
  7. #include <linux/kernel.h>
  8. #include <linux/module.h>
  9. #include <linux/slab.h>
  10. #include <linux/clk.h>
  11. #include <linux/device.h>
  12. #include <linux/dma-mapping.h>
  13. #include <linux/of_device.h>
  14. #include <linux/mutex.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/phy/phy.h>
  17. #include <linux/platform_data/s3c-hsotg.h>
  18. #include <linux/reset.h>
  19. #include <linux/usb/of.h>
  20. #include "core.h"
  21. #include "hcd.h"
  22. #include "debug.h"
  23. static const char dwc2_driver_name[] = "dwc2";
  24. /*
  25. * Check the dr_mode against the module configuration and hardware
  26. * capabilities.
  27. *
  28. * The hardware, module, and dr_mode, can each be set to host, device,
  29. * or otg. Check that all these values are compatible and adjust the
  30. * value of dr_mode if possible.
  31. *
  32. * actual
  33. * HW MOD dr_mode dr_mode
  34. * ------------------------------
  35. * HST HST any : HST
  36. * HST DEV any : ---
  37. * HST OTG any : HST
  38. *
  39. * DEV HST any : ---
  40. * DEV DEV any : DEV
  41. * DEV OTG any : DEV
  42. *
  43. * OTG HST any : HST
  44. * OTG DEV any : DEV
  45. * OTG OTG any : dr_mode
  46. */
  47. static int dwc2_get_dr_mode(struct dwc2_hsotg *hsotg)
  48. {
  49. enum usb_dr_mode mode;
  50. hsotg->dr_mode = usb_get_dr_mode(hsotg->dev);
  51. if (hsotg->dr_mode == USB_DR_MODE_UNKNOWN)
  52. hsotg->dr_mode = USB_DR_MODE_OTG;
  53. mode = hsotg->dr_mode;
  54. if (dwc2_hw_is_device(hsotg)) {
  55. if (IS_ENABLED(CONFIG_USB_DWC2_HOST)) {
  56. dev_err(hsotg->dev,
  57. "Controller does not support host mode.\n");
  58. return -EINVAL;
  59. }
  60. mode = USB_DR_MODE_PERIPHERAL;
  61. } else if (dwc2_hw_is_host(hsotg)) {
  62. if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL)) {
  63. dev_err(hsotg->dev,
  64. "Controller does not support device mode.\n");
  65. return -EINVAL;
  66. }
  67. mode = USB_DR_MODE_HOST;
  68. } else {
  69. if (IS_ENABLED(CONFIG_USB_DWC2_HOST))
  70. mode = USB_DR_MODE_HOST;
  71. else if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL))
  72. mode = USB_DR_MODE_PERIPHERAL;
  73. }
  74. if (mode != hsotg->dr_mode) {
  75. dev_warn(hsotg->dev,
  76. "Configuration mismatch. dr_mode forced to %s\n",
  77. mode == USB_DR_MODE_HOST ? "host" : "device");
  78. hsotg->dr_mode = mode;
  79. }
  80. return 0;
  81. }
  82. static int __dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
  83. {
  84. struct platform_device *pdev = to_platform_device(hsotg->dev);
  85. int ret;
  86. ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
  87. hsotg->supplies);
  88. if (ret)
  89. return ret;
  90. if (hsotg->clk) {
  91. ret = clk_prepare_enable(hsotg->clk);
  92. if (ret)
  93. return ret;
  94. }
  95. if (hsotg->uphy) {
  96. ret = usb_phy_init(hsotg->uphy);
  97. } else if (hsotg->plat && hsotg->plat->phy_init) {
  98. ret = hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
  99. } else {
  100. ret = phy_init(hsotg->phy);
  101. if (ret == 0)
  102. ret = phy_power_on(hsotg->phy);
  103. }
  104. return ret;
  105. }
  106. /**
  107. * dwc2_lowlevel_hw_enable - enable platform lowlevel hw resources
  108. * @hsotg: The driver state
  109. *
  110. * A wrapper for platform code responsible for controlling
  111. * low-level USB platform resources (phy, clock, regulators)
  112. */
  113. int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
  114. {
  115. int ret = __dwc2_lowlevel_hw_enable(hsotg);
  116. if (ret == 0)
  117. hsotg->ll_hw_enabled = true;
  118. return ret;
  119. }
  120. static int __dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
  121. {
  122. struct platform_device *pdev = to_platform_device(hsotg->dev);
  123. int ret = 0;
  124. if (hsotg->uphy) {
  125. usb_phy_shutdown(hsotg->uphy);
  126. } else if (hsotg->plat && hsotg->plat->phy_exit) {
  127. ret = hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
  128. } else {
  129. ret = phy_power_off(hsotg->phy);
  130. if (ret == 0)
  131. ret = phy_exit(hsotg->phy);
  132. }
  133. if (ret)
  134. return ret;
  135. if (hsotg->clk)
  136. clk_disable_unprepare(hsotg->clk);
  137. return regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
  138. }
  139. /**
  140. * dwc2_lowlevel_hw_disable - disable platform lowlevel hw resources
  141. * @hsotg: The driver state
  142. *
  143. * A wrapper for platform code responsible for controlling
  144. * low-level USB platform resources (phy, clock, regulators)
  145. */
  146. int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
  147. {
  148. int ret = __dwc2_lowlevel_hw_disable(hsotg);
  149. if (ret == 0)
  150. hsotg->ll_hw_enabled = false;
  151. return ret;
  152. }
  153. static void dwc2_reset_control_assert(void *data)
  154. {
  155. reset_control_assert(data);
  156. }
  157. static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
  158. {
  159. int i, ret;
  160. hsotg->reset = devm_reset_control_get_optional(hsotg->dev, "dwc2");
  161. if (IS_ERR(hsotg->reset))
  162. return dev_err_probe(hsotg->dev, PTR_ERR(hsotg->reset),
  163. "error getting reset control\n");
  164. reset_control_deassert(hsotg->reset);
  165. ret = devm_add_action_or_reset(hsotg->dev, dwc2_reset_control_assert,
  166. hsotg->reset);
  167. if (ret)
  168. return ret;
  169. hsotg->reset_ecc = devm_reset_control_get_optional(hsotg->dev, "dwc2-ecc");
  170. if (IS_ERR(hsotg->reset_ecc))
  171. return dev_err_probe(hsotg->dev, PTR_ERR(hsotg->reset_ecc),
  172. "error getting reset control for ecc\n");
  173. reset_control_deassert(hsotg->reset_ecc);
  174. ret = devm_add_action_or_reset(hsotg->dev, dwc2_reset_control_assert,
  175. hsotg->reset_ecc);
  176. if (ret)
  177. return ret;
  178. /*
  179. * Attempt to find a generic PHY, then look for an old style
  180. * USB PHY and then fall back to pdata
  181. */
  182. hsotg->phy = devm_phy_get(hsotg->dev, "usb2-phy");
  183. if (IS_ERR(hsotg->phy)) {
  184. ret = PTR_ERR(hsotg->phy);
  185. switch (ret) {
  186. case -ENODEV:
  187. case -ENOSYS:
  188. hsotg->phy = NULL;
  189. break;
  190. default:
  191. return dev_err_probe(hsotg->dev, ret, "error getting phy\n");
  192. }
  193. }
  194. if (!hsotg->phy) {
  195. hsotg->uphy = devm_usb_get_phy(hsotg->dev, USB_PHY_TYPE_USB2);
  196. if (IS_ERR(hsotg->uphy)) {
  197. ret = PTR_ERR(hsotg->uphy);
  198. switch (ret) {
  199. case -ENODEV:
  200. case -ENXIO:
  201. hsotg->uphy = NULL;
  202. break;
  203. default:
  204. return dev_err_probe(hsotg->dev, ret, "error getting usb phy\n");
  205. }
  206. }
  207. }
  208. hsotg->plat = dev_get_platdata(hsotg->dev);
  209. /* Clock */
  210. hsotg->clk = devm_clk_get_optional(hsotg->dev, "otg");
  211. if (IS_ERR(hsotg->clk))
  212. return dev_err_probe(hsotg->dev, PTR_ERR(hsotg->clk), "cannot get otg clock\n");
  213. /* Regulators */
  214. for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++)
  215. hsotg->supplies[i].supply = dwc2_hsotg_supply_names[i];
  216. ret = devm_regulator_bulk_get(hsotg->dev, ARRAY_SIZE(hsotg->supplies),
  217. hsotg->supplies);
  218. if (ret)
  219. return dev_err_probe(hsotg->dev, ret, "failed to request supplies\n");
  220. return 0;
  221. }
  222. /**
  223. * dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the
  224. * DWC_otg driver
  225. *
  226. * @dev: Platform device
  227. *
  228. * This routine is called, for example, when the rmmod command is executed. The
  229. * device may or may not be electrically present. If it is present, the driver
  230. * stops device processing. Any resources used on behalf of this device are
  231. * freed.
  232. */
  233. static int dwc2_driver_remove(struct platform_device *dev)
  234. {
  235. struct dwc2_hsotg *hsotg = platform_get_drvdata(dev);
  236. struct dwc2_gregs_backup *gr;
  237. int ret = 0;
  238. gr = &hsotg->gr_backup;
  239. /* Exit Hibernation when driver is removed. */
  240. if (hsotg->hibernated) {
  241. if (gr->gotgctl & GOTGCTL_CURMODE_HOST)
  242. ret = dwc2_exit_hibernation(hsotg, 0, 0, 1);
  243. else
  244. ret = dwc2_exit_hibernation(hsotg, 0, 0, 0);
  245. if (ret)
  246. dev_err(hsotg->dev,
  247. "exit hibernation failed.\n");
  248. }
  249. /* Exit Partial Power Down when driver is removed. */
  250. if (hsotg->in_ppd) {
  251. ret = dwc2_exit_partial_power_down(hsotg, 0, true);
  252. if (ret)
  253. dev_err(hsotg->dev,
  254. "exit partial_power_down failed\n");
  255. }
  256. /* Exit clock gating when driver is removed. */
  257. if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_NONE &&
  258. hsotg->bus_suspended) {
  259. if (dwc2_is_device_mode(hsotg))
  260. dwc2_gadget_exit_clock_gating(hsotg, 0);
  261. else
  262. dwc2_host_exit_clock_gating(hsotg, 0);
  263. }
  264. dwc2_debugfs_exit(hsotg);
  265. if (hsotg->hcd_enabled)
  266. dwc2_hcd_remove(hsotg);
  267. if (hsotg->gadget_enabled)
  268. dwc2_hsotg_remove(hsotg);
  269. dwc2_drd_exit(hsotg);
  270. if (hsotg->params.activate_stm_id_vb_detection)
  271. regulator_disable(hsotg->usb33d);
  272. if (hsotg->ll_hw_enabled)
  273. dwc2_lowlevel_hw_disable(hsotg);
  274. return 0;
  275. }
  276. /**
  277. * dwc2_driver_shutdown() - Called on device shutdown
  278. *
  279. * @dev: Platform device
  280. *
  281. * In specific conditions (involving usb hubs) dwc2 devices can create a
  282. * lot of interrupts, even to the point of overwhelming devices running
  283. * at low frequencies. Some devices need to do special clock handling
  284. * at shutdown-time which may bring the system clock below the threshold
  285. * of being able to handle the dwc2 interrupts. Disabling dwc2-irqs
  286. * prevents reboots/poweroffs from getting stuck in such cases.
  287. */
  288. static void dwc2_driver_shutdown(struct platform_device *dev)
  289. {
  290. struct dwc2_hsotg *hsotg = platform_get_drvdata(dev);
  291. dwc2_disable_global_interrupts(hsotg);
  292. synchronize_irq(hsotg->irq);
  293. }
  294. /**
  295. * dwc2_check_core_endianness() - Returns true if core and AHB have
  296. * opposite endianness.
  297. * @hsotg: Programming view of the DWC_otg controller.
  298. */
  299. static bool dwc2_check_core_endianness(struct dwc2_hsotg *hsotg)
  300. {
  301. u32 snpsid;
  302. snpsid = ioread32(hsotg->regs + GSNPSID);
  303. if ((snpsid & GSNPSID_ID_MASK) == DWC2_OTG_ID ||
  304. (snpsid & GSNPSID_ID_MASK) == DWC2_FS_IOT_ID ||
  305. (snpsid & GSNPSID_ID_MASK) == DWC2_HS_IOT_ID)
  306. return false;
  307. return true;
  308. }
  309. /**
  310. * dwc2_check_core_version() - Check core version
  311. *
  312. * @hsotg: Programming view of the DWC_otg controller
  313. *
  314. */
  315. int dwc2_check_core_version(struct dwc2_hsotg *hsotg)
  316. {
  317. struct dwc2_hw_params *hw = &hsotg->hw_params;
  318. /*
  319. * Attempt to ensure this device is really a DWC_otg Controller.
  320. * Read and verify the GSNPSID register contents. The value should be
  321. * 0x45f4xxxx, 0x5531xxxx or 0x5532xxxx
  322. */
  323. hw->snpsid = dwc2_readl(hsotg, GSNPSID);
  324. if ((hw->snpsid & GSNPSID_ID_MASK) != DWC2_OTG_ID &&
  325. (hw->snpsid & GSNPSID_ID_MASK) != DWC2_FS_IOT_ID &&
  326. (hw->snpsid & GSNPSID_ID_MASK) != DWC2_HS_IOT_ID) {
  327. dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n",
  328. hw->snpsid);
  329. return -ENODEV;
  330. }
  331. dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n",
  332. hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf,
  333. hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid);
  334. return 0;
  335. }
  336. /**
  337. * dwc2_driver_probe() - Called when the DWC_otg core is bound to the DWC_otg
  338. * driver
  339. *
  340. * @dev: Platform device
  341. *
  342. * This routine creates the driver components required to control the device
  343. * (core, HCD, and PCD) and initializes the device. The driver components are
  344. * stored in a dwc2_hsotg structure. A reference to the dwc2_hsotg is saved
  345. * in the device private data. This allows the driver to access the dwc2_hsotg
  346. * structure on subsequent calls to driver methods for this device.
  347. */
  348. static int dwc2_driver_probe(struct platform_device *dev)
  349. {
  350. struct dwc2_hsotg *hsotg;
  351. struct resource *res;
  352. int retval;
  353. hsotg = devm_kzalloc(&dev->dev, sizeof(*hsotg), GFP_KERNEL);
  354. if (!hsotg)
  355. return -ENOMEM;
  356. hsotg->dev = &dev->dev;
  357. /*
  358. * Use reasonable defaults so platforms don't have to provide these.
  359. */
  360. if (!dev->dev.dma_mask)
  361. dev->dev.dma_mask = &dev->dev.coherent_dma_mask;
  362. retval = dma_set_coherent_mask(&dev->dev, DMA_BIT_MASK(32));
  363. if (retval) {
  364. dev_err(&dev->dev, "can't set coherent DMA mask: %d\n", retval);
  365. return retval;
  366. }
  367. hsotg->regs = devm_platform_get_and_ioremap_resource(dev, 0, &res);
  368. if (IS_ERR(hsotg->regs))
  369. return PTR_ERR(hsotg->regs);
  370. dev_dbg(&dev->dev, "mapped PA %08lx to VA %p\n",
  371. (unsigned long)res->start, hsotg->regs);
  372. retval = dwc2_lowlevel_hw_init(hsotg);
  373. if (retval)
  374. return retval;
  375. spin_lock_init(&hsotg->lock);
  376. hsotg->irq = platform_get_irq(dev, 0);
  377. if (hsotg->irq < 0)
  378. return hsotg->irq;
  379. dev_dbg(hsotg->dev, "registering common handler for irq%d\n",
  380. hsotg->irq);
  381. retval = devm_request_irq(hsotg->dev, hsotg->irq,
  382. dwc2_handle_common_intr, IRQF_SHARED,
  383. dev_name(hsotg->dev), hsotg);
  384. if (retval)
  385. return retval;
  386. hsotg->vbus_supply = devm_regulator_get_optional(hsotg->dev, "vbus");
  387. if (IS_ERR(hsotg->vbus_supply)) {
  388. retval = PTR_ERR(hsotg->vbus_supply);
  389. hsotg->vbus_supply = NULL;
  390. if (retval != -ENODEV)
  391. return retval;
  392. }
  393. retval = dwc2_lowlevel_hw_enable(hsotg);
  394. if (retval)
  395. return retval;
  396. hsotg->needs_byte_swap = dwc2_check_core_endianness(hsotg);
  397. retval = dwc2_get_dr_mode(hsotg);
  398. if (retval)
  399. goto error;
  400. hsotg->need_phy_for_wake =
  401. of_property_read_bool(dev->dev.of_node,
  402. "snps,need-phy-for-wake");
  403. /*
  404. * Before performing any core related operations
  405. * check core version.
  406. */
  407. retval = dwc2_check_core_version(hsotg);
  408. if (retval)
  409. goto error;
  410. /*
  411. * Reset before dwc2_get_hwparams() then it could get power-on real
  412. * reset value form registers.
  413. */
  414. retval = dwc2_core_reset(hsotg, false);
  415. if (retval)
  416. goto error;
  417. /* Detect config values from hardware */
  418. retval = dwc2_get_hwparams(hsotg);
  419. if (retval)
  420. goto error;
  421. /*
  422. * For OTG cores, set the force mode bits to reflect the value
  423. * of dr_mode. Force mode bits should not be touched at any
  424. * other time after this.
  425. */
  426. dwc2_force_dr_mode(hsotg);
  427. retval = dwc2_init_params(hsotg);
  428. if (retval)
  429. goto error;
  430. if (hsotg->params.activate_stm_id_vb_detection) {
  431. u32 ggpio;
  432. hsotg->usb33d = devm_regulator_get(hsotg->dev, "usb33d");
  433. if (IS_ERR(hsotg->usb33d)) {
  434. retval = PTR_ERR(hsotg->usb33d);
  435. dev_err_probe(hsotg->dev, retval, "failed to request usb33d supply\n");
  436. goto error;
  437. }
  438. retval = regulator_enable(hsotg->usb33d);
  439. if (retval) {
  440. dev_err_probe(hsotg->dev, retval, "failed to enable usb33d supply\n");
  441. goto error;
  442. }
  443. ggpio = dwc2_readl(hsotg, GGPIO);
  444. ggpio |= GGPIO_STM32_OTG_GCCFG_IDEN;
  445. ggpio |= GGPIO_STM32_OTG_GCCFG_VBDEN;
  446. dwc2_writel(hsotg, ggpio, GGPIO);
  447. /* ID/VBUS detection startup time */
  448. usleep_range(5000, 7000);
  449. }
  450. retval = dwc2_drd_init(hsotg);
  451. if (retval) {
  452. dev_err_probe(hsotg->dev, retval, "failed to initialize dual-role\n");
  453. goto error_init;
  454. }
  455. if (hsotg->dr_mode != USB_DR_MODE_HOST) {
  456. retval = dwc2_gadget_init(hsotg);
  457. if (retval)
  458. goto error_drd;
  459. hsotg->gadget_enabled = 1;
  460. }
  461. /*
  462. * If we need PHY for wakeup we must be wakeup capable.
  463. * When we have a device that can wake without the PHY we
  464. * can adjust this condition.
  465. */
  466. if (hsotg->need_phy_for_wake)
  467. device_set_wakeup_capable(&dev->dev, true);
  468. hsotg->reset_phy_on_wake =
  469. of_property_read_bool(dev->dev.of_node,
  470. "snps,reset-phy-on-wake");
  471. if (hsotg->reset_phy_on_wake && !hsotg->phy) {
  472. dev_warn(hsotg->dev,
  473. "Quirk reset-phy-on-wake only supports generic PHYs\n");
  474. hsotg->reset_phy_on_wake = false;
  475. }
  476. if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) {
  477. retval = dwc2_hcd_init(hsotg);
  478. if (retval) {
  479. if (hsotg->gadget_enabled)
  480. dwc2_hsotg_remove(hsotg);
  481. goto error_drd;
  482. }
  483. hsotg->hcd_enabled = 1;
  484. }
  485. platform_set_drvdata(dev, hsotg);
  486. hsotg->hibernated = 0;
  487. dwc2_debugfs_init(hsotg);
  488. /* Gadget code manages lowlevel hw on its own */
  489. if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
  490. dwc2_lowlevel_hw_disable(hsotg);
  491. #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
  492. IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
  493. /* Postponed adding a new gadget to the udc class driver list */
  494. if (hsotg->gadget_enabled) {
  495. retval = usb_add_gadget_udc(hsotg->dev, &hsotg->gadget);
  496. if (retval) {
  497. hsotg->gadget.udc = NULL;
  498. dwc2_hsotg_remove(hsotg);
  499. goto error_debugfs;
  500. }
  501. }
  502. #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
  503. return 0;
  504. #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
  505. IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
  506. error_debugfs:
  507. dwc2_debugfs_exit(hsotg);
  508. if (hsotg->hcd_enabled)
  509. dwc2_hcd_remove(hsotg);
  510. #endif
  511. error_drd:
  512. dwc2_drd_exit(hsotg);
  513. error_init:
  514. if (hsotg->params.activate_stm_id_vb_detection)
  515. regulator_disable(hsotg->usb33d);
  516. error:
  517. if (hsotg->ll_hw_enabled)
  518. dwc2_lowlevel_hw_disable(hsotg);
  519. return retval;
  520. }
  521. static int __maybe_unused dwc2_suspend(struct device *dev)
  522. {
  523. struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
  524. bool is_device_mode = dwc2_is_device_mode(dwc2);
  525. int ret = 0;
  526. if (is_device_mode)
  527. dwc2_hsotg_suspend(dwc2);
  528. dwc2_drd_suspend(dwc2);
  529. if (dwc2->params.activate_stm_id_vb_detection) {
  530. unsigned long flags;
  531. u32 ggpio, gotgctl;
  532. /*
  533. * Need to force the mode to the current mode to avoid Mode
  534. * Mismatch Interrupt when ID detection will be disabled.
  535. */
  536. dwc2_force_mode(dwc2, !is_device_mode);
  537. spin_lock_irqsave(&dwc2->lock, flags);
  538. gotgctl = dwc2_readl(dwc2, GOTGCTL);
  539. /* bypass debounce filter, enable overrides */
  540. gotgctl |= GOTGCTL_DBNCE_FLTR_BYPASS;
  541. gotgctl |= GOTGCTL_BVALOEN | GOTGCTL_AVALOEN;
  542. /* Force A / B session if needed */
  543. if (gotgctl & GOTGCTL_ASESVLD)
  544. gotgctl |= GOTGCTL_AVALOVAL;
  545. if (gotgctl & GOTGCTL_BSESVLD)
  546. gotgctl |= GOTGCTL_BVALOVAL;
  547. dwc2_writel(dwc2, gotgctl, GOTGCTL);
  548. spin_unlock_irqrestore(&dwc2->lock, flags);
  549. ggpio = dwc2_readl(dwc2, GGPIO);
  550. ggpio &= ~GGPIO_STM32_OTG_GCCFG_IDEN;
  551. ggpio &= ~GGPIO_STM32_OTG_GCCFG_VBDEN;
  552. dwc2_writel(dwc2, ggpio, GGPIO);
  553. regulator_disable(dwc2->usb33d);
  554. }
  555. if (dwc2->ll_hw_enabled &&
  556. (is_device_mode || dwc2_host_can_poweroff_phy(dwc2))) {
  557. ret = __dwc2_lowlevel_hw_disable(dwc2);
  558. dwc2->phy_off_for_suspend = true;
  559. }
  560. return ret;
  561. }
  562. static int __maybe_unused dwc2_resume(struct device *dev)
  563. {
  564. struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
  565. int ret = 0;
  566. if (dwc2->phy_off_for_suspend && dwc2->ll_hw_enabled) {
  567. ret = __dwc2_lowlevel_hw_enable(dwc2);
  568. if (ret)
  569. return ret;
  570. }
  571. dwc2->phy_off_for_suspend = false;
  572. if (dwc2->params.activate_stm_id_vb_detection) {
  573. unsigned long flags;
  574. u32 ggpio, gotgctl;
  575. ret = regulator_enable(dwc2->usb33d);
  576. if (ret)
  577. return ret;
  578. ggpio = dwc2_readl(dwc2, GGPIO);
  579. ggpio |= GGPIO_STM32_OTG_GCCFG_IDEN;
  580. ggpio |= GGPIO_STM32_OTG_GCCFG_VBDEN;
  581. dwc2_writel(dwc2, ggpio, GGPIO);
  582. /* ID/VBUS detection startup time */
  583. usleep_range(5000, 7000);
  584. spin_lock_irqsave(&dwc2->lock, flags);
  585. gotgctl = dwc2_readl(dwc2, GOTGCTL);
  586. gotgctl &= ~GOTGCTL_DBNCE_FLTR_BYPASS;
  587. gotgctl &= ~(GOTGCTL_BVALOEN | GOTGCTL_AVALOEN |
  588. GOTGCTL_BVALOVAL | GOTGCTL_AVALOVAL);
  589. dwc2_writel(dwc2, gotgctl, GOTGCTL);
  590. spin_unlock_irqrestore(&dwc2->lock, flags);
  591. }
  592. if (!dwc2->role_sw) {
  593. /* Need to restore FORCEDEVMODE/FORCEHOSTMODE */
  594. dwc2_force_dr_mode(dwc2);
  595. } else {
  596. dwc2_drd_resume(dwc2);
  597. }
  598. if (dwc2_is_device_mode(dwc2))
  599. ret = dwc2_hsotg_resume(dwc2);
  600. return ret;
  601. }
  602. static const struct dev_pm_ops dwc2_dev_pm_ops = {
  603. SET_SYSTEM_SLEEP_PM_OPS(dwc2_suspend, dwc2_resume)
  604. };
  605. static struct platform_driver dwc2_platform_driver = {
  606. .driver = {
  607. .name = dwc2_driver_name,
  608. .of_match_table = dwc2_of_match_table,
  609. .acpi_match_table = ACPI_PTR(dwc2_acpi_match),
  610. .pm = &dwc2_dev_pm_ops,
  611. },
  612. .probe = dwc2_driver_probe,
  613. .remove = dwc2_driver_remove,
  614. .shutdown = dwc2_driver_shutdown,
  615. };
  616. module_platform_driver(dwc2_platform_driver);