synclink_gt.c 128 KB

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  1. // SPDX-License-Identifier: GPL-1.0+
  2. /*
  3. * Device driver for Microgate SyncLink GT serial adapters.
  4. *
  5. * written by Paul Fulghum for Microgate Corporation
  6. * [email protected]
  7. *
  8. * Microgate and SyncLink are trademarks of Microgate Corporation
  9. *
  10. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  11. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  12. * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  13. * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  14. * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  15. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  16. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  17. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  18. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  19. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  20. * OF THE POSSIBILITY OF SUCH DAMAGE.
  21. */
  22. /*
  23. * DEBUG OUTPUT DEFINITIONS
  24. *
  25. * uncomment lines below to enable specific types of debug output
  26. *
  27. * DBGINFO information - most verbose output
  28. * DBGERR serious errors
  29. * DBGBH bottom half service routine debugging
  30. * DBGISR interrupt service routine debugging
  31. * DBGDATA output receive and transmit data
  32. * DBGTBUF output transmit DMA buffers and registers
  33. * DBGRBUF output receive DMA buffers and registers
  34. */
  35. #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
  36. #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
  37. #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
  38. #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
  39. #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
  40. /*#define DBGTBUF(info) dump_tbufs(info)*/
  41. /*#define DBGRBUF(info) dump_rbufs(info)*/
  42. #include <linux/module.h>
  43. #include <linux/errno.h>
  44. #include <linux/signal.h>
  45. #include <linux/sched.h>
  46. #include <linux/timer.h>
  47. #include <linux/interrupt.h>
  48. #include <linux/pci.h>
  49. #include <linux/tty.h>
  50. #include <linux/tty_flip.h>
  51. #include <linux/serial.h>
  52. #include <linux/major.h>
  53. #include <linux/string.h>
  54. #include <linux/fcntl.h>
  55. #include <linux/ptrace.h>
  56. #include <linux/ioport.h>
  57. #include <linux/mm.h>
  58. #include <linux/seq_file.h>
  59. #include <linux/slab.h>
  60. #include <linux/netdevice.h>
  61. #include <linux/vmalloc.h>
  62. #include <linux/init.h>
  63. #include <linux/delay.h>
  64. #include <linux/ioctl.h>
  65. #include <linux/termios.h>
  66. #include <linux/bitops.h>
  67. #include <linux/workqueue.h>
  68. #include <linux/hdlc.h>
  69. #include <linux/synclink.h>
  70. #include <asm/io.h>
  71. #include <asm/irq.h>
  72. #include <asm/dma.h>
  73. #include <asm/types.h>
  74. #include <linux/uaccess.h>
  75. #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
  76. #define SYNCLINK_GENERIC_HDLC 1
  77. #else
  78. #define SYNCLINK_GENERIC_HDLC 0
  79. #endif
  80. /*
  81. * module identification
  82. */
  83. static char *driver_name = "SyncLink GT";
  84. static char *slgt_driver_name = "synclink_gt";
  85. static char *tty_dev_prefix = "ttySLG";
  86. MODULE_LICENSE("GPL");
  87. #define MAX_DEVICES 32
  88. static const struct pci_device_id pci_table[] = {
  89. {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
  90. {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
  91. {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
  92. {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
  93. {0,}, /* terminate list */
  94. };
  95. MODULE_DEVICE_TABLE(pci, pci_table);
  96. static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
  97. static void remove_one(struct pci_dev *dev);
  98. static struct pci_driver pci_driver = {
  99. .name = "synclink_gt",
  100. .id_table = pci_table,
  101. .probe = init_one,
  102. .remove = remove_one,
  103. };
  104. static bool pci_registered;
  105. /*
  106. * module configuration and status
  107. */
  108. static struct slgt_info *slgt_device_list;
  109. static int slgt_device_count;
  110. static int ttymajor;
  111. static int debug_level;
  112. static int maxframe[MAX_DEVICES];
  113. module_param(ttymajor, int, 0);
  114. module_param(debug_level, int, 0);
  115. module_param_array(maxframe, int, NULL, 0);
  116. MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
  117. MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
  118. MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
  119. /*
  120. * tty support and callbacks
  121. */
  122. static struct tty_driver *serial_driver;
  123. static void wait_until_sent(struct tty_struct *tty, int timeout);
  124. static void flush_buffer(struct tty_struct *tty);
  125. static void tx_release(struct tty_struct *tty);
  126. /*
  127. * generic HDLC support
  128. */
  129. #define dev_to_port(D) (dev_to_hdlc(D)->priv)
  130. /*
  131. * device specific structures, macros and functions
  132. */
  133. #define SLGT_MAX_PORTS 4
  134. #define SLGT_REG_SIZE 256
  135. /*
  136. * conditional wait facility
  137. */
  138. struct cond_wait {
  139. struct cond_wait *next;
  140. wait_queue_head_t q;
  141. wait_queue_entry_t wait;
  142. unsigned int data;
  143. };
  144. static void flush_cond_wait(struct cond_wait **head);
  145. /*
  146. * DMA buffer descriptor and access macros
  147. */
  148. struct slgt_desc
  149. {
  150. __le16 count;
  151. __le16 status;
  152. __le32 pbuf; /* physical address of data buffer */
  153. __le32 next; /* physical address of next descriptor */
  154. /* driver book keeping */
  155. char *buf; /* virtual address of data buffer */
  156. unsigned int pdesc; /* physical address of this descriptor */
  157. dma_addr_t buf_dma_addr;
  158. unsigned short buf_count;
  159. };
  160. #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
  161. #define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
  162. #define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
  163. #define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
  164. #define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
  165. #define desc_count(a) (le16_to_cpu((a).count))
  166. #define desc_status(a) (le16_to_cpu((a).status))
  167. #define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
  168. #define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
  169. #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
  170. #define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
  171. #define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
  172. struct _input_signal_events {
  173. int ri_up;
  174. int ri_down;
  175. int dsr_up;
  176. int dsr_down;
  177. int dcd_up;
  178. int dcd_down;
  179. int cts_up;
  180. int cts_down;
  181. };
  182. /*
  183. * device instance data structure
  184. */
  185. struct slgt_info {
  186. void *if_ptr; /* General purpose pointer (used by SPPP) */
  187. struct tty_port port;
  188. struct slgt_info *next_device; /* device list link */
  189. char device_name[25];
  190. struct pci_dev *pdev;
  191. int port_count; /* count of ports on adapter */
  192. int adapter_num; /* adapter instance number */
  193. int port_num; /* port instance number */
  194. /* array of pointers to port contexts on this adapter */
  195. struct slgt_info *port_array[SLGT_MAX_PORTS];
  196. int line; /* tty line instance number */
  197. struct mgsl_icount icount;
  198. int timeout;
  199. int x_char; /* xon/xoff character */
  200. unsigned int read_status_mask;
  201. unsigned int ignore_status_mask;
  202. wait_queue_head_t status_event_wait_q;
  203. wait_queue_head_t event_wait_q;
  204. struct timer_list tx_timer;
  205. struct timer_list rx_timer;
  206. unsigned int gpio_present;
  207. struct cond_wait *gpio_wait_q;
  208. spinlock_t lock; /* spinlock for synchronizing with ISR */
  209. struct work_struct task;
  210. u32 pending_bh;
  211. bool bh_requested;
  212. bool bh_running;
  213. int isr_overflow;
  214. bool irq_requested; /* true if IRQ requested */
  215. bool irq_occurred; /* for diagnostics use */
  216. /* device configuration */
  217. unsigned int bus_type;
  218. unsigned int irq_level;
  219. unsigned long irq_flags;
  220. unsigned char __iomem * reg_addr; /* memory mapped registers address */
  221. u32 phys_reg_addr;
  222. bool reg_addr_requested;
  223. MGSL_PARAMS params; /* communications parameters */
  224. u32 idle_mode;
  225. u32 max_frame_size; /* as set by device config */
  226. unsigned int rbuf_fill_level;
  227. unsigned int rx_pio;
  228. unsigned int if_mode;
  229. unsigned int base_clock;
  230. unsigned int xsync;
  231. unsigned int xctrl;
  232. /* device status */
  233. bool rx_enabled;
  234. bool rx_restart;
  235. bool tx_enabled;
  236. bool tx_active;
  237. unsigned char signals; /* serial signal states */
  238. int init_error; /* initialization error */
  239. unsigned char *tx_buf;
  240. int tx_count;
  241. char *flag_buf;
  242. bool drop_rts_on_tx_done;
  243. struct _input_signal_events input_signal_events;
  244. int dcd_chkcount; /* check counts to prevent */
  245. int cts_chkcount; /* too many IRQs if a signal */
  246. int dsr_chkcount; /* is floating */
  247. int ri_chkcount;
  248. char *bufs; /* virtual address of DMA buffer lists */
  249. dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
  250. unsigned int rbuf_count;
  251. struct slgt_desc *rbufs;
  252. unsigned int rbuf_current;
  253. unsigned int rbuf_index;
  254. unsigned int rbuf_fill_index;
  255. unsigned short rbuf_fill_count;
  256. unsigned int tbuf_count;
  257. struct slgt_desc *tbufs;
  258. unsigned int tbuf_current;
  259. unsigned int tbuf_start;
  260. unsigned char *tmp_rbuf;
  261. unsigned int tmp_rbuf_count;
  262. /* SPPP/Cisco HDLC device parts */
  263. int netcount;
  264. spinlock_t netlock;
  265. #if SYNCLINK_GENERIC_HDLC
  266. struct net_device *netdev;
  267. #endif
  268. };
  269. static MGSL_PARAMS default_params = {
  270. .mode = MGSL_MODE_HDLC,
  271. .loopback = 0,
  272. .flags = HDLC_FLAG_UNDERRUN_ABORT15,
  273. .encoding = HDLC_ENCODING_NRZI_SPACE,
  274. .clock_speed = 0,
  275. .addr_filter = 0xff,
  276. .crc_type = HDLC_CRC_16_CCITT,
  277. .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
  278. .preamble = HDLC_PREAMBLE_PATTERN_NONE,
  279. .data_rate = 9600,
  280. .data_bits = 8,
  281. .stop_bits = 1,
  282. .parity = ASYNC_PARITY_NONE
  283. };
  284. #define BH_RECEIVE 1
  285. #define BH_TRANSMIT 2
  286. #define BH_STATUS 4
  287. #define IO_PIN_SHUTDOWN_LIMIT 100
  288. #define DMABUFSIZE 256
  289. #define DESC_LIST_SIZE 4096
  290. #define MASK_PARITY BIT1
  291. #define MASK_FRAMING BIT0
  292. #define MASK_BREAK BIT14
  293. #define MASK_OVERRUN BIT4
  294. #define GSR 0x00 /* global status */
  295. #define JCR 0x04 /* JTAG control */
  296. #define IODR 0x08 /* GPIO direction */
  297. #define IOER 0x0c /* GPIO interrupt enable */
  298. #define IOVR 0x10 /* GPIO value */
  299. #define IOSR 0x14 /* GPIO interrupt status */
  300. #define TDR 0x80 /* tx data */
  301. #define RDR 0x80 /* rx data */
  302. #define TCR 0x82 /* tx control */
  303. #define TIR 0x84 /* tx idle */
  304. #define TPR 0x85 /* tx preamble */
  305. #define RCR 0x86 /* rx control */
  306. #define VCR 0x88 /* V.24 control */
  307. #define CCR 0x89 /* clock control */
  308. #define BDR 0x8a /* baud divisor */
  309. #define SCR 0x8c /* serial control */
  310. #define SSR 0x8e /* serial status */
  311. #define RDCSR 0x90 /* rx DMA control/status */
  312. #define TDCSR 0x94 /* tx DMA control/status */
  313. #define RDDAR 0x98 /* rx DMA descriptor address */
  314. #define TDDAR 0x9c /* tx DMA descriptor address */
  315. #define XSR 0x40 /* extended sync pattern */
  316. #define XCR 0x44 /* extended control */
  317. #define RXIDLE BIT14
  318. #define RXBREAK BIT14
  319. #define IRQ_TXDATA BIT13
  320. #define IRQ_TXIDLE BIT12
  321. #define IRQ_TXUNDER BIT11 /* HDLC */
  322. #define IRQ_RXDATA BIT10
  323. #define IRQ_RXIDLE BIT9 /* HDLC */
  324. #define IRQ_RXBREAK BIT9 /* async */
  325. #define IRQ_RXOVER BIT8
  326. #define IRQ_DSR BIT7
  327. #define IRQ_CTS BIT6
  328. #define IRQ_DCD BIT5
  329. #define IRQ_RI BIT4
  330. #define IRQ_ALL 0x3ff0
  331. #define IRQ_MASTER BIT0
  332. #define slgt_irq_on(info, mask) \
  333. wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
  334. #define slgt_irq_off(info, mask) \
  335. wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
  336. static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
  337. static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
  338. static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
  339. static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
  340. static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
  341. static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
  342. static void msc_set_vcr(struct slgt_info *info);
  343. static int startup(struct slgt_info *info);
  344. static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
  345. static void shutdown(struct slgt_info *info);
  346. static void program_hw(struct slgt_info *info);
  347. static void change_params(struct slgt_info *info);
  348. static int adapter_test(struct slgt_info *info);
  349. static void reset_port(struct slgt_info *info);
  350. static void async_mode(struct slgt_info *info);
  351. static void sync_mode(struct slgt_info *info);
  352. static void rx_stop(struct slgt_info *info);
  353. static void rx_start(struct slgt_info *info);
  354. static void reset_rbufs(struct slgt_info *info);
  355. static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
  356. static bool rx_get_frame(struct slgt_info *info);
  357. static bool rx_get_buf(struct slgt_info *info);
  358. static void tx_start(struct slgt_info *info);
  359. static void tx_stop(struct slgt_info *info);
  360. static void tx_set_idle(struct slgt_info *info);
  361. static unsigned int tbuf_bytes(struct slgt_info *info);
  362. static void reset_tbufs(struct slgt_info *info);
  363. static void tdma_reset(struct slgt_info *info);
  364. static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count);
  365. static void get_gtsignals(struct slgt_info *info);
  366. static void set_gtsignals(struct slgt_info *info);
  367. static void set_rate(struct slgt_info *info, u32 data_rate);
  368. static void bh_transmit(struct slgt_info *info);
  369. static void isr_txeom(struct slgt_info *info, unsigned short status);
  370. static void tx_timeout(struct timer_list *t);
  371. static void rx_timeout(struct timer_list *t);
  372. /*
  373. * ioctl handlers
  374. */
  375. static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
  376. static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
  377. static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
  378. static int get_txidle(struct slgt_info *info, int __user *idle_mode);
  379. static int set_txidle(struct slgt_info *info, int idle_mode);
  380. static int tx_enable(struct slgt_info *info, int enable);
  381. static int tx_abort(struct slgt_info *info);
  382. static int rx_enable(struct slgt_info *info, int enable);
  383. static int modem_input_wait(struct slgt_info *info,int arg);
  384. static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
  385. static int get_interface(struct slgt_info *info, int __user *if_mode);
  386. static int set_interface(struct slgt_info *info, int if_mode);
  387. static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
  388. static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
  389. static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
  390. static int get_xsync(struct slgt_info *info, int __user *if_mode);
  391. static int set_xsync(struct slgt_info *info, int if_mode);
  392. static int get_xctrl(struct slgt_info *info, int __user *if_mode);
  393. static int set_xctrl(struct slgt_info *info, int if_mode);
  394. /*
  395. * driver functions
  396. */
  397. static void release_resources(struct slgt_info *info);
  398. /*
  399. * DEBUG OUTPUT CODE
  400. */
  401. #ifndef DBGINFO
  402. #define DBGINFO(fmt)
  403. #endif
  404. #ifndef DBGERR
  405. #define DBGERR(fmt)
  406. #endif
  407. #ifndef DBGBH
  408. #define DBGBH(fmt)
  409. #endif
  410. #ifndef DBGISR
  411. #define DBGISR(fmt)
  412. #endif
  413. #ifdef DBGDATA
  414. static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
  415. {
  416. int i;
  417. int linecount;
  418. printk("%s %s data:\n",info->device_name, label);
  419. while(count) {
  420. linecount = (count > 16) ? 16 : count;
  421. for(i=0; i < linecount; i++)
  422. printk("%02X ",(unsigned char)data[i]);
  423. for(;i<17;i++)
  424. printk(" ");
  425. for(i=0;i<linecount;i++) {
  426. if (data[i]>=040 && data[i]<=0176)
  427. printk("%c",data[i]);
  428. else
  429. printk(".");
  430. }
  431. printk("\n");
  432. data += linecount;
  433. count -= linecount;
  434. }
  435. }
  436. #else
  437. #define DBGDATA(info, buf, size, label)
  438. #endif
  439. #ifdef DBGTBUF
  440. static void dump_tbufs(struct slgt_info *info)
  441. {
  442. int i;
  443. printk("tbuf_current=%d\n", info->tbuf_current);
  444. for (i=0 ; i < info->tbuf_count ; i++) {
  445. printk("%d: count=%04X status=%04X\n",
  446. i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
  447. }
  448. }
  449. #else
  450. #define DBGTBUF(info)
  451. #endif
  452. #ifdef DBGRBUF
  453. static void dump_rbufs(struct slgt_info *info)
  454. {
  455. int i;
  456. printk("rbuf_current=%d\n", info->rbuf_current);
  457. for (i=0 ; i < info->rbuf_count ; i++) {
  458. printk("%d: count=%04X status=%04X\n",
  459. i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
  460. }
  461. }
  462. #else
  463. #define DBGRBUF(info)
  464. #endif
  465. static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
  466. {
  467. #ifdef SANITY_CHECK
  468. if (!info) {
  469. printk("null struct slgt_info for (%s) in %s\n", devname, name);
  470. return 1;
  471. }
  472. #else
  473. if (!info)
  474. return 1;
  475. #endif
  476. return 0;
  477. }
  478. /*
  479. * line discipline callback wrappers
  480. *
  481. * The wrappers maintain line discipline references
  482. * while calling into the line discipline.
  483. *
  484. * ldisc_receive_buf - pass receive data to line discipline
  485. */
  486. static void ldisc_receive_buf(struct tty_struct *tty,
  487. const __u8 *data, char *flags, int count)
  488. {
  489. struct tty_ldisc *ld;
  490. if (!tty)
  491. return;
  492. ld = tty_ldisc_ref(tty);
  493. if (ld) {
  494. if (ld->ops->receive_buf)
  495. ld->ops->receive_buf(tty, data, flags, count);
  496. tty_ldisc_deref(ld);
  497. }
  498. }
  499. /* tty callbacks */
  500. static int open(struct tty_struct *tty, struct file *filp)
  501. {
  502. struct slgt_info *info;
  503. int retval, line;
  504. unsigned long flags;
  505. line = tty->index;
  506. if (line >= slgt_device_count) {
  507. DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
  508. return -ENODEV;
  509. }
  510. info = slgt_device_list;
  511. while(info && info->line != line)
  512. info = info->next_device;
  513. if (sanity_check(info, tty->name, "open"))
  514. return -ENODEV;
  515. if (info->init_error) {
  516. DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
  517. return -ENODEV;
  518. }
  519. tty->driver_data = info;
  520. info->port.tty = tty;
  521. DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
  522. mutex_lock(&info->port.mutex);
  523. spin_lock_irqsave(&info->netlock, flags);
  524. if (info->netcount) {
  525. retval = -EBUSY;
  526. spin_unlock_irqrestore(&info->netlock, flags);
  527. mutex_unlock(&info->port.mutex);
  528. goto cleanup;
  529. }
  530. info->port.count++;
  531. spin_unlock_irqrestore(&info->netlock, flags);
  532. if (info->port.count == 1) {
  533. /* 1st open on this device, init hardware */
  534. retval = startup(info);
  535. if (retval < 0) {
  536. mutex_unlock(&info->port.mutex);
  537. goto cleanup;
  538. }
  539. }
  540. mutex_unlock(&info->port.mutex);
  541. retval = block_til_ready(tty, filp, info);
  542. if (retval) {
  543. DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
  544. goto cleanup;
  545. }
  546. retval = 0;
  547. cleanup:
  548. if (retval) {
  549. if (tty->count == 1)
  550. info->port.tty = NULL; /* tty layer will release tty struct */
  551. if(info->port.count)
  552. info->port.count--;
  553. }
  554. DBGINFO(("%s open rc=%d\n", info->device_name, retval));
  555. return retval;
  556. }
  557. static void close(struct tty_struct *tty, struct file *filp)
  558. {
  559. struct slgt_info *info = tty->driver_data;
  560. if (sanity_check(info, tty->name, "close"))
  561. return;
  562. DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
  563. if (tty_port_close_start(&info->port, tty, filp) == 0)
  564. goto cleanup;
  565. mutex_lock(&info->port.mutex);
  566. if (tty_port_initialized(&info->port))
  567. wait_until_sent(tty, info->timeout);
  568. flush_buffer(tty);
  569. tty_ldisc_flush(tty);
  570. shutdown(info);
  571. mutex_unlock(&info->port.mutex);
  572. tty_port_close_end(&info->port, tty);
  573. info->port.tty = NULL;
  574. cleanup:
  575. DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
  576. }
  577. static void hangup(struct tty_struct *tty)
  578. {
  579. struct slgt_info *info = tty->driver_data;
  580. unsigned long flags;
  581. if (sanity_check(info, tty->name, "hangup"))
  582. return;
  583. DBGINFO(("%s hangup\n", info->device_name));
  584. flush_buffer(tty);
  585. mutex_lock(&info->port.mutex);
  586. shutdown(info);
  587. spin_lock_irqsave(&info->port.lock, flags);
  588. info->port.count = 0;
  589. info->port.tty = NULL;
  590. spin_unlock_irqrestore(&info->port.lock, flags);
  591. tty_port_set_active(&info->port, 0);
  592. mutex_unlock(&info->port.mutex);
  593. wake_up_interruptible(&info->port.open_wait);
  594. }
  595. static void set_termios(struct tty_struct *tty,
  596. const struct ktermios *old_termios)
  597. {
  598. struct slgt_info *info = tty->driver_data;
  599. unsigned long flags;
  600. DBGINFO(("%s set_termios\n", tty->driver->name));
  601. change_params(info);
  602. /* Handle transition to B0 status */
  603. if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
  604. info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
  605. spin_lock_irqsave(&info->lock,flags);
  606. set_gtsignals(info);
  607. spin_unlock_irqrestore(&info->lock,flags);
  608. }
  609. /* Handle transition away from B0 status */
  610. if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
  611. info->signals |= SerialSignal_DTR;
  612. if (!C_CRTSCTS(tty) || !tty_throttled(tty))
  613. info->signals |= SerialSignal_RTS;
  614. spin_lock_irqsave(&info->lock,flags);
  615. set_gtsignals(info);
  616. spin_unlock_irqrestore(&info->lock,flags);
  617. }
  618. /* Handle turning off CRTSCTS */
  619. if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) {
  620. tty->hw_stopped = 0;
  621. tx_release(tty);
  622. }
  623. }
  624. static void update_tx_timer(struct slgt_info *info)
  625. {
  626. /*
  627. * use worst case speed of 1200bps to calculate transmit timeout
  628. * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
  629. */
  630. if (info->params.mode == MGSL_MODE_HDLC) {
  631. int timeout = (tbuf_bytes(info) * 7) + 1000;
  632. mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
  633. }
  634. }
  635. static int write(struct tty_struct *tty,
  636. const unsigned char *buf, int count)
  637. {
  638. int ret = 0;
  639. struct slgt_info *info = tty->driver_data;
  640. unsigned long flags;
  641. if (sanity_check(info, tty->name, "write"))
  642. return -EIO;
  643. DBGINFO(("%s write count=%d\n", info->device_name, count));
  644. if (!info->tx_buf || (count > info->max_frame_size))
  645. return -EIO;
  646. if (!count || tty->flow.stopped || tty->hw_stopped)
  647. return 0;
  648. spin_lock_irqsave(&info->lock, flags);
  649. if (info->tx_count) {
  650. /* send accumulated data from send_char() */
  651. if (!tx_load(info, info->tx_buf, info->tx_count))
  652. goto cleanup;
  653. info->tx_count = 0;
  654. }
  655. if (tx_load(info, buf, count))
  656. ret = count;
  657. cleanup:
  658. spin_unlock_irqrestore(&info->lock, flags);
  659. DBGINFO(("%s write rc=%d\n", info->device_name, ret));
  660. return ret;
  661. }
  662. static int put_char(struct tty_struct *tty, unsigned char ch)
  663. {
  664. struct slgt_info *info = tty->driver_data;
  665. unsigned long flags;
  666. int ret = 0;
  667. if (sanity_check(info, tty->name, "put_char"))
  668. return 0;
  669. DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
  670. if (!info->tx_buf)
  671. return 0;
  672. spin_lock_irqsave(&info->lock,flags);
  673. if (info->tx_count < info->max_frame_size) {
  674. info->tx_buf[info->tx_count++] = ch;
  675. ret = 1;
  676. }
  677. spin_unlock_irqrestore(&info->lock,flags);
  678. return ret;
  679. }
  680. static void send_xchar(struct tty_struct *tty, char ch)
  681. {
  682. struct slgt_info *info = tty->driver_data;
  683. unsigned long flags;
  684. if (sanity_check(info, tty->name, "send_xchar"))
  685. return;
  686. DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
  687. info->x_char = ch;
  688. if (ch) {
  689. spin_lock_irqsave(&info->lock,flags);
  690. if (!info->tx_enabled)
  691. tx_start(info);
  692. spin_unlock_irqrestore(&info->lock,flags);
  693. }
  694. }
  695. static void wait_until_sent(struct tty_struct *tty, int timeout)
  696. {
  697. struct slgt_info *info = tty->driver_data;
  698. unsigned long orig_jiffies, char_time;
  699. if (!info )
  700. return;
  701. if (sanity_check(info, tty->name, "wait_until_sent"))
  702. return;
  703. DBGINFO(("%s wait_until_sent entry\n", info->device_name));
  704. if (!tty_port_initialized(&info->port))
  705. goto exit;
  706. orig_jiffies = jiffies;
  707. /* Set check interval to 1/5 of estimated time to
  708. * send a character, and make it at least 1. The check
  709. * interval should also be less than the timeout.
  710. * Note: use tight timings here to satisfy the NIST-PCTS.
  711. */
  712. if (info->params.data_rate) {
  713. char_time = info->timeout/(32 * 5);
  714. if (!char_time)
  715. char_time++;
  716. } else
  717. char_time = 1;
  718. if (timeout)
  719. char_time = min_t(unsigned long, char_time, timeout);
  720. while (info->tx_active) {
  721. msleep_interruptible(jiffies_to_msecs(char_time));
  722. if (signal_pending(current))
  723. break;
  724. if (timeout && time_after(jiffies, orig_jiffies + timeout))
  725. break;
  726. }
  727. exit:
  728. DBGINFO(("%s wait_until_sent exit\n", info->device_name));
  729. }
  730. static unsigned int write_room(struct tty_struct *tty)
  731. {
  732. struct slgt_info *info = tty->driver_data;
  733. unsigned int ret;
  734. if (sanity_check(info, tty->name, "write_room"))
  735. return 0;
  736. ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
  737. DBGINFO(("%s write_room=%u\n", info->device_name, ret));
  738. return ret;
  739. }
  740. static void flush_chars(struct tty_struct *tty)
  741. {
  742. struct slgt_info *info = tty->driver_data;
  743. unsigned long flags;
  744. if (sanity_check(info, tty->name, "flush_chars"))
  745. return;
  746. DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
  747. if (info->tx_count <= 0 || tty->flow.stopped ||
  748. tty->hw_stopped || !info->tx_buf)
  749. return;
  750. DBGINFO(("%s flush_chars start transmit\n", info->device_name));
  751. spin_lock_irqsave(&info->lock,flags);
  752. if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
  753. info->tx_count = 0;
  754. spin_unlock_irqrestore(&info->lock,flags);
  755. }
  756. static void flush_buffer(struct tty_struct *tty)
  757. {
  758. struct slgt_info *info = tty->driver_data;
  759. unsigned long flags;
  760. if (sanity_check(info, tty->name, "flush_buffer"))
  761. return;
  762. DBGINFO(("%s flush_buffer\n", info->device_name));
  763. spin_lock_irqsave(&info->lock, flags);
  764. info->tx_count = 0;
  765. spin_unlock_irqrestore(&info->lock, flags);
  766. tty_wakeup(tty);
  767. }
  768. /*
  769. * throttle (stop) transmitter
  770. */
  771. static void tx_hold(struct tty_struct *tty)
  772. {
  773. struct slgt_info *info = tty->driver_data;
  774. unsigned long flags;
  775. if (sanity_check(info, tty->name, "tx_hold"))
  776. return;
  777. DBGINFO(("%s tx_hold\n", info->device_name));
  778. spin_lock_irqsave(&info->lock,flags);
  779. if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
  780. tx_stop(info);
  781. spin_unlock_irqrestore(&info->lock,flags);
  782. }
  783. /*
  784. * release (start) transmitter
  785. */
  786. static void tx_release(struct tty_struct *tty)
  787. {
  788. struct slgt_info *info = tty->driver_data;
  789. unsigned long flags;
  790. if (sanity_check(info, tty->name, "tx_release"))
  791. return;
  792. DBGINFO(("%s tx_release\n", info->device_name));
  793. spin_lock_irqsave(&info->lock, flags);
  794. if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
  795. info->tx_count = 0;
  796. spin_unlock_irqrestore(&info->lock, flags);
  797. }
  798. /*
  799. * Service an IOCTL request
  800. *
  801. * Arguments
  802. *
  803. * tty pointer to tty instance data
  804. * cmd IOCTL command code
  805. * arg command argument/context
  806. *
  807. * Return 0 if success, otherwise error code
  808. */
  809. static int ioctl(struct tty_struct *tty,
  810. unsigned int cmd, unsigned long arg)
  811. {
  812. struct slgt_info *info = tty->driver_data;
  813. void __user *argp = (void __user *)arg;
  814. int ret;
  815. if (sanity_check(info, tty->name, "ioctl"))
  816. return -ENODEV;
  817. DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
  818. if (cmd != TIOCMIWAIT) {
  819. if (tty_io_error(tty))
  820. return -EIO;
  821. }
  822. switch (cmd) {
  823. case MGSL_IOCWAITEVENT:
  824. return wait_mgsl_event(info, argp);
  825. case TIOCMIWAIT:
  826. return modem_input_wait(info,(int)arg);
  827. case MGSL_IOCSGPIO:
  828. return set_gpio(info, argp);
  829. case MGSL_IOCGGPIO:
  830. return get_gpio(info, argp);
  831. case MGSL_IOCWAITGPIO:
  832. return wait_gpio(info, argp);
  833. case MGSL_IOCGXSYNC:
  834. return get_xsync(info, argp);
  835. case MGSL_IOCSXSYNC:
  836. return set_xsync(info, (int)arg);
  837. case MGSL_IOCGXCTRL:
  838. return get_xctrl(info, argp);
  839. case MGSL_IOCSXCTRL:
  840. return set_xctrl(info, (int)arg);
  841. }
  842. mutex_lock(&info->port.mutex);
  843. switch (cmd) {
  844. case MGSL_IOCGPARAMS:
  845. ret = get_params(info, argp);
  846. break;
  847. case MGSL_IOCSPARAMS:
  848. ret = set_params(info, argp);
  849. break;
  850. case MGSL_IOCGTXIDLE:
  851. ret = get_txidle(info, argp);
  852. break;
  853. case MGSL_IOCSTXIDLE:
  854. ret = set_txidle(info, (int)arg);
  855. break;
  856. case MGSL_IOCTXENABLE:
  857. ret = tx_enable(info, (int)arg);
  858. break;
  859. case MGSL_IOCRXENABLE:
  860. ret = rx_enable(info, (int)arg);
  861. break;
  862. case MGSL_IOCTXABORT:
  863. ret = tx_abort(info);
  864. break;
  865. case MGSL_IOCGSTATS:
  866. ret = get_stats(info, argp);
  867. break;
  868. case MGSL_IOCGIF:
  869. ret = get_interface(info, argp);
  870. break;
  871. case MGSL_IOCSIF:
  872. ret = set_interface(info,(int)arg);
  873. break;
  874. default:
  875. ret = -ENOIOCTLCMD;
  876. }
  877. mutex_unlock(&info->port.mutex);
  878. return ret;
  879. }
  880. static int get_icount(struct tty_struct *tty,
  881. struct serial_icounter_struct *icount)
  882. {
  883. struct slgt_info *info = tty->driver_data;
  884. struct mgsl_icount cnow; /* kernel counter temps */
  885. unsigned long flags;
  886. spin_lock_irqsave(&info->lock,flags);
  887. cnow = info->icount;
  888. spin_unlock_irqrestore(&info->lock,flags);
  889. icount->cts = cnow.cts;
  890. icount->dsr = cnow.dsr;
  891. icount->rng = cnow.rng;
  892. icount->dcd = cnow.dcd;
  893. icount->rx = cnow.rx;
  894. icount->tx = cnow.tx;
  895. icount->frame = cnow.frame;
  896. icount->overrun = cnow.overrun;
  897. icount->parity = cnow.parity;
  898. icount->brk = cnow.brk;
  899. icount->buf_overrun = cnow.buf_overrun;
  900. return 0;
  901. }
  902. /*
  903. * support for 32 bit ioctl calls on 64 bit systems
  904. */
  905. #ifdef CONFIG_COMPAT
  906. static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
  907. {
  908. struct MGSL_PARAMS32 tmp_params;
  909. DBGINFO(("%s get_params32\n", info->device_name));
  910. memset(&tmp_params, 0, sizeof(tmp_params));
  911. tmp_params.mode = (compat_ulong_t)info->params.mode;
  912. tmp_params.loopback = info->params.loopback;
  913. tmp_params.flags = info->params.flags;
  914. tmp_params.encoding = info->params.encoding;
  915. tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed;
  916. tmp_params.addr_filter = info->params.addr_filter;
  917. tmp_params.crc_type = info->params.crc_type;
  918. tmp_params.preamble_length = info->params.preamble_length;
  919. tmp_params.preamble = info->params.preamble;
  920. tmp_params.data_rate = (compat_ulong_t)info->params.data_rate;
  921. tmp_params.data_bits = info->params.data_bits;
  922. tmp_params.stop_bits = info->params.stop_bits;
  923. tmp_params.parity = info->params.parity;
  924. if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
  925. return -EFAULT;
  926. return 0;
  927. }
  928. static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
  929. {
  930. struct MGSL_PARAMS32 tmp_params;
  931. DBGINFO(("%s set_params32\n", info->device_name));
  932. if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
  933. return -EFAULT;
  934. spin_lock(&info->lock);
  935. if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
  936. info->base_clock = tmp_params.clock_speed;
  937. } else {
  938. info->params.mode = tmp_params.mode;
  939. info->params.loopback = tmp_params.loopback;
  940. info->params.flags = tmp_params.flags;
  941. info->params.encoding = tmp_params.encoding;
  942. info->params.clock_speed = tmp_params.clock_speed;
  943. info->params.addr_filter = tmp_params.addr_filter;
  944. info->params.crc_type = tmp_params.crc_type;
  945. info->params.preamble_length = tmp_params.preamble_length;
  946. info->params.preamble = tmp_params.preamble;
  947. info->params.data_rate = tmp_params.data_rate;
  948. info->params.data_bits = tmp_params.data_bits;
  949. info->params.stop_bits = tmp_params.stop_bits;
  950. info->params.parity = tmp_params.parity;
  951. }
  952. spin_unlock(&info->lock);
  953. program_hw(info);
  954. return 0;
  955. }
  956. static long slgt_compat_ioctl(struct tty_struct *tty,
  957. unsigned int cmd, unsigned long arg)
  958. {
  959. struct slgt_info *info = tty->driver_data;
  960. int rc;
  961. if (sanity_check(info, tty->name, "compat_ioctl"))
  962. return -ENODEV;
  963. DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
  964. switch (cmd) {
  965. case MGSL_IOCSPARAMS32:
  966. rc = set_params32(info, compat_ptr(arg));
  967. break;
  968. case MGSL_IOCGPARAMS32:
  969. rc = get_params32(info, compat_ptr(arg));
  970. break;
  971. case MGSL_IOCGPARAMS:
  972. case MGSL_IOCSPARAMS:
  973. case MGSL_IOCGTXIDLE:
  974. case MGSL_IOCGSTATS:
  975. case MGSL_IOCWAITEVENT:
  976. case MGSL_IOCGIF:
  977. case MGSL_IOCSGPIO:
  978. case MGSL_IOCGGPIO:
  979. case MGSL_IOCWAITGPIO:
  980. case MGSL_IOCGXSYNC:
  981. case MGSL_IOCGXCTRL:
  982. rc = ioctl(tty, cmd, (unsigned long)compat_ptr(arg));
  983. break;
  984. default:
  985. rc = ioctl(tty, cmd, arg);
  986. }
  987. DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
  988. return rc;
  989. }
  990. #else
  991. #define slgt_compat_ioctl NULL
  992. #endif /* ifdef CONFIG_COMPAT */
  993. /*
  994. * proc fs support
  995. */
  996. static inline void line_info(struct seq_file *m, struct slgt_info *info)
  997. {
  998. char stat_buf[30];
  999. unsigned long flags;
  1000. seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
  1001. info->device_name, info->phys_reg_addr,
  1002. info->irq_level, info->max_frame_size);
  1003. /* output current serial signal states */
  1004. spin_lock_irqsave(&info->lock,flags);
  1005. get_gtsignals(info);
  1006. spin_unlock_irqrestore(&info->lock,flags);
  1007. stat_buf[0] = 0;
  1008. stat_buf[1] = 0;
  1009. if (info->signals & SerialSignal_RTS)
  1010. strcat(stat_buf, "|RTS");
  1011. if (info->signals & SerialSignal_CTS)
  1012. strcat(stat_buf, "|CTS");
  1013. if (info->signals & SerialSignal_DTR)
  1014. strcat(stat_buf, "|DTR");
  1015. if (info->signals & SerialSignal_DSR)
  1016. strcat(stat_buf, "|DSR");
  1017. if (info->signals & SerialSignal_DCD)
  1018. strcat(stat_buf, "|CD");
  1019. if (info->signals & SerialSignal_RI)
  1020. strcat(stat_buf, "|RI");
  1021. if (info->params.mode != MGSL_MODE_ASYNC) {
  1022. seq_printf(m, "\tHDLC txok:%d rxok:%d",
  1023. info->icount.txok, info->icount.rxok);
  1024. if (info->icount.txunder)
  1025. seq_printf(m, " txunder:%d", info->icount.txunder);
  1026. if (info->icount.txabort)
  1027. seq_printf(m, " txabort:%d", info->icount.txabort);
  1028. if (info->icount.rxshort)
  1029. seq_printf(m, " rxshort:%d", info->icount.rxshort);
  1030. if (info->icount.rxlong)
  1031. seq_printf(m, " rxlong:%d", info->icount.rxlong);
  1032. if (info->icount.rxover)
  1033. seq_printf(m, " rxover:%d", info->icount.rxover);
  1034. if (info->icount.rxcrc)
  1035. seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
  1036. } else {
  1037. seq_printf(m, "\tASYNC tx:%d rx:%d",
  1038. info->icount.tx, info->icount.rx);
  1039. if (info->icount.frame)
  1040. seq_printf(m, " fe:%d", info->icount.frame);
  1041. if (info->icount.parity)
  1042. seq_printf(m, " pe:%d", info->icount.parity);
  1043. if (info->icount.brk)
  1044. seq_printf(m, " brk:%d", info->icount.brk);
  1045. if (info->icount.overrun)
  1046. seq_printf(m, " oe:%d", info->icount.overrun);
  1047. }
  1048. /* Append serial signal status to end */
  1049. seq_printf(m, " %s\n", stat_buf+1);
  1050. seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
  1051. info->tx_active,info->bh_requested,info->bh_running,
  1052. info->pending_bh);
  1053. }
  1054. /* Called to print information about devices
  1055. */
  1056. static int synclink_gt_proc_show(struct seq_file *m, void *v)
  1057. {
  1058. struct slgt_info *info;
  1059. seq_puts(m, "synclink_gt driver\n");
  1060. info = slgt_device_list;
  1061. while( info ) {
  1062. line_info(m, info);
  1063. info = info->next_device;
  1064. }
  1065. return 0;
  1066. }
  1067. /*
  1068. * return count of bytes in transmit buffer
  1069. */
  1070. static unsigned int chars_in_buffer(struct tty_struct *tty)
  1071. {
  1072. struct slgt_info *info = tty->driver_data;
  1073. unsigned int count;
  1074. if (sanity_check(info, tty->name, "chars_in_buffer"))
  1075. return 0;
  1076. count = tbuf_bytes(info);
  1077. DBGINFO(("%s chars_in_buffer()=%u\n", info->device_name, count));
  1078. return count;
  1079. }
  1080. /*
  1081. * signal remote device to throttle send data (our receive data)
  1082. */
  1083. static void throttle(struct tty_struct * tty)
  1084. {
  1085. struct slgt_info *info = tty->driver_data;
  1086. unsigned long flags;
  1087. if (sanity_check(info, tty->name, "throttle"))
  1088. return;
  1089. DBGINFO(("%s throttle\n", info->device_name));
  1090. if (I_IXOFF(tty))
  1091. send_xchar(tty, STOP_CHAR(tty));
  1092. if (C_CRTSCTS(tty)) {
  1093. spin_lock_irqsave(&info->lock,flags);
  1094. info->signals &= ~SerialSignal_RTS;
  1095. set_gtsignals(info);
  1096. spin_unlock_irqrestore(&info->lock,flags);
  1097. }
  1098. }
  1099. /*
  1100. * signal remote device to stop throttling send data (our receive data)
  1101. */
  1102. static void unthrottle(struct tty_struct * tty)
  1103. {
  1104. struct slgt_info *info = tty->driver_data;
  1105. unsigned long flags;
  1106. if (sanity_check(info, tty->name, "unthrottle"))
  1107. return;
  1108. DBGINFO(("%s unthrottle\n", info->device_name));
  1109. if (I_IXOFF(tty)) {
  1110. if (info->x_char)
  1111. info->x_char = 0;
  1112. else
  1113. send_xchar(tty, START_CHAR(tty));
  1114. }
  1115. if (C_CRTSCTS(tty)) {
  1116. spin_lock_irqsave(&info->lock,flags);
  1117. info->signals |= SerialSignal_RTS;
  1118. set_gtsignals(info);
  1119. spin_unlock_irqrestore(&info->lock,flags);
  1120. }
  1121. }
  1122. /*
  1123. * set or clear transmit break condition
  1124. * break_state -1=set break condition, 0=clear
  1125. */
  1126. static int set_break(struct tty_struct *tty, int break_state)
  1127. {
  1128. struct slgt_info *info = tty->driver_data;
  1129. unsigned short value;
  1130. unsigned long flags;
  1131. if (sanity_check(info, tty->name, "set_break"))
  1132. return -EINVAL;
  1133. DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
  1134. spin_lock_irqsave(&info->lock,flags);
  1135. value = rd_reg16(info, TCR);
  1136. if (break_state == -1)
  1137. value |= BIT6;
  1138. else
  1139. value &= ~BIT6;
  1140. wr_reg16(info, TCR, value);
  1141. spin_unlock_irqrestore(&info->lock,flags);
  1142. return 0;
  1143. }
  1144. #if SYNCLINK_GENERIC_HDLC
  1145. /**
  1146. * hdlcdev_attach - called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
  1147. * @dev: pointer to network device structure
  1148. * @encoding: serial encoding setting
  1149. * @parity: FCS setting
  1150. *
  1151. * Set encoding and frame check sequence (FCS) options.
  1152. *
  1153. * Return: 0 if success, otherwise error code
  1154. */
  1155. static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
  1156. unsigned short parity)
  1157. {
  1158. struct slgt_info *info = dev_to_port(dev);
  1159. unsigned char new_encoding;
  1160. unsigned short new_crctype;
  1161. /* return error if TTY interface open */
  1162. if (info->port.count)
  1163. return -EBUSY;
  1164. DBGINFO(("%s hdlcdev_attach\n", info->device_name));
  1165. switch (encoding)
  1166. {
  1167. case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
  1168. case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
  1169. case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
  1170. case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
  1171. case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
  1172. default: return -EINVAL;
  1173. }
  1174. switch (parity)
  1175. {
  1176. case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
  1177. case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
  1178. case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
  1179. default: return -EINVAL;
  1180. }
  1181. info->params.encoding = new_encoding;
  1182. info->params.crc_type = new_crctype;
  1183. /* if network interface up, reprogram hardware */
  1184. if (info->netcount)
  1185. program_hw(info);
  1186. return 0;
  1187. }
  1188. /**
  1189. * hdlcdev_xmit - called by generic HDLC layer to send a frame
  1190. * @skb: socket buffer containing HDLC frame
  1191. * @dev: pointer to network device structure
  1192. */
  1193. static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
  1194. struct net_device *dev)
  1195. {
  1196. struct slgt_info *info = dev_to_port(dev);
  1197. unsigned long flags;
  1198. DBGINFO(("%s hdlc_xmit\n", dev->name));
  1199. if (!skb->len)
  1200. return NETDEV_TX_OK;
  1201. /* stop sending until this frame completes */
  1202. netif_stop_queue(dev);
  1203. /* update network statistics */
  1204. dev->stats.tx_packets++;
  1205. dev->stats.tx_bytes += skb->len;
  1206. /* save start time for transmit timeout detection */
  1207. netif_trans_update(dev);
  1208. spin_lock_irqsave(&info->lock, flags);
  1209. tx_load(info, skb->data, skb->len);
  1210. spin_unlock_irqrestore(&info->lock, flags);
  1211. /* done with socket buffer, so free it */
  1212. dev_kfree_skb(skb);
  1213. return NETDEV_TX_OK;
  1214. }
  1215. /**
  1216. * hdlcdev_open - called by network layer when interface enabled
  1217. * @dev: pointer to network device structure
  1218. *
  1219. * Claim resources and initialize hardware.
  1220. *
  1221. * Return: 0 if success, otherwise error code
  1222. */
  1223. static int hdlcdev_open(struct net_device *dev)
  1224. {
  1225. struct slgt_info *info = dev_to_port(dev);
  1226. int rc;
  1227. unsigned long flags;
  1228. if (!try_module_get(THIS_MODULE))
  1229. return -EBUSY;
  1230. DBGINFO(("%s hdlcdev_open\n", dev->name));
  1231. /* generic HDLC layer open processing */
  1232. rc = hdlc_open(dev);
  1233. if (rc)
  1234. return rc;
  1235. /* arbitrate between network and tty opens */
  1236. spin_lock_irqsave(&info->netlock, flags);
  1237. if (info->port.count != 0 || info->netcount != 0) {
  1238. DBGINFO(("%s hdlc_open busy\n", dev->name));
  1239. spin_unlock_irqrestore(&info->netlock, flags);
  1240. return -EBUSY;
  1241. }
  1242. info->netcount=1;
  1243. spin_unlock_irqrestore(&info->netlock, flags);
  1244. /* claim resources and init adapter */
  1245. if ((rc = startup(info)) != 0) {
  1246. spin_lock_irqsave(&info->netlock, flags);
  1247. info->netcount=0;
  1248. spin_unlock_irqrestore(&info->netlock, flags);
  1249. return rc;
  1250. }
  1251. /* assert RTS and DTR, apply hardware settings */
  1252. info->signals |= SerialSignal_RTS | SerialSignal_DTR;
  1253. program_hw(info);
  1254. /* enable network layer transmit */
  1255. netif_trans_update(dev);
  1256. netif_start_queue(dev);
  1257. /* inform generic HDLC layer of current DCD status */
  1258. spin_lock_irqsave(&info->lock, flags);
  1259. get_gtsignals(info);
  1260. spin_unlock_irqrestore(&info->lock, flags);
  1261. if (info->signals & SerialSignal_DCD)
  1262. netif_carrier_on(dev);
  1263. else
  1264. netif_carrier_off(dev);
  1265. return 0;
  1266. }
  1267. /**
  1268. * hdlcdev_close - called by network layer when interface is disabled
  1269. * @dev: pointer to network device structure
  1270. *
  1271. * Shutdown hardware and release resources.
  1272. *
  1273. * Return: 0 if success, otherwise error code
  1274. */
  1275. static int hdlcdev_close(struct net_device *dev)
  1276. {
  1277. struct slgt_info *info = dev_to_port(dev);
  1278. unsigned long flags;
  1279. DBGINFO(("%s hdlcdev_close\n", dev->name));
  1280. netif_stop_queue(dev);
  1281. /* shutdown adapter and release resources */
  1282. shutdown(info);
  1283. hdlc_close(dev);
  1284. spin_lock_irqsave(&info->netlock, flags);
  1285. info->netcount=0;
  1286. spin_unlock_irqrestore(&info->netlock, flags);
  1287. module_put(THIS_MODULE);
  1288. return 0;
  1289. }
  1290. /**
  1291. * hdlcdev_ioctl - called by network layer to process IOCTL call to network device
  1292. * @dev: pointer to network device structure
  1293. * @ifr: pointer to network interface request structure
  1294. * @cmd: IOCTL command code
  1295. *
  1296. * Return: 0 if success, otherwise error code
  1297. */
  1298. static int hdlcdev_ioctl(struct net_device *dev, struct if_settings *ifs)
  1299. {
  1300. const size_t size = sizeof(sync_serial_settings);
  1301. sync_serial_settings new_line;
  1302. sync_serial_settings __user *line = ifs->ifs_ifsu.sync;
  1303. struct slgt_info *info = dev_to_port(dev);
  1304. unsigned int flags;
  1305. DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
  1306. /* return error if TTY interface open */
  1307. if (info->port.count)
  1308. return -EBUSY;
  1309. memset(&new_line, 0, sizeof(new_line));
  1310. switch (ifs->type) {
  1311. case IF_GET_IFACE: /* return current sync_serial_settings */
  1312. ifs->type = IF_IFACE_SYNC_SERIAL;
  1313. if (ifs->size < size) {
  1314. ifs->size = size; /* data size wanted */
  1315. return -ENOBUFS;
  1316. }
  1317. flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  1318. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  1319. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  1320. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
  1321. switch (flags){
  1322. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
  1323. case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
  1324. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
  1325. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
  1326. default: new_line.clock_type = CLOCK_DEFAULT;
  1327. }
  1328. new_line.clock_rate = info->params.clock_speed;
  1329. new_line.loopback = info->params.loopback ? 1:0;
  1330. if (copy_to_user(line, &new_line, size))
  1331. return -EFAULT;
  1332. return 0;
  1333. case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
  1334. if(!capable(CAP_NET_ADMIN))
  1335. return -EPERM;
  1336. if (copy_from_user(&new_line, line, size))
  1337. return -EFAULT;
  1338. switch (new_line.clock_type)
  1339. {
  1340. case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
  1341. case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
  1342. case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
  1343. case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
  1344. case CLOCK_DEFAULT: flags = info->params.flags &
  1345. (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  1346. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  1347. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  1348. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
  1349. default: return -EINVAL;
  1350. }
  1351. if (new_line.loopback != 0 && new_line.loopback != 1)
  1352. return -EINVAL;
  1353. info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  1354. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  1355. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  1356. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
  1357. info->params.flags |= flags;
  1358. info->params.loopback = new_line.loopback;
  1359. if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
  1360. info->params.clock_speed = new_line.clock_rate;
  1361. else
  1362. info->params.clock_speed = 0;
  1363. /* if network interface up, reprogram hardware */
  1364. if (info->netcount)
  1365. program_hw(info);
  1366. return 0;
  1367. default:
  1368. return hdlc_ioctl(dev, ifs);
  1369. }
  1370. }
  1371. /**
  1372. * hdlcdev_tx_timeout - called by network layer when transmit timeout is detected
  1373. * @dev: pointer to network device structure
  1374. * @txqueue: unused
  1375. */
  1376. static void hdlcdev_tx_timeout(struct net_device *dev, unsigned int txqueue)
  1377. {
  1378. struct slgt_info *info = dev_to_port(dev);
  1379. unsigned long flags;
  1380. DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
  1381. dev->stats.tx_errors++;
  1382. dev->stats.tx_aborted_errors++;
  1383. spin_lock_irqsave(&info->lock,flags);
  1384. tx_stop(info);
  1385. spin_unlock_irqrestore(&info->lock,flags);
  1386. netif_wake_queue(dev);
  1387. }
  1388. /**
  1389. * hdlcdev_tx_done - called by device driver when transmit completes
  1390. * @info: pointer to device instance information
  1391. *
  1392. * Reenable network layer transmit if stopped.
  1393. */
  1394. static void hdlcdev_tx_done(struct slgt_info *info)
  1395. {
  1396. if (netif_queue_stopped(info->netdev))
  1397. netif_wake_queue(info->netdev);
  1398. }
  1399. /**
  1400. * hdlcdev_rx - called by device driver when frame received
  1401. * @info: pointer to device instance information
  1402. * @buf: pointer to buffer contianing frame data
  1403. * @size: count of data bytes in buf
  1404. *
  1405. * Pass frame to network layer.
  1406. */
  1407. static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
  1408. {
  1409. struct sk_buff *skb = dev_alloc_skb(size);
  1410. struct net_device *dev = info->netdev;
  1411. DBGINFO(("%s hdlcdev_rx\n", dev->name));
  1412. if (skb == NULL) {
  1413. DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
  1414. dev->stats.rx_dropped++;
  1415. return;
  1416. }
  1417. skb_put_data(skb, buf, size);
  1418. skb->protocol = hdlc_type_trans(skb, dev);
  1419. dev->stats.rx_packets++;
  1420. dev->stats.rx_bytes += size;
  1421. netif_rx(skb);
  1422. }
  1423. static const struct net_device_ops hdlcdev_ops = {
  1424. .ndo_open = hdlcdev_open,
  1425. .ndo_stop = hdlcdev_close,
  1426. .ndo_start_xmit = hdlc_start_xmit,
  1427. .ndo_siocwandev = hdlcdev_ioctl,
  1428. .ndo_tx_timeout = hdlcdev_tx_timeout,
  1429. };
  1430. /**
  1431. * hdlcdev_init - called by device driver when adding device instance
  1432. * @info: pointer to device instance information
  1433. *
  1434. * Do generic HDLC initialization.
  1435. *
  1436. * Return: 0 if success, otherwise error code
  1437. */
  1438. static int hdlcdev_init(struct slgt_info *info)
  1439. {
  1440. int rc;
  1441. struct net_device *dev;
  1442. hdlc_device *hdlc;
  1443. /* allocate and initialize network and HDLC layer objects */
  1444. dev = alloc_hdlcdev(info);
  1445. if (!dev) {
  1446. printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
  1447. return -ENOMEM;
  1448. }
  1449. /* for network layer reporting purposes only */
  1450. dev->mem_start = info->phys_reg_addr;
  1451. dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
  1452. dev->irq = info->irq_level;
  1453. /* network layer callbacks and settings */
  1454. dev->netdev_ops = &hdlcdev_ops;
  1455. dev->watchdog_timeo = 10 * HZ;
  1456. dev->tx_queue_len = 50;
  1457. /* generic HDLC layer callbacks and settings */
  1458. hdlc = dev_to_hdlc(dev);
  1459. hdlc->attach = hdlcdev_attach;
  1460. hdlc->xmit = hdlcdev_xmit;
  1461. /* register objects with HDLC layer */
  1462. rc = register_hdlc_device(dev);
  1463. if (rc) {
  1464. printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
  1465. free_netdev(dev);
  1466. return rc;
  1467. }
  1468. info->netdev = dev;
  1469. return 0;
  1470. }
  1471. /**
  1472. * hdlcdev_exit - called by device driver when removing device instance
  1473. * @info: pointer to device instance information
  1474. *
  1475. * Do generic HDLC cleanup.
  1476. */
  1477. static void hdlcdev_exit(struct slgt_info *info)
  1478. {
  1479. if (!info->netdev)
  1480. return;
  1481. unregister_hdlc_device(info->netdev);
  1482. free_netdev(info->netdev);
  1483. info->netdev = NULL;
  1484. }
  1485. #endif /* ifdef CONFIG_HDLC */
  1486. /*
  1487. * get async data from rx DMA buffers
  1488. */
  1489. static void rx_async(struct slgt_info *info)
  1490. {
  1491. struct mgsl_icount *icount = &info->icount;
  1492. unsigned int start, end;
  1493. unsigned char *p;
  1494. unsigned char status;
  1495. struct slgt_desc *bufs = info->rbufs;
  1496. int i, count;
  1497. int chars = 0;
  1498. int stat;
  1499. unsigned char ch;
  1500. start = end = info->rbuf_current;
  1501. while(desc_complete(bufs[end])) {
  1502. count = desc_count(bufs[end]) - info->rbuf_index;
  1503. p = bufs[end].buf + info->rbuf_index;
  1504. DBGISR(("%s rx_async count=%d\n", info->device_name, count));
  1505. DBGDATA(info, p, count, "rx");
  1506. for(i=0 ; i < count; i+=2, p+=2) {
  1507. ch = *p;
  1508. icount->rx++;
  1509. stat = 0;
  1510. status = *(p + 1) & (BIT1 + BIT0);
  1511. if (status) {
  1512. if (status & BIT1)
  1513. icount->parity++;
  1514. else if (status & BIT0)
  1515. icount->frame++;
  1516. /* discard char if tty control flags say so */
  1517. if (status & info->ignore_status_mask)
  1518. continue;
  1519. if (status & BIT1)
  1520. stat = TTY_PARITY;
  1521. else if (status & BIT0)
  1522. stat = TTY_FRAME;
  1523. }
  1524. tty_insert_flip_char(&info->port, ch, stat);
  1525. chars++;
  1526. }
  1527. if (i < count) {
  1528. /* receive buffer not completed */
  1529. info->rbuf_index += i;
  1530. mod_timer(&info->rx_timer, jiffies + 1);
  1531. break;
  1532. }
  1533. info->rbuf_index = 0;
  1534. free_rbufs(info, end, end);
  1535. if (++end == info->rbuf_count)
  1536. end = 0;
  1537. /* if entire list searched then no frame available */
  1538. if (end == start)
  1539. break;
  1540. }
  1541. if (chars)
  1542. tty_flip_buffer_push(&info->port);
  1543. }
  1544. /*
  1545. * return next bottom half action to perform
  1546. */
  1547. static int bh_action(struct slgt_info *info)
  1548. {
  1549. unsigned long flags;
  1550. int rc;
  1551. spin_lock_irqsave(&info->lock,flags);
  1552. if (info->pending_bh & BH_RECEIVE) {
  1553. info->pending_bh &= ~BH_RECEIVE;
  1554. rc = BH_RECEIVE;
  1555. } else if (info->pending_bh & BH_TRANSMIT) {
  1556. info->pending_bh &= ~BH_TRANSMIT;
  1557. rc = BH_TRANSMIT;
  1558. } else if (info->pending_bh & BH_STATUS) {
  1559. info->pending_bh &= ~BH_STATUS;
  1560. rc = BH_STATUS;
  1561. } else {
  1562. /* Mark BH routine as complete */
  1563. info->bh_running = false;
  1564. info->bh_requested = false;
  1565. rc = 0;
  1566. }
  1567. spin_unlock_irqrestore(&info->lock,flags);
  1568. return rc;
  1569. }
  1570. /*
  1571. * perform bottom half processing
  1572. */
  1573. static void bh_handler(struct work_struct *work)
  1574. {
  1575. struct slgt_info *info = container_of(work, struct slgt_info, task);
  1576. int action;
  1577. info->bh_running = true;
  1578. while((action = bh_action(info))) {
  1579. switch (action) {
  1580. case BH_RECEIVE:
  1581. DBGBH(("%s bh receive\n", info->device_name));
  1582. switch(info->params.mode) {
  1583. case MGSL_MODE_ASYNC:
  1584. rx_async(info);
  1585. break;
  1586. case MGSL_MODE_HDLC:
  1587. while(rx_get_frame(info));
  1588. break;
  1589. case MGSL_MODE_RAW:
  1590. case MGSL_MODE_MONOSYNC:
  1591. case MGSL_MODE_BISYNC:
  1592. case MGSL_MODE_XSYNC:
  1593. while(rx_get_buf(info));
  1594. break;
  1595. }
  1596. /* restart receiver if rx DMA buffers exhausted */
  1597. if (info->rx_restart)
  1598. rx_start(info);
  1599. break;
  1600. case BH_TRANSMIT:
  1601. bh_transmit(info);
  1602. break;
  1603. case BH_STATUS:
  1604. DBGBH(("%s bh status\n", info->device_name));
  1605. info->ri_chkcount = 0;
  1606. info->dsr_chkcount = 0;
  1607. info->dcd_chkcount = 0;
  1608. info->cts_chkcount = 0;
  1609. break;
  1610. default:
  1611. DBGBH(("%s unknown action\n", info->device_name));
  1612. break;
  1613. }
  1614. }
  1615. DBGBH(("%s bh_handler exit\n", info->device_name));
  1616. }
  1617. static void bh_transmit(struct slgt_info *info)
  1618. {
  1619. struct tty_struct *tty = info->port.tty;
  1620. DBGBH(("%s bh_transmit\n", info->device_name));
  1621. if (tty)
  1622. tty_wakeup(tty);
  1623. }
  1624. static void dsr_change(struct slgt_info *info, unsigned short status)
  1625. {
  1626. if (status & BIT3) {
  1627. info->signals |= SerialSignal_DSR;
  1628. info->input_signal_events.dsr_up++;
  1629. } else {
  1630. info->signals &= ~SerialSignal_DSR;
  1631. info->input_signal_events.dsr_down++;
  1632. }
  1633. DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
  1634. if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
  1635. slgt_irq_off(info, IRQ_DSR);
  1636. return;
  1637. }
  1638. info->icount.dsr++;
  1639. wake_up_interruptible(&info->status_event_wait_q);
  1640. wake_up_interruptible(&info->event_wait_q);
  1641. info->pending_bh |= BH_STATUS;
  1642. }
  1643. static void cts_change(struct slgt_info *info, unsigned short status)
  1644. {
  1645. if (status & BIT2) {
  1646. info->signals |= SerialSignal_CTS;
  1647. info->input_signal_events.cts_up++;
  1648. } else {
  1649. info->signals &= ~SerialSignal_CTS;
  1650. info->input_signal_events.cts_down++;
  1651. }
  1652. DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
  1653. if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
  1654. slgt_irq_off(info, IRQ_CTS);
  1655. return;
  1656. }
  1657. info->icount.cts++;
  1658. wake_up_interruptible(&info->status_event_wait_q);
  1659. wake_up_interruptible(&info->event_wait_q);
  1660. info->pending_bh |= BH_STATUS;
  1661. if (tty_port_cts_enabled(&info->port)) {
  1662. if (info->port.tty) {
  1663. if (info->port.tty->hw_stopped) {
  1664. if (info->signals & SerialSignal_CTS) {
  1665. info->port.tty->hw_stopped = 0;
  1666. info->pending_bh |= BH_TRANSMIT;
  1667. return;
  1668. }
  1669. } else {
  1670. if (!(info->signals & SerialSignal_CTS))
  1671. info->port.tty->hw_stopped = 1;
  1672. }
  1673. }
  1674. }
  1675. }
  1676. static void dcd_change(struct slgt_info *info, unsigned short status)
  1677. {
  1678. if (status & BIT1) {
  1679. info->signals |= SerialSignal_DCD;
  1680. info->input_signal_events.dcd_up++;
  1681. } else {
  1682. info->signals &= ~SerialSignal_DCD;
  1683. info->input_signal_events.dcd_down++;
  1684. }
  1685. DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
  1686. if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
  1687. slgt_irq_off(info, IRQ_DCD);
  1688. return;
  1689. }
  1690. info->icount.dcd++;
  1691. #if SYNCLINK_GENERIC_HDLC
  1692. if (info->netcount) {
  1693. if (info->signals & SerialSignal_DCD)
  1694. netif_carrier_on(info->netdev);
  1695. else
  1696. netif_carrier_off(info->netdev);
  1697. }
  1698. #endif
  1699. wake_up_interruptible(&info->status_event_wait_q);
  1700. wake_up_interruptible(&info->event_wait_q);
  1701. info->pending_bh |= BH_STATUS;
  1702. if (tty_port_check_carrier(&info->port)) {
  1703. if (info->signals & SerialSignal_DCD)
  1704. wake_up_interruptible(&info->port.open_wait);
  1705. else {
  1706. if (info->port.tty)
  1707. tty_hangup(info->port.tty);
  1708. }
  1709. }
  1710. }
  1711. static void ri_change(struct slgt_info *info, unsigned short status)
  1712. {
  1713. if (status & BIT0) {
  1714. info->signals |= SerialSignal_RI;
  1715. info->input_signal_events.ri_up++;
  1716. } else {
  1717. info->signals &= ~SerialSignal_RI;
  1718. info->input_signal_events.ri_down++;
  1719. }
  1720. DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
  1721. if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
  1722. slgt_irq_off(info, IRQ_RI);
  1723. return;
  1724. }
  1725. info->icount.rng++;
  1726. wake_up_interruptible(&info->status_event_wait_q);
  1727. wake_up_interruptible(&info->event_wait_q);
  1728. info->pending_bh |= BH_STATUS;
  1729. }
  1730. static void isr_rxdata(struct slgt_info *info)
  1731. {
  1732. unsigned int count = info->rbuf_fill_count;
  1733. unsigned int i = info->rbuf_fill_index;
  1734. unsigned short reg;
  1735. while (rd_reg16(info, SSR) & IRQ_RXDATA) {
  1736. reg = rd_reg16(info, RDR);
  1737. DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
  1738. if (desc_complete(info->rbufs[i])) {
  1739. /* all buffers full */
  1740. rx_stop(info);
  1741. info->rx_restart = true;
  1742. continue;
  1743. }
  1744. info->rbufs[i].buf[count++] = (unsigned char)reg;
  1745. /* async mode saves status byte to buffer for each data byte */
  1746. if (info->params.mode == MGSL_MODE_ASYNC)
  1747. info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
  1748. if (count == info->rbuf_fill_level || (reg & BIT10)) {
  1749. /* buffer full or end of frame */
  1750. set_desc_count(info->rbufs[i], count);
  1751. set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
  1752. info->rbuf_fill_count = count = 0;
  1753. if (++i == info->rbuf_count)
  1754. i = 0;
  1755. info->pending_bh |= BH_RECEIVE;
  1756. }
  1757. }
  1758. info->rbuf_fill_index = i;
  1759. info->rbuf_fill_count = count;
  1760. }
  1761. static void isr_serial(struct slgt_info *info)
  1762. {
  1763. unsigned short status = rd_reg16(info, SSR);
  1764. DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
  1765. wr_reg16(info, SSR, status); /* clear pending */
  1766. info->irq_occurred = true;
  1767. if (info->params.mode == MGSL_MODE_ASYNC) {
  1768. if (status & IRQ_TXIDLE) {
  1769. if (info->tx_active)
  1770. isr_txeom(info, status);
  1771. }
  1772. if (info->rx_pio && (status & IRQ_RXDATA))
  1773. isr_rxdata(info);
  1774. if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
  1775. info->icount.brk++;
  1776. /* process break detection if tty control allows */
  1777. if (info->port.tty) {
  1778. if (!(status & info->ignore_status_mask)) {
  1779. if (info->read_status_mask & MASK_BREAK) {
  1780. tty_insert_flip_char(&info->port, 0, TTY_BREAK);
  1781. if (info->port.flags & ASYNC_SAK)
  1782. do_SAK(info->port.tty);
  1783. }
  1784. }
  1785. }
  1786. }
  1787. } else {
  1788. if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
  1789. isr_txeom(info, status);
  1790. if (info->rx_pio && (status & IRQ_RXDATA))
  1791. isr_rxdata(info);
  1792. if (status & IRQ_RXIDLE) {
  1793. if (status & RXIDLE)
  1794. info->icount.rxidle++;
  1795. else
  1796. info->icount.exithunt++;
  1797. wake_up_interruptible(&info->event_wait_q);
  1798. }
  1799. if (status & IRQ_RXOVER)
  1800. rx_start(info);
  1801. }
  1802. if (status & IRQ_DSR)
  1803. dsr_change(info, status);
  1804. if (status & IRQ_CTS)
  1805. cts_change(info, status);
  1806. if (status & IRQ_DCD)
  1807. dcd_change(info, status);
  1808. if (status & IRQ_RI)
  1809. ri_change(info, status);
  1810. }
  1811. static void isr_rdma(struct slgt_info *info)
  1812. {
  1813. unsigned int status = rd_reg32(info, RDCSR);
  1814. DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
  1815. /* RDCSR (rx DMA control/status)
  1816. *
  1817. * 31..07 reserved
  1818. * 06 save status byte to DMA buffer
  1819. * 05 error
  1820. * 04 eol (end of list)
  1821. * 03 eob (end of buffer)
  1822. * 02 IRQ enable
  1823. * 01 reset
  1824. * 00 enable
  1825. */
  1826. wr_reg32(info, RDCSR, status); /* clear pending */
  1827. if (status & (BIT5 + BIT4)) {
  1828. DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
  1829. info->rx_restart = true;
  1830. }
  1831. info->pending_bh |= BH_RECEIVE;
  1832. }
  1833. static void isr_tdma(struct slgt_info *info)
  1834. {
  1835. unsigned int status = rd_reg32(info, TDCSR);
  1836. DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
  1837. /* TDCSR (tx DMA control/status)
  1838. *
  1839. * 31..06 reserved
  1840. * 05 error
  1841. * 04 eol (end of list)
  1842. * 03 eob (end of buffer)
  1843. * 02 IRQ enable
  1844. * 01 reset
  1845. * 00 enable
  1846. */
  1847. wr_reg32(info, TDCSR, status); /* clear pending */
  1848. if (status & (BIT5 + BIT4 + BIT3)) {
  1849. // another transmit buffer has completed
  1850. // run bottom half to get more send data from user
  1851. info->pending_bh |= BH_TRANSMIT;
  1852. }
  1853. }
  1854. /*
  1855. * return true if there are unsent tx DMA buffers, otherwise false
  1856. *
  1857. * if there are unsent buffers then info->tbuf_start
  1858. * is set to index of first unsent buffer
  1859. */
  1860. static bool unsent_tbufs(struct slgt_info *info)
  1861. {
  1862. unsigned int i = info->tbuf_current;
  1863. bool rc = false;
  1864. /*
  1865. * search backwards from last loaded buffer (precedes tbuf_current)
  1866. * for first unsent buffer (desc_count > 0)
  1867. */
  1868. do {
  1869. if (i)
  1870. i--;
  1871. else
  1872. i = info->tbuf_count - 1;
  1873. if (!desc_count(info->tbufs[i]))
  1874. break;
  1875. info->tbuf_start = i;
  1876. rc = true;
  1877. } while (i != info->tbuf_current);
  1878. return rc;
  1879. }
  1880. static void isr_txeom(struct slgt_info *info, unsigned short status)
  1881. {
  1882. DBGISR(("%s txeom status=%04x\n", info->device_name, status));
  1883. slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
  1884. tdma_reset(info);
  1885. if (status & IRQ_TXUNDER) {
  1886. unsigned short val = rd_reg16(info, TCR);
  1887. wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
  1888. wr_reg16(info, TCR, val); /* clear reset bit */
  1889. }
  1890. if (info->tx_active) {
  1891. if (info->params.mode != MGSL_MODE_ASYNC) {
  1892. if (status & IRQ_TXUNDER)
  1893. info->icount.txunder++;
  1894. else if (status & IRQ_TXIDLE)
  1895. info->icount.txok++;
  1896. }
  1897. if (unsent_tbufs(info)) {
  1898. tx_start(info);
  1899. update_tx_timer(info);
  1900. return;
  1901. }
  1902. info->tx_active = false;
  1903. del_timer(&info->tx_timer);
  1904. if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
  1905. info->signals &= ~SerialSignal_RTS;
  1906. info->drop_rts_on_tx_done = false;
  1907. set_gtsignals(info);
  1908. }
  1909. #if SYNCLINK_GENERIC_HDLC
  1910. if (info->netcount)
  1911. hdlcdev_tx_done(info);
  1912. else
  1913. #endif
  1914. {
  1915. if (info->port.tty && (info->port.tty->flow.stopped || info->port.tty->hw_stopped)) {
  1916. tx_stop(info);
  1917. return;
  1918. }
  1919. info->pending_bh |= BH_TRANSMIT;
  1920. }
  1921. }
  1922. }
  1923. static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
  1924. {
  1925. struct cond_wait *w, *prev;
  1926. /* wake processes waiting for specific transitions */
  1927. for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
  1928. if (w->data & changed) {
  1929. w->data = state;
  1930. wake_up_interruptible(&w->q);
  1931. if (prev != NULL)
  1932. prev->next = w->next;
  1933. else
  1934. info->gpio_wait_q = w->next;
  1935. } else
  1936. prev = w;
  1937. }
  1938. }
  1939. /* interrupt service routine
  1940. *
  1941. * irq interrupt number
  1942. * dev_id device ID supplied during interrupt registration
  1943. */
  1944. static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
  1945. {
  1946. struct slgt_info *info = dev_id;
  1947. unsigned int gsr;
  1948. unsigned int i;
  1949. DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
  1950. while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
  1951. DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
  1952. info->irq_occurred = true;
  1953. for(i=0; i < info->port_count ; i++) {
  1954. if (info->port_array[i] == NULL)
  1955. continue;
  1956. spin_lock(&info->port_array[i]->lock);
  1957. if (gsr & (BIT8 << i))
  1958. isr_serial(info->port_array[i]);
  1959. if (gsr & (BIT16 << (i*2)))
  1960. isr_rdma(info->port_array[i]);
  1961. if (gsr & (BIT17 << (i*2)))
  1962. isr_tdma(info->port_array[i]);
  1963. spin_unlock(&info->port_array[i]->lock);
  1964. }
  1965. }
  1966. if (info->gpio_present) {
  1967. unsigned int state;
  1968. unsigned int changed;
  1969. spin_lock(&info->lock);
  1970. while ((changed = rd_reg32(info, IOSR)) != 0) {
  1971. DBGISR(("%s iosr=%08x\n", info->device_name, changed));
  1972. /* read latched state of GPIO signals */
  1973. state = rd_reg32(info, IOVR);
  1974. /* clear pending GPIO interrupt bits */
  1975. wr_reg32(info, IOSR, changed);
  1976. for (i=0 ; i < info->port_count ; i++) {
  1977. if (info->port_array[i] != NULL)
  1978. isr_gpio(info->port_array[i], changed, state);
  1979. }
  1980. }
  1981. spin_unlock(&info->lock);
  1982. }
  1983. for(i=0; i < info->port_count ; i++) {
  1984. struct slgt_info *port = info->port_array[i];
  1985. if (port == NULL)
  1986. continue;
  1987. spin_lock(&port->lock);
  1988. if ((port->port.count || port->netcount) &&
  1989. port->pending_bh && !port->bh_running &&
  1990. !port->bh_requested) {
  1991. DBGISR(("%s bh queued\n", port->device_name));
  1992. schedule_work(&port->task);
  1993. port->bh_requested = true;
  1994. }
  1995. spin_unlock(&port->lock);
  1996. }
  1997. DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
  1998. return IRQ_HANDLED;
  1999. }
  2000. static int startup(struct slgt_info *info)
  2001. {
  2002. DBGINFO(("%s startup\n", info->device_name));
  2003. if (tty_port_initialized(&info->port))
  2004. return 0;
  2005. if (!info->tx_buf) {
  2006. info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
  2007. if (!info->tx_buf) {
  2008. DBGERR(("%s can't allocate tx buffer\n", info->device_name));
  2009. return -ENOMEM;
  2010. }
  2011. }
  2012. info->pending_bh = 0;
  2013. memset(&info->icount, 0, sizeof(info->icount));
  2014. /* program hardware for current parameters */
  2015. change_params(info);
  2016. if (info->port.tty)
  2017. clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
  2018. tty_port_set_initialized(&info->port, 1);
  2019. return 0;
  2020. }
  2021. /*
  2022. * called by close() and hangup() to shutdown hardware
  2023. */
  2024. static void shutdown(struct slgt_info *info)
  2025. {
  2026. unsigned long flags;
  2027. if (!tty_port_initialized(&info->port))
  2028. return;
  2029. DBGINFO(("%s shutdown\n", info->device_name));
  2030. /* clear status wait queue because status changes */
  2031. /* can't happen after shutting down the hardware */
  2032. wake_up_interruptible(&info->status_event_wait_q);
  2033. wake_up_interruptible(&info->event_wait_q);
  2034. del_timer_sync(&info->tx_timer);
  2035. del_timer_sync(&info->rx_timer);
  2036. kfree(info->tx_buf);
  2037. info->tx_buf = NULL;
  2038. spin_lock_irqsave(&info->lock,flags);
  2039. tx_stop(info);
  2040. rx_stop(info);
  2041. slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
  2042. if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
  2043. info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
  2044. set_gtsignals(info);
  2045. }
  2046. flush_cond_wait(&info->gpio_wait_q);
  2047. spin_unlock_irqrestore(&info->lock,flags);
  2048. if (info->port.tty)
  2049. set_bit(TTY_IO_ERROR, &info->port.tty->flags);
  2050. tty_port_set_initialized(&info->port, 0);
  2051. }
  2052. static void program_hw(struct slgt_info *info)
  2053. {
  2054. unsigned long flags;
  2055. spin_lock_irqsave(&info->lock,flags);
  2056. rx_stop(info);
  2057. tx_stop(info);
  2058. if (info->params.mode != MGSL_MODE_ASYNC ||
  2059. info->netcount)
  2060. sync_mode(info);
  2061. else
  2062. async_mode(info);
  2063. set_gtsignals(info);
  2064. info->dcd_chkcount = 0;
  2065. info->cts_chkcount = 0;
  2066. info->ri_chkcount = 0;
  2067. info->dsr_chkcount = 0;
  2068. slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
  2069. get_gtsignals(info);
  2070. if (info->netcount ||
  2071. (info->port.tty && info->port.tty->termios.c_cflag & CREAD))
  2072. rx_start(info);
  2073. spin_unlock_irqrestore(&info->lock,flags);
  2074. }
  2075. /*
  2076. * reconfigure adapter based on new parameters
  2077. */
  2078. static void change_params(struct slgt_info *info)
  2079. {
  2080. unsigned cflag;
  2081. int bits_per_char;
  2082. if (!info->port.tty)
  2083. return;
  2084. DBGINFO(("%s change_params\n", info->device_name));
  2085. cflag = info->port.tty->termios.c_cflag;
  2086. /* if B0 rate (hangup) specified then negate RTS and DTR */
  2087. /* otherwise assert RTS and DTR */
  2088. if (cflag & CBAUD)
  2089. info->signals |= SerialSignal_RTS | SerialSignal_DTR;
  2090. else
  2091. info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
  2092. /* byte size and parity */
  2093. info->params.data_bits = tty_get_char_size(cflag);
  2094. info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
  2095. if (cflag & PARENB)
  2096. info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
  2097. else
  2098. info->params.parity = ASYNC_PARITY_NONE;
  2099. /* calculate number of jiffies to transmit a full
  2100. * FIFO (32 bytes) at specified data rate
  2101. */
  2102. bits_per_char = info->params.data_bits +
  2103. info->params.stop_bits + 1;
  2104. info->params.data_rate = tty_get_baud_rate(info->port.tty);
  2105. if (info->params.data_rate) {
  2106. info->timeout = (32*HZ*bits_per_char) /
  2107. info->params.data_rate;
  2108. }
  2109. info->timeout += HZ/50; /* Add .02 seconds of slop */
  2110. tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
  2111. tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
  2112. /* process tty input control flags */
  2113. info->read_status_mask = IRQ_RXOVER;
  2114. if (I_INPCK(info->port.tty))
  2115. info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
  2116. if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
  2117. info->read_status_mask |= MASK_BREAK;
  2118. if (I_IGNPAR(info->port.tty))
  2119. info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
  2120. if (I_IGNBRK(info->port.tty)) {
  2121. info->ignore_status_mask |= MASK_BREAK;
  2122. /* If ignoring parity and break indicators, ignore
  2123. * overruns too. (For real raw support).
  2124. */
  2125. if (I_IGNPAR(info->port.tty))
  2126. info->ignore_status_mask |= MASK_OVERRUN;
  2127. }
  2128. program_hw(info);
  2129. }
  2130. static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
  2131. {
  2132. DBGINFO(("%s get_stats\n", info->device_name));
  2133. if (!user_icount) {
  2134. memset(&info->icount, 0, sizeof(info->icount));
  2135. } else {
  2136. if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
  2137. return -EFAULT;
  2138. }
  2139. return 0;
  2140. }
  2141. static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
  2142. {
  2143. DBGINFO(("%s get_params\n", info->device_name));
  2144. if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
  2145. return -EFAULT;
  2146. return 0;
  2147. }
  2148. static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
  2149. {
  2150. unsigned long flags;
  2151. MGSL_PARAMS tmp_params;
  2152. DBGINFO(("%s set_params\n", info->device_name));
  2153. if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
  2154. return -EFAULT;
  2155. spin_lock_irqsave(&info->lock, flags);
  2156. if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
  2157. info->base_clock = tmp_params.clock_speed;
  2158. else
  2159. memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
  2160. spin_unlock_irqrestore(&info->lock, flags);
  2161. program_hw(info);
  2162. return 0;
  2163. }
  2164. static int get_txidle(struct slgt_info *info, int __user *idle_mode)
  2165. {
  2166. DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
  2167. if (put_user(info->idle_mode, idle_mode))
  2168. return -EFAULT;
  2169. return 0;
  2170. }
  2171. static int set_txidle(struct slgt_info *info, int idle_mode)
  2172. {
  2173. unsigned long flags;
  2174. DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
  2175. spin_lock_irqsave(&info->lock,flags);
  2176. info->idle_mode = idle_mode;
  2177. if (info->params.mode != MGSL_MODE_ASYNC)
  2178. tx_set_idle(info);
  2179. spin_unlock_irqrestore(&info->lock,flags);
  2180. return 0;
  2181. }
  2182. static int tx_enable(struct slgt_info *info, int enable)
  2183. {
  2184. unsigned long flags;
  2185. DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
  2186. spin_lock_irqsave(&info->lock,flags);
  2187. if (enable) {
  2188. if (!info->tx_enabled)
  2189. tx_start(info);
  2190. } else {
  2191. if (info->tx_enabled)
  2192. tx_stop(info);
  2193. }
  2194. spin_unlock_irqrestore(&info->lock,flags);
  2195. return 0;
  2196. }
  2197. /*
  2198. * abort transmit HDLC frame
  2199. */
  2200. static int tx_abort(struct slgt_info *info)
  2201. {
  2202. unsigned long flags;
  2203. DBGINFO(("%s tx_abort\n", info->device_name));
  2204. spin_lock_irqsave(&info->lock,flags);
  2205. tdma_reset(info);
  2206. spin_unlock_irqrestore(&info->lock,flags);
  2207. return 0;
  2208. }
  2209. static int rx_enable(struct slgt_info *info, int enable)
  2210. {
  2211. unsigned long flags;
  2212. unsigned int rbuf_fill_level;
  2213. DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
  2214. spin_lock_irqsave(&info->lock,flags);
  2215. /*
  2216. * enable[31..16] = receive DMA buffer fill level
  2217. * 0 = noop (leave fill level unchanged)
  2218. * fill level must be multiple of 4 and <= buffer size
  2219. */
  2220. rbuf_fill_level = ((unsigned int)enable) >> 16;
  2221. if (rbuf_fill_level) {
  2222. if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
  2223. spin_unlock_irqrestore(&info->lock, flags);
  2224. return -EINVAL;
  2225. }
  2226. info->rbuf_fill_level = rbuf_fill_level;
  2227. if (rbuf_fill_level < 128)
  2228. info->rx_pio = 1; /* PIO mode */
  2229. else
  2230. info->rx_pio = 0; /* DMA mode */
  2231. rx_stop(info); /* restart receiver to use new fill level */
  2232. }
  2233. /*
  2234. * enable[1..0] = receiver enable command
  2235. * 0 = disable
  2236. * 1 = enable
  2237. * 2 = enable or force hunt mode if already enabled
  2238. */
  2239. enable &= 3;
  2240. if (enable) {
  2241. if (!info->rx_enabled)
  2242. rx_start(info);
  2243. else if (enable == 2) {
  2244. /* force hunt mode (write 1 to RCR[3]) */
  2245. wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
  2246. }
  2247. } else {
  2248. if (info->rx_enabled)
  2249. rx_stop(info);
  2250. }
  2251. spin_unlock_irqrestore(&info->lock,flags);
  2252. return 0;
  2253. }
  2254. /*
  2255. * wait for specified event to occur
  2256. */
  2257. static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
  2258. {
  2259. unsigned long flags;
  2260. int s;
  2261. int rc=0;
  2262. struct mgsl_icount cprev, cnow;
  2263. int events;
  2264. int mask;
  2265. struct _input_signal_events oldsigs, newsigs;
  2266. DECLARE_WAITQUEUE(wait, current);
  2267. if (get_user(mask, mask_ptr))
  2268. return -EFAULT;
  2269. DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
  2270. spin_lock_irqsave(&info->lock,flags);
  2271. /* return immediately if state matches requested events */
  2272. get_gtsignals(info);
  2273. s = info->signals;
  2274. events = mask &
  2275. ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
  2276. ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
  2277. ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
  2278. ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
  2279. if (events) {
  2280. spin_unlock_irqrestore(&info->lock,flags);
  2281. goto exit;
  2282. }
  2283. /* save current irq counts */
  2284. cprev = info->icount;
  2285. oldsigs = info->input_signal_events;
  2286. /* enable hunt and idle irqs if needed */
  2287. if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
  2288. unsigned short val = rd_reg16(info, SCR);
  2289. if (!(val & IRQ_RXIDLE))
  2290. wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
  2291. }
  2292. set_current_state(TASK_INTERRUPTIBLE);
  2293. add_wait_queue(&info->event_wait_q, &wait);
  2294. spin_unlock_irqrestore(&info->lock,flags);
  2295. for(;;) {
  2296. schedule();
  2297. if (signal_pending(current)) {
  2298. rc = -ERESTARTSYS;
  2299. break;
  2300. }
  2301. /* get current irq counts */
  2302. spin_lock_irqsave(&info->lock,flags);
  2303. cnow = info->icount;
  2304. newsigs = info->input_signal_events;
  2305. set_current_state(TASK_INTERRUPTIBLE);
  2306. spin_unlock_irqrestore(&info->lock,flags);
  2307. /* if no change, wait aborted for some reason */
  2308. if (newsigs.dsr_up == oldsigs.dsr_up &&
  2309. newsigs.dsr_down == oldsigs.dsr_down &&
  2310. newsigs.dcd_up == oldsigs.dcd_up &&
  2311. newsigs.dcd_down == oldsigs.dcd_down &&
  2312. newsigs.cts_up == oldsigs.cts_up &&
  2313. newsigs.cts_down == oldsigs.cts_down &&
  2314. newsigs.ri_up == oldsigs.ri_up &&
  2315. newsigs.ri_down == oldsigs.ri_down &&
  2316. cnow.exithunt == cprev.exithunt &&
  2317. cnow.rxidle == cprev.rxidle) {
  2318. rc = -EIO;
  2319. break;
  2320. }
  2321. events = mask &
  2322. ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
  2323. (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
  2324. (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
  2325. (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
  2326. (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
  2327. (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
  2328. (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
  2329. (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
  2330. (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
  2331. (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
  2332. if (events)
  2333. break;
  2334. cprev = cnow;
  2335. oldsigs = newsigs;
  2336. }
  2337. remove_wait_queue(&info->event_wait_q, &wait);
  2338. set_current_state(TASK_RUNNING);
  2339. if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
  2340. spin_lock_irqsave(&info->lock,flags);
  2341. if (!waitqueue_active(&info->event_wait_q)) {
  2342. /* disable enable exit hunt mode/idle rcvd IRQs */
  2343. wr_reg16(info, SCR,
  2344. (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
  2345. }
  2346. spin_unlock_irqrestore(&info->lock,flags);
  2347. }
  2348. exit:
  2349. if (rc == 0)
  2350. rc = put_user(events, mask_ptr);
  2351. return rc;
  2352. }
  2353. static int get_interface(struct slgt_info *info, int __user *if_mode)
  2354. {
  2355. DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
  2356. if (put_user(info->if_mode, if_mode))
  2357. return -EFAULT;
  2358. return 0;
  2359. }
  2360. static int set_interface(struct slgt_info *info, int if_mode)
  2361. {
  2362. unsigned long flags;
  2363. unsigned short val;
  2364. DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
  2365. spin_lock_irqsave(&info->lock,flags);
  2366. info->if_mode = if_mode;
  2367. msc_set_vcr(info);
  2368. /* TCR (tx control) 07 1=RTS driver control */
  2369. val = rd_reg16(info, TCR);
  2370. if (info->if_mode & MGSL_INTERFACE_RTS_EN)
  2371. val |= BIT7;
  2372. else
  2373. val &= ~BIT7;
  2374. wr_reg16(info, TCR, val);
  2375. spin_unlock_irqrestore(&info->lock,flags);
  2376. return 0;
  2377. }
  2378. static int get_xsync(struct slgt_info *info, int __user *xsync)
  2379. {
  2380. DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync));
  2381. if (put_user(info->xsync, xsync))
  2382. return -EFAULT;
  2383. return 0;
  2384. }
  2385. /*
  2386. * set extended sync pattern (1 to 4 bytes) for extended sync mode
  2387. *
  2388. * sync pattern is contained in least significant bytes of value
  2389. * most significant byte of sync pattern is oldest (1st sent/detected)
  2390. */
  2391. static int set_xsync(struct slgt_info *info, int xsync)
  2392. {
  2393. unsigned long flags;
  2394. DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync));
  2395. spin_lock_irqsave(&info->lock, flags);
  2396. info->xsync = xsync;
  2397. wr_reg32(info, XSR, xsync);
  2398. spin_unlock_irqrestore(&info->lock, flags);
  2399. return 0;
  2400. }
  2401. static int get_xctrl(struct slgt_info *info, int __user *xctrl)
  2402. {
  2403. DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl));
  2404. if (put_user(info->xctrl, xctrl))
  2405. return -EFAULT;
  2406. return 0;
  2407. }
  2408. /*
  2409. * set extended control options
  2410. *
  2411. * xctrl[31:19] reserved, must be zero
  2412. * xctrl[18:17] extended sync pattern length in bytes
  2413. * 00 = 1 byte in xsr[7:0]
  2414. * 01 = 2 bytes in xsr[15:0]
  2415. * 10 = 3 bytes in xsr[23:0]
  2416. * 11 = 4 bytes in xsr[31:0]
  2417. * xctrl[16] 1 = enable terminal count, 0=disabled
  2418. * xctrl[15:0] receive terminal count for fixed length packets
  2419. * value is count minus one (0 = 1 byte packet)
  2420. * when terminal count is reached, receiver
  2421. * automatically returns to hunt mode and receive
  2422. * FIFO contents are flushed to DMA buffers with
  2423. * end of frame (EOF) status
  2424. */
  2425. static int set_xctrl(struct slgt_info *info, int xctrl)
  2426. {
  2427. unsigned long flags;
  2428. DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl));
  2429. spin_lock_irqsave(&info->lock, flags);
  2430. info->xctrl = xctrl;
  2431. wr_reg32(info, XCR, xctrl);
  2432. spin_unlock_irqrestore(&info->lock, flags);
  2433. return 0;
  2434. }
  2435. /*
  2436. * set general purpose IO pin state and direction
  2437. *
  2438. * user_gpio fields:
  2439. * state each bit indicates a pin state
  2440. * smask set bit indicates pin state to set
  2441. * dir each bit indicates a pin direction (0=input, 1=output)
  2442. * dmask set bit indicates pin direction to set
  2443. */
  2444. static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
  2445. {
  2446. unsigned long flags;
  2447. struct gpio_desc gpio;
  2448. __u32 data;
  2449. if (!info->gpio_present)
  2450. return -EINVAL;
  2451. if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
  2452. return -EFAULT;
  2453. DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
  2454. info->device_name, gpio.state, gpio.smask,
  2455. gpio.dir, gpio.dmask));
  2456. spin_lock_irqsave(&info->port_array[0]->lock, flags);
  2457. if (gpio.dmask) {
  2458. data = rd_reg32(info, IODR);
  2459. data |= gpio.dmask & gpio.dir;
  2460. data &= ~(gpio.dmask & ~gpio.dir);
  2461. wr_reg32(info, IODR, data);
  2462. }
  2463. if (gpio.smask) {
  2464. data = rd_reg32(info, IOVR);
  2465. data |= gpio.smask & gpio.state;
  2466. data &= ~(gpio.smask & ~gpio.state);
  2467. wr_reg32(info, IOVR, data);
  2468. }
  2469. spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
  2470. return 0;
  2471. }
  2472. /*
  2473. * get general purpose IO pin state and direction
  2474. */
  2475. static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
  2476. {
  2477. struct gpio_desc gpio;
  2478. if (!info->gpio_present)
  2479. return -EINVAL;
  2480. gpio.state = rd_reg32(info, IOVR);
  2481. gpio.smask = 0xffffffff;
  2482. gpio.dir = rd_reg32(info, IODR);
  2483. gpio.dmask = 0xffffffff;
  2484. if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
  2485. return -EFAULT;
  2486. DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
  2487. info->device_name, gpio.state, gpio.dir));
  2488. return 0;
  2489. }
  2490. /*
  2491. * conditional wait facility
  2492. */
  2493. static void init_cond_wait(struct cond_wait *w, unsigned int data)
  2494. {
  2495. init_waitqueue_head(&w->q);
  2496. init_waitqueue_entry(&w->wait, current);
  2497. w->data = data;
  2498. }
  2499. static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
  2500. {
  2501. set_current_state(TASK_INTERRUPTIBLE);
  2502. add_wait_queue(&w->q, &w->wait);
  2503. w->next = *head;
  2504. *head = w;
  2505. }
  2506. static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
  2507. {
  2508. struct cond_wait *w, *prev;
  2509. remove_wait_queue(&cw->q, &cw->wait);
  2510. set_current_state(TASK_RUNNING);
  2511. for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
  2512. if (w == cw) {
  2513. if (prev != NULL)
  2514. prev->next = w->next;
  2515. else
  2516. *head = w->next;
  2517. break;
  2518. }
  2519. }
  2520. }
  2521. static void flush_cond_wait(struct cond_wait **head)
  2522. {
  2523. while (*head != NULL) {
  2524. wake_up_interruptible(&(*head)->q);
  2525. *head = (*head)->next;
  2526. }
  2527. }
  2528. /*
  2529. * wait for general purpose I/O pin(s) to enter specified state
  2530. *
  2531. * user_gpio fields:
  2532. * state - bit indicates target pin state
  2533. * smask - set bit indicates watched pin
  2534. *
  2535. * The wait ends when at least one watched pin enters the specified
  2536. * state. When 0 (no error) is returned, user_gpio->state is set to the
  2537. * state of all GPIO pins when the wait ends.
  2538. *
  2539. * Note: Each pin may be a dedicated input, dedicated output, or
  2540. * configurable input/output. The number and configuration of pins
  2541. * varies with the specific adapter model. Only input pins (dedicated
  2542. * or configured) can be monitored with this function.
  2543. */
  2544. static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
  2545. {
  2546. unsigned long flags;
  2547. int rc = 0;
  2548. struct gpio_desc gpio;
  2549. struct cond_wait wait;
  2550. u32 state;
  2551. if (!info->gpio_present)
  2552. return -EINVAL;
  2553. if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
  2554. return -EFAULT;
  2555. DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
  2556. info->device_name, gpio.state, gpio.smask));
  2557. /* ignore output pins identified by set IODR bit */
  2558. if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
  2559. return -EINVAL;
  2560. init_cond_wait(&wait, gpio.smask);
  2561. spin_lock_irqsave(&info->port_array[0]->lock, flags);
  2562. /* enable interrupts for watched pins */
  2563. wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
  2564. /* get current pin states */
  2565. state = rd_reg32(info, IOVR);
  2566. if (gpio.smask & ~(state ^ gpio.state)) {
  2567. /* already in target state */
  2568. gpio.state = state;
  2569. } else {
  2570. /* wait for target state */
  2571. add_cond_wait(&info->gpio_wait_q, &wait);
  2572. spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
  2573. schedule();
  2574. if (signal_pending(current))
  2575. rc = -ERESTARTSYS;
  2576. else
  2577. gpio.state = wait.data;
  2578. spin_lock_irqsave(&info->port_array[0]->lock, flags);
  2579. remove_cond_wait(&info->gpio_wait_q, &wait);
  2580. }
  2581. /* disable all GPIO interrupts if no waiting processes */
  2582. if (info->gpio_wait_q == NULL)
  2583. wr_reg32(info, IOER, 0);
  2584. spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
  2585. if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
  2586. rc = -EFAULT;
  2587. return rc;
  2588. }
  2589. static int modem_input_wait(struct slgt_info *info,int arg)
  2590. {
  2591. unsigned long flags;
  2592. int rc;
  2593. struct mgsl_icount cprev, cnow;
  2594. DECLARE_WAITQUEUE(wait, current);
  2595. /* save current irq counts */
  2596. spin_lock_irqsave(&info->lock,flags);
  2597. cprev = info->icount;
  2598. add_wait_queue(&info->status_event_wait_q, &wait);
  2599. set_current_state(TASK_INTERRUPTIBLE);
  2600. spin_unlock_irqrestore(&info->lock,flags);
  2601. for(;;) {
  2602. schedule();
  2603. if (signal_pending(current)) {
  2604. rc = -ERESTARTSYS;
  2605. break;
  2606. }
  2607. /* get new irq counts */
  2608. spin_lock_irqsave(&info->lock,flags);
  2609. cnow = info->icount;
  2610. set_current_state(TASK_INTERRUPTIBLE);
  2611. spin_unlock_irqrestore(&info->lock,flags);
  2612. /* if no change, wait aborted for some reason */
  2613. if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
  2614. cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
  2615. rc = -EIO;
  2616. break;
  2617. }
  2618. /* check for change in caller specified modem input */
  2619. if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
  2620. (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
  2621. (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
  2622. (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
  2623. rc = 0;
  2624. break;
  2625. }
  2626. cprev = cnow;
  2627. }
  2628. remove_wait_queue(&info->status_event_wait_q, &wait);
  2629. set_current_state(TASK_RUNNING);
  2630. return rc;
  2631. }
  2632. /*
  2633. * return state of serial control and status signals
  2634. */
  2635. static int tiocmget(struct tty_struct *tty)
  2636. {
  2637. struct slgt_info *info = tty->driver_data;
  2638. unsigned int result;
  2639. unsigned long flags;
  2640. spin_lock_irqsave(&info->lock,flags);
  2641. get_gtsignals(info);
  2642. spin_unlock_irqrestore(&info->lock,flags);
  2643. result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
  2644. ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
  2645. ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
  2646. ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
  2647. ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
  2648. ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
  2649. DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
  2650. return result;
  2651. }
  2652. /*
  2653. * set modem control signals (DTR/RTS)
  2654. *
  2655. * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
  2656. * TIOCMSET = set/clear signal values
  2657. * value bit mask for command
  2658. */
  2659. static int tiocmset(struct tty_struct *tty,
  2660. unsigned int set, unsigned int clear)
  2661. {
  2662. struct slgt_info *info = tty->driver_data;
  2663. unsigned long flags;
  2664. DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
  2665. if (set & TIOCM_RTS)
  2666. info->signals |= SerialSignal_RTS;
  2667. if (set & TIOCM_DTR)
  2668. info->signals |= SerialSignal_DTR;
  2669. if (clear & TIOCM_RTS)
  2670. info->signals &= ~SerialSignal_RTS;
  2671. if (clear & TIOCM_DTR)
  2672. info->signals &= ~SerialSignal_DTR;
  2673. spin_lock_irqsave(&info->lock,flags);
  2674. set_gtsignals(info);
  2675. spin_unlock_irqrestore(&info->lock,flags);
  2676. return 0;
  2677. }
  2678. static int carrier_raised(struct tty_port *port)
  2679. {
  2680. unsigned long flags;
  2681. struct slgt_info *info = container_of(port, struct slgt_info, port);
  2682. spin_lock_irqsave(&info->lock,flags);
  2683. get_gtsignals(info);
  2684. spin_unlock_irqrestore(&info->lock,flags);
  2685. return (info->signals & SerialSignal_DCD) ? 1 : 0;
  2686. }
  2687. static void dtr_rts(struct tty_port *port, int on)
  2688. {
  2689. unsigned long flags;
  2690. struct slgt_info *info = container_of(port, struct slgt_info, port);
  2691. spin_lock_irqsave(&info->lock,flags);
  2692. if (on)
  2693. info->signals |= SerialSignal_RTS | SerialSignal_DTR;
  2694. else
  2695. info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
  2696. set_gtsignals(info);
  2697. spin_unlock_irqrestore(&info->lock,flags);
  2698. }
  2699. /*
  2700. * block current process until the device is ready to open
  2701. */
  2702. static int block_til_ready(struct tty_struct *tty, struct file *filp,
  2703. struct slgt_info *info)
  2704. {
  2705. DECLARE_WAITQUEUE(wait, current);
  2706. int retval;
  2707. bool do_clocal = false;
  2708. unsigned long flags;
  2709. int cd;
  2710. struct tty_port *port = &info->port;
  2711. DBGINFO(("%s block_til_ready\n", tty->driver->name));
  2712. if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
  2713. /* nonblock mode is set or port is not enabled */
  2714. tty_port_set_active(port, 1);
  2715. return 0;
  2716. }
  2717. if (C_CLOCAL(tty))
  2718. do_clocal = true;
  2719. /* Wait for carrier detect and the line to become
  2720. * free (i.e., not in use by the callout). While we are in
  2721. * this loop, port->count is dropped by one, so that
  2722. * close() knows when to free things. We restore it upon
  2723. * exit, either normal or abnormal.
  2724. */
  2725. retval = 0;
  2726. add_wait_queue(&port->open_wait, &wait);
  2727. spin_lock_irqsave(&info->lock, flags);
  2728. port->count--;
  2729. spin_unlock_irqrestore(&info->lock, flags);
  2730. port->blocked_open++;
  2731. while (1) {
  2732. if (C_BAUD(tty) && tty_port_initialized(port))
  2733. tty_port_raise_dtr_rts(port);
  2734. set_current_state(TASK_INTERRUPTIBLE);
  2735. if (tty_hung_up_p(filp) || !tty_port_initialized(port)) {
  2736. retval = (port->flags & ASYNC_HUP_NOTIFY) ?
  2737. -EAGAIN : -ERESTARTSYS;
  2738. break;
  2739. }
  2740. cd = tty_port_carrier_raised(port);
  2741. if (do_clocal || cd)
  2742. break;
  2743. if (signal_pending(current)) {
  2744. retval = -ERESTARTSYS;
  2745. break;
  2746. }
  2747. DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
  2748. tty_unlock(tty);
  2749. schedule();
  2750. tty_lock(tty);
  2751. }
  2752. set_current_state(TASK_RUNNING);
  2753. remove_wait_queue(&port->open_wait, &wait);
  2754. if (!tty_hung_up_p(filp))
  2755. port->count++;
  2756. port->blocked_open--;
  2757. if (!retval)
  2758. tty_port_set_active(port, 1);
  2759. DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
  2760. return retval;
  2761. }
  2762. /*
  2763. * allocate buffers used for calling line discipline receive_buf
  2764. * directly in synchronous mode
  2765. * note: add 5 bytes to max frame size to allow appending
  2766. * 32-bit CRC and status byte when configured to do so
  2767. */
  2768. static int alloc_tmp_rbuf(struct slgt_info *info)
  2769. {
  2770. info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
  2771. if (info->tmp_rbuf == NULL)
  2772. return -ENOMEM;
  2773. /* unused flag buffer to satisfy receive_buf calling interface */
  2774. info->flag_buf = kzalloc(info->max_frame_size + 5, GFP_KERNEL);
  2775. if (!info->flag_buf) {
  2776. kfree(info->tmp_rbuf);
  2777. info->tmp_rbuf = NULL;
  2778. return -ENOMEM;
  2779. }
  2780. return 0;
  2781. }
  2782. static void free_tmp_rbuf(struct slgt_info *info)
  2783. {
  2784. kfree(info->tmp_rbuf);
  2785. info->tmp_rbuf = NULL;
  2786. kfree(info->flag_buf);
  2787. info->flag_buf = NULL;
  2788. }
  2789. /*
  2790. * allocate DMA descriptor lists.
  2791. */
  2792. static int alloc_desc(struct slgt_info *info)
  2793. {
  2794. unsigned int i;
  2795. unsigned int pbufs;
  2796. /* allocate memory to hold descriptor lists */
  2797. info->bufs = dma_alloc_coherent(&info->pdev->dev, DESC_LIST_SIZE,
  2798. &info->bufs_dma_addr, GFP_KERNEL);
  2799. if (info->bufs == NULL)
  2800. return -ENOMEM;
  2801. info->rbufs = (struct slgt_desc*)info->bufs;
  2802. info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
  2803. pbufs = (unsigned int)info->bufs_dma_addr;
  2804. /*
  2805. * Build circular lists of descriptors
  2806. */
  2807. for (i=0; i < info->rbuf_count; i++) {
  2808. /* physical address of this descriptor */
  2809. info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
  2810. /* physical address of next descriptor */
  2811. if (i == info->rbuf_count - 1)
  2812. info->rbufs[i].next = cpu_to_le32(pbufs);
  2813. else
  2814. info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
  2815. set_desc_count(info->rbufs[i], DMABUFSIZE);
  2816. }
  2817. for (i=0; i < info->tbuf_count; i++) {
  2818. /* physical address of this descriptor */
  2819. info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
  2820. /* physical address of next descriptor */
  2821. if (i == info->tbuf_count - 1)
  2822. info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
  2823. else
  2824. info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
  2825. }
  2826. return 0;
  2827. }
  2828. static void free_desc(struct slgt_info *info)
  2829. {
  2830. if (info->bufs != NULL) {
  2831. dma_free_coherent(&info->pdev->dev, DESC_LIST_SIZE,
  2832. info->bufs, info->bufs_dma_addr);
  2833. info->bufs = NULL;
  2834. info->rbufs = NULL;
  2835. info->tbufs = NULL;
  2836. }
  2837. }
  2838. static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
  2839. {
  2840. int i;
  2841. for (i=0; i < count; i++) {
  2842. bufs[i].buf = dma_alloc_coherent(&info->pdev->dev, DMABUFSIZE,
  2843. &bufs[i].buf_dma_addr, GFP_KERNEL);
  2844. if (!bufs[i].buf)
  2845. return -ENOMEM;
  2846. bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
  2847. }
  2848. return 0;
  2849. }
  2850. static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
  2851. {
  2852. int i;
  2853. for (i=0; i < count; i++) {
  2854. if (bufs[i].buf == NULL)
  2855. continue;
  2856. dma_free_coherent(&info->pdev->dev, DMABUFSIZE, bufs[i].buf,
  2857. bufs[i].buf_dma_addr);
  2858. bufs[i].buf = NULL;
  2859. }
  2860. }
  2861. static int alloc_dma_bufs(struct slgt_info *info)
  2862. {
  2863. info->rbuf_count = 32;
  2864. info->tbuf_count = 32;
  2865. if (alloc_desc(info) < 0 ||
  2866. alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
  2867. alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
  2868. alloc_tmp_rbuf(info) < 0) {
  2869. DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
  2870. return -ENOMEM;
  2871. }
  2872. reset_rbufs(info);
  2873. return 0;
  2874. }
  2875. static void free_dma_bufs(struct slgt_info *info)
  2876. {
  2877. if (info->bufs) {
  2878. free_bufs(info, info->rbufs, info->rbuf_count);
  2879. free_bufs(info, info->tbufs, info->tbuf_count);
  2880. free_desc(info);
  2881. }
  2882. free_tmp_rbuf(info);
  2883. }
  2884. static int claim_resources(struct slgt_info *info)
  2885. {
  2886. if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
  2887. DBGERR(("%s reg addr conflict, addr=%08X\n",
  2888. info->device_name, info->phys_reg_addr));
  2889. info->init_error = DiagStatus_AddressConflict;
  2890. goto errout;
  2891. }
  2892. else
  2893. info->reg_addr_requested = true;
  2894. info->reg_addr = ioremap(info->phys_reg_addr, SLGT_REG_SIZE);
  2895. if (!info->reg_addr) {
  2896. DBGERR(("%s can't map device registers, addr=%08X\n",
  2897. info->device_name, info->phys_reg_addr));
  2898. info->init_error = DiagStatus_CantAssignPciResources;
  2899. goto errout;
  2900. }
  2901. return 0;
  2902. errout:
  2903. release_resources(info);
  2904. return -ENODEV;
  2905. }
  2906. static void release_resources(struct slgt_info *info)
  2907. {
  2908. if (info->irq_requested) {
  2909. free_irq(info->irq_level, info);
  2910. info->irq_requested = false;
  2911. }
  2912. if (info->reg_addr_requested) {
  2913. release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
  2914. info->reg_addr_requested = false;
  2915. }
  2916. if (info->reg_addr) {
  2917. iounmap(info->reg_addr);
  2918. info->reg_addr = NULL;
  2919. }
  2920. }
  2921. /* Add the specified device instance data structure to the
  2922. * global linked list of devices and increment the device count.
  2923. */
  2924. static void add_device(struct slgt_info *info)
  2925. {
  2926. char *devstr;
  2927. info->next_device = NULL;
  2928. info->line = slgt_device_count;
  2929. sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
  2930. if (info->line < MAX_DEVICES) {
  2931. if (maxframe[info->line])
  2932. info->max_frame_size = maxframe[info->line];
  2933. }
  2934. slgt_device_count++;
  2935. if (!slgt_device_list)
  2936. slgt_device_list = info;
  2937. else {
  2938. struct slgt_info *current_dev = slgt_device_list;
  2939. while(current_dev->next_device)
  2940. current_dev = current_dev->next_device;
  2941. current_dev->next_device = info;
  2942. }
  2943. if (info->max_frame_size < 4096)
  2944. info->max_frame_size = 4096;
  2945. else if (info->max_frame_size > 65535)
  2946. info->max_frame_size = 65535;
  2947. switch(info->pdev->device) {
  2948. case SYNCLINK_GT_DEVICE_ID:
  2949. devstr = "GT";
  2950. break;
  2951. case SYNCLINK_GT2_DEVICE_ID:
  2952. devstr = "GT2";
  2953. break;
  2954. case SYNCLINK_GT4_DEVICE_ID:
  2955. devstr = "GT4";
  2956. break;
  2957. case SYNCLINK_AC_DEVICE_ID:
  2958. devstr = "AC";
  2959. info->params.mode = MGSL_MODE_ASYNC;
  2960. break;
  2961. default:
  2962. devstr = "(unknown model)";
  2963. }
  2964. printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
  2965. devstr, info->device_name, info->phys_reg_addr,
  2966. info->irq_level, info->max_frame_size);
  2967. #if SYNCLINK_GENERIC_HDLC
  2968. hdlcdev_init(info);
  2969. #endif
  2970. }
  2971. static const struct tty_port_operations slgt_port_ops = {
  2972. .carrier_raised = carrier_raised,
  2973. .dtr_rts = dtr_rts,
  2974. };
  2975. /*
  2976. * allocate device instance structure, return NULL on failure
  2977. */
  2978. static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
  2979. {
  2980. struct slgt_info *info;
  2981. info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
  2982. if (!info) {
  2983. DBGERR(("%s device alloc failed adapter=%d port=%d\n",
  2984. driver_name, adapter_num, port_num));
  2985. } else {
  2986. tty_port_init(&info->port);
  2987. info->port.ops = &slgt_port_ops;
  2988. INIT_WORK(&info->task, bh_handler);
  2989. info->max_frame_size = 4096;
  2990. info->base_clock = 14745600;
  2991. info->rbuf_fill_level = DMABUFSIZE;
  2992. init_waitqueue_head(&info->status_event_wait_q);
  2993. init_waitqueue_head(&info->event_wait_q);
  2994. spin_lock_init(&info->netlock);
  2995. memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
  2996. info->idle_mode = HDLC_TXIDLE_FLAGS;
  2997. info->adapter_num = adapter_num;
  2998. info->port_num = port_num;
  2999. timer_setup(&info->tx_timer, tx_timeout, 0);
  3000. timer_setup(&info->rx_timer, rx_timeout, 0);
  3001. /* Copy configuration info to device instance data */
  3002. info->pdev = pdev;
  3003. info->irq_level = pdev->irq;
  3004. info->phys_reg_addr = pci_resource_start(pdev,0);
  3005. info->bus_type = MGSL_BUS_TYPE_PCI;
  3006. info->irq_flags = IRQF_SHARED;
  3007. info->init_error = -1; /* assume error, set to 0 on successful init */
  3008. }
  3009. return info;
  3010. }
  3011. static void device_init(int adapter_num, struct pci_dev *pdev)
  3012. {
  3013. struct slgt_info *port_array[SLGT_MAX_PORTS];
  3014. int i;
  3015. int port_count = 1;
  3016. if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
  3017. port_count = 2;
  3018. else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
  3019. port_count = 4;
  3020. /* allocate device instances for all ports */
  3021. for (i=0; i < port_count; ++i) {
  3022. port_array[i] = alloc_dev(adapter_num, i, pdev);
  3023. if (port_array[i] == NULL) {
  3024. for (--i; i >= 0; --i) {
  3025. tty_port_destroy(&port_array[i]->port);
  3026. kfree(port_array[i]);
  3027. }
  3028. return;
  3029. }
  3030. }
  3031. /* give copy of port_array to all ports and add to device list */
  3032. for (i=0; i < port_count; ++i) {
  3033. memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
  3034. add_device(port_array[i]);
  3035. port_array[i]->port_count = port_count;
  3036. spin_lock_init(&port_array[i]->lock);
  3037. }
  3038. /* Allocate and claim adapter resources */
  3039. if (!claim_resources(port_array[0])) {
  3040. alloc_dma_bufs(port_array[0]);
  3041. /* copy resource information from first port to others */
  3042. for (i = 1; i < port_count; ++i) {
  3043. port_array[i]->irq_level = port_array[0]->irq_level;
  3044. port_array[i]->reg_addr = port_array[0]->reg_addr;
  3045. alloc_dma_bufs(port_array[i]);
  3046. }
  3047. if (request_irq(port_array[0]->irq_level,
  3048. slgt_interrupt,
  3049. port_array[0]->irq_flags,
  3050. port_array[0]->device_name,
  3051. port_array[0]) < 0) {
  3052. DBGERR(("%s request_irq failed IRQ=%d\n",
  3053. port_array[0]->device_name,
  3054. port_array[0]->irq_level));
  3055. } else {
  3056. port_array[0]->irq_requested = true;
  3057. adapter_test(port_array[0]);
  3058. for (i=1 ; i < port_count ; i++) {
  3059. port_array[i]->init_error = port_array[0]->init_error;
  3060. port_array[i]->gpio_present = port_array[0]->gpio_present;
  3061. }
  3062. }
  3063. }
  3064. for (i = 0; i < port_count; ++i) {
  3065. struct slgt_info *info = port_array[i];
  3066. tty_port_register_device(&info->port, serial_driver, info->line,
  3067. &info->pdev->dev);
  3068. }
  3069. }
  3070. static int init_one(struct pci_dev *dev,
  3071. const struct pci_device_id *ent)
  3072. {
  3073. if (pci_enable_device(dev)) {
  3074. printk("error enabling pci device %p\n", dev);
  3075. return -EIO;
  3076. }
  3077. pci_set_master(dev);
  3078. device_init(slgt_device_count, dev);
  3079. return 0;
  3080. }
  3081. static void remove_one(struct pci_dev *dev)
  3082. {
  3083. }
  3084. static const struct tty_operations ops = {
  3085. .open = open,
  3086. .close = close,
  3087. .write = write,
  3088. .put_char = put_char,
  3089. .flush_chars = flush_chars,
  3090. .write_room = write_room,
  3091. .chars_in_buffer = chars_in_buffer,
  3092. .flush_buffer = flush_buffer,
  3093. .ioctl = ioctl,
  3094. .compat_ioctl = slgt_compat_ioctl,
  3095. .throttle = throttle,
  3096. .unthrottle = unthrottle,
  3097. .send_xchar = send_xchar,
  3098. .break_ctl = set_break,
  3099. .wait_until_sent = wait_until_sent,
  3100. .set_termios = set_termios,
  3101. .stop = tx_hold,
  3102. .start = tx_release,
  3103. .hangup = hangup,
  3104. .tiocmget = tiocmget,
  3105. .tiocmset = tiocmset,
  3106. .get_icount = get_icount,
  3107. .proc_show = synclink_gt_proc_show,
  3108. };
  3109. static void slgt_cleanup(void)
  3110. {
  3111. struct slgt_info *info;
  3112. struct slgt_info *tmp;
  3113. printk(KERN_INFO "unload %s\n", driver_name);
  3114. if (serial_driver) {
  3115. for (info=slgt_device_list ; info != NULL ; info=info->next_device)
  3116. tty_unregister_device(serial_driver, info->line);
  3117. tty_unregister_driver(serial_driver);
  3118. tty_driver_kref_put(serial_driver);
  3119. }
  3120. /* reset devices */
  3121. info = slgt_device_list;
  3122. while(info) {
  3123. reset_port(info);
  3124. info = info->next_device;
  3125. }
  3126. /* release devices */
  3127. info = slgt_device_list;
  3128. while(info) {
  3129. #if SYNCLINK_GENERIC_HDLC
  3130. hdlcdev_exit(info);
  3131. #endif
  3132. free_dma_bufs(info);
  3133. free_tmp_rbuf(info);
  3134. if (info->port_num == 0)
  3135. release_resources(info);
  3136. tmp = info;
  3137. info = info->next_device;
  3138. tty_port_destroy(&tmp->port);
  3139. kfree(tmp);
  3140. }
  3141. if (pci_registered)
  3142. pci_unregister_driver(&pci_driver);
  3143. }
  3144. /*
  3145. * Driver initialization entry point.
  3146. */
  3147. static int __init slgt_init(void)
  3148. {
  3149. int rc;
  3150. printk(KERN_INFO "%s\n", driver_name);
  3151. serial_driver = tty_alloc_driver(MAX_DEVICES, TTY_DRIVER_REAL_RAW |
  3152. TTY_DRIVER_DYNAMIC_DEV);
  3153. if (IS_ERR(serial_driver)) {
  3154. printk("%s can't allocate tty driver\n", driver_name);
  3155. return PTR_ERR(serial_driver);
  3156. }
  3157. /* Initialize the tty_driver structure */
  3158. serial_driver->driver_name = slgt_driver_name;
  3159. serial_driver->name = tty_dev_prefix;
  3160. serial_driver->major = ttymajor;
  3161. serial_driver->minor_start = 64;
  3162. serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
  3163. serial_driver->subtype = SERIAL_TYPE_NORMAL;
  3164. serial_driver->init_termios = tty_std_termios;
  3165. serial_driver->init_termios.c_cflag =
  3166. B9600 | CS8 | CREAD | HUPCL | CLOCAL;
  3167. serial_driver->init_termios.c_ispeed = 9600;
  3168. serial_driver->init_termios.c_ospeed = 9600;
  3169. tty_set_operations(serial_driver, &ops);
  3170. if ((rc = tty_register_driver(serial_driver)) < 0) {
  3171. DBGERR(("%s can't register serial driver\n", driver_name));
  3172. tty_driver_kref_put(serial_driver);
  3173. serial_driver = NULL;
  3174. goto error;
  3175. }
  3176. printk(KERN_INFO "%s, tty major#%d\n",
  3177. driver_name, serial_driver->major);
  3178. slgt_device_count = 0;
  3179. if ((rc = pci_register_driver(&pci_driver)) < 0) {
  3180. printk("%s pci_register_driver error=%d\n", driver_name, rc);
  3181. goto error;
  3182. }
  3183. pci_registered = true;
  3184. if (!slgt_device_list)
  3185. printk("%s no devices found\n",driver_name);
  3186. return 0;
  3187. error:
  3188. slgt_cleanup();
  3189. return rc;
  3190. }
  3191. static void __exit slgt_exit(void)
  3192. {
  3193. slgt_cleanup();
  3194. }
  3195. module_init(slgt_init);
  3196. module_exit(slgt_exit);
  3197. /*
  3198. * register access routines
  3199. */
  3200. #define CALC_REGADDR() \
  3201. unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
  3202. if (addr >= 0x80) \
  3203. reg_addr += (info->port_num) * 32; \
  3204. else if (addr >= 0x40) \
  3205. reg_addr += (info->port_num) * 16;
  3206. static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
  3207. {
  3208. CALC_REGADDR();
  3209. return readb((void __iomem *)reg_addr);
  3210. }
  3211. static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
  3212. {
  3213. CALC_REGADDR();
  3214. writeb(value, (void __iomem *)reg_addr);
  3215. }
  3216. static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
  3217. {
  3218. CALC_REGADDR();
  3219. return readw((void __iomem *)reg_addr);
  3220. }
  3221. static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
  3222. {
  3223. CALC_REGADDR();
  3224. writew(value, (void __iomem *)reg_addr);
  3225. }
  3226. static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
  3227. {
  3228. CALC_REGADDR();
  3229. return readl((void __iomem *)reg_addr);
  3230. }
  3231. static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
  3232. {
  3233. CALC_REGADDR();
  3234. writel(value, (void __iomem *)reg_addr);
  3235. }
  3236. static void rdma_reset(struct slgt_info *info)
  3237. {
  3238. unsigned int i;
  3239. /* set reset bit */
  3240. wr_reg32(info, RDCSR, BIT1);
  3241. /* wait for enable bit cleared */
  3242. for(i=0 ; i < 1000 ; i++)
  3243. if (!(rd_reg32(info, RDCSR) & BIT0))
  3244. break;
  3245. }
  3246. static void tdma_reset(struct slgt_info *info)
  3247. {
  3248. unsigned int i;
  3249. /* set reset bit */
  3250. wr_reg32(info, TDCSR, BIT1);
  3251. /* wait for enable bit cleared */
  3252. for(i=0 ; i < 1000 ; i++)
  3253. if (!(rd_reg32(info, TDCSR) & BIT0))
  3254. break;
  3255. }
  3256. /*
  3257. * enable internal loopback
  3258. * TxCLK and RxCLK are generated from BRG
  3259. * and TxD is looped back to RxD internally.
  3260. */
  3261. static void enable_loopback(struct slgt_info *info)
  3262. {
  3263. /* SCR (serial control) BIT2=loopback enable */
  3264. wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
  3265. if (info->params.mode != MGSL_MODE_ASYNC) {
  3266. /* CCR (clock control)
  3267. * 07..05 tx clock source (010 = BRG)
  3268. * 04..02 rx clock source (010 = BRG)
  3269. * 01 auxclk enable (0 = disable)
  3270. * 00 BRG enable (1 = enable)
  3271. *
  3272. * 0100 1001
  3273. */
  3274. wr_reg8(info, CCR, 0x49);
  3275. /* set speed if available, otherwise use default */
  3276. if (info->params.clock_speed)
  3277. set_rate(info, info->params.clock_speed);
  3278. else
  3279. set_rate(info, 3686400);
  3280. }
  3281. }
  3282. /*
  3283. * set baud rate generator to specified rate
  3284. */
  3285. static void set_rate(struct slgt_info *info, u32 rate)
  3286. {
  3287. unsigned int div;
  3288. unsigned int osc = info->base_clock;
  3289. /* div = osc/rate - 1
  3290. *
  3291. * Round div up if osc/rate is not integer to
  3292. * force to next slowest rate.
  3293. */
  3294. if (rate) {
  3295. div = osc/rate;
  3296. if (!(osc % rate) && div)
  3297. div--;
  3298. wr_reg16(info, BDR, (unsigned short)div);
  3299. }
  3300. }
  3301. static void rx_stop(struct slgt_info *info)
  3302. {
  3303. unsigned short val;
  3304. /* disable and reset receiver */
  3305. val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
  3306. wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
  3307. wr_reg16(info, RCR, val); /* clear reset bit */
  3308. slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
  3309. /* clear pending rx interrupts */
  3310. wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
  3311. rdma_reset(info);
  3312. info->rx_enabled = false;
  3313. info->rx_restart = false;
  3314. }
  3315. static void rx_start(struct slgt_info *info)
  3316. {
  3317. unsigned short val;
  3318. slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
  3319. /* clear pending rx overrun IRQ */
  3320. wr_reg16(info, SSR, IRQ_RXOVER);
  3321. /* reset and disable receiver */
  3322. val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
  3323. wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
  3324. wr_reg16(info, RCR, val); /* clear reset bit */
  3325. rdma_reset(info);
  3326. reset_rbufs(info);
  3327. if (info->rx_pio) {
  3328. /* rx request when rx FIFO not empty */
  3329. wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
  3330. slgt_irq_on(info, IRQ_RXDATA);
  3331. if (info->params.mode == MGSL_MODE_ASYNC) {
  3332. /* enable saving of rx status */
  3333. wr_reg32(info, RDCSR, BIT6);
  3334. }
  3335. } else {
  3336. /* rx request when rx FIFO half full */
  3337. wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
  3338. /* set 1st descriptor address */
  3339. wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
  3340. if (info->params.mode != MGSL_MODE_ASYNC) {
  3341. /* enable rx DMA and DMA interrupt */
  3342. wr_reg32(info, RDCSR, (BIT2 + BIT0));
  3343. } else {
  3344. /* enable saving of rx status, rx DMA and DMA interrupt */
  3345. wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
  3346. }
  3347. }
  3348. slgt_irq_on(info, IRQ_RXOVER);
  3349. /* enable receiver */
  3350. wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
  3351. info->rx_restart = false;
  3352. info->rx_enabled = true;
  3353. }
  3354. static void tx_start(struct slgt_info *info)
  3355. {
  3356. if (!info->tx_enabled) {
  3357. wr_reg16(info, TCR,
  3358. (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
  3359. info->tx_enabled = true;
  3360. }
  3361. if (desc_count(info->tbufs[info->tbuf_start])) {
  3362. info->drop_rts_on_tx_done = false;
  3363. if (info->params.mode != MGSL_MODE_ASYNC) {
  3364. if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
  3365. get_gtsignals(info);
  3366. if (!(info->signals & SerialSignal_RTS)) {
  3367. info->signals |= SerialSignal_RTS;
  3368. set_gtsignals(info);
  3369. info->drop_rts_on_tx_done = true;
  3370. }
  3371. }
  3372. slgt_irq_off(info, IRQ_TXDATA);
  3373. slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
  3374. /* clear tx idle and underrun status bits */
  3375. wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
  3376. } else {
  3377. slgt_irq_off(info, IRQ_TXDATA);
  3378. slgt_irq_on(info, IRQ_TXIDLE);
  3379. /* clear tx idle status bit */
  3380. wr_reg16(info, SSR, IRQ_TXIDLE);
  3381. }
  3382. /* set 1st descriptor address and start DMA */
  3383. wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
  3384. wr_reg32(info, TDCSR, BIT2 + BIT0);
  3385. info->tx_active = true;
  3386. }
  3387. }
  3388. static void tx_stop(struct slgt_info *info)
  3389. {
  3390. unsigned short val;
  3391. del_timer(&info->tx_timer);
  3392. tdma_reset(info);
  3393. /* reset and disable transmitter */
  3394. val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
  3395. wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
  3396. slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
  3397. /* clear tx idle and underrun status bit */
  3398. wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
  3399. reset_tbufs(info);
  3400. info->tx_enabled = false;
  3401. info->tx_active = false;
  3402. }
  3403. static void reset_port(struct slgt_info *info)
  3404. {
  3405. if (!info->reg_addr)
  3406. return;
  3407. tx_stop(info);
  3408. rx_stop(info);
  3409. info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
  3410. set_gtsignals(info);
  3411. slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
  3412. }
  3413. static void reset_adapter(struct slgt_info *info)
  3414. {
  3415. int i;
  3416. for (i=0; i < info->port_count; ++i) {
  3417. if (info->port_array[i])
  3418. reset_port(info->port_array[i]);
  3419. }
  3420. }
  3421. static void async_mode(struct slgt_info *info)
  3422. {
  3423. unsigned short val;
  3424. slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
  3425. tx_stop(info);
  3426. rx_stop(info);
  3427. /* TCR (tx control)
  3428. *
  3429. * 15..13 mode, 010=async
  3430. * 12..10 encoding, 000=NRZ
  3431. * 09 parity enable
  3432. * 08 1=odd parity, 0=even parity
  3433. * 07 1=RTS driver control
  3434. * 06 1=break enable
  3435. * 05..04 character length
  3436. * 00=5 bits
  3437. * 01=6 bits
  3438. * 10=7 bits
  3439. * 11=8 bits
  3440. * 03 0=1 stop bit, 1=2 stop bits
  3441. * 02 reset
  3442. * 01 enable
  3443. * 00 auto-CTS enable
  3444. */
  3445. val = 0x4000;
  3446. if (info->if_mode & MGSL_INTERFACE_RTS_EN)
  3447. val |= BIT7;
  3448. if (info->params.parity != ASYNC_PARITY_NONE) {
  3449. val |= BIT9;
  3450. if (info->params.parity == ASYNC_PARITY_ODD)
  3451. val |= BIT8;
  3452. }
  3453. switch (info->params.data_bits)
  3454. {
  3455. case 6: val |= BIT4; break;
  3456. case 7: val |= BIT5; break;
  3457. case 8: val |= BIT5 + BIT4; break;
  3458. }
  3459. if (info->params.stop_bits != 1)
  3460. val |= BIT3;
  3461. if (info->params.flags & HDLC_FLAG_AUTO_CTS)
  3462. val |= BIT0;
  3463. wr_reg16(info, TCR, val);
  3464. /* RCR (rx control)
  3465. *
  3466. * 15..13 mode, 010=async
  3467. * 12..10 encoding, 000=NRZ
  3468. * 09 parity enable
  3469. * 08 1=odd parity, 0=even parity
  3470. * 07..06 reserved, must be 0
  3471. * 05..04 character length
  3472. * 00=5 bits
  3473. * 01=6 bits
  3474. * 10=7 bits
  3475. * 11=8 bits
  3476. * 03 reserved, must be zero
  3477. * 02 reset
  3478. * 01 enable
  3479. * 00 auto-DCD enable
  3480. */
  3481. val = 0x4000;
  3482. if (info->params.parity != ASYNC_PARITY_NONE) {
  3483. val |= BIT9;
  3484. if (info->params.parity == ASYNC_PARITY_ODD)
  3485. val |= BIT8;
  3486. }
  3487. switch (info->params.data_bits)
  3488. {
  3489. case 6: val |= BIT4; break;
  3490. case 7: val |= BIT5; break;
  3491. case 8: val |= BIT5 + BIT4; break;
  3492. }
  3493. if (info->params.flags & HDLC_FLAG_AUTO_DCD)
  3494. val |= BIT0;
  3495. wr_reg16(info, RCR, val);
  3496. /* CCR (clock control)
  3497. *
  3498. * 07..05 011 = tx clock source is BRG/16
  3499. * 04..02 010 = rx clock source is BRG
  3500. * 01 0 = auxclk disabled
  3501. * 00 1 = BRG enabled
  3502. *
  3503. * 0110 1001
  3504. */
  3505. wr_reg8(info, CCR, 0x69);
  3506. msc_set_vcr(info);
  3507. /* SCR (serial control)
  3508. *
  3509. * 15 1=tx req on FIFO half empty
  3510. * 14 1=rx req on FIFO half full
  3511. * 13 tx data IRQ enable
  3512. * 12 tx idle IRQ enable
  3513. * 11 rx break on IRQ enable
  3514. * 10 rx data IRQ enable
  3515. * 09 rx break off IRQ enable
  3516. * 08 overrun IRQ enable
  3517. * 07 DSR IRQ enable
  3518. * 06 CTS IRQ enable
  3519. * 05 DCD IRQ enable
  3520. * 04 RI IRQ enable
  3521. * 03 0=16x sampling, 1=8x sampling
  3522. * 02 1=txd->rxd internal loopback enable
  3523. * 01 reserved, must be zero
  3524. * 00 1=master IRQ enable
  3525. */
  3526. val = BIT15 + BIT14 + BIT0;
  3527. /* JCR[8] : 1 = x8 async mode feature available */
  3528. if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
  3529. ((info->base_clock < (info->params.data_rate * 16)) ||
  3530. (info->base_clock % (info->params.data_rate * 16)))) {
  3531. /* use 8x sampling */
  3532. val |= BIT3;
  3533. set_rate(info, info->params.data_rate * 8);
  3534. } else {
  3535. /* use 16x sampling */
  3536. set_rate(info, info->params.data_rate * 16);
  3537. }
  3538. wr_reg16(info, SCR, val);
  3539. slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
  3540. if (info->params.loopback)
  3541. enable_loopback(info);
  3542. }
  3543. static void sync_mode(struct slgt_info *info)
  3544. {
  3545. unsigned short val;
  3546. slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
  3547. tx_stop(info);
  3548. rx_stop(info);
  3549. /* TCR (tx control)
  3550. *
  3551. * 15..13 mode
  3552. * 000=HDLC/SDLC
  3553. * 001=raw bit synchronous
  3554. * 010=asynchronous/isochronous
  3555. * 011=monosync byte synchronous
  3556. * 100=bisync byte synchronous
  3557. * 101=xsync byte synchronous
  3558. * 12..10 encoding
  3559. * 09 CRC enable
  3560. * 08 CRC32
  3561. * 07 1=RTS driver control
  3562. * 06 preamble enable
  3563. * 05..04 preamble length
  3564. * 03 share open/close flag
  3565. * 02 reset
  3566. * 01 enable
  3567. * 00 auto-CTS enable
  3568. */
  3569. val = BIT2;
  3570. switch(info->params.mode) {
  3571. case MGSL_MODE_XSYNC:
  3572. val |= BIT15 + BIT13;
  3573. break;
  3574. case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
  3575. case MGSL_MODE_BISYNC: val |= BIT15; break;
  3576. case MGSL_MODE_RAW: val |= BIT13; break;
  3577. }
  3578. if (info->if_mode & MGSL_INTERFACE_RTS_EN)
  3579. val |= BIT7;
  3580. switch(info->params.encoding)
  3581. {
  3582. case HDLC_ENCODING_NRZB: val |= BIT10; break;
  3583. case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
  3584. case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
  3585. case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
  3586. case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
  3587. case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
  3588. case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
  3589. }
  3590. switch (info->params.crc_type & HDLC_CRC_MASK)
  3591. {
  3592. case HDLC_CRC_16_CCITT: val |= BIT9; break;
  3593. case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
  3594. }
  3595. if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
  3596. val |= BIT6;
  3597. switch (info->params.preamble_length)
  3598. {
  3599. case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
  3600. case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
  3601. case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
  3602. }
  3603. if (info->params.flags & HDLC_FLAG_AUTO_CTS)
  3604. val |= BIT0;
  3605. wr_reg16(info, TCR, val);
  3606. /* TPR (transmit preamble) */
  3607. switch (info->params.preamble)
  3608. {
  3609. case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
  3610. case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
  3611. case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
  3612. case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
  3613. case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
  3614. default: val = 0x7e; break;
  3615. }
  3616. wr_reg8(info, TPR, (unsigned char)val);
  3617. /* RCR (rx control)
  3618. *
  3619. * 15..13 mode
  3620. * 000=HDLC/SDLC
  3621. * 001=raw bit synchronous
  3622. * 010=asynchronous/isochronous
  3623. * 011=monosync byte synchronous
  3624. * 100=bisync byte synchronous
  3625. * 101=xsync byte synchronous
  3626. * 12..10 encoding
  3627. * 09 CRC enable
  3628. * 08 CRC32
  3629. * 07..03 reserved, must be 0
  3630. * 02 reset
  3631. * 01 enable
  3632. * 00 auto-DCD enable
  3633. */
  3634. val = 0;
  3635. switch(info->params.mode) {
  3636. case MGSL_MODE_XSYNC:
  3637. val |= BIT15 + BIT13;
  3638. break;
  3639. case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
  3640. case MGSL_MODE_BISYNC: val |= BIT15; break;
  3641. case MGSL_MODE_RAW: val |= BIT13; break;
  3642. }
  3643. switch(info->params.encoding)
  3644. {
  3645. case HDLC_ENCODING_NRZB: val |= BIT10; break;
  3646. case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
  3647. case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
  3648. case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
  3649. case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
  3650. case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
  3651. case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
  3652. }
  3653. switch (info->params.crc_type & HDLC_CRC_MASK)
  3654. {
  3655. case HDLC_CRC_16_CCITT: val |= BIT9; break;
  3656. case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
  3657. }
  3658. if (info->params.flags & HDLC_FLAG_AUTO_DCD)
  3659. val |= BIT0;
  3660. wr_reg16(info, RCR, val);
  3661. /* CCR (clock control)
  3662. *
  3663. * 07..05 tx clock source
  3664. * 04..02 rx clock source
  3665. * 01 auxclk enable
  3666. * 00 BRG enable
  3667. */
  3668. val = 0;
  3669. if (info->params.flags & HDLC_FLAG_TXC_BRG)
  3670. {
  3671. // when RxC source is DPLL, BRG generates 16X DPLL
  3672. // reference clock, so take TxC from BRG/16 to get
  3673. // transmit clock at actual data rate
  3674. if (info->params.flags & HDLC_FLAG_RXC_DPLL)
  3675. val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
  3676. else
  3677. val |= BIT6; /* 010, txclk = BRG */
  3678. }
  3679. else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
  3680. val |= BIT7; /* 100, txclk = DPLL Input */
  3681. else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
  3682. val |= BIT5; /* 001, txclk = RXC Input */
  3683. if (info->params.flags & HDLC_FLAG_RXC_BRG)
  3684. val |= BIT3; /* 010, rxclk = BRG */
  3685. else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
  3686. val |= BIT4; /* 100, rxclk = DPLL */
  3687. else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
  3688. val |= BIT2; /* 001, rxclk = TXC Input */
  3689. if (info->params.clock_speed)
  3690. val |= BIT1 + BIT0;
  3691. wr_reg8(info, CCR, (unsigned char)val);
  3692. if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
  3693. {
  3694. // program DPLL mode
  3695. switch(info->params.encoding)
  3696. {
  3697. case HDLC_ENCODING_BIPHASE_MARK:
  3698. case HDLC_ENCODING_BIPHASE_SPACE:
  3699. val = BIT7; break;
  3700. case HDLC_ENCODING_BIPHASE_LEVEL:
  3701. case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
  3702. val = BIT7 + BIT6; break;
  3703. default: val = BIT6; // NRZ encodings
  3704. }
  3705. wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
  3706. // DPLL requires a 16X reference clock from BRG
  3707. set_rate(info, info->params.clock_speed * 16);
  3708. }
  3709. else
  3710. set_rate(info, info->params.clock_speed);
  3711. tx_set_idle(info);
  3712. msc_set_vcr(info);
  3713. /* SCR (serial control)
  3714. *
  3715. * 15 1=tx req on FIFO half empty
  3716. * 14 1=rx req on FIFO half full
  3717. * 13 tx data IRQ enable
  3718. * 12 tx idle IRQ enable
  3719. * 11 underrun IRQ enable
  3720. * 10 rx data IRQ enable
  3721. * 09 rx idle IRQ enable
  3722. * 08 overrun IRQ enable
  3723. * 07 DSR IRQ enable
  3724. * 06 CTS IRQ enable
  3725. * 05 DCD IRQ enable
  3726. * 04 RI IRQ enable
  3727. * 03 reserved, must be zero
  3728. * 02 1=txd->rxd internal loopback enable
  3729. * 01 reserved, must be zero
  3730. * 00 1=master IRQ enable
  3731. */
  3732. wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
  3733. if (info->params.loopback)
  3734. enable_loopback(info);
  3735. }
  3736. /*
  3737. * set transmit idle mode
  3738. */
  3739. static void tx_set_idle(struct slgt_info *info)
  3740. {
  3741. unsigned char val;
  3742. unsigned short tcr;
  3743. /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
  3744. * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
  3745. */
  3746. tcr = rd_reg16(info, TCR);
  3747. if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
  3748. /* disable preamble, set idle size to 16 bits */
  3749. tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
  3750. /* MSB of 16 bit idle specified in tx preamble register (TPR) */
  3751. wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
  3752. } else if (!(tcr & BIT6)) {
  3753. /* preamble is disabled, set idle size to 8 bits */
  3754. tcr &= ~(BIT5 + BIT4);
  3755. }
  3756. wr_reg16(info, TCR, tcr);
  3757. if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
  3758. /* LSB of custom tx idle specified in tx idle register */
  3759. val = (unsigned char)(info->idle_mode & 0xff);
  3760. } else {
  3761. /* standard 8 bit idle patterns */
  3762. switch(info->idle_mode)
  3763. {
  3764. case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
  3765. case HDLC_TXIDLE_ALT_ZEROS_ONES:
  3766. case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
  3767. case HDLC_TXIDLE_ZEROS:
  3768. case HDLC_TXIDLE_SPACE: val = 0x00; break;
  3769. default: val = 0xff;
  3770. }
  3771. }
  3772. wr_reg8(info, TIR, val);
  3773. }
  3774. /*
  3775. * get state of V24 status (input) signals
  3776. */
  3777. static void get_gtsignals(struct slgt_info *info)
  3778. {
  3779. unsigned short status = rd_reg16(info, SSR);
  3780. /* clear all serial signals except RTS and DTR */
  3781. info->signals &= SerialSignal_RTS | SerialSignal_DTR;
  3782. if (status & BIT3)
  3783. info->signals |= SerialSignal_DSR;
  3784. if (status & BIT2)
  3785. info->signals |= SerialSignal_CTS;
  3786. if (status & BIT1)
  3787. info->signals |= SerialSignal_DCD;
  3788. if (status & BIT0)
  3789. info->signals |= SerialSignal_RI;
  3790. }
  3791. /*
  3792. * set V.24 Control Register based on current configuration
  3793. */
  3794. static void msc_set_vcr(struct slgt_info *info)
  3795. {
  3796. unsigned char val = 0;
  3797. /* VCR (V.24 control)
  3798. *
  3799. * 07..04 serial IF select
  3800. * 03 DTR
  3801. * 02 RTS
  3802. * 01 LL
  3803. * 00 RL
  3804. */
  3805. switch(info->if_mode & MGSL_INTERFACE_MASK)
  3806. {
  3807. case MGSL_INTERFACE_RS232:
  3808. val |= BIT5; /* 0010 */
  3809. break;
  3810. case MGSL_INTERFACE_V35:
  3811. val |= BIT7 + BIT6 + BIT5; /* 1110 */
  3812. break;
  3813. case MGSL_INTERFACE_RS422:
  3814. val |= BIT6; /* 0100 */
  3815. break;
  3816. }
  3817. if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
  3818. val |= BIT4;
  3819. if (info->signals & SerialSignal_DTR)
  3820. val |= BIT3;
  3821. if (info->signals & SerialSignal_RTS)
  3822. val |= BIT2;
  3823. if (info->if_mode & MGSL_INTERFACE_LL)
  3824. val |= BIT1;
  3825. if (info->if_mode & MGSL_INTERFACE_RL)
  3826. val |= BIT0;
  3827. wr_reg8(info, VCR, val);
  3828. }
  3829. /*
  3830. * set state of V24 control (output) signals
  3831. */
  3832. static void set_gtsignals(struct slgt_info *info)
  3833. {
  3834. unsigned char val = rd_reg8(info, VCR);
  3835. if (info->signals & SerialSignal_DTR)
  3836. val |= BIT3;
  3837. else
  3838. val &= ~BIT3;
  3839. if (info->signals & SerialSignal_RTS)
  3840. val |= BIT2;
  3841. else
  3842. val &= ~BIT2;
  3843. wr_reg8(info, VCR, val);
  3844. }
  3845. /*
  3846. * free range of receive DMA buffers (i to last)
  3847. */
  3848. static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
  3849. {
  3850. int done = 0;
  3851. while(!done) {
  3852. /* reset current buffer for reuse */
  3853. info->rbufs[i].status = 0;
  3854. set_desc_count(info->rbufs[i], info->rbuf_fill_level);
  3855. if (i == last)
  3856. done = 1;
  3857. if (++i == info->rbuf_count)
  3858. i = 0;
  3859. }
  3860. info->rbuf_current = i;
  3861. }
  3862. /*
  3863. * mark all receive DMA buffers as free
  3864. */
  3865. static void reset_rbufs(struct slgt_info *info)
  3866. {
  3867. free_rbufs(info, 0, info->rbuf_count - 1);
  3868. info->rbuf_fill_index = 0;
  3869. info->rbuf_fill_count = 0;
  3870. }
  3871. /*
  3872. * pass receive HDLC frame to upper layer
  3873. *
  3874. * return true if frame available, otherwise false
  3875. */
  3876. static bool rx_get_frame(struct slgt_info *info)
  3877. {
  3878. unsigned int start, end;
  3879. unsigned short status;
  3880. unsigned int framesize = 0;
  3881. unsigned long flags;
  3882. struct tty_struct *tty = info->port.tty;
  3883. unsigned char addr_field = 0xff;
  3884. unsigned int crc_size = 0;
  3885. switch (info->params.crc_type & HDLC_CRC_MASK) {
  3886. case HDLC_CRC_16_CCITT: crc_size = 2; break;
  3887. case HDLC_CRC_32_CCITT: crc_size = 4; break;
  3888. }
  3889. check_again:
  3890. framesize = 0;
  3891. addr_field = 0xff;
  3892. start = end = info->rbuf_current;
  3893. for (;;) {
  3894. if (!desc_complete(info->rbufs[end]))
  3895. goto cleanup;
  3896. if (framesize == 0 && info->params.addr_filter != 0xff)
  3897. addr_field = info->rbufs[end].buf[0];
  3898. framesize += desc_count(info->rbufs[end]);
  3899. if (desc_eof(info->rbufs[end]))
  3900. break;
  3901. if (++end == info->rbuf_count)
  3902. end = 0;
  3903. if (end == info->rbuf_current) {
  3904. if (info->rx_enabled){
  3905. spin_lock_irqsave(&info->lock,flags);
  3906. rx_start(info);
  3907. spin_unlock_irqrestore(&info->lock,flags);
  3908. }
  3909. goto cleanup;
  3910. }
  3911. }
  3912. /* status
  3913. *
  3914. * 15 buffer complete
  3915. * 14..06 reserved
  3916. * 05..04 residue
  3917. * 02 eof (end of frame)
  3918. * 01 CRC error
  3919. * 00 abort
  3920. */
  3921. status = desc_status(info->rbufs[end]);
  3922. /* ignore CRC bit if not using CRC (bit is undefined) */
  3923. if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
  3924. status &= ~BIT1;
  3925. if (framesize == 0 ||
  3926. (addr_field != 0xff && addr_field != info->params.addr_filter)) {
  3927. free_rbufs(info, start, end);
  3928. goto check_again;
  3929. }
  3930. if (framesize < (2 + crc_size) || status & BIT0) {
  3931. info->icount.rxshort++;
  3932. framesize = 0;
  3933. } else if (status & BIT1) {
  3934. info->icount.rxcrc++;
  3935. if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
  3936. framesize = 0;
  3937. }
  3938. #if SYNCLINK_GENERIC_HDLC
  3939. if (framesize == 0) {
  3940. info->netdev->stats.rx_errors++;
  3941. info->netdev->stats.rx_frame_errors++;
  3942. }
  3943. #endif
  3944. DBGBH(("%s rx frame status=%04X size=%d\n",
  3945. info->device_name, status, framesize));
  3946. DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
  3947. if (framesize) {
  3948. if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
  3949. framesize -= crc_size;
  3950. crc_size = 0;
  3951. }
  3952. if (framesize > info->max_frame_size + crc_size)
  3953. info->icount.rxlong++;
  3954. else {
  3955. /* copy dma buffer(s) to contiguous temp buffer */
  3956. int copy_count = framesize;
  3957. int i = start;
  3958. unsigned char *p = info->tmp_rbuf;
  3959. info->tmp_rbuf_count = framesize;
  3960. info->icount.rxok++;
  3961. while(copy_count) {
  3962. int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
  3963. memcpy(p, info->rbufs[i].buf, partial_count);
  3964. p += partial_count;
  3965. copy_count -= partial_count;
  3966. if (++i == info->rbuf_count)
  3967. i = 0;
  3968. }
  3969. if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
  3970. *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
  3971. framesize++;
  3972. }
  3973. #if SYNCLINK_GENERIC_HDLC
  3974. if (info->netcount)
  3975. hdlcdev_rx(info,info->tmp_rbuf, framesize);
  3976. else
  3977. #endif
  3978. ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
  3979. }
  3980. }
  3981. free_rbufs(info, start, end);
  3982. return true;
  3983. cleanup:
  3984. return false;
  3985. }
  3986. /*
  3987. * pass receive buffer (RAW synchronous mode) to tty layer
  3988. * return true if buffer available, otherwise false
  3989. */
  3990. static bool rx_get_buf(struct slgt_info *info)
  3991. {
  3992. unsigned int i = info->rbuf_current;
  3993. unsigned int count;
  3994. if (!desc_complete(info->rbufs[i]))
  3995. return false;
  3996. count = desc_count(info->rbufs[i]);
  3997. switch(info->params.mode) {
  3998. case MGSL_MODE_MONOSYNC:
  3999. case MGSL_MODE_BISYNC:
  4000. case MGSL_MODE_XSYNC:
  4001. /* ignore residue in byte synchronous modes */
  4002. if (desc_residue(info->rbufs[i]))
  4003. count--;
  4004. break;
  4005. }
  4006. DBGDATA(info, info->rbufs[i].buf, count, "rx");
  4007. DBGINFO(("rx_get_buf size=%d\n", count));
  4008. if (count)
  4009. ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
  4010. info->flag_buf, count);
  4011. free_rbufs(info, i, i);
  4012. return true;
  4013. }
  4014. static void reset_tbufs(struct slgt_info *info)
  4015. {
  4016. unsigned int i;
  4017. info->tbuf_current = 0;
  4018. for (i=0 ; i < info->tbuf_count ; i++) {
  4019. info->tbufs[i].status = 0;
  4020. info->tbufs[i].count = 0;
  4021. }
  4022. }
  4023. /*
  4024. * return number of free transmit DMA buffers
  4025. */
  4026. static unsigned int free_tbuf_count(struct slgt_info *info)
  4027. {
  4028. unsigned int count = 0;
  4029. unsigned int i = info->tbuf_current;
  4030. do
  4031. {
  4032. if (desc_count(info->tbufs[i]))
  4033. break; /* buffer in use */
  4034. ++count;
  4035. if (++i == info->tbuf_count)
  4036. i=0;
  4037. } while (i != info->tbuf_current);
  4038. /* if tx DMA active, last zero count buffer is in use */
  4039. if (count && (rd_reg32(info, TDCSR) & BIT0))
  4040. --count;
  4041. return count;
  4042. }
  4043. /*
  4044. * return number of bytes in unsent transmit DMA buffers
  4045. * and the serial controller tx FIFO
  4046. */
  4047. static unsigned int tbuf_bytes(struct slgt_info *info)
  4048. {
  4049. unsigned int total_count = 0;
  4050. unsigned int i = info->tbuf_current;
  4051. unsigned int reg_value;
  4052. unsigned int count;
  4053. unsigned int active_buf_count = 0;
  4054. /*
  4055. * Add descriptor counts for all tx DMA buffers.
  4056. * If count is zero (cleared by DMA controller after read),
  4057. * the buffer is complete or is actively being read from.
  4058. *
  4059. * Record buf_count of last buffer with zero count starting
  4060. * from current ring position. buf_count is mirror
  4061. * copy of count and is not cleared by serial controller.
  4062. * If DMA controller is active, that buffer is actively
  4063. * being read so add to total.
  4064. */
  4065. do {
  4066. count = desc_count(info->tbufs[i]);
  4067. if (count)
  4068. total_count += count;
  4069. else if (!total_count)
  4070. active_buf_count = info->tbufs[i].buf_count;
  4071. if (++i == info->tbuf_count)
  4072. i = 0;
  4073. } while (i != info->tbuf_current);
  4074. /* read tx DMA status register */
  4075. reg_value = rd_reg32(info, TDCSR);
  4076. /* if tx DMA active, last zero count buffer is in use */
  4077. if (reg_value & BIT0)
  4078. total_count += active_buf_count;
  4079. /* add tx FIFO count = reg_value[15..8] */
  4080. total_count += (reg_value >> 8) & 0xff;
  4081. /* if transmitter active add one byte for shift register */
  4082. if (info->tx_active)
  4083. total_count++;
  4084. return total_count;
  4085. }
  4086. /*
  4087. * load data into transmit DMA buffer ring and start transmitter if needed
  4088. * return true if data accepted, otherwise false (buffers full)
  4089. */
  4090. static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size)
  4091. {
  4092. unsigned short count;
  4093. unsigned int i;
  4094. struct slgt_desc *d;
  4095. /* check required buffer space */
  4096. if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
  4097. return false;
  4098. DBGDATA(info, buf, size, "tx");
  4099. /*
  4100. * copy data to one or more DMA buffers in circular ring
  4101. * tbuf_start = first buffer for this data
  4102. * tbuf_current = next free buffer
  4103. *
  4104. * Copy all data before making data visible to DMA controller by
  4105. * setting descriptor count of the first buffer.
  4106. * This prevents an active DMA controller from reading the first DMA
  4107. * buffers of a frame and stopping before the final buffers are filled.
  4108. */
  4109. info->tbuf_start = i = info->tbuf_current;
  4110. while (size) {
  4111. d = &info->tbufs[i];
  4112. count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
  4113. memcpy(d->buf, buf, count);
  4114. size -= count;
  4115. buf += count;
  4116. /*
  4117. * set EOF bit for last buffer of HDLC frame or
  4118. * for every buffer in raw mode
  4119. */
  4120. if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
  4121. info->params.mode == MGSL_MODE_RAW)
  4122. set_desc_eof(*d, 1);
  4123. else
  4124. set_desc_eof(*d, 0);
  4125. /* set descriptor count for all but first buffer */
  4126. if (i != info->tbuf_start)
  4127. set_desc_count(*d, count);
  4128. d->buf_count = count;
  4129. if (++i == info->tbuf_count)
  4130. i = 0;
  4131. }
  4132. info->tbuf_current = i;
  4133. /* set first buffer count to make new data visible to DMA controller */
  4134. d = &info->tbufs[info->tbuf_start];
  4135. set_desc_count(*d, d->buf_count);
  4136. /* start transmitter if needed and update transmit timeout */
  4137. if (!info->tx_active)
  4138. tx_start(info);
  4139. update_tx_timer(info);
  4140. return true;
  4141. }
  4142. static int register_test(struct slgt_info *info)
  4143. {
  4144. static unsigned short patterns[] =
  4145. {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
  4146. static unsigned int count = ARRAY_SIZE(patterns);
  4147. unsigned int i;
  4148. int rc = 0;
  4149. for (i=0 ; i < count ; i++) {
  4150. wr_reg16(info, TIR, patterns[i]);
  4151. wr_reg16(info, BDR, patterns[(i+1)%count]);
  4152. if ((rd_reg16(info, TIR) != patterns[i]) ||
  4153. (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
  4154. rc = -ENODEV;
  4155. break;
  4156. }
  4157. }
  4158. info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
  4159. info->init_error = rc ? 0 : DiagStatus_AddressFailure;
  4160. return rc;
  4161. }
  4162. static int irq_test(struct slgt_info *info)
  4163. {
  4164. unsigned long timeout;
  4165. unsigned long flags;
  4166. struct tty_struct *oldtty = info->port.tty;
  4167. u32 speed = info->params.data_rate;
  4168. info->params.data_rate = 921600;
  4169. info->port.tty = NULL;
  4170. spin_lock_irqsave(&info->lock, flags);
  4171. async_mode(info);
  4172. slgt_irq_on(info, IRQ_TXIDLE);
  4173. /* enable transmitter */
  4174. wr_reg16(info, TCR,
  4175. (unsigned short)(rd_reg16(info, TCR) | BIT1));
  4176. /* write one byte and wait for tx idle */
  4177. wr_reg16(info, TDR, 0);
  4178. /* assume failure */
  4179. info->init_error = DiagStatus_IrqFailure;
  4180. info->irq_occurred = false;
  4181. spin_unlock_irqrestore(&info->lock, flags);
  4182. timeout=100;
  4183. while(timeout-- && !info->irq_occurred)
  4184. msleep_interruptible(10);
  4185. spin_lock_irqsave(&info->lock,flags);
  4186. reset_port(info);
  4187. spin_unlock_irqrestore(&info->lock,flags);
  4188. info->params.data_rate = speed;
  4189. info->port.tty = oldtty;
  4190. info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
  4191. return info->irq_occurred ? 0 : -ENODEV;
  4192. }
  4193. static int loopback_test_rx(struct slgt_info *info)
  4194. {
  4195. unsigned char *src, *dest;
  4196. int count;
  4197. if (desc_complete(info->rbufs[0])) {
  4198. count = desc_count(info->rbufs[0]);
  4199. src = info->rbufs[0].buf;
  4200. dest = info->tmp_rbuf;
  4201. for( ; count ; count-=2, src+=2) {
  4202. /* src=data byte (src+1)=status byte */
  4203. if (!(*(src+1) & (BIT9 + BIT8))) {
  4204. *dest = *src;
  4205. dest++;
  4206. info->tmp_rbuf_count++;
  4207. }
  4208. }
  4209. DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
  4210. return 1;
  4211. }
  4212. return 0;
  4213. }
  4214. static int loopback_test(struct slgt_info *info)
  4215. {
  4216. #define TESTFRAMESIZE 20
  4217. unsigned long timeout;
  4218. u16 count;
  4219. unsigned char buf[TESTFRAMESIZE];
  4220. int rc = -ENODEV;
  4221. unsigned long flags;
  4222. struct tty_struct *oldtty = info->port.tty;
  4223. MGSL_PARAMS params;
  4224. memcpy(&params, &info->params, sizeof(params));
  4225. info->params.mode = MGSL_MODE_ASYNC;
  4226. info->params.data_rate = 921600;
  4227. info->params.loopback = 1;
  4228. info->port.tty = NULL;
  4229. /* build and send transmit frame */
  4230. for (count = 0; count < TESTFRAMESIZE; ++count)
  4231. buf[count] = (unsigned char)count;
  4232. info->tmp_rbuf_count = 0;
  4233. memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
  4234. /* program hardware for HDLC and enabled receiver */
  4235. spin_lock_irqsave(&info->lock,flags);
  4236. async_mode(info);
  4237. rx_start(info);
  4238. tx_load(info, buf, count);
  4239. spin_unlock_irqrestore(&info->lock, flags);
  4240. /* wait for receive complete */
  4241. for (timeout = 100; timeout; --timeout) {
  4242. msleep_interruptible(10);
  4243. if (loopback_test_rx(info)) {
  4244. rc = 0;
  4245. break;
  4246. }
  4247. }
  4248. /* verify received frame length and contents */
  4249. if (!rc && (info->tmp_rbuf_count != count ||
  4250. memcmp(buf, info->tmp_rbuf, count))) {
  4251. rc = -ENODEV;
  4252. }
  4253. spin_lock_irqsave(&info->lock,flags);
  4254. reset_adapter(info);
  4255. spin_unlock_irqrestore(&info->lock,flags);
  4256. memcpy(&info->params, &params, sizeof(info->params));
  4257. info->port.tty = oldtty;
  4258. info->init_error = rc ? DiagStatus_DmaFailure : 0;
  4259. return rc;
  4260. }
  4261. static int adapter_test(struct slgt_info *info)
  4262. {
  4263. DBGINFO(("testing %s\n", info->device_name));
  4264. if (register_test(info) < 0) {
  4265. printk("register test failure %s addr=%08X\n",
  4266. info->device_name, info->phys_reg_addr);
  4267. } else if (irq_test(info) < 0) {
  4268. printk("IRQ test failure %s IRQ=%d\n",
  4269. info->device_name, info->irq_level);
  4270. } else if (loopback_test(info) < 0) {
  4271. printk("loopback test failure %s\n", info->device_name);
  4272. }
  4273. return info->init_error;
  4274. }
  4275. /*
  4276. * transmit timeout handler
  4277. */
  4278. static void tx_timeout(struct timer_list *t)
  4279. {
  4280. struct slgt_info *info = from_timer(info, t, tx_timer);
  4281. unsigned long flags;
  4282. DBGINFO(("%s tx_timeout\n", info->device_name));
  4283. if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
  4284. info->icount.txtimeout++;
  4285. }
  4286. spin_lock_irqsave(&info->lock,flags);
  4287. tx_stop(info);
  4288. spin_unlock_irqrestore(&info->lock,flags);
  4289. #if SYNCLINK_GENERIC_HDLC
  4290. if (info->netcount)
  4291. hdlcdev_tx_done(info);
  4292. else
  4293. #endif
  4294. bh_transmit(info);
  4295. }
  4296. /*
  4297. * receive buffer polling timer
  4298. */
  4299. static void rx_timeout(struct timer_list *t)
  4300. {
  4301. struct slgt_info *info = from_timer(info, t, rx_timer);
  4302. unsigned long flags;
  4303. DBGINFO(("%s rx_timeout\n", info->device_name));
  4304. spin_lock_irqsave(&info->lock, flags);
  4305. info->pending_bh |= BH_RECEIVE;
  4306. spin_unlock_irqrestore(&info->lock, flags);
  4307. bh_handler(&info->task);
  4308. }