zs.c 31 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * zs.c: Serial port driver for IOASIC DECstations.
  4. *
  5. * Derived from drivers/sbus/char/sunserial.c by Paul Mackerras.
  6. * Derived from drivers/macintosh/macserial.c by Harald Koerfgen.
  7. *
  8. * DECstation changes
  9. * Copyright (C) 1998-2000 Harald Koerfgen
  10. * Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
  11. *
  12. * For the rest of the code the original Copyright applies:
  13. * Copyright (C) 1996 Paul Mackerras ([email protected])
  14. * Copyright (C) 1995 David S. Miller ([email protected])
  15. *
  16. *
  17. * Note: for IOASIC systems the wiring is as follows:
  18. *
  19. * mouse/keyboard:
  20. * DIN-7 MJ-4 signal SCC
  21. * 2 1 TxD <- A.TxD
  22. * 3 4 RxD -> A.RxD
  23. *
  24. * EIA-232/EIA-423:
  25. * DB-25 MMJ-6 signal SCC
  26. * 2 2 TxD <- B.TxD
  27. * 3 5 RxD -> B.RxD
  28. * 4 RTS <- ~A.RTS
  29. * 5 CTS -> ~B.CTS
  30. * 6 6 DSR -> ~A.SYNC
  31. * 8 CD -> ~B.DCD
  32. * 12 DSRS(DCE) -> ~A.CTS (*)
  33. * 15 TxC -> B.TxC
  34. * 17 RxC -> B.RxC
  35. * 20 1 DTR <- ~A.DTR
  36. * 22 RI -> ~A.DCD
  37. * 23 DSRS(DTE) <- ~B.RTS
  38. *
  39. * (*) EIA-232 defines the signal at this pin to be SCD, while DSRS(DCE)
  40. * is shared with DSRS(DTE) at pin 23.
  41. *
  42. * As you can immediately notice the wiring of the RTS, DTR and DSR signals
  43. * is a bit odd. This makes the handling of port B unnecessarily
  44. * complicated and prevents the use of some automatic modes of operation.
  45. */
  46. #include <linux/bug.h>
  47. #include <linux/console.h>
  48. #include <linux/delay.h>
  49. #include <linux/errno.h>
  50. #include <linux/init.h>
  51. #include <linux/interrupt.h>
  52. #include <linux/io.h>
  53. #include <linux/ioport.h>
  54. #include <linux/irqflags.h>
  55. #include <linux/kernel.h>
  56. #include <linux/module.h>
  57. #include <linux/major.h>
  58. #include <linux/serial.h>
  59. #include <linux/serial_core.h>
  60. #include <linux/spinlock.h>
  61. #include <linux/sysrq.h>
  62. #include <linux/tty.h>
  63. #include <linux/tty_flip.h>
  64. #include <linux/types.h>
  65. #include <linux/atomic.h>
  66. #include <asm/dec/interrupts.h>
  67. #include <asm/dec/ioasic_addrs.h>
  68. #include <asm/dec/system.h>
  69. #include "zs.h"
  70. MODULE_AUTHOR("Maciej W. Rozycki <[email protected]>");
  71. MODULE_DESCRIPTION("DECstation Z85C30 serial driver");
  72. MODULE_LICENSE("GPL");
  73. static char zs_name[] __initdata = "DECstation Z85C30 serial driver version ";
  74. static char zs_version[] __initdata = "0.10";
  75. /*
  76. * It would be nice to dynamically allocate everything that
  77. * depends on ZS_NUM_SCCS, so we could support any number of
  78. * Z85C30s, but for now...
  79. */
  80. #define ZS_NUM_SCCS 2 /* Max # of ZS chips supported. */
  81. #define ZS_NUM_CHAN 2 /* 2 channels per chip. */
  82. #define ZS_CHAN_A 0 /* Index of the channel A. */
  83. #define ZS_CHAN_B 1 /* Index of the channel B. */
  84. #define ZS_CHAN_IO_SIZE 8 /* IOMEM space size. */
  85. #define ZS_CHAN_IO_STRIDE 4 /* Register alignment. */
  86. #define ZS_CHAN_IO_OFFSET 1 /* The SCC resides on the high byte
  87. of the 16-bit IOBUS. */
  88. #define ZS_CLOCK 7372800 /* Z85C30 PCLK input clock rate. */
  89. #define to_zport(uport) container_of(uport, struct zs_port, port)
  90. struct zs_parms {
  91. resource_size_t scc[ZS_NUM_SCCS];
  92. int irq[ZS_NUM_SCCS];
  93. };
  94. static struct zs_scc zs_sccs[ZS_NUM_SCCS];
  95. static u8 zs_init_regs[ZS_NUM_REGS] __initdata = {
  96. 0, /* write 0 */
  97. PAR_SPEC, /* write 1 */
  98. 0, /* write 2 */
  99. 0, /* write 3 */
  100. X16CLK | SB1, /* write 4 */
  101. 0, /* write 5 */
  102. 0, 0, 0, /* write 6, 7, 8 */
  103. MIE | DLC | NV, /* write 9 */
  104. NRZ, /* write 10 */
  105. TCBR | RCBR, /* write 11 */
  106. 0, 0, /* BRG time constant, write 12 + 13 */
  107. BRSRC | BRENABL, /* write 14 */
  108. 0, /* write 15 */
  109. };
  110. /*
  111. * Debugging.
  112. */
  113. #undef ZS_DEBUG_REGS
  114. /*
  115. * Reading and writing Z85C30 registers.
  116. */
  117. static void recovery_delay(void)
  118. {
  119. udelay(2);
  120. }
  121. static u8 read_zsreg(struct zs_port *zport, int reg)
  122. {
  123. void __iomem *control = zport->port.membase + ZS_CHAN_IO_OFFSET;
  124. u8 retval;
  125. if (reg != 0) {
  126. writeb(reg & 0xf, control);
  127. fast_iob();
  128. recovery_delay();
  129. }
  130. retval = readb(control);
  131. recovery_delay();
  132. return retval;
  133. }
  134. static void write_zsreg(struct zs_port *zport, int reg, u8 value)
  135. {
  136. void __iomem *control = zport->port.membase + ZS_CHAN_IO_OFFSET;
  137. if (reg != 0) {
  138. writeb(reg & 0xf, control);
  139. fast_iob(); recovery_delay();
  140. }
  141. writeb(value, control);
  142. fast_iob();
  143. recovery_delay();
  144. return;
  145. }
  146. static u8 read_zsdata(struct zs_port *zport)
  147. {
  148. void __iomem *data = zport->port.membase +
  149. ZS_CHAN_IO_STRIDE + ZS_CHAN_IO_OFFSET;
  150. u8 retval;
  151. retval = readb(data);
  152. recovery_delay();
  153. return retval;
  154. }
  155. static void write_zsdata(struct zs_port *zport, u8 value)
  156. {
  157. void __iomem *data = zport->port.membase +
  158. ZS_CHAN_IO_STRIDE + ZS_CHAN_IO_OFFSET;
  159. writeb(value, data);
  160. fast_iob();
  161. recovery_delay();
  162. return;
  163. }
  164. #ifdef ZS_DEBUG_REGS
  165. void zs_dump(void)
  166. {
  167. struct zs_port *zport;
  168. int i, j;
  169. for (i = 0; i < ZS_NUM_SCCS * ZS_NUM_CHAN; i++) {
  170. zport = &zs_sccs[i / ZS_NUM_CHAN].zport[i % ZS_NUM_CHAN];
  171. if (!zport->scc)
  172. continue;
  173. for (j = 0; j < 16; j++)
  174. printk("W%-2d = 0x%02x\t", j, zport->regs[j]);
  175. printk("\n");
  176. for (j = 0; j < 16; j++)
  177. printk("R%-2d = 0x%02x\t", j, read_zsreg(zport, j));
  178. printk("\n\n");
  179. }
  180. }
  181. #endif
  182. static void zs_spin_lock_cond_irq(spinlock_t *lock, int irq)
  183. {
  184. if (irq)
  185. spin_lock_irq(lock);
  186. else
  187. spin_lock(lock);
  188. }
  189. static void zs_spin_unlock_cond_irq(spinlock_t *lock, int irq)
  190. {
  191. if (irq)
  192. spin_unlock_irq(lock);
  193. else
  194. spin_unlock(lock);
  195. }
  196. static int zs_receive_drain(struct zs_port *zport)
  197. {
  198. int loops = 10000;
  199. while ((read_zsreg(zport, R0) & Rx_CH_AV) && --loops)
  200. read_zsdata(zport);
  201. return loops;
  202. }
  203. static int zs_transmit_drain(struct zs_port *zport, int irq)
  204. {
  205. struct zs_scc *scc = zport->scc;
  206. int loops = 10000;
  207. while (!(read_zsreg(zport, R0) & Tx_BUF_EMP) && --loops) {
  208. zs_spin_unlock_cond_irq(&scc->zlock, irq);
  209. udelay(2);
  210. zs_spin_lock_cond_irq(&scc->zlock, irq);
  211. }
  212. return loops;
  213. }
  214. static int zs_line_drain(struct zs_port *zport, int irq)
  215. {
  216. struct zs_scc *scc = zport->scc;
  217. int loops = 10000;
  218. while (!(read_zsreg(zport, R1) & ALL_SNT) && --loops) {
  219. zs_spin_unlock_cond_irq(&scc->zlock, irq);
  220. udelay(2);
  221. zs_spin_lock_cond_irq(&scc->zlock, irq);
  222. }
  223. return loops;
  224. }
  225. static void load_zsregs(struct zs_port *zport, u8 *regs, int irq)
  226. {
  227. /* Let the current transmission finish. */
  228. zs_line_drain(zport, irq);
  229. /* Load 'em up. */
  230. write_zsreg(zport, R3, regs[3] & ~RxENABLE);
  231. write_zsreg(zport, R5, regs[5] & ~TxENAB);
  232. write_zsreg(zport, R4, regs[4]);
  233. write_zsreg(zport, R9, regs[9]);
  234. write_zsreg(zport, R1, regs[1]);
  235. write_zsreg(zport, R2, regs[2]);
  236. write_zsreg(zport, R10, regs[10]);
  237. write_zsreg(zport, R14, regs[14] & ~BRENABL);
  238. write_zsreg(zport, R11, regs[11]);
  239. write_zsreg(zport, R12, regs[12]);
  240. write_zsreg(zport, R13, regs[13]);
  241. write_zsreg(zport, R14, regs[14]);
  242. write_zsreg(zport, R15, regs[15]);
  243. if (regs[3] & RxENABLE)
  244. write_zsreg(zport, R3, regs[3]);
  245. if (regs[5] & TxENAB)
  246. write_zsreg(zport, R5, regs[5]);
  247. return;
  248. }
  249. /*
  250. * Status handling routines.
  251. */
  252. /*
  253. * zs_tx_empty() -- get the transmitter empty status
  254. *
  255. * Purpose: Let user call ioctl() to get info when the UART physically
  256. * is emptied. On bus types like RS485, the transmitter must
  257. * release the bus after transmitting. This must be done when
  258. * the transmit shift register is empty, not be done when the
  259. * transmit holding register is empty. This functionality
  260. * allows an RS485 driver to be written in user space.
  261. */
  262. static unsigned int zs_tx_empty(struct uart_port *uport)
  263. {
  264. struct zs_port *zport = to_zport(uport);
  265. struct zs_scc *scc = zport->scc;
  266. unsigned long flags;
  267. u8 status;
  268. spin_lock_irqsave(&scc->zlock, flags);
  269. status = read_zsreg(zport, R1);
  270. spin_unlock_irqrestore(&scc->zlock, flags);
  271. return status & ALL_SNT ? TIOCSER_TEMT : 0;
  272. }
  273. static unsigned int zs_raw_get_ab_mctrl(struct zs_port *zport_a,
  274. struct zs_port *zport_b)
  275. {
  276. u8 status_a, status_b;
  277. unsigned int mctrl;
  278. status_a = read_zsreg(zport_a, R0);
  279. status_b = read_zsreg(zport_b, R0);
  280. mctrl = ((status_b & CTS) ? TIOCM_CTS : 0) |
  281. ((status_b & DCD) ? TIOCM_CAR : 0) |
  282. ((status_a & DCD) ? TIOCM_RNG : 0) |
  283. ((status_a & SYNC_HUNT) ? TIOCM_DSR : 0);
  284. return mctrl;
  285. }
  286. static unsigned int zs_raw_get_mctrl(struct zs_port *zport)
  287. {
  288. struct zs_port *zport_a = &zport->scc->zport[ZS_CHAN_A];
  289. return zport != zport_a ? zs_raw_get_ab_mctrl(zport_a, zport) : 0;
  290. }
  291. static unsigned int zs_raw_xor_mctrl(struct zs_port *zport)
  292. {
  293. struct zs_port *zport_a = &zport->scc->zport[ZS_CHAN_A];
  294. unsigned int mmask, mctrl, delta;
  295. u8 mask_a, mask_b;
  296. if (zport == zport_a)
  297. return 0;
  298. mask_a = zport_a->regs[15];
  299. mask_b = zport->regs[15];
  300. mmask = ((mask_b & CTSIE) ? TIOCM_CTS : 0) |
  301. ((mask_b & DCDIE) ? TIOCM_CAR : 0) |
  302. ((mask_a & DCDIE) ? TIOCM_RNG : 0) |
  303. ((mask_a & SYNCIE) ? TIOCM_DSR : 0);
  304. mctrl = zport->mctrl;
  305. if (mmask) {
  306. mctrl &= ~mmask;
  307. mctrl |= zs_raw_get_ab_mctrl(zport_a, zport) & mmask;
  308. }
  309. delta = mctrl ^ zport->mctrl;
  310. if (delta)
  311. zport->mctrl = mctrl;
  312. return delta;
  313. }
  314. static unsigned int zs_get_mctrl(struct uart_port *uport)
  315. {
  316. struct zs_port *zport = to_zport(uport);
  317. struct zs_scc *scc = zport->scc;
  318. unsigned int mctrl;
  319. spin_lock(&scc->zlock);
  320. mctrl = zs_raw_get_mctrl(zport);
  321. spin_unlock(&scc->zlock);
  322. return mctrl;
  323. }
  324. static void zs_set_mctrl(struct uart_port *uport, unsigned int mctrl)
  325. {
  326. struct zs_port *zport = to_zport(uport);
  327. struct zs_scc *scc = zport->scc;
  328. struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];
  329. u8 oldloop, newloop;
  330. spin_lock(&scc->zlock);
  331. if (zport != zport_a) {
  332. if (mctrl & TIOCM_DTR)
  333. zport_a->regs[5] |= DTR;
  334. else
  335. zport_a->regs[5] &= ~DTR;
  336. if (mctrl & TIOCM_RTS)
  337. zport_a->regs[5] |= RTS;
  338. else
  339. zport_a->regs[5] &= ~RTS;
  340. write_zsreg(zport_a, R5, zport_a->regs[5]);
  341. }
  342. /* Rarely modified, so don't poke at hardware unless necessary. */
  343. oldloop = zport->regs[14];
  344. newloop = oldloop;
  345. if (mctrl & TIOCM_LOOP)
  346. newloop |= LOOPBAK;
  347. else
  348. newloop &= ~LOOPBAK;
  349. if (newloop != oldloop) {
  350. zport->regs[14] = newloop;
  351. write_zsreg(zport, R14, zport->regs[14]);
  352. }
  353. spin_unlock(&scc->zlock);
  354. }
  355. static void zs_raw_stop_tx(struct zs_port *zport)
  356. {
  357. write_zsreg(zport, R0, RES_Tx_P);
  358. zport->tx_stopped = 1;
  359. }
  360. static void zs_stop_tx(struct uart_port *uport)
  361. {
  362. struct zs_port *zport = to_zport(uport);
  363. struct zs_scc *scc = zport->scc;
  364. spin_lock(&scc->zlock);
  365. zs_raw_stop_tx(zport);
  366. spin_unlock(&scc->zlock);
  367. }
  368. static void zs_raw_transmit_chars(struct zs_port *);
  369. static void zs_start_tx(struct uart_port *uport)
  370. {
  371. struct zs_port *zport = to_zport(uport);
  372. struct zs_scc *scc = zport->scc;
  373. spin_lock(&scc->zlock);
  374. if (zport->tx_stopped) {
  375. zs_transmit_drain(zport, 0);
  376. zport->tx_stopped = 0;
  377. zs_raw_transmit_chars(zport);
  378. }
  379. spin_unlock(&scc->zlock);
  380. }
  381. static void zs_stop_rx(struct uart_port *uport)
  382. {
  383. struct zs_port *zport = to_zport(uport);
  384. struct zs_scc *scc = zport->scc;
  385. struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];
  386. spin_lock(&scc->zlock);
  387. zport->regs[15] &= ~BRKIE;
  388. zport->regs[1] &= ~(RxINT_MASK | TxINT_ENAB);
  389. zport->regs[1] |= RxINT_DISAB;
  390. if (zport != zport_a) {
  391. /* A-side DCD tracks RI and SYNC tracks DSR. */
  392. zport_a->regs[15] &= ~(DCDIE | SYNCIE);
  393. write_zsreg(zport_a, R15, zport_a->regs[15]);
  394. if (!(zport_a->regs[15] & BRKIE)) {
  395. zport_a->regs[1] &= ~EXT_INT_ENAB;
  396. write_zsreg(zport_a, R1, zport_a->regs[1]);
  397. }
  398. /* This-side DCD tracks DCD and CTS tracks CTS. */
  399. zport->regs[15] &= ~(DCDIE | CTSIE);
  400. zport->regs[1] &= ~EXT_INT_ENAB;
  401. } else {
  402. /* DCD tracks RI and SYNC tracks DSR for the B side. */
  403. if (!(zport->regs[15] & (DCDIE | SYNCIE)))
  404. zport->regs[1] &= ~EXT_INT_ENAB;
  405. }
  406. write_zsreg(zport, R15, zport->regs[15]);
  407. write_zsreg(zport, R1, zport->regs[1]);
  408. spin_unlock(&scc->zlock);
  409. }
  410. static void zs_enable_ms(struct uart_port *uport)
  411. {
  412. struct zs_port *zport = to_zport(uport);
  413. struct zs_scc *scc = zport->scc;
  414. struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];
  415. if (zport == zport_a)
  416. return;
  417. spin_lock(&scc->zlock);
  418. /* Clear Ext interrupts if not being handled already. */
  419. if (!(zport_a->regs[1] & EXT_INT_ENAB))
  420. write_zsreg(zport_a, R0, RES_EXT_INT);
  421. /* A-side DCD tracks RI and SYNC tracks DSR. */
  422. zport_a->regs[1] |= EXT_INT_ENAB;
  423. zport_a->regs[15] |= DCDIE | SYNCIE;
  424. /* This-side DCD tracks DCD and CTS tracks CTS. */
  425. zport->regs[15] |= DCDIE | CTSIE;
  426. zs_raw_xor_mctrl(zport);
  427. write_zsreg(zport_a, R1, zport_a->regs[1]);
  428. write_zsreg(zport_a, R15, zport_a->regs[15]);
  429. write_zsreg(zport, R15, zport->regs[15]);
  430. spin_unlock(&scc->zlock);
  431. }
  432. static void zs_break_ctl(struct uart_port *uport, int break_state)
  433. {
  434. struct zs_port *zport = to_zport(uport);
  435. struct zs_scc *scc = zport->scc;
  436. unsigned long flags;
  437. spin_lock_irqsave(&scc->zlock, flags);
  438. if (break_state == -1)
  439. zport->regs[5] |= SND_BRK;
  440. else
  441. zport->regs[5] &= ~SND_BRK;
  442. write_zsreg(zport, R5, zport->regs[5]);
  443. spin_unlock_irqrestore(&scc->zlock, flags);
  444. }
  445. /*
  446. * Interrupt handling routines.
  447. */
  448. #define Rx_BRK 0x0100 /* BREAK event software flag. */
  449. #define Rx_SYS 0x0200 /* SysRq event software flag. */
  450. static void zs_receive_chars(struct zs_port *zport)
  451. {
  452. struct uart_port *uport = &zport->port;
  453. struct zs_scc *scc = zport->scc;
  454. struct uart_icount *icount;
  455. unsigned int avail, status, ch, flag;
  456. int count;
  457. for (count = 16; count; count--) {
  458. spin_lock(&scc->zlock);
  459. avail = read_zsreg(zport, R0) & Rx_CH_AV;
  460. spin_unlock(&scc->zlock);
  461. if (!avail)
  462. break;
  463. spin_lock(&scc->zlock);
  464. status = read_zsreg(zport, R1) & (Rx_OVR | FRM_ERR | PAR_ERR);
  465. ch = read_zsdata(zport);
  466. spin_unlock(&scc->zlock);
  467. flag = TTY_NORMAL;
  468. icount = &uport->icount;
  469. icount->rx++;
  470. /* Handle the null char got when BREAK is removed. */
  471. if (!ch)
  472. status |= zport->tty_break;
  473. if (unlikely(status &
  474. (Rx_OVR | FRM_ERR | PAR_ERR | Rx_SYS | Rx_BRK))) {
  475. zport->tty_break = 0;
  476. /* Reset the error indication. */
  477. if (status & (Rx_OVR | FRM_ERR | PAR_ERR)) {
  478. spin_lock(&scc->zlock);
  479. write_zsreg(zport, R0, ERR_RES);
  480. spin_unlock(&scc->zlock);
  481. }
  482. if (status & (Rx_SYS | Rx_BRK)) {
  483. icount->brk++;
  484. /* SysRq discards the null char. */
  485. if (status & Rx_SYS)
  486. continue;
  487. } else if (status & FRM_ERR)
  488. icount->frame++;
  489. else if (status & PAR_ERR)
  490. icount->parity++;
  491. if (status & Rx_OVR)
  492. icount->overrun++;
  493. status &= uport->read_status_mask;
  494. if (status & Rx_BRK)
  495. flag = TTY_BREAK;
  496. else if (status & FRM_ERR)
  497. flag = TTY_FRAME;
  498. else if (status & PAR_ERR)
  499. flag = TTY_PARITY;
  500. }
  501. if (uart_handle_sysrq_char(uport, ch))
  502. continue;
  503. uart_insert_char(uport, status, Rx_OVR, ch, flag);
  504. }
  505. tty_flip_buffer_push(&uport->state->port);
  506. }
  507. static void zs_raw_transmit_chars(struct zs_port *zport)
  508. {
  509. struct circ_buf *xmit = &zport->port.state->xmit;
  510. /* XON/XOFF chars. */
  511. if (zport->port.x_char) {
  512. write_zsdata(zport, zport->port.x_char);
  513. zport->port.icount.tx++;
  514. zport->port.x_char = 0;
  515. return;
  516. }
  517. /* If nothing to do or stopped or hardware stopped. */
  518. if (uart_circ_empty(xmit) || uart_tx_stopped(&zport->port)) {
  519. zs_raw_stop_tx(zport);
  520. return;
  521. }
  522. /* Send char. */
  523. write_zsdata(zport, xmit->buf[xmit->tail]);
  524. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  525. zport->port.icount.tx++;
  526. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  527. uart_write_wakeup(&zport->port);
  528. /* Are we are done? */
  529. if (uart_circ_empty(xmit))
  530. zs_raw_stop_tx(zport);
  531. }
  532. static void zs_transmit_chars(struct zs_port *zport)
  533. {
  534. struct zs_scc *scc = zport->scc;
  535. spin_lock(&scc->zlock);
  536. zs_raw_transmit_chars(zport);
  537. spin_unlock(&scc->zlock);
  538. }
  539. static void zs_status_handle(struct zs_port *zport, struct zs_port *zport_a)
  540. {
  541. struct uart_port *uport = &zport->port;
  542. struct zs_scc *scc = zport->scc;
  543. unsigned int delta;
  544. u8 status, brk;
  545. spin_lock(&scc->zlock);
  546. /* Get status from Read Register 0. */
  547. status = read_zsreg(zport, R0);
  548. if (zport->regs[15] & BRKIE) {
  549. brk = status & BRK_ABRT;
  550. if (brk && !zport->brk) {
  551. spin_unlock(&scc->zlock);
  552. if (uart_handle_break(uport))
  553. zport->tty_break = Rx_SYS;
  554. else
  555. zport->tty_break = Rx_BRK;
  556. spin_lock(&scc->zlock);
  557. }
  558. zport->brk = brk;
  559. }
  560. if (zport != zport_a) {
  561. delta = zs_raw_xor_mctrl(zport);
  562. spin_unlock(&scc->zlock);
  563. if (delta & TIOCM_CTS)
  564. uart_handle_cts_change(uport,
  565. zport->mctrl & TIOCM_CTS);
  566. if (delta & TIOCM_CAR)
  567. uart_handle_dcd_change(uport,
  568. zport->mctrl & TIOCM_CAR);
  569. if (delta & TIOCM_RNG)
  570. uport->icount.dsr++;
  571. if (delta & TIOCM_DSR)
  572. uport->icount.rng++;
  573. if (delta)
  574. wake_up_interruptible(&uport->state->port.delta_msr_wait);
  575. spin_lock(&scc->zlock);
  576. }
  577. /* Clear the status condition... */
  578. write_zsreg(zport, R0, RES_EXT_INT);
  579. spin_unlock(&scc->zlock);
  580. }
  581. /*
  582. * This is the Z85C30 driver's generic interrupt routine.
  583. */
  584. static irqreturn_t zs_interrupt(int irq, void *dev_id)
  585. {
  586. struct zs_scc *scc = dev_id;
  587. struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];
  588. struct zs_port *zport_b = &scc->zport[ZS_CHAN_B];
  589. irqreturn_t status = IRQ_NONE;
  590. u8 zs_intreg;
  591. int count;
  592. /*
  593. * NOTE: The read register 3, which holds the irq status,
  594. * does so for both channels on each chip. Although
  595. * the status value itself must be read from the A
  596. * channel and is only valid when read from channel A.
  597. * Yes... broken hardware...
  598. */
  599. for (count = 16; count; count--) {
  600. spin_lock(&scc->zlock);
  601. zs_intreg = read_zsreg(zport_a, R3);
  602. spin_unlock(&scc->zlock);
  603. if (!zs_intreg)
  604. break;
  605. /*
  606. * We do not like losing characters, so we prioritise
  607. * interrupt sources a little bit differently than
  608. * the SCC would, was it allowed to.
  609. */
  610. if (zs_intreg & CHBRxIP)
  611. zs_receive_chars(zport_b);
  612. if (zs_intreg & CHARxIP)
  613. zs_receive_chars(zport_a);
  614. if (zs_intreg & CHBEXT)
  615. zs_status_handle(zport_b, zport_a);
  616. if (zs_intreg & CHAEXT)
  617. zs_status_handle(zport_a, zport_a);
  618. if (zs_intreg & CHBTxIP)
  619. zs_transmit_chars(zport_b);
  620. if (zs_intreg & CHATxIP)
  621. zs_transmit_chars(zport_a);
  622. status = IRQ_HANDLED;
  623. }
  624. return status;
  625. }
  626. /*
  627. * Finally, routines used to initialize the serial port.
  628. */
  629. static int zs_startup(struct uart_port *uport)
  630. {
  631. struct zs_port *zport = to_zport(uport);
  632. struct zs_scc *scc = zport->scc;
  633. unsigned long flags;
  634. int irq_guard;
  635. int ret;
  636. irq_guard = atomic_add_return(1, &scc->irq_guard);
  637. if (irq_guard == 1) {
  638. ret = request_irq(zport->port.irq, zs_interrupt,
  639. IRQF_SHARED, "scc", scc);
  640. if (ret) {
  641. atomic_add(-1, &scc->irq_guard);
  642. printk(KERN_ERR "zs: can't get irq %d\n",
  643. zport->port.irq);
  644. return ret;
  645. }
  646. }
  647. spin_lock_irqsave(&scc->zlock, flags);
  648. /* Clear the receive FIFO. */
  649. zs_receive_drain(zport);
  650. /* Clear the interrupt registers. */
  651. write_zsreg(zport, R0, ERR_RES);
  652. write_zsreg(zport, R0, RES_Tx_P);
  653. /* But Ext only if not being handled already. */
  654. if (!(zport->regs[1] & EXT_INT_ENAB))
  655. write_zsreg(zport, R0, RES_EXT_INT);
  656. /* Finally, enable sequencing and interrupts. */
  657. zport->regs[1] &= ~RxINT_MASK;
  658. zport->regs[1] |= RxINT_ALL | TxINT_ENAB | EXT_INT_ENAB;
  659. zport->regs[3] |= RxENABLE;
  660. zport->regs[15] |= BRKIE;
  661. write_zsreg(zport, R1, zport->regs[1]);
  662. write_zsreg(zport, R3, zport->regs[3]);
  663. write_zsreg(zport, R5, zport->regs[5]);
  664. write_zsreg(zport, R15, zport->regs[15]);
  665. /* Record the current state of RR0. */
  666. zport->mctrl = zs_raw_get_mctrl(zport);
  667. zport->brk = read_zsreg(zport, R0) & BRK_ABRT;
  668. zport->tx_stopped = 1;
  669. spin_unlock_irqrestore(&scc->zlock, flags);
  670. return 0;
  671. }
  672. static void zs_shutdown(struct uart_port *uport)
  673. {
  674. struct zs_port *zport = to_zport(uport);
  675. struct zs_scc *scc = zport->scc;
  676. unsigned long flags;
  677. int irq_guard;
  678. spin_lock_irqsave(&scc->zlock, flags);
  679. zport->regs[3] &= ~RxENABLE;
  680. write_zsreg(zport, R5, zport->regs[5]);
  681. write_zsreg(zport, R3, zport->regs[3]);
  682. spin_unlock_irqrestore(&scc->zlock, flags);
  683. irq_guard = atomic_add_return(-1, &scc->irq_guard);
  684. if (!irq_guard)
  685. free_irq(zport->port.irq, scc);
  686. }
  687. static void zs_reset(struct zs_port *zport)
  688. {
  689. struct zs_scc *scc = zport->scc;
  690. int irq;
  691. unsigned long flags;
  692. spin_lock_irqsave(&scc->zlock, flags);
  693. irq = !irqs_disabled_flags(flags);
  694. if (!scc->initialised) {
  695. /* Reset the pointer first, just in case... */
  696. read_zsreg(zport, R0);
  697. /* And let the current transmission finish. */
  698. zs_line_drain(zport, irq);
  699. write_zsreg(zport, R9, FHWRES);
  700. udelay(10);
  701. write_zsreg(zport, R9, 0);
  702. scc->initialised = 1;
  703. }
  704. load_zsregs(zport, zport->regs, irq);
  705. spin_unlock_irqrestore(&scc->zlock, flags);
  706. }
  707. static void zs_set_termios(struct uart_port *uport, struct ktermios *termios,
  708. const struct ktermios *old_termios)
  709. {
  710. struct zs_port *zport = to_zport(uport);
  711. struct zs_scc *scc = zport->scc;
  712. struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];
  713. int irq;
  714. unsigned int baud, brg;
  715. unsigned long flags;
  716. spin_lock_irqsave(&scc->zlock, flags);
  717. irq = !irqs_disabled_flags(flags);
  718. /* Byte size. */
  719. zport->regs[3] &= ~RxNBITS_MASK;
  720. zport->regs[5] &= ~TxNBITS_MASK;
  721. switch (termios->c_cflag & CSIZE) {
  722. case CS5:
  723. zport->regs[3] |= Rx5;
  724. zport->regs[5] |= Tx5;
  725. break;
  726. case CS6:
  727. zport->regs[3] |= Rx6;
  728. zport->regs[5] |= Tx6;
  729. break;
  730. case CS7:
  731. zport->regs[3] |= Rx7;
  732. zport->regs[5] |= Tx7;
  733. break;
  734. case CS8:
  735. default:
  736. zport->regs[3] |= Rx8;
  737. zport->regs[5] |= Tx8;
  738. break;
  739. }
  740. /* Parity and stop bits. */
  741. zport->regs[4] &= ~(XCLK_MASK | SB_MASK | PAR_ENA | PAR_EVEN);
  742. if (termios->c_cflag & CSTOPB)
  743. zport->regs[4] |= SB2;
  744. else
  745. zport->regs[4] |= SB1;
  746. if (termios->c_cflag & PARENB)
  747. zport->regs[4] |= PAR_ENA;
  748. if (!(termios->c_cflag & PARODD))
  749. zport->regs[4] |= PAR_EVEN;
  750. switch (zport->clk_mode) {
  751. case 64:
  752. zport->regs[4] |= X64CLK;
  753. break;
  754. case 32:
  755. zport->regs[4] |= X32CLK;
  756. break;
  757. case 16:
  758. zport->regs[4] |= X16CLK;
  759. break;
  760. case 1:
  761. zport->regs[4] |= X1CLK;
  762. break;
  763. default:
  764. BUG();
  765. }
  766. baud = uart_get_baud_rate(uport, termios, old_termios, 0,
  767. uport->uartclk / zport->clk_mode / 4);
  768. brg = ZS_BPS_TO_BRG(baud, uport->uartclk / zport->clk_mode);
  769. zport->regs[12] = brg & 0xff;
  770. zport->regs[13] = (brg >> 8) & 0xff;
  771. uart_update_timeout(uport, termios->c_cflag, baud);
  772. uport->read_status_mask = Rx_OVR;
  773. if (termios->c_iflag & INPCK)
  774. uport->read_status_mask |= FRM_ERR | PAR_ERR;
  775. if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
  776. uport->read_status_mask |= Rx_BRK;
  777. uport->ignore_status_mask = 0;
  778. if (termios->c_iflag & IGNPAR)
  779. uport->ignore_status_mask |= FRM_ERR | PAR_ERR;
  780. if (termios->c_iflag & IGNBRK) {
  781. uport->ignore_status_mask |= Rx_BRK;
  782. if (termios->c_iflag & IGNPAR)
  783. uport->ignore_status_mask |= Rx_OVR;
  784. }
  785. if (termios->c_cflag & CREAD)
  786. zport->regs[3] |= RxENABLE;
  787. else
  788. zport->regs[3] &= ~RxENABLE;
  789. if (zport != zport_a) {
  790. if (!(termios->c_cflag & CLOCAL)) {
  791. zport->regs[15] |= DCDIE;
  792. } else
  793. zport->regs[15] &= ~DCDIE;
  794. if (termios->c_cflag & CRTSCTS) {
  795. zport->regs[15] |= CTSIE;
  796. } else
  797. zport->regs[15] &= ~CTSIE;
  798. zs_raw_xor_mctrl(zport);
  799. }
  800. /* Load up the new values. */
  801. load_zsregs(zport, zport->regs, irq);
  802. spin_unlock_irqrestore(&scc->zlock, flags);
  803. }
  804. /*
  805. * Hack alert!
  806. * Required solely so that the initial PROM-based console
  807. * works undisturbed in parallel with this one.
  808. */
  809. static void zs_pm(struct uart_port *uport, unsigned int state,
  810. unsigned int oldstate)
  811. {
  812. struct zs_port *zport = to_zport(uport);
  813. if (state < 3)
  814. zport->regs[5] |= TxENAB;
  815. else
  816. zport->regs[5] &= ~TxENAB;
  817. write_zsreg(zport, R5, zport->regs[5]);
  818. }
  819. static const char *zs_type(struct uart_port *uport)
  820. {
  821. return "Z85C30 SCC";
  822. }
  823. static void zs_release_port(struct uart_port *uport)
  824. {
  825. iounmap(uport->membase);
  826. uport->membase = NULL;
  827. release_mem_region(uport->mapbase, ZS_CHAN_IO_SIZE);
  828. }
  829. static int zs_map_port(struct uart_port *uport)
  830. {
  831. if (!uport->membase)
  832. uport->membase = ioremap(uport->mapbase,
  833. ZS_CHAN_IO_SIZE);
  834. if (!uport->membase) {
  835. printk(KERN_ERR "zs: Cannot map MMIO\n");
  836. return -ENOMEM;
  837. }
  838. return 0;
  839. }
  840. static int zs_request_port(struct uart_port *uport)
  841. {
  842. int ret;
  843. if (!request_mem_region(uport->mapbase, ZS_CHAN_IO_SIZE, "scc")) {
  844. printk(KERN_ERR "zs: Unable to reserve MMIO resource\n");
  845. return -EBUSY;
  846. }
  847. ret = zs_map_port(uport);
  848. if (ret) {
  849. release_mem_region(uport->mapbase, ZS_CHAN_IO_SIZE);
  850. return ret;
  851. }
  852. return 0;
  853. }
  854. static void zs_config_port(struct uart_port *uport, int flags)
  855. {
  856. struct zs_port *zport = to_zport(uport);
  857. if (flags & UART_CONFIG_TYPE) {
  858. if (zs_request_port(uport))
  859. return;
  860. uport->type = PORT_ZS;
  861. zs_reset(zport);
  862. }
  863. }
  864. static int zs_verify_port(struct uart_port *uport, struct serial_struct *ser)
  865. {
  866. struct zs_port *zport = to_zport(uport);
  867. int ret = 0;
  868. if (ser->type != PORT_UNKNOWN && ser->type != PORT_ZS)
  869. ret = -EINVAL;
  870. if (ser->irq != uport->irq)
  871. ret = -EINVAL;
  872. if (ser->baud_base != uport->uartclk / zport->clk_mode / 4)
  873. ret = -EINVAL;
  874. return ret;
  875. }
  876. static const struct uart_ops zs_ops = {
  877. .tx_empty = zs_tx_empty,
  878. .set_mctrl = zs_set_mctrl,
  879. .get_mctrl = zs_get_mctrl,
  880. .stop_tx = zs_stop_tx,
  881. .start_tx = zs_start_tx,
  882. .stop_rx = zs_stop_rx,
  883. .enable_ms = zs_enable_ms,
  884. .break_ctl = zs_break_ctl,
  885. .startup = zs_startup,
  886. .shutdown = zs_shutdown,
  887. .set_termios = zs_set_termios,
  888. .pm = zs_pm,
  889. .type = zs_type,
  890. .release_port = zs_release_port,
  891. .request_port = zs_request_port,
  892. .config_port = zs_config_port,
  893. .verify_port = zs_verify_port,
  894. };
  895. /*
  896. * Initialize Z85C30 port structures.
  897. */
  898. static int __init zs_probe_sccs(void)
  899. {
  900. static int probed;
  901. struct zs_parms zs_parms;
  902. int chip, side, irq;
  903. int n_chips = 0;
  904. int i;
  905. if (probed)
  906. return 0;
  907. irq = dec_interrupt[DEC_IRQ_SCC0];
  908. if (irq >= 0) {
  909. zs_parms.scc[n_chips] = IOASIC_SCC0;
  910. zs_parms.irq[n_chips] = dec_interrupt[DEC_IRQ_SCC0];
  911. n_chips++;
  912. }
  913. irq = dec_interrupt[DEC_IRQ_SCC1];
  914. if (irq >= 0) {
  915. zs_parms.scc[n_chips] = IOASIC_SCC1;
  916. zs_parms.irq[n_chips] = dec_interrupt[DEC_IRQ_SCC1];
  917. n_chips++;
  918. }
  919. if (!n_chips)
  920. return -ENXIO;
  921. probed = 1;
  922. for (chip = 0; chip < n_chips; chip++) {
  923. spin_lock_init(&zs_sccs[chip].zlock);
  924. for (side = 0; side < ZS_NUM_CHAN; side++) {
  925. struct zs_port *zport = &zs_sccs[chip].zport[side];
  926. struct uart_port *uport = &zport->port;
  927. zport->scc = &zs_sccs[chip];
  928. zport->clk_mode = 16;
  929. uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_ZS_CONSOLE);
  930. uport->irq = zs_parms.irq[chip];
  931. uport->uartclk = ZS_CLOCK;
  932. uport->fifosize = 1;
  933. uport->iotype = UPIO_MEM;
  934. uport->flags = UPF_BOOT_AUTOCONF;
  935. uport->ops = &zs_ops;
  936. uport->line = chip * ZS_NUM_CHAN + side;
  937. uport->mapbase = dec_kn_slot_base +
  938. zs_parms.scc[chip] +
  939. (side ^ ZS_CHAN_B) * ZS_CHAN_IO_SIZE;
  940. for (i = 0; i < ZS_NUM_REGS; i++)
  941. zport->regs[i] = zs_init_regs[i];
  942. }
  943. }
  944. return 0;
  945. }
  946. #ifdef CONFIG_SERIAL_ZS_CONSOLE
  947. static void zs_console_putchar(struct uart_port *uport, unsigned char ch)
  948. {
  949. struct zs_port *zport = to_zport(uport);
  950. struct zs_scc *scc = zport->scc;
  951. int irq;
  952. unsigned long flags;
  953. spin_lock_irqsave(&scc->zlock, flags);
  954. irq = !irqs_disabled_flags(flags);
  955. if (zs_transmit_drain(zport, irq))
  956. write_zsdata(zport, ch);
  957. spin_unlock_irqrestore(&scc->zlock, flags);
  958. }
  959. /*
  960. * Print a string to the serial port trying not to disturb
  961. * any possible real use of the port...
  962. */
  963. static void zs_console_write(struct console *co, const char *s,
  964. unsigned int count)
  965. {
  966. int chip = co->index / ZS_NUM_CHAN, side = co->index % ZS_NUM_CHAN;
  967. struct zs_port *zport = &zs_sccs[chip].zport[side];
  968. struct zs_scc *scc = zport->scc;
  969. unsigned long flags;
  970. u8 txint, txenb;
  971. int irq;
  972. /* Disable transmit interrupts and enable the transmitter. */
  973. spin_lock_irqsave(&scc->zlock, flags);
  974. txint = zport->regs[1];
  975. txenb = zport->regs[5];
  976. if (txint & TxINT_ENAB) {
  977. zport->regs[1] = txint & ~TxINT_ENAB;
  978. write_zsreg(zport, R1, zport->regs[1]);
  979. }
  980. if (!(txenb & TxENAB)) {
  981. zport->regs[5] = txenb | TxENAB;
  982. write_zsreg(zport, R5, zport->regs[5]);
  983. }
  984. spin_unlock_irqrestore(&scc->zlock, flags);
  985. uart_console_write(&zport->port, s, count, zs_console_putchar);
  986. /* Restore transmit interrupts and the transmitter enable. */
  987. spin_lock_irqsave(&scc->zlock, flags);
  988. irq = !irqs_disabled_flags(flags);
  989. zs_line_drain(zport, irq);
  990. if (!(txenb & TxENAB)) {
  991. zport->regs[5] &= ~TxENAB;
  992. write_zsreg(zport, R5, zport->regs[5]);
  993. }
  994. if (txint & TxINT_ENAB) {
  995. zport->regs[1] |= TxINT_ENAB;
  996. write_zsreg(zport, R1, zport->regs[1]);
  997. /* Resume any transmission as the TxIP bit won't be set. */
  998. if (!zport->tx_stopped)
  999. zs_raw_transmit_chars(zport);
  1000. }
  1001. spin_unlock_irqrestore(&scc->zlock, flags);
  1002. }
  1003. /*
  1004. * Setup serial console baud/bits/parity. We do two things here:
  1005. * - construct a cflag setting for the first uart_open()
  1006. * - initialise the serial port
  1007. * Return non-zero if we didn't find a serial port.
  1008. */
  1009. static int __init zs_console_setup(struct console *co, char *options)
  1010. {
  1011. int chip = co->index / ZS_NUM_CHAN, side = co->index % ZS_NUM_CHAN;
  1012. struct zs_port *zport = &zs_sccs[chip].zport[side];
  1013. struct uart_port *uport = &zport->port;
  1014. int baud = 9600;
  1015. int bits = 8;
  1016. int parity = 'n';
  1017. int flow = 'n';
  1018. int ret;
  1019. ret = zs_map_port(uport);
  1020. if (ret)
  1021. return ret;
  1022. zs_reset(zport);
  1023. zs_pm(uport, 0, -1);
  1024. if (options)
  1025. uart_parse_options(options, &baud, &parity, &bits, &flow);
  1026. return uart_set_options(uport, co, baud, parity, bits, flow);
  1027. }
  1028. static struct uart_driver zs_reg;
  1029. static struct console zs_console = {
  1030. .name = "ttyS",
  1031. .write = zs_console_write,
  1032. .device = uart_console_device,
  1033. .setup = zs_console_setup,
  1034. .flags = CON_PRINTBUFFER,
  1035. .index = -1,
  1036. .data = &zs_reg,
  1037. };
  1038. /*
  1039. * Register console.
  1040. */
  1041. static int __init zs_serial_console_init(void)
  1042. {
  1043. int ret;
  1044. ret = zs_probe_sccs();
  1045. if (ret)
  1046. return ret;
  1047. register_console(&zs_console);
  1048. return 0;
  1049. }
  1050. console_initcall(zs_serial_console_init);
  1051. #define SERIAL_ZS_CONSOLE &zs_console
  1052. #else
  1053. #define SERIAL_ZS_CONSOLE NULL
  1054. #endif /* CONFIG_SERIAL_ZS_CONSOLE */
  1055. static struct uart_driver zs_reg = {
  1056. .owner = THIS_MODULE,
  1057. .driver_name = "serial",
  1058. .dev_name = "ttyS",
  1059. .major = TTY_MAJOR,
  1060. .minor = 64,
  1061. .nr = ZS_NUM_SCCS * ZS_NUM_CHAN,
  1062. .cons = SERIAL_ZS_CONSOLE,
  1063. };
  1064. /* zs_init inits the driver. */
  1065. static int __init zs_init(void)
  1066. {
  1067. int i, ret;
  1068. pr_info("%s%s\n", zs_name, zs_version);
  1069. /* Find out how many Z85C30 SCCs we have. */
  1070. ret = zs_probe_sccs();
  1071. if (ret)
  1072. return ret;
  1073. ret = uart_register_driver(&zs_reg);
  1074. if (ret)
  1075. return ret;
  1076. for (i = 0; i < ZS_NUM_SCCS * ZS_NUM_CHAN; i++) {
  1077. struct zs_scc *scc = &zs_sccs[i / ZS_NUM_CHAN];
  1078. struct zs_port *zport = &scc->zport[i % ZS_NUM_CHAN];
  1079. struct uart_port *uport = &zport->port;
  1080. if (zport->scc)
  1081. uart_add_one_port(&zs_reg, uport);
  1082. }
  1083. return 0;
  1084. }
  1085. static void __exit zs_exit(void)
  1086. {
  1087. int i;
  1088. for (i = ZS_NUM_SCCS * ZS_NUM_CHAN - 1; i >= 0; i--) {
  1089. struct zs_scc *scc = &zs_sccs[i / ZS_NUM_CHAN];
  1090. struct zs_port *zport = &scc->zport[i % ZS_NUM_CHAN];
  1091. struct uart_port *uport = &zport->port;
  1092. if (zport->scc)
  1093. uart_remove_one_port(&zs_reg, uport);
  1094. }
  1095. uart_unregister_driver(&zs_reg);
  1096. }
  1097. module_init(zs_init);
  1098. module_exit(zs_exit);