vt8500_serial.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2010 Alexey Charkov <[email protected]>
  4. *
  5. * Based on msm_serial.c, which is:
  6. * Copyright (C) 2007 Google, Inc.
  7. * Author: Robert Love <[email protected]>
  8. */
  9. #include <linux/hrtimer.h>
  10. #include <linux/delay.h>
  11. #include <linux/io.h>
  12. #include <linux/ioport.h>
  13. #include <linux/irq.h>
  14. #include <linux/init.h>
  15. #include <linux/console.h>
  16. #include <linux/tty.h>
  17. #include <linux/tty_flip.h>
  18. #include <linux/serial_core.h>
  19. #include <linux/serial.h>
  20. #include <linux/slab.h>
  21. #include <linux/clk.h>
  22. #include <linux/of.h>
  23. #include <linux/of_device.h>
  24. #include <linux/err.h>
  25. /*
  26. * UART Register offsets
  27. */
  28. #define VT8500_URTDR 0x0000 /* Transmit data */
  29. #define VT8500_URRDR 0x0004 /* Receive data */
  30. #define VT8500_URDIV 0x0008 /* Clock/Baud rate divisor */
  31. #define VT8500_URLCR 0x000C /* Line control */
  32. #define VT8500_URICR 0x0010 /* IrDA control */
  33. #define VT8500_URIER 0x0014 /* Interrupt enable */
  34. #define VT8500_URISR 0x0018 /* Interrupt status */
  35. #define VT8500_URUSR 0x001c /* UART status */
  36. #define VT8500_URFCR 0x0020 /* FIFO control */
  37. #define VT8500_URFIDX 0x0024 /* FIFO index */
  38. #define VT8500_URBKR 0x0028 /* Break signal count */
  39. #define VT8500_URTOD 0x002c /* Time out divisor */
  40. #define VT8500_TXFIFO 0x1000 /* Transmit FIFO (16x8) */
  41. #define VT8500_RXFIFO 0x1020 /* Receive FIFO (16x10) */
  42. /*
  43. * Interrupt enable and status bits
  44. */
  45. #define TXDE (1 << 0) /* Tx Data empty */
  46. #define RXDF (1 << 1) /* Rx Data full */
  47. #define TXFAE (1 << 2) /* Tx FIFO almost empty */
  48. #define TXFE (1 << 3) /* Tx FIFO empty */
  49. #define RXFAF (1 << 4) /* Rx FIFO almost full */
  50. #define RXFF (1 << 5) /* Rx FIFO full */
  51. #define TXUDR (1 << 6) /* Tx underrun */
  52. #define RXOVER (1 << 7) /* Rx overrun */
  53. #define PER (1 << 8) /* Parity error */
  54. #define FER (1 << 9) /* Frame error */
  55. #define TCTS (1 << 10) /* Toggle of CTS */
  56. #define RXTOUT (1 << 11) /* Rx timeout */
  57. #define BKDONE (1 << 12) /* Break signal done */
  58. #define ERR (1 << 13) /* AHB error response */
  59. #define RX_FIFO_INTS (RXFAF | RXFF | RXOVER | PER | FER | RXTOUT)
  60. #define TX_FIFO_INTS (TXFAE | TXFE | TXUDR)
  61. /*
  62. * Line control bits
  63. */
  64. #define VT8500_TXEN (1 << 0) /* Enable transmit logic */
  65. #define VT8500_RXEN (1 << 1) /* Enable receive logic */
  66. #define VT8500_CS8 (1 << 2) /* 8-bit data length (vs. 7-bit) */
  67. #define VT8500_CSTOPB (1 << 3) /* 2 stop bits (vs. 1) */
  68. #define VT8500_PARENB (1 << 4) /* Enable parity */
  69. #define VT8500_PARODD (1 << 5) /* Odd parity (vs. even) */
  70. #define VT8500_RTS (1 << 6) /* Ready to send */
  71. #define VT8500_LOOPBK (1 << 7) /* Enable internal loopback */
  72. #define VT8500_DMA (1 << 8) /* Enable DMA mode (needs FIFO) */
  73. #define VT8500_BREAK (1 << 9) /* Initiate break signal */
  74. #define VT8500_PSLVERR (1 << 10) /* APB error upon empty RX FIFO read */
  75. #define VT8500_SWRTSCTS (1 << 11) /* Software-controlled RTS/CTS */
  76. /*
  77. * Capability flags (driver-internal)
  78. */
  79. #define VT8500_HAS_SWRTSCTS_SWITCH (1 << 1)
  80. #define VT8500_RECOMMENDED_CLK 12000000
  81. #define VT8500_OVERSAMPLING_DIVISOR 13
  82. #define VT8500_MAX_PORTS 6
  83. struct vt8500_port {
  84. struct uart_port uart;
  85. char name[16];
  86. struct clk *clk;
  87. unsigned int clk_predivisor;
  88. unsigned int ier;
  89. unsigned int vt8500_uart_flags;
  90. };
  91. /*
  92. * we use this variable to keep track of which ports
  93. * have been allocated as we can't use pdev->id in
  94. * devicetree
  95. */
  96. static DECLARE_BITMAP(vt8500_ports_in_use, VT8500_MAX_PORTS);
  97. static inline void vt8500_write(struct uart_port *port, unsigned int val,
  98. unsigned int off)
  99. {
  100. writel(val, port->membase + off);
  101. }
  102. static inline unsigned int vt8500_read(struct uart_port *port, unsigned int off)
  103. {
  104. return readl(port->membase + off);
  105. }
  106. static void vt8500_stop_tx(struct uart_port *port)
  107. {
  108. struct vt8500_port *vt8500_port = container_of(port,
  109. struct vt8500_port,
  110. uart);
  111. vt8500_port->ier &= ~TX_FIFO_INTS;
  112. vt8500_write(port, vt8500_port->ier, VT8500_URIER);
  113. }
  114. static void vt8500_stop_rx(struct uart_port *port)
  115. {
  116. struct vt8500_port *vt8500_port = container_of(port,
  117. struct vt8500_port,
  118. uart);
  119. vt8500_port->ier &= ~RX_FIFO_INTS;
  120. vt8500_write(port, vt8500_port->ier, VT8500_URIER);
  121. }
  122. static void vt8500_enable_ms(struct uart_port *port)
  123. {
  124. struct vt8500_port *vt8500_port = container_of(port,
  125. struct vt8500_port,
  126. uart);
  127. vt8500_port->ier |= TCTS;
  128. vt8500_write(port, vt8500_port->ier, VT8500_URIER);
  129. }
  130. static void handle_rx(struct uart_port *port)
  131. {
  132. struct tty_port *tport = &port->state->port;
  133. /*
  134. * Handle overrun
  135. */
  136. if ((vt8500_read(port, VT8500_URISR) & RXOVER)) {
  137. port->icount.overrun++;
  138. tty_insert_flip_char(tport, 0, TTY_OVERRUN);
  139. }
  140. /* and now the main RX loop */
  141. while (vt8500_read(port, VT8500_URFIDX) & 0x1f00) {
  142. unsigned int c;
  143. char flag = TTY_NORMAL;
  144. c = readw(port->membase + VT8500_RXFIFO) & 0x3ff;
  145. /* Mask conditions we're ignorning. */
  146. c &= ~port->read_status_mask;
  147. if (c & FER) {
  148. port->icount.frame++;
  149. flag = TTY_FRAME;
  150. } else if (c & PER) {
  151. port->icount.parity++;
  152. flag = TTY_PARITY;
  153. }
  154. port->icount.rx++;
  155. if (!uart_handle_sysrq_char(port, c))
  156. tty_insert_flip_char(tport, c, flag);
  157. }
  158. tty_flip_buffer_push(tport);
  159. }
  160. static unsigned int vt8500_tx_empty(struct uart_port *port)
  161. {
  162. unsigned int idx = vt8500_read(port, VT8500_URFIDX) & 0x1f;
  163. return idx < 16 ? TIOCSER_TEMT : 0;
  164. }
  165. static void handle_tx(struct uart_port *port)
  166. {
  167. struct circ_buf *xmit = &port->state->xmit;
  168. if (port->x_char) {
  169. writeb(port->x_char, port->membase + VT8500_TXFIFO);
  170. port->icount.tx++;
  171. port->x_char = 0;
  172. }
  173. if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
  174. vt8500_stop_tx(port);
  175. return;
  176. }
  177. while (vt8500_tx_empty(port)) {
  178. if (uart_circ_empty(xmit))
  179. break;
  180. writeb(xmit->buf[xmit->tail], port->membase + VT8500_TXFIFO);
  181. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  182. port->icount.tx++;
  183. }
  184. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  185. uart_write_wakeup(port);
  186. if (uart_circ_empty(xmit))
  187. vt8500_stop_tx(port);
  188. }
  189. static void vt8500_start_tx(struct uart_port *port)
  190. {
  191. struct vt8500_port *vt8500_port = container_of(port,
  192. struct vt8500_port,
  193. uart);
  194. vt8500_port->ier &= ~TX_FIFO_INTS;
  195. vt8500_write(port, vt8500_port->ier, VT8500_URIER);
  196. handle_tx(port);
  197. vt8500_port->ier |= TX_FIFO_INTS;
  198. vt8500_write(port, vt8500_port->ier, VT8500_URIER);
  199. }
  200. static void handle_delta_cts(struct uart_port *port)
  201. {
  202. port->icount.cts++;
  203. wake_up_interruptible(&port->state->port.delta_msr_wait);
  204. }
  205. static irqreturn_t vt8500_irq(int irq, void *dev_id)
  206. {
  207. struct uart_port *port = dev_id;
  208. unsigned long isr;
  209. spin_lock(&port->lock);
  210. isr = vt8500_read(port, VT8500_URISR);
  211. /* Acknowledge active status bits */
  212. vt8500_write(port, isr, VT8500_URISR);
  213. if (isr & RX_FIFO_INTS)
  214. handle_rx(port);
  215. if (isr & TX_FIFO_INTS)
  216. handle_tx(port);
  217. if (isr & TCTS)
  218. handle_delta_cts(port);
  219. spin_unlock(&port->lock);
  220. return IRQ_HANDLED;
  221. }
  222. static unsigned int vt8500_get_mctrl(struct uart_port *port)
  223. {
  224. unsigned int usr;
  225. usr = vt8500_read(port, VT8500_URUSR);
  226. if (usr & (1 << 4))
  227. return TIOCM_CTS;
  228. else
  229. return 0;
  230. }
  231. static void vt8500_set_mctrl(struct uart_port *port, unsigned int mctrl)
  232. {
  233. unsigned int lcr = vt8500_read(port, VT8500_URLCR);
  234. if (mctrl & TIOCM_RTS)
  235. lcr |= VT8500_RTS;
  236. else
  237. lcr &= ~VT8500_RTS;
  238. vt8500_write(port, lcr, VT8500_URLCR);
  239. }
  240. static void vt8500_break_ctl(struct uart_port *port, int break_ctl)
  241. {
  242. if (break_ctl)
  243. vt8500_write(port,
  244. vt8500_read(port, VT8500_URLCR) | VT8500_BREAK,
  245. VT8500_URLCR);
  246. }
  247. static int vt8500_set_baud_rate(struct uart_port *port, unsigned int baud)
  248. {
  249. struct vt8500_port *vt8500_port =
  250. container_of(port, struct vt8500_port, uart);
  251. unsigned long div;
  252. unsigned int loops = 1000;
  253. div = ((vt8500_port->clk_predivisor - 1) & 0xf) << 16;
  254. div |= (uart_get_divisor(port, baud) - 1) & 0x3ff;
  255. /* Effective baud rate */
  256. baud = port->uartclk / 16 / ((div & 0x3ff) + 1);
  257. while ((vt8500_read(port, VT8500_URUSR) & (1 << 5)) && --loops)
  258. cpu_relax();
  259. vt8500_write(port, div, VT8500_URDIV);
  260. /* Break signal timing depends on baud rate, update accordingly */
  261. vt8500_write(port, mult_frac(baud, 4096, 1000000), VT8500_URBKR);
  262. return baud;
  263. }
  264. static int vt8500_startup(struct uart_port *port)
  265. {
  266. struct vt8500_port *vt8500_port =
  267. container_of(port, struct vt8500_port, uart);
  268. int ret;
  269. snprintf(vt8500_port->name, sizeof(vt8500_port->name),
  270. "vt8500_serial%d", port->line);
  271. ret = request_irq(port->irq, vt8500_irq, IRQF_TRIGGER_HIGH,
  272. vt8500_port->name, port);
  273. if (unlikely(ret))
  274. return ret;
  275. vt8500_write(port, 0x03, VT8500_URLCR); /* enable TX & RX */
  276. return 0;
  277. }
  278. static void vt8500_shutdown(struct uart_port *port)
  279. {
  280. struct vt8500_port *vt8500_port =
  281. container_of(port, struct vt8500_port, uart);
  282. vt8500_port->ier = 0;
  283. /* disable interrupts and FIFOs */
  284. vt8500_write(&vt8500_port->uart, 0, VT8500_URIER);
  285. vt8500_write(&vt8500_port->uart, 0x880, VT8500_URFCR);
  286. free_irq(port->irq, port);
  287. }
  288. static void vt8500_set_termios(struct uart_port *port,
  289. struct ktermios *termios,
  290. const struct ktermios *old)
  291. {
  292. struct vt8500_port *vt8500_port =
  293. container_of(port, struct vt8500_port, uart);
  294. unsigned long flags;
  295. unsigned int baud, lcr;
  296. unsigned int loops = 1000;
  297. spin_lock_irqsave(&port->lock, flags);
  298. /* calculate and set baud rate */
  299. baud = uart_get_baud_rate(port, termios, old, 900, 921600);
  300. baud = vt8500_set_baud_rate(port, baud);
  301. if (tty_termios_baud_rate(termios))
  302. tty_termios_encode_baud_rate(termios, baud, baud);
  303. /* calculate parity */
  304. lcr = vt8500_read(&vt8500_port->uart, VT8500_URLCR);
  305. lcr &= ~(VT8500_PARENB | VT8500_PARODD);
  306. if (termios->c_cflag & PARENB) {
  307. lcr |= VT8500_PARENB;
  308. termios->c_cflag &= ~CMSPAR;
  309. if (termios->c_cflag & PARODD)
  310. lcr |= VT8500_PARODD;
  311. }
  312. /* calculate bits per char */
  313. lcr &= ~VT8500_CS8;
  314. switch (termios->c_cflag & CSIZE) {
  315. case CS7:
  316. break;
  317. case CS8:
  318. default:
  319. lcr |= VT8500_CS8;
  320. termios->c_cflag &= ~CSIZE;
  321. termios->c_cflag |= CS8;
  322. break;
  323. }
  324. /* calculate stop bits */
  325. lcr &= ~VT8500_CSTOPB;
  326. if (termios->c_cflag & CSTOPB)
  327. lcr |= VT8500_CSTOPB;
  328. lcr &= ~VT8500_SWRTSCTS;
  329. if (vt8500_port->vt8500_uart_flags & VT8500_HAS_SWRTSCTS_SWITCH)
  330. lcr |= VT8500_SWRTSCTS;
  331. /* set parity, bits per char, and stop bit */
  332. vt8500_write(&vt8500_port->uart, lcr, VT8500_URLCR);
  333. /* Configure status bits to ignore based on termio flags. */
  334. port->read_status_mask = 0;
  335. if (termios->c_iflag & IGNPAR)
  336. port->read_status_mask = FER | PER;
  337. uart_update_timeout(port, termios->c_cflag, baud);
  338. /* Reset FIFOs */
  339. vt8500_write(&vt8500_port->uart, 0x88c, VT8500_URFCR);
  340. while ((vt8500_read(&vt8500_port->uart, VT8500_URFCR) & 0xc)
  341. && --loops)
  342. cpu_relax();
  343. /* Every possible FIFO-related interrupt */
  344. vt8500_port->ier = RX_FIFO_INTS | TX_FIFO_INTS;
  345. /*
  346. * CTS flow control
  347. */
  348. if (UART_ENABLE_MS(&vt8500_port->uart, termios->c_cflag))
  349. vt8500_port->ier |= TCTS;
  350. vt8500_write(&vt8500_port->uart, 0x881, VT8500_URFCR);
  351. vt8500_write(&vt8500_port->uart, vt8500_port->ier, VT8500_URIER);
  352. spin_unlock_irqrestore(&port->lock, flags);
  353. }
  354. static const char *vt8500_type(struct uart_port *port)
  355. {
  356. struct vt8500_port *vt8500_port =
  357. container_of(port, struct vt8500_port, uart);
  358. return vt8500_port->name;
  359. }
  360. static void vt8500_release_port(struct uart_port *port)
  361. {
  362. }
  363. static int vt8500_request_port(struct uart_port *port)
  364. {
  365. return 0;
  366. }
  367. static void vt8500_config_port(struct uart_port *port, int flags)
  368. {
  369. port->type = PORT_VT8500;
  370. }
  371. static int vt8500_verify_port(struct uart_port *port,
  372. struct serial_struct *ser)
  373. {
  374. if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_VT8500))
  375. return -EINVAL;
  376. if (unlikely(port->irq != ser->irq))
  377. return -EINVAL;
  378. return 0;
  379. }
  380. static struct vt8500_port *vt8500_uart_ports[VT8500_MAX_PORTS];
  381. static struct uart_driver vt8500_uart_driver;
  382. #ifdef CONFIG_SERIAL_VT8500_CONSOLE
  383. static void wait_for_xmitr(struct uart_port *port)
  384. {
  385. unsigned int status, tmout = 10000;
  386. /* Wait up to 10ms for the character(s) to be sent. */
  387. do {
  388. status = vt8500_read(port, VT8500_URFIDX);
  389. if (--tmout == 0)
  390. break;
  391. udelay(1);
  392. } while (status & 0x10);
  393. }
  394. static void vt8500_console_putchar(struct uart_port *port, unsigned char c)
  395. {
  396. wait_for_xmitr(port);
  397. writeb(c, port->membase + VT8500_TXFIFO);
  398. }
  399. static void vt8500_console_write(struct console *co, const char *s,
  400. unsigned int count)
  401. {
  402. struct vt8500_port *vt8500_port = vt8500_uart_ports[co->index];
  403. unsigned long ier;
  404. BUG_ON(co->index < 0 || co->index >= vt8500_uart_driver.nr);
  405. ier = vt8500_read(&vt8500_port->uart, VT8500_URIER);
  406. vt8500_write(&vt8500_port->uart, VT8500_URIER, 0);
  407. uart_console_write(&vt8500_port->uart, s, count,
  408. vt8500_console_putchar);
  409. /*
  410. * Finally, wait for transmitter to become empty
  411. * and switch back to FIFO
  412. */
  413. wait_for_xmitr(&vt8500_port->uart);
  414. vt8500_write(&vt8500_port->uart, VT8500_URIER, ier);
  415. }
  416. static int __init vt8500_console_setup(struct console *co, char *options)
  417. {
  418. struct vt8500_port *vt8500_port;
  419. int baud = 9600;
  420. int bits = 8;
  421. int parity = 'n';
  422. int flow = 'n';
  423. if (unlikely(co->index >= vt8500_uart_driver.nr || co->index < 0))
  424. return -ENXIO;
  425. vt8500_port = vt8500_uart_ports[co->index];
  426. if (!vt8500_port)
  427. return -ENODEV;
  428. if (options)
  429. uart_parse_options(options, &baud, &parity, &bits, &flow);
  430. return uart_set_options(&vt8500_port->uart,
  431. co, baud, parity, bits, flow);
  432. }
  433. static struct console vt8500_console = {
  434. .name = "ttyWMT",
  435. .write = vt8500_console_write,
  436. .device = uart_console_device,
  437. .setup = vt8500_console_setup,
  438. .flags = CON_PRINTBUFFER,
  439. .index = -1,
  440. .data = &vt8500_uart_driver,
  441. };
  442. #define VT8500_CONSOLE (&vt8500_console)
  443. #else
  444. #define VT8500_CONSOLE NULL
  445. #endif
  446. #ifdef CONFIG_CONSOLE_POLL
  447. static int vt8500_get_poll_char(struct uart_port *port)
  448. {
  449. unsigned int status = vt8500_read(port, VT8500_URFIDX);
  450. if (!(status & 0x1f00))
  451. return NO_POLL_CHAR;
  452. return vt8500_read(port, VT8500_RXFIFO) & 0xff;
  453. }
  454. static void vt8500_put_poll_char(struct uart_port *port, unsigned char c)
  455. {
  456. unsigned int status, tmout = 10000;
  457. do {
  458. status = vt8500_read(port, VT8500_URFIDX);
  459. if (--tmout == 0)
  460. break;
  461. udelay(1);
  462. } while (status & 0x10);
  463. vt8500_write(port, c, VT8500_TXFIFO);
  464. }
  465. #endif
  466. static const struct uart_ops vt8500_uart_pops = {
  467. .tx_empty = vt8500_tx_empty,
  468. .set_mctrl = vt8500_set_mctrl,
  469. .get_mctrl = vt8500_get_mctrl,
  470. .stop_tx = vt8500_stop_tx,
  471. .start_tx = vt8500_start_tx,
  472. .stop_rx = vt8500_stop_rx,
  473. .enable_ms = vt8500_enable_ms,
  474. .break_ctl = vt8500_break_ctl,
  475. .startup = vt8500_startup,
  476. .shutdown = vt8500_shutdown,
  477. .set_termios = vt8500_set_termios,
  478. .type = vt8500_type,
  479. .release_port = vt8500_release_port,
  480. .request_port = vt8500_request_port,
  481. .config_port = vt8500_config_port,
  482. .verify_port = vt8500_verify_port,
  483. #ifdef CONFIG_CONSOLE_POLL
  484. .poll_get_char = vt8500_get_poll_char,
  485. .poll_put_char = vt8500_put_poll_char,
  486. #endif
  487. };
  488. static struct uart_driver vt8500_uart_driver = {
  489. .owner = THIS_MODULE,
  490. .driver_name = "vt8500_serial",
  491. .dev_name = "ttyWMT",
  492. .nr = 6,
  493. .cons = VT8500_CONSOLE,
  494. };
  495. static unsigned int vt8500_flags; /* none required so far */
  496. static unsigned int wm8880_flags = VT8500_HAS_SWRTSCTS_SWITCH;
  497. static const struct of_device_id wmt_dt_ids[] = {
  498. { .compatible = "via,vt8500-uart", .data = &vt8500_flags},
  499. { .compatible = "wm,wm8880-uart", .data = &wm8880_flags},
  500. {}
  501. };
  502. static int vt8500_serial_probe(struct platform_device *pdev)
  503. {
  504. struct vt8500_port *vt8500_port;
  505. struct resource *mmres;
  506. struct device_node *np = pdev->dev.of_node;
  507. const unsigned int *flags;
  508. int ret;
  509. int port;
  510. int irq;
  511. flags = of_device_get_match_data(&pdev->dev);
  512. if (!flags)
  513. return -EINVAL;
  514. mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  515. if (!mmres)
  516. return -ENODEV;
  517. irq = platform_get_irq(pdev, 0);
  518. if (irq < 0)
  519. return irq;
  520. if (np) {
  521. port = of_alias_get_id(np, "serial");
  522. if (port >= VT8500_MAX_PORTS)
  523. port = -1;
  524. } else {
  525. port = -1;
  526. }
  527. if (port < 0) {
  528. /* calculate the port id */
  529. port = find_first_zero_bit(vt8500_ports_in_use,
  530. VT8500_MAX_PORTS);
  531. }
  532. if (port >= VT8500_MAX_PORTS)
  533. return -ENODEV;
  534. /* reserve the port id */
  535. if (test_and_set_bit(port, vt8500_ports_in_use)) {
  536. /* port already in use - shouldn't really happen */
  537. return -EBUSY;
  538. }
  539. vt8500_port = devm_kzalloc(&pdev->dev, sizeof(struct vt8500_port),
  540. GFP_KERNEL);
  541. if (!vt8500_port)
  542. return -ENOMEM;
  543. vt8500_port->uart.membase = devm_ioremap_resource(&pdev->dev, mmres);
  544. if (IS_ERR(vt8500_port->uart.membase))
  545. return PTR_ERR(vt8500_port->uart.membase);
  546. vt8500_port->clk = of_clk_get(pdev->dev.of_node, 0);
  547. if (IS_ERR(vt8500_port->clk)) {
  548. dev_err(&pdev->dev, "failed to get clock\n");
  549. return -EINVAL;
  550. }
  551. ret = clk_prepare_enable(vt8500_port->clk);
  552. if (ret) {
  553. dev_err(&pdev->dev, "failed to enable clock\n");
  554. return ret;
  555. }
  556. vt8500_port->vt8500_uart_flags = *flags;
  557. vt8500_port->clk_predivisor = DIV_ROUND_CLOSEST(
  558. clk_get_rate(vt8500_port->clk),
  559. VT8500_RECOMMENDED_CLK
  560. );
  561. vt8500_port->uart.type = PORT_VT8500;
  562. vt8500_port->uart.iotype = UPIO_MEM;
  563. vt8500_port->uart.mapbase = mmres->start;
  564. vt8500_port->uart.irq = irq;
  565. vt8500_port->uart.fifosize = 16;
  566. vt8500_port->uart.ops = &vt8500_uart_pops;
  567. vt8500_port->uart.line = port;
  568. vt8500_port->uart.dev = &pdev->dev;
  569. vt8500_port->uart.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
  570. vt8500_port->uart.has_sysrq = IS_ENABLED(CONFIG_SERIAL_VT8500_CONSOLE);
  571. /* Serial core uses the magic "16" everywhere - adjust for it */
  572. vt8500_port->uart.uartclk = 16 * clk_get_rate(vt8500_port->clk) /
  573. vt8500_port->clk_predivisor /
  574. VT8500_OVERSAMPLING_DIVISOR;
  575. snprintf(vt8500_port->name, sizeof(vt8500_port->name),
  576. "VT8500 UART%d", pdev->id);
  577. vt8500_uart_ports[port] = vt8500_port;
  578. uart_add_one_port(&vt8500_uart_driver, &vt8500_port->uart);
  579. platform_set_drvdata(pdev, vt8500_port);
  580. return 0;
  581. }
  582. static struct platform_driver vt8500_platform_driver = {
  583. .probe = vt8500_serial_probe,
  584. .driver = {
  585. .name = "vt8500_serial",
  586. .of_match_table = wmt_dt_ids,
  587. .suppress_bind_attrs = true,
  588. },
  589. };
  590. static int __init vt8500_serial_init(void)
  591. {
  592. int ret;
  593. ret = uart_register_driver(&vt8500_uart_driver);
  594. if (unlikely(ret))
  595. return ret;
  596. ret = platform_driver_register(&vt8500_platform_driver);
  597. if (unlikely(ret))
  598. uart_unregister_driver(&vt8500_uart_driver);
  599. return ret;
  600. }
  601. device_initcall(vt8500_serial_init);