sprd_serial.c 30 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2012-2015 Spreadtrum Communications Inc.
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/console.h>
  7. #include <linux/delay.h>
  8. #include <linux/dmaengine.h>
  9. #include <linux/dma-mapping.h>
  10. #include <linux/dma/sprd-dma.h>
  11. #include <linux/io.h>
  12. #include <linux/ioport.h>
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/of.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/serial_core.h>
  18. #include <linux/serial.h>
  19. #include <linux/slab.h>
  20. #include <linux/tty.h>
  21. #include <linux/tty_flip.h>
  22. /* device name */
  23. #define UART_NR_MAX 8
  24. #define SPRD_TTY_NAME "ttyS"
  25. #define SPRD_FIFO_SIZE 128
  26. #define SPRD_DEF_RATE 26000000
  27. #define SPRD_BAUD_IO_LIMIT 3000000
  28. #define SPRD_TIMEOUT 256000
  29. /* the offset of serial registers and BITs for them */
  30. /* data registers */
  31. #define SPRD_TXD 0x0000
  32. #define SPRD_RXD 0x0004
  33. /* line status register and its BITs */
  34. #define SPRD_LSR 0x0008
  35. #define SPRD_LSR_OE BIT(4)
  36. #define SPRD_LSR_FE BIT(3)
  37. #define SPRD_LSR_PE BIT(2)
  38. #define SPRD_LSR_BI BIT(7)
  39. #define SPRD_LSR_TX_OVER BIT(15)
  40. /* data number in TX and RX fifo */
  41. #define SPRD_STS1 0x000C
  42. #define SPRD_RX_FIFO_CNT_MASK GENMASK(7, 0)
  43. #define SPRD_TX_FIFO_CNT_MASK GENMASK(15, 8)
  44. /* interrupt enable register and its BITs */
  45. #define SPRD_IEN 0x0010
  46. #define SPRD_IEN_RX_FULL BIT(0)
  47. #define SPRD_IEN_TX_EMPTY BIT(1)
  48. #define SPRD_IEN_BREAK_DETECT BIT(7)
  49. #define SPRD_IEN_TIMEOUT BIT(13)
  50. /* interrupt clear register */
  51. #define SPRD_ICLR 0x0014
  52. #define SPRD_ICLR_TIMEOUT BIT(13)
  53. /* line control register */
  54. #define SPRD_LCR 0x0018
  55. #define SPRD_LCR_STOP_1BIT 0x10
  56. #define SPRD_LCR_STOP_2BIT 0x30
  57. #define SPRD_LCR_DATA_LEN (BIT(2) | BIT(3))
  58. #define SPRD_LCR_DATA_LEN5 0x0
  59. #define SPRD_LCR_DATA_LEN6 0x4
  60. #define SPRD_LCR_DATA_LEN7 0x8
  61. #define SPRD_LCR_DATA_LEN8 0xc
  62. #define SPRD_LCR_PARITY (BIT(0) | BIT(1))
  63. #define SPRD_LCR_PARITY_EN 0x2
  64. #define SPRD_LCR_EVEN_PAR 0x0
  65. #define SPRD_LCR_ODD_PAR 0x1
  66. /* control register 1 */
  67. #define SPRD_CTL1 0x001C
  68. #define SPRD_DMA_EN BIT(15)
  69. #define SPRD_LOOPBACK_EN BIT(14)
  70. #define RX_HW_FLOW_CTL_THLD BIT(6)
  71. #define RX_HW_FLOW_CTL_EN BIT(7)
  72. #define TX_HW_FLOW_CTL_EN BIT(8)
  73. #define RX_TOUT_THLD_DEF 0x3E00
  74. #define RX_HFC_THLD_DEF 0x40
  75. /* fifo threshold register */
  76. #define SPRD_CTL2 0x0020
  77. #define THLD_TX_EMPTY 0x40
  78. #define THLD_TX_EMPTY_SHIFT 8
  79. #define THLD_RX_FULL 0x40
  80. #define THLD_RX_FULL_MASK GENMASK(6, 0)
  81. /* config baud rate register */
  82. #define SPRD_CLKD0 0x0024
  83. #define SPRD_CLKD0_MASK GENMASK(15, 0)
  84. #define SPRD_CLKD1 0x0028
  85. #define SPRD_CLKD1_MASK GENMASK(20, 16)
  86. #define SPRD_CLKD1_SHIFT 16
  87. /* interrupt mask status register */
  88. #define SPRD_IMSR 0x002C
  89. #define SPRD_IMSR_RX_FIFO_FULL BIT(0)
  90. #define SPRD_IMSR_TX_FIFO_EMPTY BIT(1)
  91. #define SPRD_IMSR_BREAK_DETECT BIT(7)
  92. #define SPRD_IMSR_TIMEOUT BIT(13)
  93. #define SPRD_DEFAULT_SOURCE_CLK 26000000
  94. #define SPRD_RX_DMA_STEP 1
  95. #define SPRD_RX_FIFO_FULL 1
  96. #define SPRD_TX_FIFO_FULL 0x20
  97. #define SPRD_UART_RX_SIZE (UART_XMIT_SIZE / 4)
  98. struct sprd_uart_dma {
  99. struct dma_chan *chn;
  100. unsigned char *virt;
  101. dma_addr_t phys_addr;
  102. dma_cookie_t cookie;
  103. u32 trans_len;
  104. bool enable;
  105. };
  106. struct sprd_uart_port {
  107. struct uart_port port;
  108. char name[16];
  109. struct clk *clk;
  110. struct sprd_uart_dma tx_dma;
  111. struct sprd_uart_dma rx_dma;
  112. dma_addr_t pos;
  113. unsigned char *rx_buf_tail;
  114. };
  115. static struct sprd_uart_port *sprd_port[UART_NR_MAX];
  116. static int sprd_ports_num;
  117. static int sprd_start_dma_rx(struct uart_port *port);
  118. static int sprd_tx_dma_config(struct uart_port *port);
  119. static inline unsigned int serial_in(struct uart_port *port,
  120. unsigned int offset)
  121. {
  122. return readl_relaxed(port->membase + offset);
  123. }
  124. static inline void serial_out(struct uart_port *port, unsigned int offset,
  125. int value)
  126. {
  127. writel_relaxed(value, port->membase + offset);
  128. }
  129. static unsigned int sprd_tx_empty(struct uart_port *port)
  130. {
  131. if (serial_in(port, SPRD_STS1) & SPRD_TX_FIFO_CNT_MASK)
  132. return 0;
  133. else
  134. return TIOCSER_TEMT;
  135. }
  136. static unsigned int sprd_get_mctrl(struct uart_port *port)
  137. {
  138. return TIOCM_DSR | TIOCM_CTS;
  139. }
  140. static void sprd_set_mctrl(struct uart_port *port, unsigned int mctrl)
  141. {
  142. u32 val = serial_in(port, SPRD_CTL1);
  143. if (mctrl & TIOCM_LOOP)
  144. val |= SPRD_LOOPBACK_EN;
  145. else
  146. val &= ~SPRD_LOOPBACK_EN;
  147. serial_out(port, SPRD_CTL1, val);
  148. }
  149. static void sprd_stop_rx(struct uart_port *port)
  150. {
  151. struct sprd_uart_port *sp =
  152. container_of(port, struct sprd_uart_port, port);
  153. unsigned int ien, iclr;
  154. if (sp->rx_dma.enable)
  155. dmaengine_terminate_all(sp->rx_dma.chn);
  156. iclr = serial_in(port, SPRD_ICLR);
  157. ien = serial_in(port, SPRD_IEN);
  158. ien &= ~(SPRD_IEN_RX_FULL | SPRD_IEN_BREAK_DETECT);
  159. iclr |= SPRD_IEN_RX_FULL | SPRD_IEN_BREAK_DETECT;
  160. serial_out(port, SPRD_IEN, ien);
  161. serial_out(port, SPRD_ICLR, iclr);
  162. }
  163. static void sprd_uart_dma_enable(struct uart_port *port, bool enable)
  164. {
  165. u32 val = serial_in(port, SPRD_CTL1);
  166. if (enable)
  167. val |= SPRD_DMA_EN;
  168. else
  169. val &= ~SPRD_DMA_EN;
  170. serial_out(port, SPRD_CTL1, val);
  171. }
  172. static void sprd_stop_tx_dma(struct uart_port *port)
  173. {
  174. struct sprd_uart_port *sp =
  175. container_of(port, struct sprd_uart_port, port);
  176. struct circ_buf *xmit = &port->state->xmit;
  177. struct dma_tx_state state;
  178. u32 trans_len;
  179. dmaengine_pause(sp->tx_dma.chn);
  180. dmaengine_tx_status(sp->tx_dma.chn, sp->tx_dma.cookie, &state);
  181. if (state.residue) {
  182. trans_len = state.residue - sp->tx_dma.phys_addr;
  183. xmit->tail = (xmit->tail + trans_len) & (UART_XMIT_SIZE - 1);
  184. port->icount.tx += trans_len;
  185. dma_unmap_single(port->dev, sp->tx_dma.phys_addr,
  186. sp->tx_dma.trans_len, DMA_TO_DEVICE);
  187. }
  188. dmaengine_terminate_all(sp->tx_dma.chn);
  189. sp->tx_dma.trans_len = 0;
  190. }
  191. static int sprd_tx_buf_remap(struct uart_port *port)
  192. {
  193. struct sprd_uart_port *sp =
  194. container_of(port, struct sprd_uart_port, port);
  195. struct circ_buf *xmit = &port->state->xmit;
  196. sp->tx_dma.trans_len =
  197. CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
  198. sp->tx_dma.phys_addr = dma_map_single(port->dev,
  199. (void *)&(xmit->buf[xmit->tail]),
  200. sp->tx_dma.trans_len,
  201. DMA_TO_DEVICE);
  202. return dma_mapping_error(port->dev, sp->tx_dma.phys_addr);
  203. }
  204. static void sprd_complete_tx_dma(void *data)
  205. {
  206. struct uart_port *port = (struct uart_port *)data;
  207. struct sprd_uart_port *sp =
  208. container_of(port, struct sprd_uart_port, port);
  209. struct circ_buf *xmit = &port->state->xmit;
  210. unsigned long flags;
  211. spin_lock_irqsave(&port->lock, flags);
  212. dma_unmap_single(port->dev, sp->tx_dma.phys_addr,
  213. sp->tx_dma.trans_len, DMA_TO_DEVICE);
  214. xmit->tail = (xmit->tail + sp->tx_dma.trans_len) & (UART_XMIT_SIZE - 1);
  215. port->icount.tx += sp->tx_dma.trans_len;
  216. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  217. uart_write_wakeup(port);
  218. if (uart_circ_empty(xmit) || sprd_tx_buf_remap(port) ||
  219. sprd_tx_dma_config(port))
  220. sp->tx_dma.trans_len = 0;
  221. spin_unlock_irqrestore(&port->lock, flags);
  222. }
  223. static int sprd_uart_dma_submit(struct uart_port *port,
  224. struct sprd_uart_dma *ud, u32 trans_len,
  225. enum dma_transfer_direction direction,
  226. dma_async_tx_callback callback)
  227. {
  228. struct dma_async_tx_descriptor *dma_des;
  229. unsigned long flags;
  230. flags = SPRD_DMA_FLAGS(SPRD_DMA_CHN_MODE_NONE,
  231. SPRD_DMA_NO_TRG,
  232. SPRD_DMA_FRAG_REQ,
  233. SPRD_DMA_TRANS_INT);
  234. dma_des = dmaengine_prep_slave_single(ud->chn, ud->phys_addr, trans_len,
  235. direction, flags);
  236. if (!dma_des)
  237. return -ENODEV;
  238. dma_des->callback = callback;
  239. dma_des->callback_param = port;
  240. ud->cookie = dmaengine_submit(dma_des);
  241. if (dma_submit_error(ud->cookie))
  242. return dma_submit_error(ud->cookie);
  243. dma_async_issue_pending(ud->chn);
  244. return 0;
  245. }
  246. static int sprd_tx_dma_config(struct uart_port *port)
  247. {
  248. struct sprd_uart_port *sp =
  249. container_of(port, struct sprd_uart_port, port);
  250. u32 burst = sp->tx_dma.trans_len > SPRD_TX_FIFO_FULL ?
  251. SPRD_TX_FIFO_FULL : sp->tx_dma.trans_len;
  252. int ret;
  253. struct dma_slave_config cfg = {
  254. .dst_addr = port->mapbase + SPRD_TXD,
  255. .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
  256. .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
  257. .src_maxburst = burst,
  258. };
  259. ret = dmaengine_slave_config(sp->tx_dma.chn, &cfg);
  260. if (ret < 0)
  261. return ret;
  262. return sprd_uart_dma_submit(port, &sp->tx_dma, sp->tx_dma.trans_len,
  263. DMA_MEM_TO_DEV, sprd_complete_tx_dma);
  264. }
  265. static void sprd_start_tx_dma(struct uart_port *port)
  266. {
  267. struct sprd_uart_port *sp =
  268. container_of(port, struct sprd_uart_port, port);
  269. struct circ_buf *xmit = &port->state->xmit;
  270. if (port->x_char) {
  271. serial_out(port, SPRD_TXD, port->x_char);
  272. port->icount.tx++;
  273. port->x_char = 0;
  274. return;
  275. }
  276. if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
  277. sprd_stop_tx_dma(port);
  278. return;
  279. }
  280. if (sp->tx_dma.trans_len)
  281. return;
  282. if (sprd_tx_buf_remap(port) || sprd_tx_dma_config(port))
  283. sp->tx_dma.trans_len = 0;
  284. }
  285. static void sprd_rx_full_thld(struct uart_port *port, u32 thld)
  286. {
  287. u32 val = serial_in(port, SPRD_CTL2);
  288. val &= ~THLD_RX_FULL_MASK;
  289. val |= thld & THLD_RX_FULL_MASK;
  290. serial_out(port, SPRD_CTL2, val);
  291. }
  292. static int sprd_rx_alloc_buf(struct sprd_uart_port *sp)
  293. {
  294. sp->rx_dma.virt = dma_alloc_coherent(sp->port.dev, SPRD_UART_RX_SIZE,
  295. &sp->rx_dma.phys_addr, GFP_KERNEL);
  296. if (!sp->rx_dma.virt)
  297. return -ENOMEM;
  298. return 0;
  299. }
  300. static void sprd_rx_free_buf(struct sprd_uart_port *sp)
  301. {
  302. if (sp->rx_dma.virt)
  303. dma_free_coherent(sp->port.dev, SPRD_UART_RX_SIZE,
  304. sp->rx_dma.virt, sp->rx_dma.phys_addr);
  305. sp->rx_dma.virt = NULL;
  306. }
  307. static int sprd_rx_dma_config(struct uart_port *port, u32 burst)
  308. {
  309. struct sprd_uart_port *sp =
  310. container_of(port, struct sprd_uart_port, port);
  311. struct dma_slave_config cfg = {
  312. .src_addr = port->mapbase + SPRD_RXD,
  313. .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
  314. .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
  315. .src_maxburst = burst,
  316. };
  317. return dmaengine_slave_config(sp->rx_dma.chn, &cfg);
  318. }
  319. static void sprd_uart_dma_rx(struct uart_port *port)
  320. {
  321. struct sprd_uart_port *sp =
  322. container_of(port, struct sprd_uart_port, port);
  323. struct tty_port *tty = &port->state->port;
  324. port->icount.rx += sp->rx_dma.trans_len;
  325. tty_insert_flip_string(tty, sp->rx_buf_tail, sp->rx_dma.trans_len);
  326. tty_flip_buffer_push(tty);
  327. }
  328. static void sprd_uart_dma_irq(struct uart_port *port)
  329. {
  330. struct sprd_uart_port *sp =
  331. container_of(port, struct sprd_uart_port, port);
  332. struct dma_tx_state state;
  333. enum dma_status status;
  334. status = dmaengine_tx_status(sp->rx_dma.chn,
  335. sp->rx_dma.cookie, &state);
  336. if (status == DMA_ERROR)
  337. sprd_stop_rx(port);
  338. if (!state.residue && sp->pos == sp->rx_dma.phys_addr)
  339. return;
  340. if (!state.residue) {
  341. sp->rx_dma.trans_len = SPRD_UART_RX_SIZE +
  342. sp->rx_dma.phys_addr - sp->pos;
  343. sp->pos = sp->rx_dma.phys_addr;
  344. } else {
  345. sp->rx_dma.trans_len = state.residue - sp->pos;
  346. sp->pos = state.residue;
  347. }
  348. sprd_uart_dma_rx(port);
  349. sp->rx_buf_tail += sp->rx_dma.trans_len;
  350. }
  351. static void sprd_complete_rx_dma(void *data)
  352. {
  353. struct uart_port *port = (struct uart_port *)data;
  354. struct sprd_uart_port *sp =
  355. container_of(port, struct sprd_uart_port, port);
  356. struct dma_tx_state state;
  357. enum dma_status status;
  358. unsigned long flags;
  359. spin_lock_irqsave(&port->lock, flags);
  360. status = dmaengine_tx_status(sp->rx_dma.chn,
  361. sp->rx_dma.cookie, &state);
  362. if (status != DMA_COMPLETE) {
  363. sprd_stop_rx(port);
  364. spin_unlock_irqrestore(&port->lock, flags);
  365. return;
  366. }
  367. if (sp->pos != sp->rx_dma.phys_addr) {
  368. sp->rx_dma.trans_len = SPRD_UART_RX_SIZE +
  369. sp->rx_dma.phys_addr - sp->pos;
  370. sprd_uart_dma_rx(port);
  371. sp->rx_buf_tail += sp->rx_dma.trans_len;
  372. }
  373. if (sprd_start_dma_rx(port))
  374. sprd_stop_rx(port);
  375. spin_unlock_irqrestore(&port->lock, flags);
  376. }
  377. static int sprd_start_dma_rx(struct uart_port *port)
  378. {
  379. struct sprd_uart_port *sp =
  380. container_of(port, struct sprd_uart_port, port);
  381. int ret;
  382. if (!sp->rx_dma.enable)
  383. return 0;
  384. sp->pos = sp->rx_dma.phys_addr;
  385. sp->rx_buf_tail = sp->rx_dma.virt;
  386. sprd_rx_full_thld(port, SPRD_RX_FIFO_FULL);
  387. ret = sprd_rx_dma_config(port, SPRD_RX_DMA_STEP);
  388. if (ret)
  389. return ret;
  390. return sprd_uart_dma_submit(port, &sp->rx_dma, SPRD_UART_RX_SIZE,
  391. DMA_DEV_TO_MEM, sprd_complete_rx_dma);
  392. }
  393. static void sprd_release_dma(struct uart_port *port)
  394. {
  395. struct sprd_uart_port *sp =
  396. container_of(port, struct sprd_uart_port, port);
  397. sprd_uart_dma_enable(port, false);
  398. if (sp->rx_dma.enable)
  399. dma_release_channel(sp->rx_dma.chn);
  400. if (sp->tx_dma.enable)
  401. dma_release_channel(sp->tx_dma.chn);
  402. sp->tx_dma.enable = false;
  403. sp->rx_dma.enable = false;
  404. }
  405. static void sprd_request_dma(struct uart_port *port)
  406. {
  407. struct sprd_uart_port *sp =
  408. container_of(port, struct sprd_uart_port, port);
  409. sp->tx_dma.enable = true;
  410. sp->rx_dma.enable = true;
  411. sp->tx_dma.chn = dma_request_chan(port->dev, "tx");
  412. if (IS_ERR(sp->tx_dma.chn)) {
  413. dev_err(port->dev, "request TX DMA channel failed, ret = %ld\n",
  414. PTR_ERR(sp->tx_dma.chn));
  415. sp->tx_dma.enable = false;
  416. }
  417. sp->rx_dma.chn = dma_request_chan(port->dev, "rx");
  418. if (IS_ERR(sp->rx_dma.chn)) {
  419. dev_err(port->dev, "request RX DMA channel failed, ret = %ld\n",
  420. PTR_ERR(sp->rx_dma.chn));
  421. sp->rx_dma.enable = false;
  422. }
  423. }
  424. static void sprd_stop_tx(struct uart_port *port)
  425. {
  426. struct sprd_uart_port *sp = container_of(port, struct sprd_uart_port,
  427. port);
  428. unsigned int ien, iclr;
  429. if (sp->tx_dma.enable) {
  430. sprd_stop_tx_dma(port);
  431. return;
  432. }
  433. iclr = serial_in(port, SPRD_ICLR);
  434. ien = serial_in(port, SPRD_IEN);
  435. iclr |= SPRD_IEN_TX_EMPTY;
  436. ien &= ~SPRD_IEN_TX_EMPTY;
  437. serial_out(port, SPRD_IEN, ien);
  438. serial_out(port, SPRD_ICLR, iclr);
  439. }
  440. static void sprd_start_tx(struct uart_port *port)
  441. {
  442. struct sprd_uart_port *sp = container_of(port, struct sprd_uart_port,
  443. port);
  444. unsigned int ien;
  445. if (sp->tx_dma.enable) {
  446. sprd_start_tx_dma(port);
  447. return;
  448. }
  449. ien = serial_in(port, SPRD_IEN);
  450. if (!(ien & SPRD_IEN_TX_EMPTY)) {
  451. ien |= SPRD_IEN_TX_EMPTY;
  452. serial_out(port, SPRD_IEN, ien);
  453. }
  454. }
  455. /* The Sprd serial does not support this function. */
  456. static void sprd_break_ctl(struct uart_port *port, int break_state)
  457. {
  458. /* nothing to do */
  459. }
  460. static int handle_lsr_errors(struct uart_port *port,
  461. unsigned int *flag,
  462. unsigned int *lsr)
  463. {
  464. int ret = 0;
  465. /* statistics */
  466. if (*lsr & SPRD_LSR_BI) {
  467. *lsr &= ~(SPRD_LSR_FE | SPRD_LSR_PE);
  468. port->icount.brk++;
  469. ret = uart_handle_break(port);
  470. if (ret)
  471. return ret;
  472. } else if (*lsr & SPRD_LSR_PE)
  473. port->icount.parity++;
  474. else if (*lsr & SPRD_LSR_FE)
  475. port->icount.frame++;
  476. if (*lsr & SPRD_LSR_OE)
  477. port->icount.overrun++;
  478. /* mask off conditions which should be ignored */
  479. *lsr &= port->read_status_mask;
  480. if (*lsr & SPRD_LSR_BI)
  481. *flag = TTY_BREAK;
  482. else if (*lsr & SPRD_LSR_PE)
  483. *flag = TTY_PARITY;
  484. else if (*lsr & SPRD_LSR_FE)
  485. *flag = TTY_FRAME;
  486. return ret;
  487. }
  488. static inline void sprd_rx(struct uart_port *port)
  489. {
  490. struct sprd_uart_port *sp = container_of(port, struct sprd_uart_port,
  491. port);
  492. struct tty_port *tty = &port->state->port;
  493. unsigned int ch, flag, lsr, max_count = SPRD_TIMEOUT;
  494. if (sp->rx_dma.enable) {
  495. sprd_uart_dma_irq(port);
  496. return;
  497. }
  498. while ((serial_in(port, SPRD_STS1) & SPRD_RX_FIFO_CNT_MASK) &&
  499. max_count--) {
  500. lsr = serial_in(port, SPRD_LSR);
  501. ch = serial_in(port, SPRD_RXD);
  502. flag = TTY_NORMAL;
  503. port->icount.rx++;
  504. if (lsr & (SPRD_LSR_BI | SPRD_LSR_PE |
  505. SPRD_LSR_FE | SPRD_LSR_OE))
  506. if (handle_lsr_errors(port, &flag, &lsr))
  507. continue;
  508. if (uart_handle_sysrq_char(port, ch))
  509. continue;
  510. uart_insert_char(port, lsr, SPRD_LSR_OE, ch, flag);
  511. }
  512. tty_flip_buffer_push(tty);
  513. }
  514. static inline void sprd_tx(struct uart_port *port)
  515. {
  516. struct circ_buf *xmit = &port->state->xmit;
  517. int count;
  518. if (port->x_char) {
  519. serial_out(port, SPRD_TXD, port->x_char);
  520. port->icount.tx++;
  521. port->x_char = 0;
  522. return;
  523. }
  524. if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
  525. sprd_stop_tx(port);
  526. return;
  527. }
  528. count = THLD_TX_EMPTY;
  529. do {
  530. serial_out(port, SPRD_TXD, xmit->buf[xmit->tail]);
  531. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  532. port->icount.tx++;
  533. if (uart_circ_empty(xmit))
  534. break;
  535. } while (--count > 0);
  536. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  537. uart_write_wakeup(port);
  538. if (uart_circ_empty(xmit))
  539. sprd_stop_tx(port);
  540. }
  541. /* this handles the interrupt from one port */
  542. static irqreturn_t sprd_handle_irq(int irq, void *dev_id)
  543. {
  544. struct uart_port *port = dev_id;
  545. unsigned int ims;
  546. spin_lock(&port->lock);
  547. ims = serial_in(port, SPRD_IMSR);
  548. if (!ims) {
  549. spin_unlock(&port->lock);
  550. return IRQ_NONE;
  551. }
  552. if (ims & SPRD_IMSR_TIMEOUT)
  553. serial_out(port, SPRD_ICLR, SPRD_ICLR_TIMEOUT);
  554. if (ims & SPRD_IMSR_BREAK_DETECT)
  555. serial_out(port, SPRD_ICLR, SPRD_IMSR_BREAK_DETECT);
  556. if (ims & (SPRD_IMSR_RX_FIFO_FULL | SPRD_IMSR_BREAK_DETECT |
  557. SPRD_IMSR_TIMEOUT))
  558. sprd_rx(port);
  559. if (ims & SPRD_IMSR_TX_FIFO_EMPTY)
  560. sprd_tx(port);
  561. spin_unlock(&port->lock);
  562. return IRQ_HANDLED;
  563. }
  564. static void sprd_uart_dma_startup(struct uart_port *port,
  565. struct sprd_uart_port *sp)
  566. {
  567. int ret;
  568. sprd_request_dma(port);
  569. if (!(sp->rx_dma.enable || sp->tx_dma.enable))
  570. return;
  571. ret = sprd_start_dma_rx(port);
  572. if (ret) {
  573. sp->rx_dma.enable = false;
  574. dma_release_channel(sp->rx_dma.chn);
  575. dev_warn(port->dev, "fail to start RX dma mode\n");
  576. }
  577. sprd_uart_dma_enable(port, true);
  578. }
  579. static int sprd_startup(struct uart_port *port)
  580. {
  581. int ret = 0;
  582. unsigned int ien, fc;
  583. unsigned int timeout;
  584. struct sprd_uart_port *sp;
  585. unsigned long flags;
  586. serial_out(port, SPRD_CTL2,
  587. THLD_TX_EMPTY << THLD_TX_EMPTY_SHIFT | THLD_RX_FULL);
  588. /* clear rx fifo */
  589. timeout = SPRD_TIMEOUT;
  590. while (timeout-- && serial_in(port, SPRD_STS1) & SPRD_RX_FIFO_CNT_MASK)
  591. serial_in(port, SPRD_RXD);
  592. /* clear tx fifo */
  593. timeout = SPRD_TIMEOUT;
  594. while (timeout-- && serial_in(port, SPRD_STS1) & SPRD_TX_FIFO_CNT_MASK)
  595. cpu_relax();
  596. /* clear interrupt */
  597. serial_out(port, SPRD_IEN, 0);
  598. serial_out(port, SPRD_ICLR, ~0);
  599. /* allocate irq */
  600. sp = container_of(port, struct sprd_uart_port, port);
  601. snprintf(sp->name, sizeof(sp->name), "sprd_serial%d", port->line);
  602. sprd_uart_dma_startup(port, sp);
  603. ret = devm_request_irq(port->dev, port->irq, sprd_handle_irq,
  604. IRQF_SHARED, sp->name, port);
  605. if (ret) {
  606. dev_err(port->dev, "fail to request serial irq %d, ret=%d\n",
  607. port->irq, ret);
  608. return ret;
  609. }
  610. fc = serial_in(port, SPRD_CTL1);
  611. fc |= RX_TOUT_THLD_DEF | RX_HFC_THLD_DEF;
  612. serial_out(port, SPRD_CTL1, fc);
  613. /* enable interrupt */
  614. spin_lock_irqsave(&port->lock, flags);
  615. ien = serial_in(port, SPRD_IEN);
  616. ien |= SPRD_IEN_BREAK_DETECT | SPRD_IEN_TIMEOUT;
  617. if (!sp->rx_dma.enable)
  618. ien |= SPRD_IEN_RX_FULL;
  619. serial_out(port, SPRD_IEN, ien);
  620. spin_unlock_irqrestore(&port->lock, flags);
  621. return 0;
  622. }
  623. static void sprd_shutdown(struct uart_port *port)
  624. {
  625. sprd_release_dma(port);
  626. serial_out(port, SPRD_IEN, 0);
  627. serial_out(port, SPRD_ICLR, ~0);
  628. devm_free_irq(port->dev, port->irq, port);
  629. }
  630. static void sprd_set_termios(struct uart_port *port, struct ktermios *termios,
  631. const struct ktermios *old)
  632. {
  633. unsigned int baud, quot;
  634. unsigned int lcr = 0, fc;
  635. unsigned long flags;
  636. /* ask the core to calculate the divisor for us */
  637. baud = uart_get_baud_rate(port, termios, old, 0, SPRD_BAUD_IO_LIMIT);
  638. quot = port->uartclk / baud;
  639. /* set data length */
  640. switch (termios->c_cflag & CSIZE) {
  641. case CS5:
  642. lcr |= SPRD_LCR_DATA_LEN5;
  643. break;
  644. case CS6:
  645. lcr |= SPRD_LCR_DATA_LEN6;
  646. break;
  647. case CS7:
  648. lcr |= SPRD_LCR_DATA_LEN7;
  649. break;
  650. case CS8:
  651. default:
  652. lcr |= SPRD_LCR_DATA_LEN8;
  653. break;
  654. }
  655. /* calculate stop bits */
  656. lcr &= ~(SPRD_LCR_STOP_1BIT | SPRD_LCR_STOP_2BIT);
  657. if (termios->c_cflag & CSTOPB)
  658. lcr |= SPRD_LCR_STOP_2BIT;
  659. else
  660. lcr |= SPRD_LCR_STOP_1BIT;
  661. /* calculate parity */
  662. lcr &= ~SPRD_LCR_PARITY;
  663. termios->c_cflag &= ~CMSPAR; /* no support mark/space */
  664. if (termios->c_cflag & PARENB) {
  665. lcr |= SPRD_LCR_PARITY_EN;
  666. if (termios->c_cflag & PARODD)
  667. lcr |= SPRD_LCR_ODD_PAR;
  668. else
  669. lcr |= SPRD_LCR_EVEN_PAR;
  670. }
  671. spin_lock_irqsave(&port->lock, flags);
  672. /* update the per-port timeout */
  673. uart_update_timeout(port, termios->c_cflag, baud);
  674. port->read_status_mask = SPRD_LSR_OE;
  675. if (termios->c_iflag & INPCK)
  676. port->read_status_mask |= SPRD_LSR_FE | SPRD_LSR_PE;
  677. if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
  678. port->read_status_mask |= SPRD_LSR_BI;
  679. /* characters to ignore */
  680. port->ignore_status_mask = 0;
  681. if (termios->c_iflag & IGNPAR)
  682. port->ignore_status_mask |= SPRD_LSR_PE | SPRD_LSR_FE;
  683. if (termios->c_iflag & IGNBRK) {
  684. port->ignore_status_mask |= SPRD_LSR_BI;
  685. /*
  686. * If we're ignoring parity and break indicators,
  687. * ignore overruns too (for real raw support).
  688. */
  689. if (termios->c_iflag & IGNPAR)
  690. port->ignore_status_mask |= SPRD_LSR_OE;
  691. }
  692. /* flow control */
  693. fc = serial_in(port, SPRD_CTL1);
  694. fc &= ~(RX_HW_FLOW_CTL_THLD | RX_HW_FLOW_CTL_EN | TX_HW_FLOW_CTL_EN);
  695. if (termios->c_cflag & CRTSCTS) {
  696. fc |= RX_HW_FLOW_CTL_THLD;
  697. fc |= RX_HW_FLOW_CTL_EN;
  698. fc |= TX_HW_FLOW_CTL_EN;
  699. }
  700. /* clock divider bit0~bit15 */
  701. serial_out(port, SPRD_CLKD0, quot & SPRD_CLKD0_MASK);
  702. /* clock divider bit16~bit20 */
  703. serial_out(port, SPRD_CLKD1,
  704. (quot & SPRD_CLKD1_MASK) >> SPRD_CLKD1_SHIFT);
  705. serial_out(port, SPRD_LCR, lcr);
  706. fc |= RX_TOUT_THLD_DEF | RX_HFC_THLD_DEF;
  707. serial_out(port, SPRD_CTL1, fc);
  708. spin_unlock_irqrestore(&port->lock, flags);
  709. /* Don't rewrite B0 */
  710. if (tty_termios_baud_rate(termios))
  711. tty_termios_encode_baud_rate(termios, baud, baud);
  712. }
  713. static const char *sprd_type(struct uart_port *port)
  714. {
  715. return "SPX";
  716. }
  717. static void sprd_release_port(struct uart_port *port)
  718. {
  719. /* nothing to do */
  720. }
  721. static int sprd_request_port(struct uart_port *port)
  722. {
  723. return 0;
  724. }
  725. static void sprd_config_port(struct uart_port *port, int flags)
  726. {
  727. if (flags & UART_CONFIG_TYPE)
  728. port->type = PORT_SPRD;
  729. }
  730. static int sprd_verify_port(struct uart_port *port, struct serial_struct *ser)
  731. {
  732. if (ser->type != PORT_SPRD)
  733. return -EINVAL;
  734. if (port->irq != ser->irq)
  735. return -EINVAL;
  736. if (port->iotype != ser->io_type)
  737. return -EINVAL;
  738. return 0;
  739. }
  740. static void sprd_pm(struct uart_port *port, unsigned int state,
  741. unsigned int oldstate)
  742. {
  743. struct sprd_uart_port *sup =
  744. container_of(port, struct sprd_uart_port, port);
  745. switch (state) {
  746. case UART_PM_STATE_ON:
  747. clk_prepare_enable(sup->clk);
  748. break;
  749. case UART_PM_STATE_OFF:
  750. clk_disable_unprepare(sup->clk);
  751. break;
  752. }
  753. }
  754. #ifdef CONFIG_CONSOLE_POLL
  755. static int sprd_poll_init(struct uart_port *port)
  756. {
  757. if (port->state->pm_state != UART_PM_STATE_ON) {
  758. sprd_pm(port, UART_PM_STATE_ON, 0);
  759. port->state->pm_state = UART_PM_STATE_ON;
  760. }
  761. return 0;
  762. }
  763. static int sprd_poll_get_char(struct uart_port *port)
  764. {
  765. while (!(serial_in(port, SPRD_STS1) & SPRD_RX_FIFO_CNT_MASK))
  766. cpu_relax();
  767. return serial_in(port, SPRD_RXD);
  768. }
  769. static void sprd_poll_put_char(struct uart_port *port, unsigned char ch)
  770. {
  771. while (serial_in(port, SPRD_STS1) & SPRD_TX_FIFO_CNT_MASK)
  772. cpu_relax();
  773. serial_out(port, SPRD_TXD, ch);
  774. }
  775. #endif
  776. static const struct uart_ops serial_sprd_ops = {
  777. .tx_empty = sprd_tx_empty,
  778. .get_mctrl = sprd_get_mctrl,
  779. .set_mctrl = sprd_set_mctrl,
  780. .stop_tx = sprd_stop_tx,
  781. .start_tx = sprd_start_tx,
  782. .stop_rx = sprd_stop_rx,
  783. .break_ctl = sprd_break_ctl,
  784. .startup = sprd_startup,
  785. .shutdown = sprd_shutdown,
  786. .set_termios = sprd_set_termios,
  787. .type = sprd_type,
  788. .release_port = sprd_release_port,
  789. .request_port = sprd_request_port,
  790. .config_port = sprd_config_port,
  791. .verify_port = sprd_verify_port,
  792. .pm = sprd_pm,
  793. #ifdef CONFIG_CONSOLE_POLL
  794. .poll_init = sprd_poll_init,
  795. .poll_get_char = sprd_poll_get_char,
  796. .poll_put_char = sprd_poll_put_char,
  797. #endif
  798. };
  799. #ifdef CONFIG_SERIAL_SPRD_CONSOLE
  800. static void wait_for_xmitr(struct uart_port *port)
  801. {
  802. unsigned int status, tmout = 10000;
  803. /* wait up to 10ms for the character(s) to be sent */
  804. do {
  805. status = serial_in(port, SPRD_STS1);
  806. if (--tmout == 0)
  807. break;
  808. udelay(1);
  809. } while (status & SPRD_TX_FIFO_CNT_MASK);
  810. }
  811. static void sprd_console_putchar(struct uart_port *port, unsigned char ch)
  812. {
  813. wait_for_xmitr(port);
  814. serial_out(port, SPRD_TXD, ch);
  815. }
  816. static void sprd_console_write(struct console *co, const char *s,
  817. unsigned int count)
  818. {
  819. struct uart_port *port = &sprd_port[co->index]->port;
  820. int locked = 1;
  821. unsigned long flags;
  822. if (port->sysrq)
  823. locked = 0;
  824. else if (oops_in_progress)
  825. locked = spin_trylock_irqsave(&port->lock, flags);
  826. else
  827. spin_lock_irqsave(&port->lock, flags);
  828. uart_console_write(port, s, count, sprd_console_putchar);
  829. /* wait for transmitter to become empty */
  830. wait_for_xmitr(port);
  831. if (locked)
  832. spin_unlock_irqrestore(&port->lock, flags);
  833. }
  834. static int sprd_console_setup(struct console *co, char *options)
  835. {
  836. struct sprd_uart_port *sprd_uart_port;
  837. int baud = 115200;
  838. int bits = 8;
  839. int parity = 'n';
  840. int flow = 'n';
  841. if (co->index >= UART_NR_MAX || co->index < 0)
  842. co->index = 0;
  843. sprd_uart_port = sprd_port[co->index];
  844. if (!sprd_uart_port || !sprd_uart_port->port.membase) {
  845. pr_info("serial port %d not yet initialized\n", co->index);
  846. return -ENODEV;
  847. }
  848. if (options)
  849. uart_parse_options(options, &baud, &parity, &bits, &flow);
  850. return uart_set_options(&sprd_uart_port->port, co, baud,
  851. parity, bits, flow);
  852. }
  853. static struct uart_driver sprd_uart_driver;
  854. static struct console sprd_console = {
  855. .name = SPRD_TTY_NAME,
  856. .write = sprd_console_write,
  857. .device = uart_console_device,
  858. .setup = sprd_console_setup,
  859. .flags = CON_PRINTBUFFER,
  860. .index = -1,
  861. .data = &sprd_uart_driver,
  862. };
  863. static int __init sprd_serial_console_init(void)
  864. {
  865. register_console(&sprd_console);
  866. return 0;
  867. }
  868. console_initcall(sprd_serial_console_init);
  869. #define SPRD_CONSOLE (&sprd_console)
  870. /* Support for earlycon */
  871. static void sprd_putc(struct uart_port *port, unsigned char c)
  872. {
  873. unsigned int timeout = SPRD_TIMEOUT;
  874. while (timeout-- &&
  875. !(readl(port->membase + SPRD_LSR) & SPRD_LSR_TX_OVER))
  876. cpu_relax();
  877. writeb(c, port->membase + SPRD_TXD);
  878. }
  879. static void sprd_early_write(struct console *con, const char *s, unsigned int n)
  880. {
  881. struct earlycon_device *dev = con->data;
  882. uart_console_write(&dev->port, s, n, sprd_putc);
  883. }
  884. static int __init sprd_early_console_setup(struct earlycon_device *device,
  885. const char *opt)
  886. {
  887. if (!device->port.membase)
  888. return -ENODEV;
  889. device->con->write = sprd_early_write;
  890. return 0;
  891. }
  892. OF_EARLYCON_DECLARE(sprd_serial, "sprd,sc9836-uart",
  893. sprd_early_console_setup);
  894. #else /* !CONFIG_SERIAL_SPRD_CONSOLE */
  895. #define SPRD_CONSOLE NULL
  896. #endif
  897. static struct uart_driver sprd_uart_driver = {
  898. .owner = THIS_MODULE,
  899. .driver_name = "sprd_serial",
  900. .dev_name = SPRD_TTY_NAME,
  901. .major = 0,
  902. .minor = 0,
  903. .nr = UART_NR_MAX,
  904. .cons = SPRD_CONSOLE,
  905. };
  906. static int sprd_remove(struct platform_device *dev)
  907. {
  908. struct sprd_uart_port *sup = platform_get_drvdata(dev);
  909. if (sup) {
  910. uart_remove_one_port(&sprd_uart_driver, &sup->port);
  911. sprd_port[sup->port.line] = NULL;
  912. sprd_rx_free_buf(sup);
  913. sprd_ports_num--;
  914. }
  915. if (!sprd_ports_num)
  916. uart_unregister_driver(&sprd_uart_driver);
  917. return 0;
  918. }
  919. static bool sprd_uart_is_console(struct uart_port *uport)
  920. {
  921. struct console *cons = sprd_uart_driver.cons;
  922. if ((cons && cons->index >= 0 && cons->index == uport->line) ||
  923. of_console_check(uport->dev->of_node, SPRD_TTY_NAME, uport->line))
  924. return true;
  925. return false;
  926. }
  927. static int sprd_clk_init(struct uart_port *uport)
  928. {
  929. struct clk *clk_uart, *clk_parent;
  930. struct sprd_uart_port *u = container_of(uport, struct sprd_uart_port, port);
  931. clk_uart = devm_clk_get(uport->dev, "uart");
  932. if (IS_ERR(clk_uart)) {
  933. dev_warn(uport->dev, "uart%d can't get uart clock\n",
  934. uport->line);
  935. clk_uart = NULL;
  936. }
  937. clk_parent = devm_clk_get(uport->dev, "source");
  938. if (IS_ERR(clk_parent)) {
  939. dev_warn(uport->dev, "uart%d can't get source clock\n",
  940. uport->line);
  941. clk_parent = NULL;
  942. }
  943. if (!clk_uart || clk_set_parent(clk_uart, clk_parent))
  944. uport->uartclk = SPRD_DEFAULT_SOURCE_CLK;
  945. else
  946. uport->uartclk = clk_get_rate(clk_uart);
  947. u->clk = devm_clk_get(uport->dev, "enable");
  948. if (IS_ERR(u->clk)) {
  949. if (PTR_ERR(u->clk) == -EPROBE_DEFER)
  950. return -EPROBE_DEFER;
  951. dev_warn(uport->dev, "uart%d can't get enable clock\n",
  952. uport->line);
  953. /* To keep console alive even if the error occurred */
  954. if (!sprd_uart_is_console(uport))
  955. return PTR_ERR(u->clk);
  956. u->clk = NULL;
  957. }
  958. return 0;
  959. }
  960. static int sprd_probe(struct platform_device *pdev)
  961. {
  962. struct resource *res;
  963. struct uart_port *up;
  964. struct sprd_uart_port *sport;
  965. int irq;
  966. int index;
  967. int ret;
  968. index = of_alias_get_id(pdev->dev.of_node, "serial");
  969. if (index < 0 || index >= UART_NR_MAX) {
  970. dev_err(&pdev->dev, "got a wrong serial alias id %d\n", index);
  971. return -EINVAL;
  972. }
  973. sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
  974. if (!sport)
  975. return -ENOMEM;
  976. up = &sport->port;
  977. up->dev = &pdev->dev;
  978. up->line = index;
  979. up->type = PORT_SPRD;
  980. up->iotype = UPIO_MEM;
  981. up->uartclk = SPRD_DEF_RATE;
  982. up->fifosize = SPRD_FIFO_SIZE;
  983. up->ops = &serial_sprd_ops;
  984. up->flags = UPF_BOOT_AUTOCONF;
  985. up->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SPRD_CONSOLE);
  986. ret = sprd_clk_init(up);
  987. if (ret)
  988. return ret;
  989. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  990. up->membase = devm_ioremap_resource(&pdev->dev, res);
  991. if (IS_ERR(up->membase))
  992. return PTR_ERR(up->membase);
  993. up->mapbase = res->start;
  994. irq = platform_get_irq(pdev, 0);
  995. if (irq < 0)
  996. return irq;
  997. up->irq = irq;
  998. /*
  999. * Allocate one dma buffer to prepare for receive transfer, in case
  1000. * memory allocation failure at runtime.
  1001. */
  1002. ret = sprd_rx_alloc_buf(sport);
  1003. if (ret)
  1004. return ret;
  1005. if (!sprd_ports_num) {
  1006. ret = uart_register_driver(&sprd_uart_driver);
  1007. if (ret < 0) {
  1008. pr_err("Failed to register SPRD-UART driver\n");
  1009. goto free_rx_buf;
  1010. }
  1011. }
  1012. sprd_ports_num++;
  1013. sprd_port[index] = sport;
  1014. ret = uart_add_one_port(&sprd_uart_driver, up);
  1015. if (ret)
  1016. goto clean_port;
  1017. platform_set_drvdata(pdev, up);
  1018. return 0;
  1019. clean_port:
  1020. sprd_port[index] = NULL;
  1021. if (--sprd_ports_num == 0)
  1022. uart_unregister_driver(&sprd_uart_driver);
  1023. free_rx_buf:
  1024. sprd_rx_free_buf(sport);
  1025. return ret;
  1026. }
  1027. #ifdef CONFIG_PM_SLEEP
  1028. static int sprd_suspend(struct device *dev)
  1029. {
  1030. struct sprd_uart_port *sup = dev_get_drvdata(dev);
  1031. uart_suspend_port(&sprd_uart_driver, &sup->port);
  1032. return 0;
  1033. }
  1034. static int sprd_resume(struct device *dev)
  1035. {
  1036. struct sprd_uart_port *sup = dev_get_drvdata(dev);
  1037. uart_resume_port(&sprd_uart_driver, &sup->port);
  1038. return 0;
  1039. }
  1040. #endif
  1041. static SIMPLE_DEV_PM_OPS(sprd_pm_ops, sprd_suspend, sprd_resume);
  1042. static const struct of_device_id serial_ids[] = {
  1043. {.compatible = "sprd,sc9836-uart",},
  1044. {}
  1045. };
  1046. MODULE_DEVICE_TABLE(of, serial_ids);
  1047. static struct platform_driver sprd_platform_driver = {
  1048. .probe = sprd_probe,
  1049. .remove = sprd_remove,
  1050. .driver = {
  1051. .name = "sprd_serial",
  1052. .of_match_table = of_match_ptr(serial_ids),
  1053. .pm = &sprd_pm_ops,
  1054. },
  1055. };
  1056. module_platform_driver(sprd_platform_driver);
  1057. MODULE_LICENSE("GPL v2");
  1058. MODULE_DESCRIPTION("Spreadtrum SoC serial driver series");