8250_tegra.c 4.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Serial Port driver for Tegra devices
  4. *
  5. * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
  6. */
  7. #include <linux/acpi.h>
  8. #include <linux/clk.h>
  9. #include <linux/console.h>
  10. #include <linux/delay.h>
  11. #include <linux/io.h>
  12. #include <linux/module.h>
  13. #include <linux/reset.h>
  14. #include <linux/slab.h>
  15. #include "8250.h"
  16. struct tegra_uart {
  17. struct clk *clk;
  18. struct reset_control *rst;
  19. int line;
  20. };
  21. static void tegra_uart_handle_break(struct uart_port *p)
  22. {
  23. unsigned int status, tmout = 10000;
  24. while (1) {
  25. status = p->serial_in(p, UART_LSR);
  26. if (!(status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)))
  27. break;
  28. p->serial_in(p, UART_RX);
  29. if (--tmout == 0)
  30. break;
  31. udelay(1);
  32. }
  33. }
  34. static int tegra_uart_probe(struct platform_device *pdev)
  35. {
  36. struct uart_8250_port port8250;
  37. struct tegra_uart *uart;
  38. struct uart_port *port;
  39. struct resource *res;
  40. int ret;
  41. uart = devm_kzalloc(&pdev->dev, sizeof(*uart), GFP_KERNEL);
  42. if (!uart)
  43. return -ENOMEM;
  44. memset(&port8250, 0, sizeof(port8250));
  45. port = &port8250.port;
  46. spin_lock_init(&port->lock);
  47. port->flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT |
  48. UPF_FIXED_TYPE;
  49. port->iotype = UPIO_MEM32;
  50. port->regshift = 2;
  51. port->type = PORT_TEGRA;
  52. port->irqflags |= IRQF_SHARED;
  53. port->dev = &pdev->dev;
  54. port->handle_break = tegra_uart_handle_break;
  55. ret = of_alias_get_id(pdev->dev.of_node, "serial");
  56. if (ret >= 0)
  57. port->line = ret;
  58. ret = platform_get_irq(pdev, 0);
  59. if (ret < 0)
  60. return ret;
  61. port->irq = ret;
  62. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  63. if (!res)
  64. return -ENODEV;
  65. port->membase = devm_ioremap(&pdev->dev, res->start,
  66. resource_size(res));
  67. if (!port->membase)
  68. return -ENOMEM;
  69. port->mapbase = res->start;
  70. port->mapsize = resource_size(res);
  71. uart->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
  72. if (IS_ERR(uart->rst))
  73. return PTR_ERR(uart->rst);
  74. if (device_property_read_u32(&pdev->dev, "clock-frequency",
  75. &port->uartclk)) {
  76. uart->clk = devm_clk_get(&pdev->dev, NULL);
  77. if (IS_ERR(uart->clk)) {
  78. dev_err(&pdev->dev, "failed to get clock!\n");
  79. return -ENODEV;
  80. }
  81. ret = clk_prepare_enable(uart->clk);
  82. if (ret < 0)
  83. return ret;
  84. port->uartclk = clk_get_rate(uart->clk);
  85. }
  86. ret = reset_control_deassert(uart->rst);
  87. if (ret)
  88. goto err_clkdisable;
  89. ret = serial8250_register_8250_port(&port8250);
  90. if (ret < 0)
  91. goto err_ctrl_assert;
  92. platform_set_drvdata(pdev, uart);
  93. uart->line = ret;
  94. return 0;
  95. err_ctrl_assert:
  96. reset_control_assert(uart->rst);
  97. err_clkdisable:
  98. clk_disable_unprepare(uart->clk);
  99. return ret;
  100. }
  101. static int tegra_uart_remove(struct platform_device *pdev)
  102. {
  103. struct tegra_uart *uart = platform_get_drvdata(pdev);
  104. serial8250_unregister_port(uart->line);
  105. reset_control_assert(uart->rst);
  106. clk_disable_unprepare(uart->clk);
  107. return 0;
  108. }
  109. #ifdef CONFIG_PM_SLEEP
  110. static int tegra_uart_suspend(struct device *dev)
  111. {
  112. struct tegra_uart *uart = dev_get_drvdata(dev);
  113. struct uart_8250_port *port8250 = serial8250_get_port(uart->line);
  114. struct uart_port *port = &port8250->port;
  115. serial8250_suspend_port(uart->line);
  116. if (!uart_console(port) || console_suspend_enabled)
  117. clk_disable_unprepare(uart->clk);
  118. return 0;
  119. }
  120. static int tegra_uart_resume(struct device *dev)
  121. {
  122. struct tegra_uart *uart = dev_get_drvdata(dev);
  123. struct uart_8250_port *port8250 = serial8250_get_port(uart->line);
  124. struct uart_port *port = &port8250->port;
  125. if (!uart_console(port) || console_suspend_enabled)
  126. clk_prepare_enable(uart->clk);
  127. serial8250_resume_port(uart->line);
  128. return 0;
  129. }
  130. #endif
  131. static SIMPLE_DEV_PM_OPS(tegra_uart_pm_ops, tegra_uart_suspend,
  132. tegra_uart_resume);
  133. static const struct of_device_id tegra_uart_of_match[] = {
  134. { .compatible = "nvidia,tegra20-uart", },
  135. { },
  136. };
  137. MODULE_DEVICE_TABLE(of, tegra_uart_of_match);
  138. static const struct acpi_device_id tegra_uart_acpi_match[] __maybe_unused = {
  139. { "NVDA0100", 0 },
  140. { },
  141. };
  142. MODULE_DEVICE_TABLE(acpi, tegra_uart_acpi_match);
  143. static struct platform_driver tegra_uart_driver = {
  144. .driver = {
  145. .name = "tegra-uart",
  146. .pm = &tegra_uart_pm_ops,
  147. .of_match_table = tegra_uart_of_match,
  148. .acpi_match_table = ACPI_PTR(tegra_uart_acpi_match),
  149. },
  150. .probe = tegra_uart_probe,
  151. .remove = tegra_uart_remove,
  152. };
  153. module_platform_driver(tegra_uart_driver);
  154. MODULE_AUTHOR("Jeff Brasen <[email protected]>");
  155. MODULE_DESCRIPTION("NVIDIA Tegra 8250 Driver");
  156. MODULE_LICENSE("GPL v2");