8250_mtk.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Mediatek 8250 driver.
  4. *
  5. * Copyright (c) 2014 MundoReader S.L.
  6. * Author: Matthias Brugger <[email protected]>
  7. */
  8. #include <linux/clk.h>
  9. #include <linux/io.h>
  10. #include <linux/module.h>
  11. #include <linux/of_irq.h>
  12. #include <linux/of_platform.h>
  13. #include <linux/pinctrl/consumer.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/pm_runtime.h>
  16. #include <linux/serial_8250.h>
  17. #include <linux/serial_reg.h>
  18. #include <linux/console.h>
  19. #include <linux/dma-mapping.h>
  20. #include <linux/tty.h>
  21. #include <linux/tty_flip.h>
  22. #include "8250.h"
  23. #define MTK_UART_HIGHS 0x09 /* Highspeed register */
  24. #define MTK_UART_SAMPLE_COUNT 0x0a /* Sample count register */
  25. #define MTK_UART_SAMPLE_POINT 0x0b /* Sample point register */
  26. #define MTK_UART_RATE_FIX 0x0d /* UART Rate Fix Register */
  27. #define MTK_UART_ESCAPE_DAT 0x10 /* Escape Character register */
  28. #define MTK_UART_ESCAPE_EN 0x11 /* Escape Enable register */
  29. #define MTK_UART_DMA_EN 0x13 /* DMA Enable register */
  30. #define MTK_UART_RXTRI_AD 0x14 /* RX Trigger address */
  31. #define MTK_UART_FRACDIV_L 0x15 /* Fractional divider LSB address */
  32. #define MTK_UART_FRACDIV_M 0x16 /* Fractional divider MSB address */
  33. #define MTK_UART_DEBUG0 0x18
  34. #define MTK_UART_IER_XOFFI 0x20 /* Enable XOFF character interrupt */
  35. #define MTK_UART_IER_RTSI 0x40 /* Enable RTS Modem status interrupt */
  36. #define MTK_UART_IER_CTSI 0x80 /* Enable CTS Modem status interrupt */
  37. #define MTK_UART_EFR 38 /* I/O: Extended Features Register */
  38. #define MTK_UART_EFR_EN 0x10 /* Enable enhancement feature */
  39. #define MTK_UART_EFR_RTS 0x40 /* Enable hardware rx flow control */
  40. #define MTK_UART_EFR_CTS 0x80 /* Enable hardware tx flow control */
  41. #define MTK_UART_EFR_NO_SW_FC 0x0 /* no sw flow control */
  42. #define MTK_UART_EFR_XON1_XOFF1 0xa /* XON1/XOFF1 as sw flow control */
  43. #define MTK_UART_EFR_XON2_XOFF2 0x5 /* XON2/XOFF2 as sw flow control */
  44. #define MTK_UART_EFR_SW_FC_MASK 0xf /* Enable CTS Modem status interrupt */
  45. #define MTK_UART_EFR_HW_FC (MTK_UART_EFR_RTS | MTK_UART_EFR_CTS)
  46. #define MTK_UART_DMA_EN_TX 0x2
  47. #define MTK_UART_DMA_EN_RX 0x5
  48. #define MTK_UART_ESCAPE_CHAR 0x77 /* Escape char added under sw fc */
  49. #define MTK_UART_RX_SIZE 0x8000
  50. #define MTK_UART_TX_TRIGGER 1
  51. #define MTK_UART_RX_TRIGGER MTK_UART_RX_SIZE
  52. #define MTK_UART_XON1 40 /* I/O: Xon character 1 */
  53. #define MTK_UART_XOFF1 42 /* I/O: Xoff character 1 */
  54. #ifdef CONFIG_SERIAL_8250_DMA
  55. enum dma_rx_status {
  56. DMA_RX_START = 0,
  57. DMA_RX_RUNNING = 1,
  58. DMA_RX_SHUTDOWN = 2,
  59. };
  60. #endif
  61. struct mtk8250_data {
  62. int line;
  63. unsigned int rx_pos;
  64. unsigned int clk_count;
  65. struct clk *uart_clk;
  66. struct clk *bus_clk;
  67. struct uart_8250_dma *dma;
  68. #ifdef CONFIG_SERIAL_8250_DMA
  69. enum dma_rx_status rx_status;
  70. #endif
  71. int rx_wakeup_irq;
  72. };
  73. /* flow control mode */
  74. enum {
  75. MTK_UART_FC_NONE,
  76. MTK_UART_FC_SW,
  77. MTK_UART_FC_HW,
  78. };
  79. #ifdef CONFIG_SERIAL_8250_DMA
  80. static void mtk8250_rx_dma(struct uart_8250_port *up);
  81. static void mtk8250_dma_rx_complete(void *param)
  82. {
  83. struct uart_8250_port *up = param;
  84. struct uart_8250_dma *dma = up->dma;
  85. struct mtk8250_data *data = up->port.private_data;
  86. struct tty_port *tty_port = &up->port.state->port;
  87. struct dma_tx_state state;
  88. int copied, total, cnt;
  89. unsigned char *ptr;
  90. unsigned long flags;
  91. if (data->rx_status == DMA_RX_SHUTDOWN)
  92. return;
  93. spin_lock_irqsave(&up->port.lock, flags);
  94. dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
  95. total = dma->rx_size - state.residue;
  96. cnt = total;
  97. if ((data->rx_pos + cnt) > dma->rx_size)
  98. cnt = dma->rx_size - data->rx_pos;
  99. ptr = (unsigned char *)(data->rx_pos + dma->rx_buf);
  100. copied = tty_insert_flip_string(tty_port, ptr, cnt);
  101. data->rx_pos += cnt;
  102. if (total > cnt) {
  103. ptr = (unsigned char *)(dma->rx_buf);
  104. cnt = total - cnt;
  105. copied += tty_insert_flip_string(tty_port, ptr, cnt);
  106. data->rx_pos = cnt;
  107. }
  108. up->port.icount.rx += copied;
  109. tty_flip_buffer_push(tty_port);
  110. mtk8250_rx_dma(up);
  111. spin_unlock_irqrestore(&up->port.lock, flags);
  112. }
  113. static void mtk8250_rx_dma(struct uart_8250_port *up)
  114. {
  115. struct uart_8250_dma *dma = up->dma;
  116. struct dma_async_tx_descriptor *desc;
  117. desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
  118. dma->rx_size, DMA_DEV_TO_MEM,
  119. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  120. if (!desc) {
  121. pr_err("failed to prepare rx slave single\n");
  122. return;
  123. }
  124. desc->callback = mtk8250_dma_rx_complete;
  125. desc->callback_param = up;
  126. dma->rx_cookie = dmaengine_submit(desc);
  127. dma_async_issue_pending(dma->rxchan);
  128. }
  129. static void mtk8250_dma_enable(struct uart_8250_port *up)
  130. {
  131. struct uart_8250_dma *dma = up->dma;
  132. struct mtk8250_data *data = up->port.private_data;
  133. int lcr = serial_in(up, UART_LCR);
  134. if (data->rx_status != DMA_RX_START)
  135. return;
  136. dma->rxconf.src_port_window_size = dma->rx_size;
  137. dma->rxconf.src_addr = dma->rx_addr;
  138. dma->txconf.dst_port_window_size = UART_XMIT_SIZE;
  139. dma->txconf.dst_addr = dma->tx_addr;
  140. serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR |
  141. UART_FCR_CLEAR_XMIT);
  142. serial_out(up, MTK_UART_DMA_EN,
  143. MTK_UART_DMA_EN_RX | MTK_UART_DMA_EN_TX);
  144. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
  145. serial_out(up, MTK_UART_EFR, UART_EFR_ECB);
  146. serial_out(up, UART_LCR, lcr);
  147. if (dmaengine_slave_config(dma->rxchan, &dma->rxconf) != 0)
  148. pr_err("failed to configure rx dma channel\n");
  149. if (dmaengine_slave_config(dma->txchan, &dma->txconf) != 0)
  150. pr_err("failed to configure tx dma channel\n");
  151. data->rx_status = DMA_RX_RUNNING;
  152. data->rx_pos = 0;
  153. mtk8250_rx_dma(up);
  154. }
  155. #endif
  156. static int mtk8250_startup(struct uart_port *port)
  157. {
  158. #ifdef CONFIG_SERIAL_8250_DMA
  159. struct uart_8250_port *up = up_to_u8250p(port);
  160. struct mtk8250_data *data = port->private_data;
  161. /* disable DMA for console */
  162. if (uart_console(port))
  163. up->dma = NULL;
  164. if (up->dma) {
  165. data->rx_status = DMA_RX_START;
  166. uart_circ_clear(&port->state->xmit);
  167. }
  168. #endif
  169. memset(&port->icount, 0, sizeof(port->icount));
  170. return serial8250_do_startup(port);
  171. }
  172. static void mtk8250_shutdown(struct uart_port *port)
  173. {
  174. #ifdef CONFIG_SERIAL_8250_DMA
  175. struct uart_8250_port *up = up_to_u8250p(port);
  176. struct mtk8250_data *data = port->private_data;
  177. if (up->dma)
  178. data->rx_status = DMA_RX_SHUTDOWN;
  179. #endif
  180. return serial8250_do_shutdown(port);
  181. }
  182. static void mtk8250_disable_intrs(struct uart_8250_port *up, int mask)
  183. {
  184. serial_out(up, UART_IER, serial_in(up, UART_IER) & (~mask));
  185. }
  186. static void mtk8250_enable_intrs(struct uart_8250_port *up, int mask)
  187. {
  188. serial_out(up, UART_IER, serial_in(up, UART_IER) | mask);
  189. }
  190. static void mtk8250_set_flow_ctrl(struct uart_8250_port *up, int mode)
  191. {
  192. struct uart_port *port = &up->port;
  193. int lcr = serial_in(up, UART_LCR);
  194. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
  195. serial_out(up, MTK_UART_EFR, UART_EFR_ECB);
  196. serial_out(up, UART_LCR, lcr);
  197. lcr = serial_in(up, UART_LCR);
  198. switch (mode) {
  199. case MTK_UART_FC_NONE:
  200. serial_out(up, MTK_UART_ESCAPE_DAT, MTK_UART_ESCAPE_CHAR);
  201. serial_out(up, MTK_UART_ESCAPE_EN, 0x00);
  202. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
  203. serial_out(up, MTK_UART_EFR, serial_in(up, MTK_UART_EFR) &
  204. (~(MTK_UART_EFR_HW_FC | MTK_UART_EFR_SW_FC_MASK)));
  205. serial_out(up, UART_LCR, lcr);
  206. mtk8250_disable_intrs(up, MTK_UART_IER_XOFFI |
  207. MTK_UART_IER_RTSI | MTK_UART_IER_CTSI);
  208. break;
  209. case MTK_UART_FC_HW:
  210. serial_out(up, MTK_UART_ESCAPE_DAT, MTK_UART_ESCAPE_CHAR);
  211. serial_out(up, MTK_UART_ESCAPE_EN, 0x00);
  212. serial_out(up, UART_MCR, UART_MCR_RTS);
  213. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
  214. /*enable hw flow control*/
  215. serial_out(up, MTK_UART_EFR, MTK_UART_EFR_HW_FC |
  216. (serial_in(up, MTK_UART_EFR) &
  217. (~(MTK_UART_EFR_HW_FC | MTK_UART_EFR_SW_FC_MASK))));
  218. serial_out(up, UART_LCR, lcr);
  219. mtk8250_disable_intrs(up, MTK_UART_IER_XOFFI);
  220. mtk8250_enable_intrs(up, MTK_UART_IER_CTSI | MTK_UART_IER_RTSI);
  221. break;
  222. case MTK_UART_FC_SW: /*MTK software flow control */
  223. serial_out(up, MTK_UART_ESCAPE_DAT, MTK_UART_ESCAPE_CHAR);
  224. serial_out(up, MTK_UART_ESCAPE_EN, 0x01);
  225. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
  226. /*enable sw flow control */
  227. serial_out(up, MTK_UART_EFR, MTK_UART_EFR_XON1_XOFF1 |
  228. (serial_in(up, MTK_UART_EFR) &
  229. (~(MTK_UART_EFR_HW_FC | MTK_UART_EFR_SW_FC_MASK))));
  230. serial_out(up, MTK_UART_XON1, START_CHAR(port->state->port.tty));
  231. serial_out(up, MTK_UART_XOFF1, STOP_CHAR(port->state->port.tty));
  232. serial_out(up, UART_LCR, lcr);
  233. mtk8250_disable_intrs(up, MTK_UART_IER_CTSI|MTK_UART_IER_RTSI);
  234. mtk8250_enable_intrs(up, MTK_UART_IER_XOFFI);
  235. break;
  236. default:
  237. break;
  238. }
  239. }
  240. static void
  241. mtk8250_set_termios(struct uart_port *port, struct ktermios *termios,
  242. const struct ktermios *old)
  243. {
  244. static const unsigned short fraction_L_mapping[] = {
  245. 0, 1, 0x5, 0x15, 0x55, 0x57, 0x57, 0x77, 0x7F, 0xFF, 0xFF
  246. };
  247. static const unsigned short fraction_M_mapping[] = {
  248. 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 3
  249. };
  250. struct uart_8250_port *up = up_to_u8250p(port);
  251. unsigned int baud, quot, fraction;
  252. unsigned long flags;
  253. int mode;
  254. #ifdef CONFIG_SERIAL_8250_DMA
  255. if (up->dma) {
  256. if (uart_console(port)) {
  257. devm_kfree(up->port.dev, up->dma);
  258. up->dma = NULL;
  259. } else {
  260. mtk8250_dma_enable(up);
  261. }
  262. }
  263. #endif
  264. /*
  265. * Store the requested baud rate before calling the generic 8250
  266. * set_termios method. Standard 8250 port expects bauds to be
  267. * no higher than (uartclk / 16) so the baud will be clamped if it
  268. * gets out of that bound. Mediatek 8250 port supports speed
  269. * higher than that, therefore we'll get original baud rate back
  270. * after calling the generic set_termios method and recalculate
  271. * the speed later in this method.
  272. */
  273. baud = tty_termios_baud_rate(termios);
  274. serial8250_do_set_termios(port, termios, NULL);
  275. tty_termios_encode_baud_rate(termios, baud, baud);
  276. /*
  277. * Mediatek UARTs use an extra highspeed register (MTK_UART_HIGHS)
  278. *
  279. * We need to recalcualte the quot register, as the claculation depends
  280. * on the vaule in the highspeed register.
  281. *
  282. * Some baudrates are not supported by the chip, so we use the next
  283. * lower rate supported and update termios c_flag.
  284. *
  285. * If highspeed register is set to 3, we need to specify sample count
  286. * and sample point to increase accuracy. If not, we reset the
  287. * registers to their default values.
  288. */
  289. baud = uart_get_baud_rate(port, termios, old,
  290. port->uartclk / 16 / UART_DIV_MAX,
  291. port->uartclk);
  292. if (baud < 115200) {
  293. serial_port_out(port, MTK_UART_HIGHS, 0x0);
  294. quot = uart_get_divisor(port, baud);
  295. } else {
  296. serial_port_out(port, MTK_UART_HIGHS, 0x3);
  297. quot = DIV_ROUND_UP(port->uartclk, 256 * baud);
  298. }
  299. /*
  300. * Ok, we're now changing the port state. Do it with
  301. * interrupts disabled.
  302. */
  303. spin_lock_irqsave(&port->lock, flags);
  304. /*
  305. * Update the per-port timeout.
  306. */
  307. uart_update_timeout(port, termios->c_cflag, baud);
  308. /* set DLAB we have cval saved in up->lcr from the call to the core */
  309. serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
  310. serial_dl_write(up, quot);
  311. /* reset DLAB */
  312. serial_port_out(port, UART_LCR, up->lcr);
  313. if (baud >= 115200) {
  314. unsigned int tmp;
  315. tmp = (port->uartclk / (baud * quot)) - 1;
  316. serial_port_out(port, MTK_UART_SAMPLE_COUNT, tmp);
  317. serial_port_out(port, MTK_UART_SAMPLE_POINT,
  318. (tmp >> 1) - 1);
  319. /*count fraction to set fractoin register */
  320. fraction = ((port->uartclk * 100) / baud / quot) % 100;
  321. fraction = DIV_ROUND_CLOSEST(fraction, 10);
  322. serial_port_out(port, MTK_UART_FRACDIV_L,
  323. fraction_L_mapping[fraction]);
  324. serial_port_out(port, MTK_UART_FRACDIV_M,
  325. fraction_M_mapping[fraction]);
  326. } else {
  327. serial_port_out(port, MTK_UART_SAMPLE_COUNT, 0x00);
  328. serial_port_out(port, MTK_UART_SAMPLE_POINT, 0xff);
  329. serial_port_out(port, MTK_UART_FRACDIV_L, 0x00);
  330. serial_port_out(port, MTK_UART_FRACDIV_M, 0x00);
  331. }
  332. if ((termios->c_cflag & CRTSCTS) && (!(termios->c_iflag & CRTSCTS)))
  333. mode = MTK_UART_FC_HW;
  334. else if (termios->c_iflag & CRTSCTS)
  335. mode = MTK_UART_FC_SW;
  336. else
  337. mode = MTK_UART_FC_NONE;
  338. mtk8250_set_flow_ctrl(up, mode);
  339. if (uart_console(port))
  340. up->port.cons->cflag = termios->c_cflag;
  341. spin_unlock_irqrestore(&port->lock, flags);
  342. /* Don't rewrite B0 */
  343. if (tty_termios_baud_rate(termios))
  344. tty_termios_encode_baud_rate(termios, baud, baud);
  345. }
  346. static int __maybe_unused mtk8250_runtime_suspend(struct device *dev)
  347. {
  348. struct mtk8250_data *data = dev_get_drvdata(dev);
  349. struct uart_8250_port *up = serial8250_get_port(data->line);
  350. /* wait until UART in idle status */
  351. while
  352. (serial_in(up, MTK_UART_DEBUG0));
  353. if (data->clk_count == 0U) {
  354. dev_dbg(dev, "%s clock count is 0\n", __func__);
  355. } else {
  356. clk_disable_unprepare(data->bus_clk);
  357. data->clk_count--;
  358. }
  359. return 0;
  360. }
  361. static int __maybe_unused mtk8250_runtime_resume(struct device *dev)
  362. {
  363. struct mtk8250_data *data = dev_get_drvdata(dev);
  364. int err;
  365. if (data->clk_count > 0U) {
  366. dev_dbg(dev, "%s clock count is %d\n", __func__,
  367. data->clk_count);
  368. } else {
  369. err = clk_prepare_enable(data->bus_clk);
  370. if (err) {
  371. dev_warn(dev, "Can't enable bus clock\n");
  372. return err;
  373. }
  374. data->clk_count++;
  375. }
  376. return 0;
  377. }
  378. static void
  379. mtk8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
  380. {
  381. if (!state)
  382. if (!mtk8250_runtime_resume(port->dev))
  383. pm_runtime_get_sync(port->dev);
  384. serial8250_do_pm(port, state, old);
  385. if (state)
  386. if (!pm_runtime_put_sync_suspend(port->dev))
  387. mtk8250_runtime_suspend(port->dev);
  388. }
  389. #ifdef CONFIG_SERIAL_8250_DMA
  390. static bool mtk8250_dma_filter(struct dma_chan *chan, void *param)
  391. {
  392. return false;
  393. }
  394. #endif
  395. static int mtk8250_probe_of(struct platform_device *pdev, struct uart_port *p,
  396. struct mtk8250_data *data)
  397. {
  398. #ifdef CONFIG_SERIAL_8250_DMA
  399. int dmacnt;
  400. #endif
  401. data->uart_clk = devm_clk_get(&pdev->dev, "baud");
  402. if (IS_ERR(data->uart_clk)) {
  403. /*
  404. * For compatibility with older device trees try unnamed
  405. * clk when no baud clk can be found.
  406. */
  407. data->uart_clk = devm_clk_get(&pdev->dev, NULL);
  408. if (IS_ERR(data->uart_clk)) {
  409. dev_warn(&pdev->dev, "Can't get uart clock\n");
  410. return PTR_ERR(data->uart_clk);
  411. }
  412. return 0;
  413. }
  414. data->bus_clk = devm_clk_get(&pdev->dev, "bus");
  415. if (IS_ERR(data->bus_clk))
  416. return PTR_ERR(data->bus_clk);
  417. data->dma = NULL;
  418. #ifdef CONFIG_SERIAL_8250_DMA
  419. dmacnt = of_property_count_strings(pdev->dev.of_node, "dma-names");
  420. if (dmacnt == 2) {
  421. data->dma = devm_kzalloc(&pdev->dev, sizeof(*data->dma),
  422. GFP_KERNEL);
  423. if (!data->dma)
  424. return -ENOMEM;
  425. data->dma->fn = mtk8250_dma_filter;
  426. data->dma->rx_size = MTK_UART_RX_SIZE;
  427. data->dma->rxconf.src_maxburst = MTK_UART_RX_TRIGGER;
  428. data->dma->txconf.dst_maxburst = MTK_UART_TX_TRIGGER;
  429. }
  430. #endif
  431. return 0;
  432. }
  433. static int mtk8250_probe(struct platform_device *pdev)
  434. {
  435. struct uart_8250_port uart = {};
  436. struct mtk8250_data *data;
  437. struct resource *regs;
  438. int irq, err;
  439. irq = platform_get_irq(pdev, 0);
  440. if (irq < 0)
  441. return irq;
  442. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  443. if (!regs) {
  444. dev_err(&pdev->dev, "no registers defined\n");
  445. return -EINVAL;
  446. }
  447. uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
  448. resource_size(regs));
  449. if (!uart.port.membase)
  450. return -ENOMEM;
  451. data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
  452. if (!data)
  453. return -ENOMEM;
  454. data->clk_count = 0;
  455. if (pdev->dev.of_node) {
  456. err = mtk8250_probe_of(pdev, &uart.port, data);
  457. if (err)
  458. return err;
  459. } else
  460. return -ENODEV;
  461. spin_lock_init(&uart.port.lock);
  462. uart.port.mapbase = regs->start;
  463. uart.port.irq = irq;
  464. uart.port.pm = mtk8250_do_pm;
  465. uart.port.type = PORT_16550;
  466. uart.port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
  467. uart.port.dev = &pdev->dev;
  468. uart.port.iotype = UPIO_MEM32;
  469. uart.port.regshift = 2;
  470. uart.port.private_data = data;
  471. uart.port.shutdown = mtk8250_shutdown;
  472. uart.port.startup = mtk8250_startup;
  473. uart.port.set_termios = mtk8250_set_termios;
  474. uart.port.uartclk = clk_get_rate(data->uart_clk);
  475. #ifdef CONFIG_SERIAL_8250_DMA
  476. if (data->dma)
  477. uart.dma = data->dma;
  478. #endif
  479. /* Disable Rate Fix function */
  480. writel(0x0, uart.port.membase +
  481. (MTK_UART_RATE_FIX << uart.port.regshift));
  482. platform_set_drvdata(pdev, data);
  483. pm_runtime_enable(&pdev->dev);
  484. err = mtk8250_runtime_resume(&pdev->dev);
  485. if (err)
  486. goto err_pm_disable;
  487. data->line = serial8250_register_8250_port(&uart);
  488. if (data->line < 0) {
  489. err = data->line;
  490. goto err_pm_disable;
  491. }
  492. data->rx_wakeup_irq = platform_get_irq_optional(pdev, 1);
  493. return 0;
  494. err_pm_disable:
  495. pm_runtime_disable(&pdev->dev);
  496. return err;
  497. }
  498. static int mtk8250_remove(struct platform_device *pdev)
  499. {
  500. struct mtk8250_data *data = platform_get_drvdata(pdev);
  501. pm_runtime_get_sync(&pdev->dev);
  502. serial8250_unregister_port(data->line);
  503. pm_runtime_disable(&pdev->dev);
  504. pm_runtime_put_noidle(&pdev->dev);
  505. if (!pm_runtime_status_suspended(&pdev->dev))
  506. mtk8250_runtime_suspend(&pdev->dev);
  507. return 0;
  508. }
  509. static int __maybe_unused mtk8250_suspend(struct device *dev)
  510. {
  511. struct mtk8250_data *data = dev_get_drvdata(dev);
  512. int irq = data->rx_wakeup_irq;
  513. int err;
  514. serial8250_suspend_port(data->line);
  515. pinctrl_pm_select_sleep_state(dev);
  516. if (irq >= 0) {
  517. err = enable_irq_wake(irq);
  518. if (err) {
  519. dev_err(dev,
  520. "failed to enable irq wake on IRQ %d: %d\n",
  521. irq, err);
  522. pinctrl_pm_select_default_state(dev);
  523. serial8250_resume_port(data->line);
  524. return err;
  525. }
  526. }
  527. return 0;
  528. }
  529. static int __maybe_unused mtk8250_resume(struct device *dev)
  530. {
  531. struct mtk8250_data *data = dev_get_drvdata(dev);
  532. int irq = data->rx_wakeup_irq;
  533. if (irq >= 0)
  534. disable_irq_wake(irq);
  535. pinctrl_pm_select_default_state(dev);
  536. serial8250_resume_port(data->line);
  537. return 0;
  538. }
  539. static const struct dev_pm_ops mtk8250_pm_ops = {
  540. SET_SYSTEM_SLEEP_PM_OPS(mtk8250_suspend, mtk8250_resume)
  541. SET_RUNTIME_PM_OPS(mtk8250_runtime_suspend, mtk8250_runtime_resume,
  542. NULL)
  543. };
  544. static const struct of_device_id mtk8250_of_match[] = {
  545. { .compatible = "mediatek,mt6577-uart" },
  546. { /* Sentinel */ }
  547. };
  548. MODULE_DEVICE_TABLE(of, mtk8250_of_match);
  549. static struct platform_driver mtk8250_platform_driver = {
  550. .driver = {
  551. .name = "mt6577-uart",
  552. .pm = &mtk8250_pm_ops,
  553. .of_match_table = mtk8250_of_match,
  554. },
  555. .probe = mtk8250_probe,
  556. .remove = mtk8250_remove,
  557. };
  558. module_platform_driver(mtk8250_platform_driver);
  559. #ifdef CONFIG_SERIAL_8250_CONSOLE
  560. static int __init early_mtk8250_setup(struct earlycon_device *device,
  561. const char *options)
  562. {
  563. if (!device->port.membase)
  564. return -ENODEV;
  565. device->port.iotype = UPIO_MEM32;
  566. device->port.regshift = 2;
  567. return early_serial8250_setup(device, NULL);
  568. }
  569. OF_EARLYCON_DECLARE(mtk8250, "mediatek,mt6577-uart", early_mtk8250_setup);
  570. #endif
  571. MODULE_AUTHOR("Matthias Brugger");
  572. MODULE_LICENSE("GPL");
  573. MODULE_DESCRIPTION("Mediatek 8250 serial port driver");