8250_mid.c 9.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * 8250_mid.c - Driver for UART on Intel Penwell and various other Intel SOCs
  4. *
  5. * Copyright (C) 2015 Intel Corporation
  6. * Author: Heikki Krogerus <[email protected]>
  7. */
  8. #include <linux/bitops.h>
  9. #include <linux/module.h>
  10. #include <linux/pci.h>
  11. #include <linux/rational.h>
  12. #include <linux/dma/hsu.h>
  13. #include <linux/8250_pci.h>
  14. #include "8250.h"
  15. #define PCI_DEVICE_ID_INTEL_PNW_UART1 0x081b
  16. #define PCI_DEVICE_ID_INTEL_PNW_UART2 0x081c
  17. #define PCI_DEVICE_ID_INTEL_PNW_UART3 0x081d
  18. #define PCI_DEVICE_ID_INTEL_TNG_UART 0x1191
  19. #define PCI_DEVICE_ID_INTEL_CDF_UART 0x18d8
  20. #define PCI_DEVICE_ID_INTEL_DNV_UART 0x19d8
  21. /* Intel MID Specific registers */
  22. #define INTEL_MID_UART_FISR 0x08
  23. #define INTEL_MID_UART_PS 0x30
  24. #define INTEL_MID_UART_MUL 0x34
  25. #define INTEL_MID_UART_DIV 0x38
  26. struct mid8250;
  27. struct mid8250_board {
  28. unsigned int flags;
  29. unsigned long freq;
  30. unsigned int base_baud;
  31. int (*setup)(struct mid8250 *, struct uart_port *p);
  32. void (*exit)(struct mid8250 *);
  33. };
  34. struct mid8250 {
  35. int line;
  36. int dma_index;
  37. struct pci_dev *dma_dev;
  38. struct uart_8250_dma dma;
  39. struct mid8250_board *board;
  40. struct hsu_dma_chip dma_chip;
  41. };
  42. /*****************************************************************************/
  43. static int pnw_setup(struct mid8250 *mid, struct uart_port *p)
  44. {
  45. struct pci_dev *pdev = to_pci_dev(p->dev);
  46. switch (pdev->device) {
  47. case PCI_DEVICE_ID_INTEL_PNW_UART1:
  48. mid->dma_index = 0;
  49. break;
  50. case PCI_DEVICE_ID_INTEL_PNW_UART2:
  51. mid->dma_index = 1;
  52. break;
  53. case PCI_DEVICE_ID_INTEL_PNW_UART3:
  54. mid->dma_index = 2;
  55. break;
  56. default:
  57. return -EINVAL;
  58. }
  59. mid->dma_dev = pci_get_slot(pdev->bus,
  60. PCI_DEVFN(PCI_SLOT(pdev->devfn), 3));
  61. return 0;
  62. }
  63. static void pnw_exit(struct mid8250 *mid)
  64. {
  65. pci_dev_put(mid->dma_dev);
  66. }
  67. static int tng_handle_irq(struct uart_port *p)
  68. {
  69. struct mid8250 *mid = p->private_data;
  70. struct uart_8250_port *up = up_to_u8250p(p);
  71. struct hsu_dma_chip *chip;
  72. u32 status;
  73. int ret = 0;
  74. int err;
  75. chip = pci_get_drvdata(mid->dma_dev);
  76. /* Rx DMA */
  77. err = hsu_dma_get_status(chip, mid->dma_index * 2 + 1, &status);
  78. if (err > 0) {
  79. serial8250_rx_dma_flush(up);
  80. ret |= 1;
  81. } else if (err == 0)
  82. ret |= hsu_dma_do_irq(chip, mid->dma_index * 2 + 1, status);
  83. /* Tx DMA */
  84. err = hsu_dma_get_status(chip, mid->dma_index * 2, &status);
  85. if (err > 0)
  86. ret |= 1;
  87. else if (err == 0)
  88. ret |= hsu_dma_do_irq(chip, mid->dma_index * 2, status);
  89. /* UART */
  90. ret |= serial8250_handle_irq(p, serial_port_in(p, UART_IIR));
  91. return IRQ_RETVAL(ret);
  92. }
  93. static int tng_setup(struct mid8250 *mid, struct uart_port *p)
  94. {
  95. struct pci_dev *pdev = to_pci_dev(p->dev);
  96. int index = PCI_FUNC(pdev->devfn);
  97. /*
  98. * Device 0000:00:04.0 is not a real HSU port. It provides a global
  99. * register set for all HSU ports, although it has the same PCI ID.
  100. * Skip it here.
  101. */
  102. if (index-- == 0)
  103. return -ENODEV;
  104. mid->dma_index = index;
  105. mid->dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(5, 0));
  106. p->handle_irq = tng_handle_irq;
  107. return 0;
  108. }
  109. static void tng_exit(struct mid8250 *mid)
  110. {
  111. pci_dev_put(mid->dma_dev);
  112. }
  113. static int dnv_handle_irq(struct uart_port *p)
  114. {
  115. struct mid8250 *mid = p->private_data;
  116. struct uart_8250_port *up = up_to_u8250p(p);
  117. unsigned int fisr = serial_port_in(p, INTEL_MID_UART_FISR);
  118. u32 status;
  119. int ret = 0;
  120. int err;
  121. if (fisr & BIT(2)) {
  122. err = hsu_dma_get_status(&mid->dma_chip, 1, &status);
  123. if (err > 0) {
  124. serial8250_rx_dma_flush(up);
  125. ret |= 1;
  126. } else if (err == 0)
  127. ret |= hsu_dma_do_irq(&mid->dma_chip, 1, status);
  128. }
  129. if (fisr & BIT(1)) {
  130. err = hsu_dma_get_status(&mid->dma_chip, 0, &status);
  131. if (err > 0)
  132. ret |= 1;
  133. else if (err == 0)
  134. ret |= hsu_dma_do_irq(&mid->dma_chip, 0, status);
  135. }
  136. if (fisr & BIT(0))
  137. ret |= serial8250_handle_irq(p, serial_port_in(p, UART_IIR));
  138. return IRQ_RETVAL(ret);
  139. }
  140. #define DNV_DMA_CHAN_OFFSET 0x80
  141. static int dnv_setup(struct mid8250 *mid, struct uart_port *p)
  142. {
  143. struct hsu_dma_chip *chip = &mid->dma_chip;
  144. struct pci_dev *pdev = to_pci_dev(p->dev);
  145. unsigned int bar = FL_GET_BASE(mid->board->flags);
  146. int ret;
  147. pci_set_master(pdev);
  148. ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
  149. if (ret < 0)
  150. return ret;
  151. p->irq = pci_irq_vector(pdev, 0);
  152. chip->dev = &pdev->dev;
  153. chip->irq = pci_irq_vector(pdev, 0);
  154. chip->regs = p->membase;
  155. chip->length = pci_resource_len(pdev, bar);
  156. chip->offset = DNV_DMA_CHAN_OFFSET;
  157. /* Falling back to PIO mode if DMA probing fails */
  158. ret = hsu_dma_probe(chip);
  159. if (ret)
  160. return 0;
  161. mid->dma_dev = pdev;
  162. p->handle_irq = dnv_handle_irq;
  163. return 0;
  164. }
  165. static void dnv_exit(struct mid8250 *mid)
  166. {
  167. if (!mid->dma_dev)
  168. return;
  169. hsu_dma_remove(&mid->dma_chip);
  170. }
  171. /*****************************************************************************/
  172. static void mid8250_set_termios(struct uart_port *p, struct ktermios *termios,
  173. const struct ktermios *old)
  174. {
  175. unsigned int baud = tty_termios_baud_rate(termios);
  176. struct mid8250 *mid = p->private_data;
  177. unsigned short ps = 16;
  178. unsigned long fuart = baud * ps;
  179. unsigned long w = BIT(24) - 1;
  180. unsigned long mul, div;
  181. /* Gracefully handle the B0 case: fall back to B9600 */
  182. fuart = fuart ? fuart : 9600 * 16;
  183. if (mid->board->freq < fuart) {
  184. /* Find prescaler value that satisfies Fuart < Fref */
  185. if (mid->board->freq > baud)
  186. ps = mid->board->freq / baud; /* baud rate too high */
  187. else
  188. ps = 1; /* PLL case */
  189. fuart = baud * ps;
  190. } else {
  191. /* Get Fuart closer to Fref */
  192. fuart *= rounddown_pow_of_two(mid->board->freq / fuart);
  193. }
  194. rational_best_approximation(fuart, mid->board->freq, w, w, &mul, &div);
  195. p->uartclk = fuart * 16 / ps; /* core uses ps = 16 always */
  196. writel(ps, p->membase + INTEL_MID_UART_PS); /* set PS */
  197. writel(mul, p->membase + INTEL_MID_UART_MUL); /* set MUL */
  198. writel(div, p->membase + INTEL_MID_UART_DIV);
  199. serial8250_do_set_termios(p, termios, old);
  200. }
  201. static bool mid8250_dma_filter(struct dma_chan *chan, void *param)
  202. {
  203. struct hsu_dma_slave *s = param;
  204. if (s->dma_dev != chan->device->dev || s->chan_id != chan->chan_id)
  205. return false;
  206. chan->private = s;
  207. return true;
  208. }
  209. static int mid8250_dma_setup(struct mid8250 *mid, struct uart_8250_port *port)
  210. {
  211. struct uart_8250_dma *dma = &mid->dma;
  212. struct device *dev = port->port.dev;
  213. struct hsu_dma_slave *rx_param;
  214. struct hsu_dma_slave *tx_param;
  215. if (!mid->dma_dev)
  216. return 0;
  217. rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
  218. if (!rx_param)
  219. return -ENOMEM;
  220. tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
  221. if (!tx_param)
  222. return -ENOMEM;
  223. rx_param->chan_id = mid->dma_index * 2 + 1;
  224. tx_param->chan_id = mid->dma_index * 2;
  225. dma->rxconf.src_maxburst = 64;
  226. dma->txconf.dst_maxburst = 64;
  227. rx_param->dma_dev = &mid->dma_dev->dev;
  228. tx_param->dma_dev = &mid->dma_dev->dev;
  229. dma->fn = mid8250_dma_filter;
  230. dma->rx_param = rx_param;
  231. dma->tx_param = tx_param;
  232. port->dma = dma;
  233. return 0;
  234. }
  235. static int mid8250_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  236. {
  237. struct uart_8250_port uart;
  238. struct mid8250 *mid;
  239. unsigned int bar;
  240. int ret;
  241. ret = pcim_enable_device(pdev);
  242. if (ret)
  243. return ret;
  244. mid = devm_kzalloc(&pdev->dev, sizeof(*mid), GFP_KERNEL);
  245. if (!mid)
  246. return -ENOMEM;
  247. mid->board = (struct mid8250_board *)id->driver_data;
  248. bar = FL_GET_BASE(mid->board->flags);
  249. memset(&uart, 0, sizeof(struct uart_8250_port));
  250. uart.port.dev = &pdev->dev;
  251. uart.port.irq = pdev->irq;
  252. uart.port.private_data = mid;
  253. uart.port.type = PORT_16750;
  254. uart.port.iotype = UPIO_MEM;
  255. uart.port.uartclk = mid->board->base_baud * 16;
  256. uart.port.flags = UPF_SHARE_IRQ | UPF_FIXED_PORT | UPF_FIXED_TYPE;
  257. uart.port.set_termios = mid8250_set_termios;
  258. uart.port.mapbase = pci_resource_start(pdev, bar);
  259. uart.port.membase = pcim_iomap(pdev, bar, 0);
  260. if (!uart.port.membase)
  261. return -ENOMEM;
  262. ret = mid->board->setup(mid, &uart.port);
  263. if (ret)
  264. return ret;
  265. ret = mid8250_dma_setup(mid, &uart);
  266. if (ret)
  267. goto err;
  268. ret = serial8250_register_8250_port(&uart);
  269. if (ret < 0)
  270. goto err;
  271. mid->line = ret;
  272. pci_set_drvdata(pdev, mid);
  273. return 0;
  274. err:
  275. mid->board->exit(mid);
  276. return ret;
  277. }
  278. static void mid8250_remove(struct pci_dev *pdev)
  279. {
  280. struct mid8250 *mid = pci_get_drvdata(pdev);
  281. serial8250_unregister_port(mid->line);
  282. mid->board->exit(mid);
  283. }
  284. static const struct mid8250_board pnw_board = {
  285. .flags = FL_BASE0,
  286. .freq = 50000000,
  287. .base_baud = 115200,
  288. .setup = pnw_setup,
  289. .exit = pnw_exit,
  290. };
  291. static const struct mid8250_board tng_board = {
  292. .flags = FL_BASE0,
  293. .freq = 38400000,
  294. .base_baud = 1843200,
  295. .setup = tng_setup,
  296. .exit = tng_exit,
  297. };
  298. static const struct mid8250_board dnv_board = {
  299. .flags = FL_BASE1,
  300. .freq = 133333333,
  301. .base_baud = 115200,
  302. .setup = dnv_setup,
  303. .exit = dnv_exit,
  304. };
  305. static const struct pci_device_id pci_ids[] = {
  306. { PCI_DEVICE_DATA(INTEL, PNW_UART1, &pnw_board) },
  307. { PCI_DEVICE_DATA(INTEL, PNW_UART2, &pnw_board) },
  308. { PCI_DEVICE_DATA(INTEL, PNW_UART3, &pnw_board) },
  309. { PCI_DEVICE_DATA(INTEL, TNG_UART, &tng_board) },
  310. { PCI_DEVICE_DATA(INTEL, CDF_UART, &dnv_board) },
  311. { PCI_DEVICE_DATA(INTEL, DNV_UART, &dnv_board) },
  312. { }
  313. };
  314. MODULE_DEVICE_TABLE(pci, pci_ids);
  315. static struct pci_driver mid8250_pci_driver = {
  316. .name = "8250_mid",
  317. .id_table = pci_ids,
  318. .probe = mid8250_probe,
  319. .remove = mid8250_remove,
  320. };
  321. module_pci_driver(mid8250_pci_driver);
  322. MODULE_AUTHOR("Intel Corporation");
  323. MODULE_LICENSE("GPL v2");
  324. MODULE_DESCRIPTION("Intel MID UART driver");