8250_ingenic.c 8.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2010 Lars-Peter Clausen <[email protected]>
  4. * Copyright (C) 2015 Imagination Technologies
  5. *
  6. * Ingenic SoC UART support
  7. */
  8. #include <linux/clk.h>
  9. #include <linux/console.h>
  10. #include <linux/io.h>
  11. #include <linux/libfdt.h>
  12. #include <linux/module.h>
  13. #include <linux/of.h>
  14. #include <linux/of_fdt.h>
  15. #include <linux/of_device.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/serial_8250.h>
  18. #include <linux/serial_core.h>
  19. #include <linux/serial_reg.h>
  20. #include "8250.h"
  21. /** ingenic_uart_config: SOC specific config data. */
  22. struct ingenic_uart_config {
  23. int tx_loadsz;
  24. int fifosize;
  25. };
  26. struct ingenic_uart_data {
  27. struct clk *clk_module;
  28. struct clk *clk_baud;
  29. int line;
  30. };
  31. static const struct of_device_id of_match[];
  32. #define UART_FCR_UME BIT(4)
  33. #define UART_MCR_MDCE BIT(7)
  34. #define UART_MCR_FCM BIT(6)
  35. static struct earlycon_device *early_device;
  36. static uint8_t early_in(struct uart_port *port, int offset)
  37. {
  38. return readl(port->membase + (offset << 2));
  39. }
  40. static void early_out(struct uart_port *port, int offset, uint8_t value)
  41. {
  42. writel(value, port->membase + (offset << 2));
  43. }
  44. static void ingenic_early_console_putc(struct uart_port *port, unsigned char c)
  45. {
  46. u16 lsr;
  47. do {
  48. lsr = early_in(port, UART_LSR);
  49. } while ((lsr & UART_LSR_TEMT) == 0);
  50. early_out(port, UART_TX, c);
  51. }
  52. static void ingenic_early_console_write(struct console *console,
  53. const char *s, unsigned int count)
  54. {
  55. uart_console_write(&early_device->port, s, count,
  56. ingenic_early_console_putc);
  57. }
  58. static void __init ingenic_early_console_setup_clock(struct earlycon_device *dev)
  59. {
  60. void *fdt = initial_boot_params;
  61. const __be32 *prop;
  62. int offset;
  63. offset = fdt_path_offset(fdt, "/ext");
  64. if (offset < 0)
  65. return;
  66. prop = fdt_getprop(fdt, offset, "clock-frequency", NULL);
  67. if (!prop)
  68. return;
  69. dev->port.uartclk = be32_to_cpup(prop);
  70. }
  71. static int __init ingenic_early_console_setup(struct earlycon_device *dev,
  72. const char *opt)
  73. {
  74. struct uart_port *port = &dev->port;
  75. unsigned int divisor;
  76. int baud = 115200;
  77. if (!dev->port.membase)
  78. return -ENODEV;
  79. if (opt) {
  80. unsigned int parity, bits, flow; /* unused for now */
  81. uart_parse_options(opt, &baud, &parity, &bits, &flow);
  82. }
  83. ingenic_early_console_setup_clock(dev);
  84. if (dev->baud)
  85. baud = dev->baud;
  86. divisor = DIV_ROUND_CLOSEST(port->uartclk, 16 * baud);
  87. early_out(port, UART_IER, 0);
  88. early_out(port, UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN8);
  89. early_out(port, UART_DLL, 0);
  90. early_out(port, UART_DLM, 0);
  91. early_out(port, UART_LCR, UART_LCR_WLEN8);
  92. early_out(port, UART_FCR, UART_FCR_UME | UART_FCR_CLEAR_XMIT |
  93. UART_FCR_CLEAR_RCVR | UART_FCR_ENABLE_FIFO);
  94. early_out(port, UART_MCR, UART_MCR_RTS | UART_MCR_DTR);
  95. early_out(port, UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN8);
  96. early_out(port, UART_DLL, divisor & 0xff);
  97. early_out(port, UART_DLM, (divisor >> 8) & 0xff);
  98. early_out(port, UART_LCR, UART_LCR_WLEN8);
  99. early_device = dev;
  100. dev->con->write = ingenic_early_console_write;
  101. return 0;
  102. }
  103. OF_EARLYCON_DECLARE(jz4740_uart, "ingenic,jz4740-uart",
  104. ingenic_early_console_setup);
  105. OF_EARLYCON_DECLARE(jz4770_uart, "ingenic,jz4770-uart",
  106. ingenic_early_console_setup);
  107. OF_EARLYCON_DECLARE(jz4775_uart, "ingenic,jz4775-uart",
  108. ingenic_early_console_setup);
  109. OF_EARLYCON_DECLARE(jz4780_uart, "ingenic,jz4780-uart",
  110. ingenic_early_console_setup);
  111. OF_EARLYCON_DECLARE(x1000_uart, "ingenic,x1000-uart",
  112. ingenic_early_console_setup);
  113. static void ingenic_uart_serial_out(struct uart_port *p, int offset, int value)
  114. {
  115. int ier;
  116. switch (offset) {
  117. case UART_FCR:
  118. /* UART module enable */
  119. value |= UART_FCR_UME;
  120. break;
  121. case UART_IER:
  122. /*
  123. * Enable receive timeout interrupt with the receive line
  124. * status interrupt.
  125. */
  126. value |= (value & 0x4) << 2;
  127. break;
  128. case UART_MCR:
  129. /*
  130. * If we have enabled modem status IRQs we should enable
  131. * modem mode.
  132. */
  133. ier = p->serial_in(p, UART_IER);
  134. if (ier & UART_IER_MSI)
  135. value |= UART_MCR_MDCE | UART_MCR_FCM;
  136. else
  137. value &= ~(UART_MCR_MDCE | UART_MCR_FCM);
  138. break;
  139. default:
  140. break;
  141. }
  142. writeb(value, p->membase + (offset << p->regshift));
  143. }
  144. static unsigned int ingenic_uart_serial_in(struct uart_port *p, int offset)
  145. {
  146. unsigned int value;
  147. value = readb(p->membase + (offset << p->regshift));
  148. /* Hide non-16550 compliant bits from higher levels */
  149. switch (offset) {
  150. case UART_FCR:
  151. value &= ~UART_FCR_UME;
  152. break;
  153. case UART_MCR:
  154. value &= ~(UART_MCR_MDCE | UART_MCR_FCM);
  155. break;
  156. default:
  157. break;
  158. }
  159. return value;
  160. }
  161. static int ingenic_uart_probe(struct platform_device *pdev)
  162. {
  163. struct uart_8250_port uart = {};
  164. struct ingenic_uart_data *data;
  165. const struct ingenic_uart_config *cdata;
  166. struct resource *regs;
  167. int irq, err, line;
  168. cdata = of_device_get_match_data(&pdev->dev);
  169. if (!cdata) {
  170. dev_err(&pdev->dev, "Error: No device match found\n");
  171. return -ENODEV;
  172. }
  173. irq = platform_get_irq(pdev, 0);
  174. if (irq < 0)
  175. return irq;
  176. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  177. if (!regs) {
  178. dev_err(&pdev->dev, "no registers defined\n");
  179. return -EINVAL;
  180. }
  181. data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
  182. if (!data)
  183. return -ENOMEM;
  184. spin_lock_init(&uart.port.lock);
  185. uart.port.type = PORT_16550A;
  186. uart.port.flags = UPF_SKIP_TEST | UPF_IOREMAP | UPF_FIXED_TYPE;
  187. uart.port.iotype = UPIO_MEM;
  188. uart.port.mapbase = regs->start;
  189. uart.port.regshift = 2;
  190. uart.port.serial_out = ingenic_uart_serial_out;
  191. uart.port.serial_in = ingenic_uart_serial_in;
  192. uart.port.irq = irq;
  193. uart.port.dev = &pdev->dev;
  194. uart.port.fifosize = cdata->fifosize;
  195. uart.tx_loadsz = cdata->tx_loadsz;
  196. uart.capabilities = UART_CAP_FIFO | UART_CAP_RTOIE;
  197. /* Check for a fixed line number */
  198. line = of_alias_get_id(pdev->dev.of_node, "serial");
  199. if (line >= 0)
  200. uart.port.line = line;
  201. uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
  202. resource_size(regs));
  203. if (!uart.port.membase)
  204. return -ENOMEM;
  205. data->clk_module = devm_clk_get(&pdev->dev, "module");
  206. if (IS_ERR(data->clk_module))
  207. return dev_err_probe(&pdev->dev, PTR_ERR(data->clk_module),
  208. "unable to get module clock\n");
  209. data->clk_baud = devm_clk_get(&pdev->dev, "baud");
  210. if (IS_ERR(data->clk_baud))
  211. return dev_err_probe(&pdev->dev, PTR_ERR(data->clk_baud),
  212. "unable to get baud clock\n");
  213. err = clk_prepare_enable(data->clk_module);
  214. if (err) {
  215. dev_err(&pdev->dev, "could not enable module clock: %d\n", err);
  216. goto out;
  217. }
  218. err = clk_prepare_enable(data->clk_baud);
  219. if (err) {
  220. dev_err(&pdev->dev, "could not enable baud clock: %d\n", err);
  221. goto out_disable_moduleclk;
  222. }
  223. uart.port.uartclk = clk_get_rate(data->clk_baud);
  224. data->line = serial8250_register_8250_port(&uart);
  225. if (data->line < 0) {
  226. err = data->line;
  227. goto out_disable_baudclk;
  228. }
  229. platform_set_drvdata(pdev, data);
  230. return 0;
  231. out_disable_baudclk:
  232. clk_disable_unprepare(data->clk_baud);
  233. out_disable_moduleclk:
  234. clk_disable_unprepare(data->clk_module);
  235. out:
  236. return err;
  237. }
  238. static int ingenic_uart_remove(struct platform_device *pdev)
  239. {
  240. struct ingenic_uart_data *data = platform_get_drvdata(pdev);
  241. serial8250_unregister_port(data->line);
  242. clk_disable_unprepare(data->clk_module);
  243. clk_disable_unprepare(data->clk_baud);
  244. return 0;
  245. }
  246. static const struct ingenic_uart_config jz4740_uart_config = {
  247. .tx_loadsz = 8,
  248. .fifosize = 16,
  249. };
  250. static const struct ingenic_uart_config jz4760_uart_config = {
  251. .tx_loadsz = 16,
  252. .fifosize = 32,
  253. };
  254. static const struct ingenic_uart_config jz4780_uart_config = {
  255. .tx_loadsz = 32,
  256. .fifosize = 64,
  257. };
  258. static const struct ingenic_uart_config x1000_uart_config = {
  259. .tx_loadsz = 32,
  260. .fifosize = 64,
  261. };
  262. static const struct of_device_id of_match[] = {
  263. { .compatible = "ingenic,jz4740-uart", .data = &jz4740_uart_config },
  264. { .compatible = "ingenic,jz4760-uart", .data = &jz4760_uart_config },
  265. { .compatible = "ingenic,jz4770-uart", .data = &jz4760_uart_config },
  266. { .compatible = "ingenic,jz4775-uart", .data = &jz4760_uart_config },
  267. { .compatible = "ingenic,jz4780-uart", .data = &jz4780_uart_config },
  268. { .compatible = "ingenic,x1000-uart", .data = &x1000_uart_config },
  269. { /* sentinel */ }
  270. };
  271. MODULE_DEVICE_TABLE(of, of_match);
  272. static struct platform_driver ingenic_uart_platform_driver = {
  273. .driver = {
  274. .name = "ingenic-uart",
  275. .of_match_table = of_match,
  276. },
  277. .probe = ingenic_uart_probe,
  278. .remove = ingenic_uart_remove,
  279. };
  280. module_platform_driver(ingenic_uart_platform_driver);
  281. MODULE_AUTHOR("Paul Burton");
  282. MODULE_LICENSE("GPL");
  283. MODULE_DESCRIPTION("Ingenic SoC UART driver");