spi-st-ssc4.c 10 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2008-2014 STMicroelectronics Limited
  4. *
  5. * Author: Angus Clark <[email protected]>
  6. * Patrice Chotard <[email protected]>
  7. * Lee Jones <[email protected]>
  8. *
  9. * SPI master mode controller driver, used in STMicroelectronics devices.
  10. */
  11. #include <linux/clk.h>
  12. #include <linux/delay.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/io.h>
  15. #include <linux/module.h>
  16. #include <linux/pinctrl/consumer.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/of.h>
  19. #include <linux/of_irq.h>
  20. #include <linux/pm_runtime.h>
  21. #include <linux/spi/spi.h>
  22. #include <linux/spi/spi_bitbang.h>
  23. /* SSC registers */
  24. #define SSC_BRG 0x000
  25. #define SSC_TBUF 0x004
  26. #define SSC_RBUF 0x008
  27. #define SSC_CTL 0x00C
  28. #define SSC_IEN 0x010
  29. #define SSC_I2C 0x018
  30. /* SSC Control */
  31. #define SSC_CTL_DATA_WIDTH_9 0x8
  32. #define SSC_CTL_DATA_WIDTH_MSK 0xf
  33. #define SSC_CTL_BM 0xf
  34. #define SSC_CTL_HB BIT(4)
  35. #define SSC_CTL_PH BIT(5)
  36. #define SSC_CTL_PO BIT(6)
  37. #define SSC_CTL_SR BIT(7)
  38. #define SSC_CTL_MS BIT(8)
  39. #define SSC_CTL_EN BIT(9)
  40. #define SSC_CTL_LPB BIT(10)
  41. #define SSC_CTL_EN_TX_FIFO BIT(11)
  42. #define SSC_CTL_EN_RX_FIFO BIT(12)
  43. #define SSC_CTL_EN_CLST_RX BIT(13)
  44. /* SSC Interrupt Enable */
  45. #define SSC_IEN_TEEN BIT(2)
  46. #define FIFO_SIZE 8
  47. struct spi_st {
  48. /* SSC SPI Controller */
  49. void __iomem *base;
  50. struct clk *clk;
  51. struct device *dev;
  52. /* SSC SPI current transaction */
  53. const u8 *tx_ptr;
  54. u8 *rx_ptr;
  55. u16 bytes_per_word;
  56. unsigned int words_remaining;
  57. unsigned int baud;
  58. struct completion done;
  59. };
  60. /* Load the TX FIFO */
  61. static void ssc_write_tx_fifo(struct spi_st *spi_st)
  62. {
  63. unsigned int count, i;
  64. uint32_t word = 0;
  65. if (spi_st->words_remaining > FIFO_SIZE)
  66. count = FIFO_SIZE;
  67. else
  68. count = spi_st->words_remaining;
  69. for (i = 0; i < count; i++) {
  70. if (spi_st->tx_ptr) {
  71. if (spi_st->bytes_per_word == 1) {
  72. word = *spi_st->tx_ptr++;
  73. } else {
  74. word = *spi_st->tx_ptr++;
  75. word = *spi_st->tx_ptr++ | (word << 8);
  76. }
  77. }
  78. writel_relaxed(word, spi_st->base + SSC_TBUF);
  79. }
  80. }
  81. /* Read the RX FIFO */
  82. static void ssc_read_rx_fifo(struct spi_st *spi_st)
  83. {
  84. unsigned int count, i;
  85. uint32_t word = 0;
  86. if (spi_st->words_remaining > FIFO_SIZE)
  87. count = FIFO_SIZE;
  88. else
  89. count = spi_st->words_remaining;
  90. for (i = 0; i < count; i++) {
  91. word = readl_relaxed(spi_st->base + SSC_RBUF);
  92. if (spi_st->rx_ptr) {
  93. if (spi_st->bytes_per_word == 1) {
  94. *spi_st->rx_ptr++ = (uint8_t)word;
  95. } else {
  96. *spi_st->rx_ptr++ = (word >> 8);
  97. *spi_st->rx_ptr++ = word & 0xff;
  98. }
  99. }
  100. }
  101. spi_st->words_remaining -= count;
  102. }
  103. static int spi_st_transfer_one(struct spi_master *master,
  104. struct spi_device *spi, struct spi_transfer *t)
  105. {
  106. struct spi_st *spi_st = spi_master_get_devdata(master);
  107. uint32_t ctl = 0;
  108. /* Setup transfer */
  109. spi_st->tx_ptr = t->tx_buf;
  110. spi_st->rx_ptr = t->rx_buf;
  111. if (spi->bits_per_word > 8) {
  112. /*
  113. * Anything greater than 8 bits-per-word requires 2
  114. * bytes-per-word in the RX/TX buffers
  115. */
  116. spi_st->bytes_per_word = 2;
  117. spi_st->words_remaining = t->len / 2;
  118. } else if (spi->bits_per_word == 8 && !(t->len & 0x1)) {
  119. /*
  120. * If transfer is even-length, and 8 bits-per-word, then
  121. * implement as half-length 16 bits-per-word transfer
  122. */
  123. spi_st->bytes_per_word = 2;
  124. spi_st->words_remaining = t->len / 2;
  125. /* Set SSC_CTL to 16 bits-per-word */
  126. ctl = readl_relaxed(spi_st->base + SSC_CTL);
  127. writel_relaxed((ctl | 0xf), spi_st->base + SSC_CTL);
  128. readl_relaxed(spi_st->base + SSC_RBUF);
  129. } else {
  130. spi_st->bytes_per_word = 1;
  131. spi_st->words_remaining = t->len;
  132. }
  133. reinit_completion(&spi_st->done);
  134. /* Start transfer by writing to the TX FIFO */
  135. ssc_write_tx_fifo(spi_st);
  136. writel_relaxed(SSC_IEN_TEEN, spi_st->base + SSC_IEN);
  137. /* Wait for transfer to complete */
  138. wait_for_completion(&spi_st->done);
  139. /* Restore SSC_CTL if necessary */
  140. if (ctl)
  141. writel_relaxed(ctl, spi_st->base + SSC_CTL);
  142. spi_finalize_current_transfer(spi->master);
  143. return t->len;
  144. }
  145. /* the spi->mode bits understood by this driver: */
  146. #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_LOOP | SPI_CS_HIGH)
  147. static int spi_st_setup(struct spi_device *spi)
  148. {
  149. struct spi_st *spi_st = spi_master_get_devdata(spi->master);
  150. u32 spi_st_clk, sscbrg, var;
  151. u32 hz = spi->max_speed_hz;
  152. if (!hz) {
  153. dev_err(&spi->dev, "max_speed_hz unspecified\n");
  154. return -EINVAL;
  155. }
  156. if (!spi->cs_gpiod) {
  157. dev_err(&spi->dev, "no valid gpio assigned\n");
  158. return -EINVAL;
  159. }
  160. spi_st_clk = clk_get_rate(spi_st->clk);
  161. /* Set SSC_BRF */
  162. sscbrg = spi_st_clk / (2 * hz);
  163. if (sscbrg < 0x07 || sscbrg > BIT(16)) {
  164. dev_err(&spi->dev,
  165. "baudrate %d outside valid range %d\n", sscbrg, hz);
  166. return -EINVAL;
  167. }
  168. spi_st->baud = spi_st_clk / (2 * sscbrg);
  169. if (sscbrg == BIT(16)) /* 16-bit counter wraps */
  170. sscbrg = 0x0;
  171. writel_relaxed(sscbrg, spi_st->base + SSC_BRG);
  172. dev_dbg(&spi->dev,
  173. "setting baudrate:target= %u hz, actual= %u hz, sscbrg= %u\n",
  174. hz, spi_st->baud, sscbrg);
  175. /* Set SSC_CTL and enable SSC */
  176. var = readl_relaxed(spi_st->base + SSC_CTL);
  177. var |= SSC_CTL_MS;
  178. if (spi->mode & SPI_CPOL)
  179. var |= SSC_CTL_PO;
  180. else
  181. var &= ~SSC_CTL_PO;
  182. if (spi->mode & SPI_CPHA)
  183. var |= SSC_CTL_PH;
  184. else
  185. var &= ~SSC_CTL_PH;
  186. if ((spi->mode & SPI_LSB_FIRST) == 0)
  187. var |= SSC_CTL_HB;
  188. else
  189. var &= ~SSC_CTL_HB;
  190. if (spi->mode & SPI_LOOP)
  191. var |= SSC_CTL_LPB;
  192. else
  193. var &= ~SSC_CTL_LPB;
  194. var &= ~SSC_CTL_DATA_WIDTH_MSK;
  195. var |= (spi->bits_per_word - 1);
  196. var |= SSC_CTL_EN_TX_FIFO | SSC_CTL_EN_RX_FIFO;
  197. var |= SSC_CTL_EN;
  198. writel_relaxed(var, spi_st->base + SSC_CTL);
  199. /* Clear the status register */
  200. readl_relaxed(spi_st->base + SSC_RBUF);
  201. return 0;
  202. }
  203. /* Interrupt fired when TX shift register becomes empty */
  204. static irqreturn_t spi_st_irq(int irq, void *dev_id)
  205. {
  206. struct spi_st *spi_st = (struct spi_st *)dev_id;
  207. /* Read RX FIFO */
  208. ssc_read_rx_fifo(spi_st);
  209. /* Fill TX FIFO */
  210. if (spi_st->words_remaining) {
  211. ssc_write_tx_fifo(spi_st);
  212. } else {
  213. /* TX/RX complete */
  214. writel_relaxed(0x0, spi_st->base + SSC_IEN);
  215. /*
  216. * read SSC_IEN to ensure that this bit is set
  217. * before re-enabling interrupt
  218. */
  219. readl(spi_st->base + SSC_IEN);
  220. complete(&spi_st->done);
  221. }
  222. return IRQ_HANDLED;
  223. }
  224. static int spi_st_probe(struct platform_device *pdev)
  225. {
  226. struct device_node *np = pdev->dev.of_node;
  227. struct spi_master *master;
  228. struct spi_st *spi_st;
  229. int irq, ret = 0;
  230. u32 var;
  231. master = spi_alloc_master(&pdev->dev, sizeof(*spi_st));
  232. if (!master)
  233. return -ENOMEM;
  234. master->dev.of_node = np;
  235. master->mode_bits = MODEBITS;
  236. master->setup = spi_st_setup;
  237. master->transfer_one = spi_st_transfer_one;
  238. master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
  239. master->auto_runtime_pm = true;
  240. master->bus_num = pdev->id;
  241. master->use_gpio_descriptors = true;
  242. spi_st = spi_master_get_devdata(master);
  243. spi_st->clk = devm_clk_get(&pdev->dev, "ssc");
  244. if (IS_ERR(spi_st->clk)) {
  245. dev_err(&pdev->dev, "Unable to request clock\n");
  246. ret = PTR_ERR(spi_st->clk);
  247. goto put_master;
  248. }
  249. ret = clk_prepare_enable(spi_st->clk);
  250. if (ret)
  251. goto put_master;
  252. init_completion(&spi_st->done);
  253. /* Get resources */
  254. spi_st->base = devm_platform_ioremap_resource(pdev, 0);
  255. if (IS_ERR(spi_st->base)) {
  256. ret = PTR_ERR(spi_st->base);
  257. goto clk_disable;
  258. }
  259. /* Disable I2C and Reset SSC */
  260. writel_relaxed(0x0, spi_st->base + SSC_I2C);
  261. var = readw_relaxed(spi_st->base + SSC_CTL);
  262. var |= SSC_CTL_SR;
  263. writel_relaxed(var, spi_st->base + SSC_CTL);
  264. udelay(1);
  265. var = readl_relaxed(spi_st->base + SSC_CTL);
  266. var &= ~SSC_CTL_SR;
  267. writel_relaxed(var, spi_st->base + SSC_CTL);
  268. /* Set SSC into slave mode before reconfiguring PIO pins */
  269. var = readl_relaxed(spi_st->base + SSC_CTL);
  270. var &= ~SSC_CTL_MS;
  271. writel_relaxed(var, spi_st->base + SSC_CTL);
  272. irq = irq_of_parse_and_map(np, 0);
  273. if (!irq) {
  274. dev_err(&pdev->dev, "IRQ missing or invalid\n");
  275. ret = -EINVAL;
  276. goto clk_disable;
  277. }
  278. ret = devm_request_irq(&pdev->dev, irq, spi_st_irq, 0,
  279. pdev->name, spi_st);
  280. if (ret) {
  281. dev_err(&pdev->dev, "Failed to request irq %d\n", irq);
  282. goto clk_disable;
  283. }
  284. /* by default the device is on */
  285. pm_runtime_set_active(&pdev->dev);
  286. pm_runtime_enable(&pdev->dev);
  287. platform_set_drvdata(pdev, master);
  288. ret = devm_spi_register_master(&pdev->dev, master);
  289. if (ret) {
  290. dev_err(&pdev->dev, "Failed to register master\n");
  291. goto rpm_disable;
  292. }
  293. return 0;
  294. rpm_disable:
  295. pm_runtime_disable(&pdev->dev);
  296. clk_disable:
  297. clk_disable_unprepare(spi_st->clk);
  298. put_master:
  299. spi_master_put(master);
  300. return ret;
  301. }
  302. static int spi_st_remove(struct platform_device *pdev)
  303. {
  304. struct spi_master *master = platform_get_drvdata(pdev);
  305. struct spi_st *spi_st = spi_master_get_devdata(master);
  306. pm_runtime_disable(&pdev->dev);
  307. clk_disable_unprepare(spi_st->clk);
  308. pinctrl_pm_select_sleep_state(&pdev->dev);
  309. return 0;
  310. }
  311. #ifdef CONFIG_PM
  312. static int spi_st_runtime_suspend(struct device *dev)
  313. {
  314. struct spi_master *master = dev_get_drvdata(dev);
  315. struct spi_st *spi_st = spi_master_get_devdata(master);
  316. writel_relaxed(0, spi_st->base + SSC_IEN);
  317. pinctrl_pm_select_sleep_state(dev);
  318. clk_disable_unprepare(spi_st->clk);
  319. return 0;
  320. }
  321. static int spi_st_runtime_resume(struct device *dev)
  322. {
  323. struct spi_master *master = dev_get_drvdata(dev);
  324. struct spi_st *spi_st = spi_master_get_devdata(master);
  325. int ret;
  326. ret = clk_prepare_enable(spi_st->clk);
  327. pinctrl_pm_select_default_state(dev);
  328. return ret;
  329. }
  330. #endif
  331. #ifdef CONFIG_PM_SLEEP
  332. static int spi_st_suspend(struct device *dev)
  333. {
  334. struct spi_master *master = dev_get_drvdata(dev);
  335. int ret;
  336. ret = spi_master_suspend(master);
  337. if (ret)
  338. return ret;
  339. return pm_runtime_force_suspend(dev);
  340. }
  341. static int spi_st_resume(struct device *dev)
  342. {
  343. struct spi_master *master = dev_get_drvdata(dev);
  344. int ret;
  345. ret = spi_master_resume(master);
  346. if (ret)
  347. return ret;
  348. return pm_runtime_force_resume(dev);
  349. }
  350. #endif
  351. static const struct dev_pm_ops spi_st_pm = {
  352. SET_SYSTEM_SLEEP_PM_OPS(spi_st_suspend, spi_st_resume)
  353. SET_RUNTIME_PM_OPS(spi_st_runtime_suspend, spi_st_runtime_resume, NULL)
  354. };
  355. static const struct of_device_id stm_spi_match[] = {
  356. { .compatible = "st,comms-ssc4-spi", },
  357. {},
  358. };
  359. MODULE_DEVICE_TABLE(of, stm_spi_match);
  360. static struct platform_driver spi_st_driver = {
  361. .driver = {
  362. .name = "spi-st",
  363. .pm = &spi_st_pm,
  364. .of_match_table = of_match_ptr(stm_spi_match),
  365. },
  366. .probe = spi_st_probe,
  367. .remove = spi_st_remove,
  368. };
  369. module_platform_driver(spi_st_driver);
  370. MODULE_AUTHOR("Patrice Chotard <[email protected]>");
  371. MODULE_DESCRIPTION("STM SSC SPI driver");
  372. MODULE_LICENSE("GPL v2");