spi-mtk-nor.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Mediatek SPI NOR controller driver
  4. //
  5. // Copyright (C) 2020 Chuanhong Guo <[email protected]>
  6. #include <linux/bits.h>
  7. #include <linux/clk.h>
  8. #include <linux/completion.h>
  9. #include <linux/dma-mapping.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/io.h>
  12. #include <linux/iopoll.h>
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/of_device.h>
  16. #include <linux/pm_runtime.h>
  17. #include <linux/spi/spi.h>
  18. #include <linux/spi/spi-mem.h>
  19. #include <linux/string.h>
  20. #define DRIVER_NAME "mtk-spi-nor"
  21. #define MTK_NOR_REG_CMD 0x00
  22. #define MTK_NOR_CMD_WRITE BIT(4)
  23. #define MTK_NOR_CMD_PROGRAM BIT(2)
  24. #define MTK_NOR_CMD_READ BIT(0)
  25. #define MTK_NOR_CMD_MASK GENMASK(5, 0)
  26. #define MTK_NOR_REG_PRG_CNT 0x04
  27. #define MTK_NOR_PRG_CNT_MAX 56
  28. #define MTK_NOR_REG_RDATA 0x0c
  29. #define MTK_NOR_REG_RADR0 0x10
  30. #define MTK_NOR_REG_RADR(n) (MTK_NOR_REG_RADR0 + 4 * (n))
  31. #define MTK_NOR_REG_RADR3 0xc8
  32. #define MTK_NOR_REG_WDATA 0x1c
  33. #define MTK_NOR_REG_PRGDATA0 0x20
  34. #define MTK_NOR_REG_PRGDATA(n) (MTK_NOR_REG_PRGDATA0 + 4 * (n))
  35. #define MTK_NOR_REG_PRGDATA_MAX 5
  36. #define MTK_NOR_REG_SHIFT0 0x38
  37. #define MTK_NOR_REG_SHIFT(n) (MTK_NOR_REG_SHIFT0 + 4 * (n))
  38. #define MTK_NOR_REG_SHIFT_MAX 9
  39. #define MTK_NOR_REG_CFG1 0x60
  40. #define MTK_NOR_FAST_READ BIT(0)
  41. #define MTK_NOR_REG_CFG2 0x64
  42. #define MTK_NOR_WR_CUSTOM_OP_EN BIT(4)
  43. #define MTK_NOR_WR_BUF_EN BIT(0)
  44. #define MTK_NOR_REG_PP_DATA 0x98
  45. #define MTK_NOR_REG_IRQ_STAT 0xa8
  46. #define MTK_NOR_REG_IRQ_EN 0xac
  47. #define MTK_NOR_IRQ_DMA BIT(7)
  48. #define MTK_NOR_IRQ_MASK GENMASK(7, 0)
  49. #define MTK_NOR_REG_CFG3 0xb4
  50. #define MTK_NOR_DISABLE_WREN BIT(7)
  51. #define MTK_NOR_DISABLE_SR_POLL BIT(5)
  52. #define MTK_NOR_REG_WP 0xc4
  53. #define MTK_NOR_ENABLE_SF_CMD 0x30
  54. #define MTK_NOR_REG_BUSCFG 0xcc
  55. #define MTK_NOR_4B_ADDR BIT(4)
  56. #define MTK_NOR_QUAD_ADDR BIT(3)
  57. #define MTK_NOR_QUAD_READ BIT(2)
  58. #define MTK_NOR_DUAL_ADDR BIT(1)
  59. #define MTK_NOR_DUAL_READ BIT(0)
  60. #define MTK_NOR_BUS_MODE_MASK GENMASK(4, 0)
  61. #define MTK_NOR_REG_DMA_CTL 0x718
  62. #define MTK_NOR_DMA_START BIT(0)
  63. #define MTK_NOR_REG_DMA_FADR 0x71c
  64. #define MTK_NOR_REG_DMA_DADR 0x720
  65. #define MTK_NOR_REG_DMA_END_DADR 0x724
  66. #define MTK_NOR_REG_DMA_DADR_HB 0x738
  67. #define MTK_NOR_REG_DMA_END_DADR_HB 0x73c
  68. #define MTK_NOR_PRG_MAX_SIZE 6
  69. // Reading DMA src/dst addresses have to be 16-byte aligned
  70. #define MTK_NOR_DMA_ALIGN 16
  71. #define MTK_NOR_DMA_ALIGN_MASK (MTK_NOR_DMA_ALIGN - 1)
  72. // and we allocate a bounce buffer if destination address isn't aligned.
  73. #define MTK_NOR_BOUNCE_BUF_SIZE PAGE_SIZE
  74. // Buffered page program can do one 128-byte transfer
  75. #define MTK_NOR_PP_SIZE 128
  76. #define CLK_TO_US(sp, clkcnt) DIV_ROUND_UP(clkcnt, sp->spi_freq / 1000000)
  77. struct mtk_nor_caps {
  78. u8 dma_bits;
  79. /* extra_dummy_bit is adding for the IP of new SoCs.
  80. * Some new SoCs modify the timing of fetching registers' values
  81. * and IDs of nor flash, they need a extra_dummy_bit which can add
  82. * more clock cycles for fetching data.
  83. */
  84. u8 extra_dummy_bit;
  85. };
  86. struct mtk_nor {
  87. struct spi_controller *ctlr;
  88. struct device *dev;
  89. void __iomem *base;
  90. u8 *buffer;
  91. dma_addr_t buffer_dma;
  92. struct clk *spi_clk;
  93. struct clk *ctlr_clk;
  94. struct clk *axi_clk;
  95. struct clk *axi_s_clk;
  96. unsigned int spi_freq;
  97. bool wbuf_en;
  98. bool has_irq;
  99. bool high_dma;
  100. struct completion op_done;
  101. const struct mtk_nor_caps *caps;
  102. };
  103. static inline void mtk_nor_rmw(struct mtk_nor *sp, u32 reg, u32 set, u32 clr)
  104. {
  105. u32 val = readl(sp->base + reg);
  106. val &= ~clr;
  107. val |= set;
  108. writel(val, sp->base + reg);
  109. }
  110. static inline int mtk_nor_cmd_exec(struct mtk_nor *sp, u32 cmd, ulong clk)
  111. {
  112. ulong delay = CLK_TO_US(sp, clk);
  113. u32 reg;
  114. int ret;
  115. writel(cmd, sp->base + MTK_NOR_REG_CMD);
  116. ret = readl_poll_timeout(sp->base + MTK_NOR_REG_CMD, reg, !(reg & cmd),
  117. delay / 3, (delay + 1) * 200);
  118. if (ret < 0)
  119. dev_err(sp->dev, "command %u timeout.\n", cmd);
  120. return ret;
  121. }
  122. static void mtk_nor_set_addr(struct mtk_nor *sp, const struct spi_mem_op *op)
  123. {
  124. u32 addr = op->addr.val;
  125. int i;
  126. for (i = 0; i < 3; i++) {
  127. writeb(addr & 0xff, sp->base + MTK_NOR_REG_RADR(i));
  128. addr >>= 8;
  129. }
  130. if (op->addr.nbytes == 4) {
  131. writeb(addr & 0xff, sp->base + MTK_NOR_REG_RADR3);
  132. mtk_nor_rmw(sp, MTK_NOR_REG_BUSCFG, MTK_NOR_4B_ADDR, 0);
  133. } else {
  134. mtk_nor_rmw(sp, MTK_NOR_REG_BUSCFG, 0, MTK_NOR_4B_ADDR);
  135. }
  136. }
  137. static bool need_bounce(struct mtk_nor *sp, const struct spi_mem_op *op)
  138. {
  139. return ((uintptr_t)op->data.buf.in & MTK_NOR_DMA_ALIGN_MASK);
  140. }
  141. static bool mtk_nor_match_read(const struct spi_mem_op *op)
  142. {
  143. int dummy = 0;
  144. if (op->dummy.nbytes)
  145. dummy = op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth;
  146. if ((op->data.buswidth == 2) || (op->data.buswidth == 4)) {
  147. if (op->addr.buswidth == 1)
  148. return dummy == 8;
  149. else if (op->addr.buswidth == 2)
  150. return dummy == 4;
  151. else if (op->addr.buswidth == 4)
  152. return dummy == 6;
  153. } else if ((op->addr.buswidth == 1) && (op->data.buswidth == 1)) {
  154. if (op->cmd.opcode == 0x03)
  155. return dummy == 0;
  156. else if (op->cmd.opcode == 0x0b)
  157. return dummy == 8;
  158. }
  159. return false;
  160. }
  161. static bool mtk_nor_match_prg(const struct spi_mem_op *op)
  162. {
  163. int tx_len, rx_len, prg_len, prg_left;
  164. // prg mode is spi-only.
  165. if ((op->cmd.buswidth > 1) || (op->addr.buswidth > 1) ||
  166. (op->dummy.buswidth > 1) || (op->data.buswidth > 1))
  167. return false;
  168. tx_len = op->cmd.nbytes + op->addr.nbytes;
  169. if (op->data.dir == SPI_MEM_DATA_OUT) {
  170. // count dummy bytes only if we need to write data after it
  171. tx_len += op->dummy.nbytes;
  172. // leave at least one byte for data
  173. if (tx_len > MTK_NOR_REG_PRGDATA_MAX)
  174. return false;
  175. // if there's no addr, meaning adjust_op_size is impossible,
  176. // check data length as well.
  177. if ((!op->addr.nbytes) &&
  178. (tx_len + op->data.nbytes > MTK_NOR_REG_PRGDATA_MAX + 1))
  179. return false;
  180. } else if (op->data.dir == SPI_MEM_DATA_IN) {
  181. if (tx_len > MTK_NOR_REG_PRGDATA_MAX + 1)
  182. return false;
  183. rx_len = op->data.nbytes;
  184. prg_left = MTK_NOR_PRG_CNT_MAX / 8 - tx_len - op->dummy.nbytes;
  185. if (prg_left > MTK_NOR_REG_SHIFT_MAX + 1)
  186. prg_left = MTK_NOR_REG_SHIFT_MAX + 1;
  187. if (rx_len > prg_left) {
  188. if (!op->addr.nbytes)
  189. return false;
  190. rx_len = prg_left;
  191. }
  192. prg_len = tx_len + op->dummy.nbytes + rx_len;
  193. if (prg_len > MTK_NOR_PRG_CNT_MAX / 8)
  194. return false;
  195. } else {
  196. prg_len = tx_len + op->dummy.nbytes;
  197. if (prg_len > MTK_NOR_PRG_CNT_MAX / 8)
  198. return false;
  199. }
  200. return true;
  201. }
  202. static void mtk_nor_adj_prg_size(struct spi_mem_op *op)
  203. {
  204. int tx_len, tx_left, prg_left;
  205. tx_len = op->cmd.nbytes + op->addr.nbytes;
  206. if (op->data.dir == SPI_MEM_DATA_OUT) {
  207. tx_len += op->dummy.nbytes;
  208. tx_left = MTK_NOR_REG_PRGDATA_MAX + 1 - tx_len;
  209. if (op->data.nbytes > tx_left)
  210. op->data.nbytes = tx_left;
  211. } else if (op->data.dir == SPI_MEM_DATA_IN) {
  212. prg_left = MTK_NOR_PRG_CNT_MAX / 8 - tx_len - op->dummy.nbytes;
  213. if (prg_left > MTK_NOR_REG_SHIFT_MAX + 1)
  214. prg_left = MTK_NOR_REG_SHIFT_MAX + 1;
  215. if (op->data.nbytes > prg_left)
  216. op->data.nbytes = prg_left;
  217. }
  218. }
  219. static int mtk_nor_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
  220. {
  221. struct mtk_nor *sp = spi_controller_get_devdata(mem->spi->master);
  222. if (!op->data.nbytes)
  223. return 0;
  224. if ((op->addr.nbytes == 3) || (op->addr.nbytes == 4)) {
  225. if ((op->data.dir == SPI_MEM_DATA_IN) &&
  226. mtk_nor_match_read(op)) {
  227. // limit size to prevent timeout calculation overflow
  228. if (op->data.nbytes > 0x400000)
  229. op->data.nbytes = 0x400000;
  230. if ((op->addr.val & MTK_NOR_DMA_ALIGN_MASK) ||
  231. (op->data.nbytes < MTK_NOR_DMA_ALIGN))
  232. op->data.nbytes = 1;
  233. else if (!need_bounce(sp, op))
  234. op->data.nbytes &= ~MTK_NOR_DMA_ALIGN_MASK;
  235. else if (op->data.nbytes > MTK_NOR_BOUNCE_BUF_SIZE)
  236. op->data.nbytes = MTK_NOR_BOUNCE_BUF_SIZE;
  237. return 0;
  238. } else if (op->data.dir == SPI_MEM_DATA_OUT) {
  239. if (op->data.nbytes >= MTK_NOR_PP_SIZE)
  240. op->data.nbytes = MTK_NOR_PP_SIZE;
  241. else
  242. op->data.nbytes = 1;
  243. return 0;
  244. }
  245. }
  246. mtk_nor_adj_prg_size(op);
  247. return 0;
  248. }
  249. static bool mtk_nor_supports_op(struct spi_mem *mem,
  250. const struct spi_mem_op *op)
  251. {
  252. if (!spi_mem_default_supports_op(mem, op))
  253. return false;
  254. if (op->cmd.buswidth != 1)
  255. return false;
  256. if ((op->addr.nbytes == 3) || (op->addr.nbytes == 4)) {
  257. switch (op->data.dir) {
  258. case SPI_MEM_DATA_IN:
  259. if (mtk_nor_match_read(op))
  260. return true;
  261. break;
  262. case SPI_MEM_DATA_OUT:
  263. if ((op->addr.buswidth == 1) &&
  264. (op->dummy.nbytes == 0) &&
  265. (op->data.buswidth == 1))
  266. return true;
  267. break;
  268. default:
  269. break;
  270. }
  271. }
  272. return mtk_nor_match_prg(op);
  273. }
  274. static void mtk_nor_setup_bus(struct mtk_nor *sp, const struct spi_mem_op *op)
  275. {
  276. u32 reg = 0;
  277. if (op->addr.nbytes == 4)
  278. reg |= MTK_NOR_4B_ADDR;
  279. if (op->data.buswidth == 4) {
  280. reg |= MTK_NOR_QUAD_READ;
  281. writeb(op->cmd.opcode, sp->base + MTK_NOR_REG_PRGDATA(4));
  282. if (op->addr.buswidth == 4)
  283. reg |= MTK_NOR_QUAD_ADDR;
  284. } else if (op->data.buswidth == 2) {
  285. reg |= MTK_NOR_DUAL_READ;
  286. writeb(op->cmd.opcode, sp->base + MTK_NOR_REG_PRGDATA(3));
  287. if (op->addr.buswidth == 2)
  288. reg |= MTK_NOR_DUAL_ADDR;
  289. } else {
  290. if (op->cmd.opcode == 0x0b)
  291. mtk_nor_rmw(sp, MTK_NOR_REG_CFG1, MTK_NOR_FAST_READ, 0);
  292. else
  293. mtk_nor_rmw(sp, MTK_NOR_REG_CFG1, 0, MTK_NOR_FAST_READ);
  294. }
  295. mtk_nor_rmw(sp, MTK_NOR_REG_BUSCFG, reg, MTK_NOR_BUS_MODE_MASK);
  296. }
  297. static int mtk_nor_dma_exec(struct mtk_nor *sp, u32 from, unsigned int length,
  298. dma_addr_t dma_addr)
  299. {
  300. int ret = 0;
  301. ulong delay;
  302. u32 reg;
  303. writel(from, sp->base + MTK_NOR_REG_DMA_FADR);
  304. writel(dma_addr, sp->base + MTK_NOR_REG_DMA_DADR);
  305. writel(dma_addr + length, sp->base + MTK_NOR_REG_DMA_END_DADR);
  306. if (sp->high_dma) {
  307. writel(upper_32_bits(dma_addr),
  308. sp->base + MTK_NOR_REG_DMA_DADR_HB);
  309. writel(upper_32_bits(dma_addr + length),
  310. sp->base + MTK_NOR_REG_DMA_END_DADR_HB);
  311. }
  312. if (sp->has_irq) {
  313. reinit_completion(&sp->op_done);
  314. mtk_nor_rmw(sp, MTK_NOR_REG_IRQ_EN, MTK_NOR_IRQ_DMA, 0);
  315. }
  316. mtk_nor_rmw(sp, MTK_NOR_REG_DMA_CTL, MTK_NOR_DMA_START, 0);
  317. delay = CLK_TO_US(sp, (length + 5) * BITS_PER_BYTE);
  318. if (sp->has_irq) {
  319. if (!wait_for_completion_timeout(&sp->op_done,
  320. (delay + 1) * 100))
  321. ret = -ETIMEDOUT;
  322. } else {
  323. ret = readl_poll_timeout(sp->base + MTK_NOR_REG_DMA_CTL, reg,
  324. !(reg & MTK_NOR_DMA_START), delay / 3,
  325. (delay + 1) * 100);
  326. }
  327. if (ret < 0)
  328. dev_err(sp->dev, "dma read timeout.\n");
  329. return ret;
  330. }
  331. static int mtk_nor_read_bounce(struct mtk_nor *sp, const struct spi_mem_op *op)
  332. {
  333. unsigned int rdlen;
  334. int ret;
  335. if (op->data.nbytes & MTK_NOR_DMA_ALIGN_MASK)
  336. rdlen = (op->data.nbytes + MTK_NOR_DMA_ALIGN) & ~MTK_NOR_DMA_ALIGN_MASK;
  337. else
  338. rdlen = op->data.nbytes;
  339. ret = mtk_nor_dma_exec(sp, op->addr.val, rdlen, sp->buffer_dma);
  340. if (!ret)
  341. memcpy(op->data.buf.in, sp->buffer, op->data.nbytes);
  342. return ret;
  343. }
  344. static int mtk_nor_read_dma(struct mtk_nor *sp, const struct spi_mem_op *op)
  345. {
  346. int ret;
  347. dma_addr_t dma_addr;
  348. if (need_bounce(sp, op))
  349. return mtk_nor_read_bounce(sp, op);
  350. dma_addr = dma_map_single(sp->dev, op->data.buf.in,
  351. op->data.nbytes, DMA_FROM_DEVICE);
  352. if (dma_mapping_error(sp->dev, dma_addr))
  353. return -EINVAL;
  354. ret = mtk_nor_dma_exec(sp, op->addr.val, op->data.nbytes, dma_addr);
  355. dma_unmap_single(sp->dev, dma_addr, op->data.nbytes, DMA_FROM_DEVICE);
  356. return ret;
  357. }
  358. static int mtk_nor_read_pio(struct mtk_nor *sp, const struct spi_mem_op *op)
  359. {
  360. u8 *buf = op->data.buf.in;
  361. int ret;
  362. ret = mtk_nor_cmd_exec(sp, MTK_NOR_CMD_READ, 6 * BITS_PER_BYTE);
  363. if (!ret)
  364. buf[0] = readb(sp->base + MTK_NOR_REG_RDATA);
  365. return ret;
  366. }
  367. static int mtk_nor_write_buffer_enable(struct mtk_nor *sp)
  368. {
  369. int ret;
  370. u32 val;
  371. if (sp->wbuf_en)
  372. return 0;
  373. val = readl(sp->base + MTK_NOR_REG_CFG2);
  374. writel(val | MTK_NOR_WR_BUF_EN, sp->base + MTK_NOR_REG_CFG2);
  375. ret = readl_poll_timeout(sp->base + MTK_NOR_REG_CFG2, val,
  376. val & MTK_NOR_WR_BUF_EN, 0, 10000);
  377. if (!ret)
  378. sp->wbuf_en = true;
  379. return ret;
  380. }
  381. static int mtk_nor_write_buffer_disable(struct mtk_nor *sp)
  382. {
  383. int ret;
  384. u32 val;
  385. if (!sp->wbuf_en)
  386. return 0;
  387. val = readl(sp->base + MTK_NOR_REG_CFG2);
  388. writel(val & ~MTK_NOR_WR_BUF_EN, sp->base + MTK_NOR_REG_CFG2);
  389. ret = readl_poll_timeout(sp->base + MTK_NOR_REG_CFG2, val,
  390. !(val & MTK_NOR_WR_BUF_EN), 0, 10000);
  391. if (!ret)
  392. sp->wbuf_en = false;
  393. return ret;
  394. }
  395. static int mtk_nor_pp_buffered(struct mtk_nor *sp, const struct spi_mem_op *op)
  396. {
  397. const u8 *buf = op->data.buf.out;
  398. u32 val;
  399. int ret, i;
  400. ret = mtk_nor_write_buffer_enable(sp);
  401. if (ret < 0)
  402. return ret;
  403. for (i = 0; i < op->data.nbytes; i += 4) {
  404. val = buf[i + 3] << 24 | buf[i + 2] << 16 | buf[i + 1] << 8 |
  405. buf[i];
  406. writel(val, sp->base + MTK_NOR_REG_PP_DATA);
  407. }
  408. return mtk_nor_cmd_exec(sp, MTK_NOR_CMD_WRITE,
  409. (op->data.nbytes + 5) * BITS_PER_BYTE);
  410. }
  411. static int mtk_nor_pp_unbuffered(struct mtk_nor *sp,
  412. const struct spi_mem_op *op)
  413. {
  414. const u8 *buf = op->data.buf.out;
  415. int ret;
  416. ret = mtk_nor_write_buffer_disable(sp);
  417. if (ret < 0)
  418. return ret;
  419. writeb(buf[0], sp->base + MTK_NOR_REG_WDATA);
  420. return mtk_nor_cmd_exec(sp, MTK_NOR_CMD_WRITE, 6 * BITS_PER_BYTE);
  421. }
  422. static int mtk_nor_spi_mem_prg(struct mtk_nor *sp, const struct spi_mem_op *op)
  423. {
  424. int rx_len = 0;
  425. int reg_offset = MTK_NOR_REG_PRGDATA_MAX;
  426. int tx_len, prg_len;
  427. int i, ret;
  428. void __iomem *reg;
  429. u8 bufbyte;
  430. tx_len = op->cmd.nbytes + op->addr.nbytes;
  431. // count dummy bytes only if we need to write data after it
  432. if (op->data.dir == SPI_MEM_DATA_OUT)
  433. tx_len += op->dummy.nbytes + op->data.nbytes;
  434. else if (op->data.dir == SPI_MEM_DATA_IN)
  435. rx_len = op->data.nbytes;
  436. prg_len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes +
  437. op->data.nbytes;
  438. // an invalid op may reach here if the caller calls exec_op without
  439. // adjust_op_size. return -EINVAL instead of -ENOTSUPP so that
  440. // spi-mem won't try this op again with generic spi transfers.
  441. if ((tx_len > MTK_NOR_REG_PRGDATA_MAX + 1) ||
  442. (rx_len > MTK_NOR_REG_SHIFT_MAX + 1) ||
  443. (prg_len > MTK_NOR_PRG_CNT_MAX / 8))
  444. return -EINVAL;
  445. // fill tx data
  446. for (i = op->cmd.nbytes; i > 0; i--, reg_offset--) {
  447. reg = sp->base + MTK_NOR_REG_PRGDATA(reg_offset);
  448. bufbyte = (op->cmd.opcode >> ((i - 1) * BITS_PER_BYTE)) & 0xff;
  449. writeb(bufbyte, reg);
  450. }
  451. for (i = op->addr.nbytes; i > 0; i--, reg_offset--) {
  452. reg = sp->base + MTK_NOR_REG_PRGDATA(reg_offset);
  453. bufbyte = (op->addr.val >> ((i - 1) * BITS_PER_BYTE)) & 0xff;
  454. writeb(bufbyte, reg);
  455. }
  456. if (op->data.dir == SPI_MEM_DATA_OUT) {
  457. for (i = 0; i < op->dummy.nbytes; i++, reg_offset--) {
  458. reg = sp->base + MTK_NOR_REG_PRGDATA(reg_offset);
  459. writeb(0, reg);
  460. }
  461. for (i = 0; i < op->data.nbytes; i++, reg_offset--) {
  462. reg = sp->base + MTK_NOR_REG_PRGDATA(reg_offset);
  463. writeb(((const u8 *)(op->data.buf.out))[i], reg);
  464. }
  465. }
  466. for (; reg_offset >= 0; reg_offset--) {
  467. reg = sp->base + MTK_NOR_REG_PRGDATA(reg_offset);
  468. writeb(0, reg);
  469. }
  470. // trigger op
  471. if (rx_len)
  472. writel(prg_len * BITS_PER_BYTE + sp->caps->extra_dummy_bit,
  473. sp->base + MTK_NOR_REG_PRG_CNT);
  474. else
  475. writel(prg_len * BITS_PER_BYTE, sp->base + MTK_NOR_REG_PRG_CNT);
  476. ret = mtk_nor_cmd_exec(sp, MTK_NOR_CMD_PROGRAM,
  477. prg_len * BITS_PER_BYTE);
  478. if (ret)
  479. return ret;
  480. // fetch read data
  481. reg_offset = 0;
  482. if (op->data.dir == SPI_MEM_DATA_IN) {
  483. for (i = op->data.nbytes - 1; i >= 0; i--, reg_offset++) {
  484. reg = sp->base + MTK_NOR_REG_SHIFT(reg_offset);
  485. ((u8 *)(op->data.buf.in))[i] = readb(reg);
  486. }
  487. }
  488. return 0;
  489. }
  490. static int mtk_nor_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
  491. {
  492. struct mtk_nor *sp = spi_controller_get_devdata(mem->spi->master);
  493. int ret;
  494. if ((op->data.nbytes == 0) ||
  495. ((op->addr.nbytes != 3) && (op->addr.nbytes != 4)))
  496. return mtk_nor_spi_mem_prg(sp, op);
  497. if (op->data.dir == SPI_MEM_DATA_OUT) {
  498. mtk_nor_set_addr(sp, op);
  499. writeb(op->cmd.opcode, sp->base + MTK_NOR_REG_PRGDATA0);
  500. if (op->data.nbytes == MTK_NOR_PP_SIZE)
  501. return mtk_nor_pp_buffered(sp, op);
  502. return mtk_nor_pp_unbuffered(sp, op);
  503. }
  504. if ((op->data.dir == SPI_MEM_DATA_IN) && mtk_nor_match_read(op)) {
  505. ret = mtk_nor_write_buffer_disable(sp);
  506. if (ret < 0)
  507. return ret;
  508. mtk_nor_setup_bus(sp, op);
  509. if (op->data.nbytes == 1) {
  510. mtk_nor_set_addr(sp, op);
  511. return mtk_nor_read_pio(sp, op);
  512. } else {
  513. return mtk_nor_read_dma(sp, op);
  514. }
  515. }
  516. return mtk_nor_spi_mem_prg(sp, op);
  517. }
  518. static int mtk_nor_setup(struct spi_device *spi)
  519. {
  520. struct mtk_nor *sp = spi_controller_get_devdata(spi->master);
  521. if (spi->max_speed_hz && (spi->max_speed_hz < sp->spi_freq)) {
  522. dev_err(&spi->dev, "spi clock should be %u Hz.\n",
  523. sp->spi_freq);
  524. return -EINVAL;
  525. }
  526. spi->max_speed_hz = sp->spi_freq;
  527. return 0;
  528. }
  529. static int mtk_nor_transfer_one_message(struct spi_controller *master,
  530. struct spi_message *m)
  531. {
  532. struct mtk_nor *sp = spi_controller_get_devdata(master);
  533. struct spi_transfer *t = NULL;
  534. unsigned long trx_len = 0;
  535. int stat = 0;
  536. int reg_offset = MTK_NOR_REG_PRGDATA_MAX;
  537. void __iomem *reg;
  538. const u8 *txbuf;
  539. u8 *rxbuf;
  540. int i;
  541. list_for_each_entry(t, &m->transfers, transfer_list) {
  542. txbuf = t->tx_buf;
  543. for (i = 0; i < t->len; i++, reg_offset--) {
  544. reg = sp->base + MTK_NOR_REG_PRGDATA(reg_offset);
  545. if (txbuf)
  546. writeb(txbuf[i], reg);
  547. else
  548. writeb(0, reg);
  549. }
  550. trx_len += t->len;
  551. }
  552. writel(trx_len * BITS_PER_BYTE, sp->base + MTK_NOR_REG_PRG_CNT);
  553. stat = mtk_nor_cmd_exec(sp, MTK_NOR_CMD_PROGRAM,
  554. trx_len * BITS_PER_BYTE);
  555. if (stat < 0)
  556. goto msg_done;
  557. reg_offset = trx_len - 1;
  558. list_for_each_entry(t, &m->transfers, transfer_list) {
  559. rxbuf = t->rx_buf;
  560. for (i = 0; i < t->len; i++, reg_offset--) {
  561. reg = sp->base + MTK_NOR_REG_SHIFT(reg_offset);
  562. if (rxbuf)
  563. rxbuf[i] = readb(reg);
  564. }
  565. }
  566. m->actual_length = trx_len;
  567. msg_done:
  568. m->status = stat;
  569. spi_finalize_current_message(master);
  570. return 0;
  571. }
  572. static void mtk_nor_disable_clk(struct mtk_nor *sp)
  573. {
  574. clk_disable_unprepare(sp->spi_clk);
  575. clk_disable_unprepare(sp->ctlr_clk);
  576. clk_disable_unprepare(sp->axi_clk);
  577. clk_disable_unprepare(sp->axi_s_clk);
  578. }
  579. static int mtk_nor_enable_clk(struct mtk_nor *sp)
  580. {
  581. int ret;
  582. ret = clk_prepare_enable(sp->spi_clk);
  583. if (ret)
  584. return ret;
  585. ret = clk_prepare_enable(sp->ctlr_clk);
  586. if (ret) {
  587. clk_disable_unprepare(sp->spi_clk);
  588. return ret;
  589. }
  590. ret = clk_prepare_enable(sp->axi_clk);
  591. if (ret) {
  592. clk_disable_unprepare(sp->spi_clk);
  593. clk_disable_unprepare(sp->ctlr_clk);
  594. return ret;
  595. }
  596. ret = clk_prepare_enable(sp->axi_s_clk);
  597. if (ret) {
  598. clk_disable_unprepare(sp->spi_clk);
  599. clk_disable_unprepare(sp->ctlr_clk);
  600. clk_disable_unprepare(sp->axi_clk);
  601. return ret;
  602. }
  603. return 0;
  604. }
  605. static void mtk_nor_init(struct mtk_nor *sp)
  606. {
  607. writel(0, sp->base + MTK_NOR_REG_IRQ_EN);
  608. writel(MTK_NOR_IRQ_MASK, sp->base + MTK_NOR_REG_IRQ_STAT);
  609. writel(MTK_NOR_ENABLE_SF_CMD, sp->base + MTK_NOR_REG_WP);
  610. mtk_nor_rmw(sp, MTK_NOR_REG_CFG2, MTK_NOR_WR_CUSTOM_OP_EN, 0);
  611. mtk_nor_rmw(sp, MTK_NOR_REG_CFG3,
  612. MTK_NOR_DISABLE_WREN | MTK_NOR_DISABLE_SR_POLL, 0);
  613. }
  614. static irqreturn_t mtk_nor_irq_handler(int irq, void *data)
  615. {
  616. struct mtk_nor *sp = data;
  617. u32 irq_status, irq_enabled;
  618. irq_status = readl(sp->base + MTK_NOR_REG_IRQ_STAT);
  619. irq_enabled = readl(sp->base + MTK_NOR_REG_IRQ_EN);
  620. // write status back to clear interrupt
  621. writel(irq_status, sp->base + MTK_NOR_REG_IRQ_STAT);
  622. if (!(irq_status & irq_enabled))
  623. return IRQ_NONE;
  624. if (irq_status & MTK_NOR_IRQ_DMA) {
  625. complete(&sp->op_done);
  626. writel(0, sp->base + MTK_NOR_REG_IRQ_EN);
  627. }
  628. return IRQ_HANDLED;
  629. }
  630. static size_t mtk_max_msg_size(struct spi_device *spi)
  631. {
  632. return MTK_NOR_PRG_MAX_SIZE;
  633. }
  634. static const struct spi_controller_mem_ops mtk_nor_mem_ops = {
  635. .adjust_op_size = mtk_nor_adjust_op_size,
  636. .supports_op = mtk_nor_supports_op,
  637. .exec_op = mtk_nor_exec_op
  638. };
  639. static const struct mtk_nor_caps mtk_nor_caps_mt8173 = {
  640. .dma_bits = 32,
  641. .extra_dummy_bit = 0,
  642. };
  643. static const struct mtk_nor_caps mtk_nor_caps_mt8186 = {
  644. .dma_bits = 32,
  645. .extra_dummy_bit = 1,
  646. };
  647. static const struct mtk_nor_caps mtk_nor_caps_mt8192 = {
  648. .dma_bits = 36,
  649. .extra_dummy_bit = 0,
  650. };
  651. static const struct of_device_id mtk_nor_match[] = {
  652. { .compatible = "mediatek,mt8173-nor", .data = &mtk_nor_caps_mt8173 },
  653. { .compatible = "mediatek,mt8186-nor", .data = &mtk_nor_caps_mt8186 },
  654. { .compatible = "mediatek,mt8192-nor", .data = &mtk_nor_caps_mt8192 },
  655. { /* sentinel */ }
  656. };
  657. MODULE_DEVICE_TABLE(of, mtk_nor_match);
  658. static int mtk_nor_probe(struct platform_device *pdev)
  659. {
  660. struct spi_controller *ctlr;
  661. struct mtk_nor *sp;
  662. struct mtk_nor_caps *caps;
  663. void __iomem *base;
  664. struct clk *spi_clk, *ctlr_clk, *axi_clk, *axi_s_clk;
  665. int ret, irq;
  666. base = devm_platform_ioremap_resource(pdev, 0);
  667. if (IS_ERR(base))
  668. return PTR_ERR(base);
  669. spi_clk = devm_clk_get(&pdev->dev, "spi");
  670. if (IS_ERR(spi_clk))
  671. return PTR_ERR(spi_clk);
  672. ctlr_clk = devm_clk_get(&pdev->dev, "sf");
  673. if (IS_ERR(ctlr_clk))
  674. return PTR_ERR(ctlr_clk);
  675. axi_clk = devm_clk_get_optional(&pdev->dev, "axi");
  676. if (IS_ERR(axi_clk))
  677. return PTR_ERR(axi_clk);
  678. axi_s_clk = devm_clk_get_optional(&pdev->dev, "axi_s");
  679. if (IS_ERR(axi_s_clk))
  680. return PTR_ERR(axi_s_clk);
  681. caps = (struct mtk_nor_caps *)of_device_get_match_data(&pdev->dev);
  682. ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(caps->dma_bits));
  683. if (ret) {
  684. dev_err(&pdev->dev, "failed to set dma mask(%u)\n", caps->dma_bits);
  685. return ret;
  686. }
  687. ctlr = devm_spi_alloc_master(&pdev->dev, sizeof(*sp));
  688. if (!ctlr) {
  689. dev_err(&pdev->dev, "failed to allocate spi controller\n");
  690. return -ENOMEM;
  691. }
  692. ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
  693. ctlr->dev.of_node = pdev->dev.of_node;
  694. ctlr->max_message_size = mtk_max_msg_size;
  695. ctlr->mem_ops = &mtk_nor_mem_ops;
  696. ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD;
  697. ctlr->num_chipselect = 1;
  698. ctlr->setup = mtk_nor_setup;
  699. ctlr->transfer_one_message = mtk_nor_transfer_one_message;
  700. ctlr->auto_runtime_pm = true;
  701. dev_set_drvdata(&pdev->dev, ctlr);
  702. sp = spi_controller_get_devdata(ctlr);
  703. sp->base = base;
  704. sp->has_irq = false;
  705. sp->wbuf_en = false;
  706. sp->ctlr = ctlr;
  707. sp->dev = &pdev->dev;
  708. sp->spi_clk = spi_clk;
  709. sp->ctlr_clk = ctlr_clk;
  710. sp->axi_clk = axi_clk;
  711. sp->axi_s_clk = axi_s_clk;
  712. sp->caps = caps;
  713. sp->high_dma = caps->dma_bits > 32;
  714. sp->buffer = dmam_alloc_coherent(&pdev->dev,
  715. MTK_NOR_BOUNCE_BUF_SIZE + MTK_NOR_DMA_ALIGN,
  716. &sp->buffer_dma, GFP_KERNEL);
  717. if (!sp->buffer)
  718. return -ENOMEM;
  719. if ((uintptr_t)sp->buffer & MTK_NOR_DMA_ALIGN_MASK) {
  720. dev_err(sp->dev, "misaligned allocation of internal buffer.\n");
  721. return -ENOMEM;
  722. }
  723. ret = mtk_nor_enable_clk(sp);
  724. if (ret < 0)
  725. return ret;
  726. sp->spi_freq = clk_get_rate(sp->spi_clk);
  727. mtk_nor_init(sp);
  728. irq = platform_get_irq_optional(pdev, 0);
  729. if (irq < 0) {
  730. dev_warn(sp->dev, "IRQ not available.");
  731. } else {
  732. ret = devm_request_irq(sp->dev, irq, mtk_nor_irq_handler, 0,
  733. pdev->name, sp);
  734. if (ret < 0) {
  735. dev_warn(sp->dev, "failed to request IRQ.");
  736. } else {
  737. init_completion(&sp->op_done);
  738. sp->has_irq = true;
  739. }
  740. }
  741. pm_runtime_set_autosuspend_delay(&pdev->dev, -1);
  742. pm_runtime_use_autosuspend(&pdev->dev);
  743. pm_runtime_set_active(&pdev->dev);
  744. pm_runtime_enable(&pdev->dev);
  745. pm_runtime_get_noresume(&pdev->dev);
  746. ret = devm_spi_register_controller(&pdev->dev, ctlr);
  747. if (ret < 0)
  748. goto err_probe;
  749. pm_runtime_mark_last_busy(&pdev->dev);
  750. pm_runtime_put_autosuspend(&pdev->dev);
  751. dev_info(&pdev->dev, "spi frequency: %d Hz\n", sp->spi_freq);
  752. return 0;
  753. err_probe:
  754. pm_runtime_disable(&pdev->dev);
  755. pm_runtime_set_suspended(&pdev->dev);
  756. pm_runtime_dont_use_autosuspend(&pdev->dev);
  757. mtk_nor_disable_clk(sp);
  758. return ret;
  759. }
  760. static int mtk_nor_remove(struct platform_device *pdev)
  761. {
  762. struct spi_controller *ctlr = dev_get_drvdata(&pdev->dev);
  763. struct mtk_nor *sp = spi_controller_get_devdata(ctlr);
  764. pm_runtime_disable(&pdev->dev);
  765. pm_runtime_set_suspended(&pdev->dev);
  766. pm_runtime_dont_use_autosuspend(&pdev->dev);
  767. mtk_nor_disable_clk(sp);
  768. return 0;
  769. }
  770. static int __maybe_unused mtk_nor_runtime_suspend(struct device *dev)
  771. {
  772. struct spi_controller *ctlr = dev_get_drvdata(dev);
  773. struct mtk_nor *sp = spi_controller_get_devdata(ctlr);
  774. mtk_nor_disable_clk(sp);
  775. return 0;
  776. }
  777. static int __maybe_unused mtk_nor_runtime_resume(struct device *dev)
  778. {
  779. struct spi_controller *ctlr = dev_get_drvdata(dev);
  780. struct mtk_nor *sp = spi_controller_get_devdata(ctlr);
  781. return mtk_nor_enable_clk(sp);
  782. }
  783. static int __maybe_unused mtk_nor_suspend(struct device *dev)
  784. {
  785. return pm_runtime_force_suspend(dev);
  786. }
  787. static int __maybe_unused mtk_nor_resume(struct device *dev)
  788. {
  789. struct spi_controller *ctlr = dev_get_drvdata(dev);
  790. struct mtk_nor *sp = spi_controller_get_devdata(ctlr);
  791. int ret;
  792. ret = pm_runtime_force_resume(dev);
  793. if (ret)
  794. return ret;
  795. mtk_nor_init(sp);
  796. return 0;
  797. }
  798. static const struct dev_pm_ops mtk_nor_pm_ops = {
  799. SET_RUNTIME_PM_OPS(mtk_nor_runtime_suspend,
  800. mtk_nor_runtime_resume, NULL)
  801. SET_SYSTEM_SLEEP_PM_OPS(mtk_nor_suspend, mtk_nor_resume)
  802. };
  803. static struct platform_driver mtk_nor_driver = {
  804. .driver = {
  805. .name = DRIVER_NAME,
  806. .of_match_table = mtk_nor_match,
  807. .pm = &mtk_nor_pm_ops,
  808. },
  809. .probe = mtk_nor_probe,
  810. .remove = mtk_nor_remove,
  811. };
  812. module_platform_driver(mtk_nor_driver);
  813. MODULE_DESCRIPTION("Mediatek SPI NOR controller driver");
  814. MODULE_AUTHOR("Chuanhong Guo <[email protected]>");
  815. MODULE_LICENSE("GPL v2");
  816. MODULE_ALIAS("platform:" DRIVER_NAME);