spi-jcore.c 5.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * J-Core SPI controller driver
  4. *
  5. * Copyright (C) 2012-2016 Smart Energy Instruments, Inc.
  6. *
  7. * Current version by Rich Felker
  8. * Based loosely on initial version by Oleksandr G Zhadan
  9. *
  10. */
  11. #include <linux/init.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/errno.h>
  14. #include <linux/module.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/spi/spi.h>
  17. #include <linux/clk.h>
  18. #include <linux/err.h>
  19. #include <linux/io.h>
  20. #include <linux/of.h>
  21. #include <linux/delay.h>
  22. #define DRV_NAME "jcore_spi"
  23. #define CTRL_REG 0x0
  24. #define DATA_REG 0x4
  25. #define JCORE_SPI_CTRL_XMIT 0x02
  26. #define JCORE_SPI_STAT_BUSY 0x02
  27. #define JCORE_SPI_CTRL_LOOP 0x08
  28. #define JCORE_SPI_CTRL_CS_BITS 0x15
  29. #define JCORE_SPI_WAIT_RDY_MAX_LOOP 2000000
  30. struct jcore_spi {
  31. struct spi_master *master;
  32. void __iomem *base;
  33. unsigned int cs_reg;
  34. unsigned int speed_reg;
  35. unsigned int speed_hz;
  36. unsigned int clock_freq;
  37. };
  38. static int jcore_spi_wait(void __iomem *ctrl_reg)
  39. {
  40. unsigned timeout = JCORE_SPI_WAIT_RDY_MAX_LOOP;
  41. do {
  42. if (!(readl(ctrl_reg) & JCORE_SPI_STAT_BUSY))
  43. return 0;
  44. cpu_relax();
  45. } while (--timeout);
  46. return -EBUSY;
  47. }
  48. static void jcore_spi_program(struct jcore_spi *hw)
  49. {
  50. void __iomem *ctrl_reg = hw->base + CTRL_REG;
  51. if (jcore_spi_wait(ctrl_reg))
  52. dev_err(hw->master->dev.parent,
  53. "timeout waiting to program ctrl reg.\n");
  54. writel(hw->cs_reg | hw->speed_reg, ctrl_reg);
  55. }
  56. static void jcore_spi_chipsel(struct spi_device *spi, bool value)
  57. {
  58. struct jcore_spi *hw = spi_master_get_devdata(spi->master);
  59. u32 csbit = 1U << (2 * spi->chip_select);
  60. dev_dbg(hw->master->dev.parent, "chipselect %d\n", spi->chip_select);
  61. if (value)
  62. hw->cs_reg |= csbit;
  63. else
  64. hw->cs_reg &= ~csbit;
  65. jcore_spi_program(hw);
  66. }
  67. static void jcore_spi_baudrate(struct jcore_spi *hw, int speed)
  68. {
  69. if (speed == hw->speed_hz)
  70. return;
  71. hw->speed_hz = speed;
  72. if (speed >= hw->clock_freq / 2)
  73. hw->speed_reg = 0;
  74. else
  75. hw->speed_reg = ((hw->clock_freq / 2 / speed) - 1) << 27;
  76. jcore_spi_program(hw);
  77. dev_dbg(hw->master->dev.parent, "speed=%d reg=0x%x\n",
  78. speed, hw->speed_reg);
  79. }
  80. static int jcore_spi_txrx(struct spi_master *master, struct spi_device *spi,
  81. struct spi_transfer *t)
  82. {
  83. struct jcore_spi *hw = spi_master_get_devdata(master);
  84. void __iomem *ctrl_reg = hw->base + CTRL_REG;
  85. void __iomem *data_reg = hw->base + DATA_REG;
  86. u32 xmit;
  87. /* data buffers */
  88. const unsigned char *tx;
  89. unsigned char *rx;
  90. unsigned int len;
  91. unsigned int count;
  92. jcore_spi_baudrate(hw, t->speed_hz);
  93. xmit = hw->cs_reg | hw->speed_reg | JCORE_SPI_CTRL_XMIT;
  94. tx = t->tx_buf;
  95. rx = t->rx_buf;
  96. len = t->len;
  97. for (count = 0; count < len; count++) {
  98. if (jcore_spi_wait(ctrl_reg))
  99. break;
  100. writel(tx ? *tx++ : 0, data_reg);
  101. writel(xmit, ctrl_reg);
  102. if (jcore_spi_wait(ctrl_reg))
  103. break;
  104. if (rx)
  105. *rx++ = readl(data_reg);
  106. }
  107. spi_finalize_current_transfer(master);
  108. if (count < len)
  109. return -EREMOTEIO;
  110. return 0;
  111. }
  112. static int jcore_spi_probe(struct platform_device *pdev)
  113. {
  114. struct device_node *node = pdev->dev.of_node;
  115. struct jcore_spi *hw;
  116. struct spi_master *master;
  117. struct resource *res;
  118. u32 clock_freq;
  119. struct clk *clk;
  120. int err = -ENODEV;
  121. master = spi_alloc_master(&pdev->dev, sizeof(struct jcore_spi));
  122. if (!master)
  123. return err;
  124. /* Setup the master state. */
  125. master->num_chipselect = 3;
  126. master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
  127. master->transfer_one = jcore_spi_txrx;
  128. master->set_cs = jcore_spi_chipsel;
  129. master->dev.of_node = node;
  130. master->bus_num = pdev->id;
  131. hw = spi_master_get_devdata(master);
  132. hw->master = master;
  133. platform_set_drvdata(pdev, hw);
  134. /* Find and map our resources */
  135. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  136. if (!res)
  137. goto exit_busy;
  138. if (!devm_request_mem_region(&pdev->dev, res->start,
  139. resource_size(res), pdev->name))
  140. goto exit_busy;
  141. hw->base = devm_ioremap(&pdev->dev, res->start,
  142. resource_size(res));
  143. if (!hw->base)
  144. goto exit_busy;
  145. /*
  146. * The SPI clock rate controlled via a configurable clock divider
  147. * which is applied to the reference clock. A 50 MHz reference is
  148. * most suitable for obtaining standard SPI clock rates, but some
  149. * designs may have a different reference clock, and the DT must
  150. * make the driver aware so that it can properly program the
  151. * requested rate. If the clock is omitted, 50 MHz is assumed.
  152. */
  153. clock_freq = 50000000;
  154. clk = devm_clk_get(&pdev->dev, "ref_clk");
  155. if (!IS_ERR(clk)) {
  156. if (clk_prepare_enable(clk) == 0) {
  157. clock_freq = clk_get_rate(clk);
  158. clk_disable_unprepare(clk);
  159. } else
  160. dev_warn(&pdev->dev, "could not enable ref_clk\n");
  161. }
  162. hw->clock_freq = clock_freq;
  163. /* Initialize all CS bits to high. */
  164. hw->cs_reg = JCORE_SPI_CTRL_CS_BITS;
  165. jcore_spi_baudrate(hw, 400000);
  166. /* Register our spi controller */
  167. err = devm_spi_register_master(&pdev->dev, master);
  168. if (err)
  169. goto exit;
  170. return 0;
  171. exit_busy:
  172. err = -EBUSY;
  173. exit:
  174. spi_master_put(master);
  175. return err;
  176. }
  177. static const struct of_device_id jcore_spi_of_match[] = {
  178. { .compatible = "jcore,spi2" },
  179. {},
  180. };
  181. MODULE_DEVICE_TABLE(of, jcore_spi_of_match);
  182. static struct platform_driver jcore_spi_driver = {
  183. .probe = jcore_spi_probe,
  184. .driver = {
  185. .name = DRV_NAME,
  186. .of_match_table = jcore_spi_of_match,
  187. },
  188. };
  189. module_platform_driver(jcore_spi_driver);
  190. MODULE_DESCRIPTION("J-Core SPI driver");
  191. MODULE_AUTHOR("Rich Felker <[email protected]>");
  192. MODULE_LICENSE("GPL");
  193. MODULE_ALIAS("platform:" DRV_NAME);