spi-cadence.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Cadence SPI controller driver (master mode only)
  4. *
  5. * Copyright (C) 2008 - 2014 Xilinx, Inc.
  6. *
  7. * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/delay.h>
  11. #include <linux/gpio/consumer.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/io.h>
  14. #include <linux/module.h>
  15. #include <linux/of_irq.h>
  16. #include <linux/of_address.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/pm_runtime.h>
  19. #include <linux/spi/spi.h>
  20. /* Name of this driver */
  21. #define CDNS_SPI_NAME "cdns-spi"
  22. /* Register offset definitions */
  23. #define CDNS_SPI_CR 0x00 /* Configuration Register, RW */
  24. #define CDNS_SPI_ISR 0x04 /* Interrupt Status Register, RO */
  25. #define CDNS_SPI_IER 0x08 /* Interrupt Enable Register, WO */
  26. #define CDNS_SPI_IDR 0x0c /* Interrupt Disable Register, WO */
  27. #define CDNS_SPI_IMR 0x10 /* Interrupt Enabled Mask Register, RO */
  28. #define CDNS_SPI_ER 0x14 /* Enable/Disable Register, RW */
  29. #define CDNS_SPI_DR 0x18 /* Delay Register, RW */
  30. #define CDNS_SPI_TXD 0x1C /* Data Transmit Register, WO */
  31. #define CDNS_SPI_RXD 0x20 /* Data Receive Register, RO */
  32. #define CDNS_SPI_SICR 0x24 /* Slave Idle Count Register, RW */
  33. #define CDNS_SPI_THLD 0x28 /* Transmit FIFO Watermark Register,RW */
  34. #define SPI_AUTOSUSPEND_TIMEOUT 3000
  35. /*
  36. * SPI Configuration Register bit Masks
  37. *
  38. * This register contains various control bits that affect the operation
  39. * of the SPI controller
  40. */
  41. #define CDNS_SPI_CR_MANSTRT 0x00010000 /* Manual TX Start */
  42. #define CDNS_SPI_CR_CPHA 0x00000004 /* Clock Phase Control */
  43. #define CDNS_SPI_CR_CPOL 0x00000002 /* Clock Polarity Control */
  44. #define CDNS_SPI_CR_SSCTRL 0x00003C00 /* Slave Select Mask */
  45. #define CDNS_SPI_CR_PERI_SEL 0x00000200 /* Peripheral Select Decode */
  46. #define CDNS_SPI_CR_BAUD_DIV 0x00000038 /* Baud Rate Divisor Mask */
  47. #define CDNS_SPI_CR_MSTREN 0x00000001 /* Master Enable Mask */
  48. #define CDNS_SPI_CR_MANSTRTEN 0x00008000 /* Manual TX Enable Mask */
  49. #define CDNS_SPI_CR_SSFORCE 0x00004000 /* Manual SS Enable Mask */
  50. #define CDNS_SPI_CR_BAUD_DIV_4 0x00000008 /* Default Baud Div Mask */
  51. #define CDNS_SPI_CR_DEFAULT (CDNS_SPI_CR_MSTREN | \
  52. CDNS_SPI_CR_SSCTRL | \
  53. CDNS_SPI_CR_SSFORCE | \
  54. CDNS_SPI_CR_BAUD_DIV_4)
  55. /*
  56. * SPI Configuration Register - Baud rate and slave select
  57. *
  58. * These are the values used in the calculation of baud rate divisor and
  59. * setting the slave select.
  60. */
  61. #define CDNS_SPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */
  62. #define CDNS_SPI_BAUD_DIV_MIN 1 /* Baud rate divisor minimum */
  63. #define CDNS_SPI_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift in CR */
  64. #define CDNS_SPI_SS_SHIFT 10 /* Slave Select field shift in CR */
  65. #define CDNS_SPI_SS0 0x1 /* Slave Select zero */
  66. #define CDNS_SPI_NOSS 0xF /* No Slave select */
  67. /*
  68. * SPI Interrupt Registers bit Masks
  69. *
  70. * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
  71. * bit definitions.
  72. */
  73. #define CDNS_SPI_IXR_TXOW 0x00000004 /* SPI TX FIFO Overwater */
  74. #define CDNS_SPI_IXR_MODF 0x00000002 /* SPI Mode Fault */
  75. #define CDNS_SPI_IXR_RXNEMTY 0x00000010 /* SPI RX FIFO Not Empty */
  76. #define CDNS_SPI_IXR_DEFAULT (CDNS_SPI_IXR_TXOW | \
  77. CDNS_SPI_IXR_MODF)
  78. #define CDNS_SPI_IXR_TXFULL 0x00000008 /* SPI TX Full */
  79. #define CDNS_SPI_IXR_ALL 0x0000007F /* SPI all interrupts */
  80. /*
  81. * SPI Enable Register bit Masks
  82. *
  83. * This register is used to enable or disable the SPI controller
  84. */
  85. #define CDNS_SPI_ER_ENABLE 0x00000001 /* SPI Enable Bit Mask */
  86. #define CDNS_SPI_ER_DISABLE 0x0 /* SPI Disable Bit Mask */
  87. /* Default number of chip select lines */
  88. #define CDNS_SPI_DEFAULT_NUM_CS 4
  89. /**
  90. * struct cdns_spi - This definition defines spi driver instance
  91. * @regs: Virtual address of the SPI controller registers
  92. * @ref_clk: Pointer to the peripheral clock
  93. * @pclk: Pointer to the APB clock
  94. * @speed_hz: Current SPI bus clock speed in Hz
  95. * @txbuf: Pointer to the TX buffer
  96. * @rxbuf: Pointer to the RX buffer
  97. * @tx_bytes: Number of bytes left to transfer
  98. * @rx_bytes: Number of bytes requested
  99. * @dev_busy: Device busy flag
  100. * @is_decoded_cs: Flag for decoder property set or not
  101. * @tx_fifo_depth: Depth of the TX FIFO
  102. */
  103. struct cdns_spi {
  104. void __iomem *regs;
  105. struct clk *ref_clk;
  106. struct clk *pclk;
  107. unsigned int clk_rate;
  108. u32 speed_hz;
  109. const u8 *txbuf;
  110. u8 *rxbuf;
  111. int tx_bytes;
  112. int rx_bytes;
  113. u8 dev_busy;
  114. u32 is_decoded_cs;
  115. unsigned int tx_fifo_depth;
  116. };
  117. /* Macros for the SPI controller read/write */
  118. static inline u32 cdns_spi_read(struct cdns_spi *xspi, u32 offset)
  119. {
  120. return readl_relaxed(xspi->regs + offset);
  121. }
  122. static inline void cdns_spi_write(struct cdns_spi *xspi, u32 offset, u32 val)
  123. {
  124. writel_relaxed(val, xspi->regs + offset);
  125. }
  126. /**
  127. * cdns_spi_init_hw - Initialize the hardware and configure the SPI controller
  128. * @xspi: Pointer to the cdns_spi structure
  129. *
  130. * On reset the SPI controller is configured to be in master mode, baud rate
  131. * divisor is set to 4, threshold value for TX FIFO not full interrupt is set
  132. * to 1 and size of the word to be transferred as 8 bit.
  133. * This function initializes the SPI controller to disable and clear all the
  134. * interrupts, enable manual slave select and manual start, deselect all the
  135. * chip select lines, and enable the SPI controller.
  136. */
  137. static void cdns_spi_init_hw(struct cdns_spi *xspi)
  138. {
  139. u32 ctrl_reg = CDNS_SPI_CR_DEFAULT;
  140. if (xspi->is_decoded_cs)
  141. ctrl_reg |= CDNS_SPI_CR_PERI_SEL;
  142. cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
  143. cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_ALL);
  144. /* Clear the RX FIFO */
  145. while (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_RXNEMTY)
  146. cdns_spi_read(xspi, CDNS_SPI_RXD);
  147. cdns_spi_write(xspi, CDNS_SPI_ISR, CDNS_SPI_IXR_ALL);
  148. cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
  149. cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
  150. }
  151. /**
  152. * cdns_spi_chipselect - Select or deselect the chip select line
  153. * @spi: Pointer to the spi_device structure
  154. * @is_high: Select(0) or deselect (1) the chip select line
  155. */
  156. static void cdns_spi_chipselect(struct spi_device *spi, bool is_high)
  157. {
  158. struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
  159. u32 ctrl_reg;
  160. ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
  161. if (is_high) {
  162. /* Deselect the slave */
  163. ctrl_reg |= CDNS_SPI_CR_SSCTRL;
  164. } else {
  165. /* Select the slave */
  166. ctrl_reg &= ~CDNS_SPI_CR_SSCTRL;
  167. if (!(xspi->is_decoded_cs))
  168. ctrl_reg |= ((~(CDNS_SPI_SS0 << spi->chip_select)) <<
  169. CDNS_SPI_SS_SHIFT) &
  170. CDNS_SPI_CR_SSCTRL;
  171. else
  172. ctrl_reg |= (spi->chip_select << CDNS_SPI_SS_SHIFT) &
  173. CDNS_SPI_CR_SSCTRL;
  174. }
  175. cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
  176. }
  177. /**
  178. * cdns_spi_config_clock_mode - Sets clock polarity and phase
  179. * @spi: Pointer to the spi_device structure
  180. *
  181. * Sets the requested clock polarity and phase.
  182. */
  183. static void cdns_spi_config_clock_mode(struct spi_device *spi)
  184. {
  185. struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
  186. u32 ctrl_reg, new_ctrl_reg;
  187. new_ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
  188. ctrl_reg = new_ctrl_reg;
  189. /* Set the SPI clock phase and clock polarity */
  190. new_ctrl_reg &= ~(CDNS_SPI_CR_CPHA | CDNS_SPI_CR_CPOL);
  191. if (spi->mode & SPI_CPHA)
  192. new_ctrl_reg |= CDNS_SPI_CR_CPHA;
  193. if (spi->mode & SPI_CPOL)
  194. new_ctrl_reg |= CDNS_SPI_CR_CPOL;
  195. if (new_ctrl_reg != ctrl_reg) {
  196. /*
  197. * Just writing the CR register does not seem to apply the clock
  198. * setting changes. This is problematic when changing the clock
  199. * polarity as it will cause the SPI slave to see spurious clock
  200. * transitions. To workaround the issue toggle the ER register.
  201. */
  202. cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
  203. cdns_spi_write(xspi, CDNS_SPI_CR, new_ctrl_reg);
  204. cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
  205. }
  206. }
  207. /**
  208. * cdns_spi_config_clock_freq - Sets clock frequency
  209. * @spi: Pointer to the spi_device structure
  210. * @transfer: Pointer to the spi_transfer structure which provides
  211. * information about next transfer setup parameters
  212. *
  213. * Sets the requested clock frequency.
  214. * Note: If the requested frequency is not an exact match with what can be
  215. * obtained using the prescalar value the driver sets the clock frequency which
  216. * is lower than the requested frequency (maximum lower) for the transfer. If
  217. * the requested frequency is higher or lower than that is supported by the SPI
  218. * controller the driver will set the highest or lowest frequency supported by
  219. * controller.
  220. */
  221. static void cdns_spi_config_clock_freq(struct spi_device *spi,
  222. struct spi_transfer *transfer)
  223. {
  224. struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
  225. u32 ctrl_reg, baud_rate_val;
  226. unsigned long frequency;
  227. frequency = xspi->clk_rate;
  228. ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
  229. /* Set the clock frequency */
  230. if (xspi->speed_hz != transfer->speed_hz) {
  231. /* first valid value is 1 */
  232. baud_rate_val = CDNS_SPI_BAUD_DIV_MIN;
  233. while ((baud_rate_val < CDNS_SPI_BAUD_DIV_MAX) &&
  234. (frequency / (2 << baud_rate_val)) > transfer->speed_hz)
  235. baud_rate_val++;
  236. ctrl_reg &= ~CDNS_SPI_CR_BAUD_DIV;
  237. ctrl_reg |= baud_rate_val << CDNS_SPI_BAUD_DIV_SHIFT;
  238. xspi->speed_hz = frequency / (2 << baud_rate_val);
  239. }
  240. cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
  241. }
  242. /**
  243. * cdns_spi_setup_transfer - Configure SPI controller for specified transfer
  244. * @spi: Pointer to the spi_device structure
  245. * @transfer: Pointer to the spi_transfer structure which provides
  246. * information about next transfer setup parameters
  247. *
  248. * Sets the operational mode of SPI controller for the next SPI transfer and
  249. * sets the requested clock frequency.
  250. *
  251. * Return: Always 0
  252. */
  253. static int cdns_spi_setup_transfer(struct spi_device *spi,
  254. struct spi_transfer *transfer)
  255. {
  256. struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
  257. cdns_spi_config_clock_freq(spi, transfer);
  258. dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u clock speed\n",
  259. __func__, spi->mode, spi->bits_per_word,
  260. xspi->speed_hz);
  261. return 0;
  262. }
  263. /**
  264. * cdns_spi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible
  265. * @xspi: Pointer to the cdns_spi structure
  266. */
  267. static void cdns_spi_fill_tx_fifo(struct cdns_spi *xspi)
  268. {
  269. unsigned long trans_cnt = 0;
  270. while ((trans_cnt < xspi->tx_fifo_depth) &&
  271. (xspi->tx_bytes > 0)) {
  272. /* When xspi in busy condition, bytes may send failed,
  273. * then spi control did't work thoroughly, add one byte delay
  274. */
  275. if (cdns_spi_read(xspi, CDNS_SPI_ISR) &
  276. CDNS_SPI_IXR_TXFULL)
  277. udelay(10);
  278. if (xspi->txbuf)
  279. cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++);
  280. else
  281. cdns_spi_write(xspi, CDNS_SPI_TXD, 0);
  282. xspi->tx_bytes--;
  283. trans_cnt++;
  284. }
  285. }
  286. /**
  287. * cdns_spi_irq - Interrupt service routine of the SPI controller
  288. * @irq: IRQ number
  289. * @dev_id: Pointer to the xspi structure
  290. *
  291. * This function handles TX empty and Mode Fault interrupts only.
  292. * On TX empty interrupt this function reads the received data from RX FIFO and
  293. * fills the TX FIFO if there is any data remaining to be transferred.
  294. * On Mode Fault interrupt this function indicates that transfer is completed,
  295. * the SPI subsystem will identify the error as the remaining bytes to be
  296. * transferred is non-zero.
  297. *
  298. * Return: IRQ_HANDLED when handled; IRQ_NONE otherwise.
  299. */
  300. static irqreturn_t cdns_spi_irq(int irq, void *dev_id)
  301. {
  302. struct spi_master *master = dev_id;
  303. struct cdns_spi *xspi = spi_master_get_devdata(master);
  304. irqreturn_t status;
  305. u32 intr_status;
  306. status = IRQ_NONE;
  307. intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR);
  308. cdns_spi_write(xspi, CDNS_SPI_ISR, intr_status);
  309. if (intr_status & CDNS_SPI_IXR_MODF) {
  310. /* Indicate that transfer is completed, the SPI subsystem will
  311. * identify the error as the remaining bytes to be
  312. * transferred is non-zero
  313. */
  314. cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_DEFAULT);
  315. spi_finalize_current_transfer(master);
  316. status = IRQ_HANDLED;
  317. } else if (intr_status & CDNS_SPI_IXR_TXOW) {
  318. unsigned long trans_cnt;
  319. trans_cnt = xspi->rx_bytes - xspi->tx_bytes;
  320. /* Read out the data from the RX FIFO */
  321. while (trans_cnt) {
  322. u8 data;
  323. data = cdns_spi_read(xspi, CDNS_SPI_RXD);
  324. if (xspi->rxbuf)
  325. *xspi->rxbuf++ = data;
  326. xspi->rx_bytes--;
  327. trans_cnt--;
  328. }
  329. if (xspi->tx_bytes) {
  330. /* There is more data to send */
  331. cdns_spi_fill_tx_fifo(xspi);
  332. } else {
  333. /* Transfer is completed */
  334. cdns_spi_write(xspi, CDNS_SPI_IDR,
  335. CDNS_SPI_IXR_DEFAULT);
  336. spi_finalize_current_transfer(master);
  337. }
  338. status = IRQ_HANDLED;
  339. }
  340. return status;
  341. }
  342. static int cdns_prepare_message(struct spi_master *master,
  343. struct spi_message *msg)
  344. {
  345. cdns_spi_config_clock_mode(msg->spi);
  346. return 0;
  347. }
  348. /**
  349. * cdns_transfer_one - Initiates the SPI transfer
  350. * @master: Pointer to spi_master structure
  351. * @spi: Pointer to the spi_device structure
  352. * @transfer: Pointer to the spi_transfer structure which provides
  353. * information about next transfer parameters
  354. *
  355. * This function fills the TX FIFO, starts the SPI transfer and
  356. * returns a positive transfer count so that core will wait for completion.
  357. *
  358. * Return: Number of bytes transferred in the last transfer
  359. */
  360. static int cdns_transfer_one(struct spi_master *master,
  361. struct spi_device *spi,
  362. struct spi_transfer *transfer)
  363. {
  364. struct cdns_spi *xspi = spi_master_get_devdata(master);
  365. xspi->txbuf = transfer->tx_buf;
  366. xspi->rxbuf = transfer->rx_buf;
  367. xspi->tx_bytes = transfer->len;
  368. xspi->rx_bytes = transfer->len;
  369. cdns_spi_setup_transfer(spi, transfer);
  370. cdns_spi_fill_tx_fifo(xspi);
  371. spi_transfer_delay_exec(transfer);
  372. cdns_spi_write(xspi, CDNS_SPI_IER, CDNS_SPI_IXR_DEFAULT);
  373. return transfer->len;
  374. }
  375. /**
  376. * cdns_prepare_transfer_hardware - Prepares hardware for transfer.
  377. * @master: Pointer to the spi_master structure which provides
  378. * information about the controller.
  379. *
  380. * This function enables SPI master controller.
  381. *
  382. * Return: 0 always
  383. */
  384. static int cdns_prepare_transfer_hardware(struct spi_master *master)
  385. {
  386. struct cdns_spi *xspi = spi_master_get_devdata(master);
  387. cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
  388. return 0;
  389. }
  390. /**
  391. * cdns_unprepare_transfer_hardware - Relaxes hardware after transfer
  392. * @master: Pointer to the spi_master structure which provides
  393. * information about the controller.
  394. *
  395. * This function disables the SPI master controller when no slave selected.
  396. *
  397. * Return: 0 always
  398. */
  399. static int cdns_unprepare_transfer_hardware(struct spi_master *master)
  400. {
  401. struct cdns_spi *xspi = spi_master_get_devdata(master);
  402. u32 ctrl_reg;
  403. /* Disable the SPI if slave is deselected */
  404. ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
  405. ctrl_reg = (ctrl_reg & CDNS_SPI_CR_SSCTRL) >> CDNS_SPI_SS_SHIFT;
  406. if (ctrl_reg == CDNS_SPI_NOSS)
  407. cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
  408. return 0;
  409. }
  410. /**
  411. * cdns_spi_detect_fifo_depth - Detect the FIFO depth of the hardware
  412. * @xspi: Pointer to the cdns_spi structure
  413. *
  414. * The depth of the TX FIFO is a synthesis configuration parameter of the SPI
  415. * IP. The FIFO threshold register is sized so that its maximum value can be the
  416. * FIFO size - 1. This is used to detect the size of the FIFO.
  417. */
  418. static void cdns_spi_detect_fifo_depth(struct cdns_spi *xspi)
  419. {
  420. /* The MSBs will get truncated giving us the size of the FIFO */
  421. cdns_spi_write(xspi, CDNS_SPI_THLD, 0xffff);
  422. xspi->tx_fifo_depth = cdns_spi_read(xspi, CDNS_SPI_THLD) + 1;
  423. /* Reset to default */
  424. cdns_spi_write(xspi, CDNS_SPI_THLD, 0x1);
  425. }
  426. /**
  427. * cdns_spi_probe - Probe method for the SPI driver
  428. * @pdev: Pointer to the platform_device structure
  429. *
  430. * This function initializes the driver data structures and the hardware.
  431. *
  432. * Return: 0 on success and error value on error
  433. */
  434. static int cdns_spi_probe(struct platform_device *pdev)
  435. {
  436. int ret = 0, irq;
  437. struct spi_master *master;
  438. struct cdns_spi *xspi;
  439. u32 num_cs;
  440. master = spi_alloc_master(&pdev->dev, sizeof(*xspi));
  441. if (!master)
  442. return -ENOMEM;
  443. xspi = spi_master_get_devdata(master);
  444. master->dev.of_node = pdev->dev.of_node;
  445. platform_set_drvdata(pdev, master);
  446. xspi->regs = devm_platform_ioremap_resource(pdev, 0);
  447. if (IS_ERR(xspi->regs)) {
  448. ret = PTR_ERR(xspi->regs);
  449. goto remove_master;
  450. }
  451. xspi->pclk = devm_clk_get(&pdev->dev, "pclk");
  452. if (IS_ERR(xspi->pclk)) {
  453. dev_err(&pdev->dev, "pclk clock not found.\n");
  454. ret = PTR_ERR(xspi->pclk);
  455. goto remove_master;
  456. }
  457. xspi->ref_clk = devm_clk_get(&pdev->dev, "ref_clk");
  458. if (IS_ERR(xspi->ref_clk)) {
  459. dev_err(&pdev->dev, "ref_clk clock not found.\n");
  460. ret = PTR_ERR(xspi->ref_clk);
  461. goto remove_master;
  462. }
  463. ret = clk_prepare_enable(xspi->pclk);
  464. if (ret) {
  465. dev_err(&pdev->dev, "Unable to enable APB clock.\n");
  466. goto remove_master;
  467. }
  468. ret = clk_prepare_enable(xspi->ref_clk);
  469. if (ret) {
  470. dev_err(&pdev->dev, "Unable to enable device clock.\n");
  471. goto clk_dis_apb;
  472. }
  473. pm_runtime_use_autosuspend(&pdev->dev);
  474. pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
  475. pm_runtime_get_noresume(&pdev->dev);
  476. pm_runtime_set_active(&pdev->dev);
  477. pm_runtime_enable(&pdev->dev);
  478. ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
  479. if (ret < 0)
  480. master->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS;
  481. else
  482. master->num_chipselect = num_cs;
  483. ret = of_property_read_u32(pdev->dev.of_node, "is-decoded-cs",
  484. &xspi->is_decoded_cs);
  485. if (ret < 0)
  486. xspi->is_decoded_cs = 0;
  487. cdns_spi_detect_fifo_depth(xspi);
  488. /* SPI controller initializations */
  489. cdns_spi_init_hw(xspi);
  490. irq = platform_get_irq(pdev, 0);
  491. if (irq <= 0) {
  492. ret = -ENXIO;
  493. goto clk_dis_all;
  494. }
  495. ret = devm_request_irq(&pdev->dev, irq, cdns_spi_irq,
  496. 0, pdev->name, master);
  497. if (ret != 0) {
  498. ret = -ENXIO;
  499. dev_err(&pdev->dev, "request_irq failed\n");
  500. goto clk_dis_all;
  501. }
  502. master->use_gpio_descriptors = true;
  503. master->prepare_transfer_hardware = cdns_prepare_transfer_hardware;
  504. master->prepare_message = cdns_prepare_message;
  505. master->transfer_one = cdns_transfer_one;
  506. master->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware;
  507. master->set_cs = cdns_spi_chipselect;
  508. master->auto_runtime_pm = true;
  509. master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
  510. xspi->clk_rate = clk_get_rate(xspi->ref_clk);
  511. /* Set to default valid value */
  512. master->max_speed_hz = xspi->clk_rate / 4;
  513. xspi->speed_hz = master->max_speed_hz;
  514. master->bits_per_word_mask = SPI_BPW_MASK(8);
  515. pm_runtime_mark_last_busy(&pdev->dev);
  516. pm_runtime_put_autosuspend(&pdev->dev);
  517. ret = spi_register_master(master);
  518. if (ret) {
  519. dev_err(&pdev->dev, "spi_register_master failed\n");
  520. goto clk_dis_all;
  521. }
  522. return ret;
  523. clk_dis_all:
  524. pm_runtime_set_suspended(&pdev->dev);
  525. pm_runtime_disable(&pdev->dev);
  526. clk_disable_unprepare(xspi->ref_clk);
  527. clk_dis_apb:
  528. clk_disable_unprepare(xspi->pclk);
  529. remove_master:
  530. spi_master_put(master);
  531. return ret;
  532. }
  533. /**
  534. * cdns_spi_remove - Remove method for the SPI driver
  535. * @pdev: Pointer to the platform_device structure
  536. *
  537. * This function is called if a device is physically removed from the system or
  538. * if the driver module is being unloaded. It frees all resources allocated to
  539. * the device.
  540. *
  541. * Return: 0 on success and error value on error
  542. */
  543. static int cdns_spi_remove(struct platform_device *pdev)
  544. {
  545. struct spi_master *master = platform_get_drvdata(pdev);
  546. struct cdns_spi *xspi = spi_master_get_devdata(master);
  547. cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
  548. clk_disable_unprepare(xspi->ref_clk);
  549. clk_disable_unprepare(xspi->pclk);
  550. pm_runtime_set_suspended(&pdev->dev);
  551. pm_runtime_disable(&pdev->dev);
  552. spi_unregister_master(master);
  553. return 0;
  554. }
  555. /**
  556. * cdns_spi_suspend - Suspend method for the SPI driver
  557. * @dev: Address of the platform_device structure
  558. *
  559. * This function disables the SPI controller and
  560. * changes the driver state to "suspend"
  561. *
  562. * Return: 0 on success and error value on error
  563. */
  564. static int __maybe_unused cdns_spi_suspend(struct device *dev)
  565. {
  566. struct spi_master *master = dev_get_drvdata(dev);
  567. return spi_master_suspend(master);
  568. }
  569. /**
  570. * cdns_spi_resume - Resume method for the SPI driver
  571. * @dev: Address of the platform_device structure
  572. *
  573. * This function changes the driver state to "ready"
  574. *
  575. * Return: 0 on success and error value on error
  576. */
  577. static int __maybe_unused cdns_spi_resume(struct device *dev)
  578. {
  579. struct spi_master *master = dev_get_drvdata(dev);
  580. struct cdns_spi *xspi = spi_master_get_devdata(master);
  581. cdns_spi_init_hw(xspi);
  582. return spi_master_resume(master);
  583. }
  584. /**
  585. * cdns_spi_runtime_resume - Runtime resume method for the SPI driver
  586. * @dev: Address of the platform_device structure
  587. *
  588. * This function enables the clocks
  589. *
  590. * Return: 0 on success and error value on error
  591. */
  592. static int __maybe_unused cdns_spi_runtime_resume(struct device *dev)
  593. {
  594. struct spi_master *master = dev_get_drvdata(dev);
  595. struct cdns_spi *xspi = spi_master_get_devdata(master);
  596. int ret;
  597. ret = clk_prepare_enable(xspi->pclk);
  598. if (ret) {
  599. dev_err(dev, "Cannot enable APB clock.\n");
  600. return ret;
  601. }
  602. ret = clk_prepare_enable(xspi->ref_clk);
  603. if (ret) {
  604. dev_err(dev, "Cannot enable device clock.\n");
  605. clk_disable_unprepare(xspi->pclk);
  606. return ret;
  607. }
  608. return 0;
  609. }
  610. /**
  611. * cdns_spi_runtime_suspend - Runtime suspend method for the SPI driver
  612. * @dev: Address of the platform_device structure
  613. *
  614. * This function disables the clocks
  615. *
  616. * Return: Always 0
  617. */
  618. static int __maybe_unused cdns_spi_runtime_suspend(struct device *dev)
  619. {
  620. struct spi_master *master = dev_get_drvdata(dev);
  621. struct cdns_spi *xspi = spi_master_get_devdata(master);
  622. clk_disable_unprepare(xspi->ref_clk);
  623. clk_disable_unprepare(xspi->pclk);
  624. return 0;
  625. }
  626. static const struct dev_pm_ops cdns_spi_dev_pm_ops = {
  627. SET_RUNTIME_PM_OPS(cdns_spi_runtime_suspend,
  628. cdns_spi_runtime_resume, NULL)
  629. SET_SYSTEM_SLEEP_PM_OPS(cdns_spi_suspend, cdns_spi_resume)
  630. };
  631. static const struct of_device_id cdns_spi_of_match[] = {
  632. { .compatible = "xlnx,zynq-spi-r1p6" },
  633. { .compatible = "cdns,spi-r1p6" },
  634. { /* end of table */ }
  635. };
  636. MODULE_DEVICE_TABLE(of, cdns_spi_of_match);
  637. /* cdns_spi_driver - This structure defines the SPI subsystem platform driver */
  638. static struct platform_driver cdns_spi_driver = {
  639. .probe = cdns_spi_probe,
  640. .remove = cdns_spi_remove,
  641. .driver = {
  642. .name = CDNS_SPI_NAME,
  643. .of_match_table = cdns_spi_of_match,
  644. .pm = &cdns_spi_dev_pm_ops,
  645. },
  646. };
  647. module_platform_driver(cdns_spi_driver);
  648. MODULE_AUTHOR("Xilinx, Inc.");
  649. MODULE_DESCRIPTION("Cadence SPI driver");
  650. MODULE_LICENSE("GPL");