spi-aspeed-smc.c 32 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * ASPEED FMC/SPI Memory Controller Driver
  4. *
  5. * Copyright (c) 2015-2022, IBM Corporation.
  6. * Copyright (c) 2020, ASPEED Corporation.
  7. */
  8. #include <linux/clk.h>
  9. #include <linux/module.h>
  10. #include <linux/of.h>
  11. #include <linux/of_platform.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/spi/spi.h>
  14. #include <linux/spi/spi-mem.h>
  15. #define DEVICE_NAME "spi-aspeed-smc"
  16. /* Type setting Register */
  17. #define CONFIG_REG 0x0
  18. #define CONFIG_TYPE_SPI 0x2
  19. /* CE Control Register */
  20. #define CE_CTRL_REG 0x4
  21. /* CEx Control Register */
  22. #define CE0_CTRL_REG 0x10
  23. #define CTRL_IO_MODE_MASK GENMASK(30, 28)
  24. #define CTRL_IO_SINGLE_DATA 0x0
  25. #define CTRL_IO_DUAL_DATA BIT(29)
  26. #define CTRL_IO_QUAD_DATA BIT(30)
  27. #define CTRL_COMMAND_SHIFT 16
  28. #define CTRL_IO_ADDRESS_4B BIT(13) /* AST2400 SPI only */
  29. #define CTRL_IO_DUMMY_SET(dummy) \
  30. (((((dummy) >> 2) & 0x1) << 14) | (((dummy) & 0x3) << 6))
  31. #define CTRL_FREQ_SEL_SHIFT 8
  32. #define CTRL_FREQ_SEL_MASK GENMASK(11, CTRL_FREQ_SEL_SHIFT)
  33. #define CTRL_CE_STOP_ACTIVE BIT(2)
  34. #define CTRL_IO_MODE_CMD_MASK GENMASK(1, 0)
  35. #define CTRL_IO_MODE_NORMAL 0x0
  36. #define CTRL_IO_MODE_READ 0x1
  37. #define CTRL_IO_MODE_WRITE 0x2
  38. #define CTRL_IO_MODE_USER 0x3
  39. #define CTRL_IO_CMD_MASK 0xf0ff40c3
  40. /* CEx Address Decoding Range Register */
  41. #define CE0_SEGMENT_ADDR_REG 0x30
  42. /* CEx Read timing compensation register */
  43. #define CE0_TIMING_COMPENSATION_REG 0x94
  44. enum aspeed_spi_ctl_reg_value {
  45. ASPEED_SPI_BASE,
  46. ASPEED_SPI_READ,
  47. ASPEED_SPI_WRITE,
  48. ASPEED_SPI_MAX,
  49. };
  50. struct aspeed_spi;
  51. struct aspeed_spi_chip {
  52. struct aspeed_spi *aspi;
  53. u32 cs;
  54. void __iomem *ctl;
  55. void __iomem *ahb_base;
  56. u32 ahb_window_size;
  57. u32 ctl_val[ASPEED_SPI_MAX];
  58. u32 clk_freq;
  59. };
  60. struct aspeed_spi_data {
  61. u32 ctl0;
  62. u32 max_cs;
  63. bool hastype;
  64. u32 mode_bits;
  65. u32 we0;
  66. u32 timing;
  67. u32 hclk_mask;
  68. u32 hdiv_max;
  69. u32 (*segment_start)(struct aspeed_spi *aspi, u32 reg);
  70. u32 (*segment_end)(struct aspeed_spi *aspi, u32 reg);
  71. u32 (*segment_reg)(struct aspeed_spi *aspi, u32 start, u32 end);
  72. int (*calibrate)(struct aspeed_spi_chip *chip, u32 hdiv,
  73. const u8 *golden_buf, u8 *test_buf);
  74. };
  75. #define ASPEED_SPI_MAX_NUM_CS 5
  76. struct aspeed_spi {
  77. const struct aspeed_spi_data *data;
  78. void __iomem *regs;
  79. void __iomem *ahb_base;
  80. u32 ahb_base_phy;
  81. u32 ahb_window_size;
  82. struct device *dev;
  83. struct clk *clk;
  84. u32 clk_freq;
  85. struct aspeed_spi_chip chips[ASPEED_SPI_MAX_NUM_CS];
  86. };
  87. static u32 aspeed_spi_get_io_mode(const struct spi_mem_op *op)
  88. {
  89. switch (op->data.buswidth) {
  90. case 1:
  91. return CTRL_IO_SINGLE_DATA;
  92. case 2:
  93. return CTRL_IO_DUAL_DATA;
  94. case 4:
  95. return CTRL_IO_QUAD_DATA;
  96. default:
  97. return CTRL_IO_SINGLE_DATA;
  98. }
  99. }
  100. static void aspeed_spi_set_io_mode(struct aspeed_spi_chip *chip, u32 io_mode)
  101. {
  102. u32 ctl;
  103. if (io_mode > 0) {
  104. ctl = readl(chip->ctl) & ~CTRL_IO_MODE_MASK;
  105. ctl |= io_mode;
  106. writel(ctl, chip->ctl);
  107. }
  108. }
  109. static void aspeed_spi_start_user(struct aspeed_spi_chip *chip)
  110. {
  111. u32 ctl = chip->ctl_val[ASPEED_SPI_BASE];
  112. ctl |= CTRL_IO_MODE_USER | CTRL_CE_STOP_ACTIVE;
  113. writel(ctl, chip->ctl);
  114. ctl &= ~CTRL_CE_STOP_ACTIVE;
  115. writel(ctl, chip->ctl);
  116. }
  117. static void aspeed_spi_stop_user(struct aspeed_spi_chip *chip)
  118. {
  119. u32 ctl = chip->ctl_val[ASPEED_SPI_READ] |
  120. CTRL_IO_MODE_USER | CTRL_CE_STOP_ACTIVE;
  121. writel(ctl, chip->ctl);
  122. /* Restore defaults */
  123. writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
  124. }
  125. static int aspeed_spi_read_from_ahb(void *buf, void __iomem *src, size_t len)
  126. {
  127. size_t offset = 0;
  128. if (IS_ALIGNED((uintptr_t)src, sizeof(uintptr_t)) &&
  129. IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) {
  130. ioread32_rep(src, buf, len >> 2);
  131. offset = len & ~0x3;
  132. len -= offset;
  133. }
  134. ioread8_rep(src, (u8 *)buf + offset, len);
  135. return 0;
  136. }
  137. static int aspeed_spi_write_to_ahb(void __iomem *dst, const void *buf, size_t len)
  138. {
  139. size_t offset = 0;
  140. if (IS_ALIGNED((uintptr_t)dst, sizeof(uintptr_t)) &&
  141. IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) {
  142. iowrite32_rep(dst, buf, len >> 2);
  143. offset = len & ~0x3;
  144. len -= offset;
  145. }
  146. iowrite8_rep(dst, (const u8 *)buf + offset, len);
  147. return 0;
  148. }
  149. static int aspeed_spi_send_cmd_addr(struct aspeed_spi_chip *chip, u8 addr_nbytes,
  150. u64 offset, u32 opcode)
  151. {
  152. __be32 temp;
  153. u32 cmdaddr;
  154. switch (addr_nbytes) {
  155. case 3:
  156. cmdaddr = offset & 0xFFFFFF;
  157. cmdaddr |= opcode << 24;
  158. temp = cpu_to_be32(cmdaddr);
  159. aspeed_spi_write_to_ahb(chip->ahb_base, &temp, 4);
  160. break;
  161. case 4:
  162. temp = cpu_to_be32(offset);
  163. aspeed_spi_write_to_ahb(chip->ahb_base, &opcode, 1);
  164. aspeed_spi_write_to_ahb(chip->ahb_base, &temp, 4);
  165. break;
  166. default:
  167. WARN_ONCE(1, "Unexpected address width %u", addr_nbytes);
  168. return -EOPNOTSUPP;
  169. }
  170. return 0;
  171. }
  172. static int aspeed_spi_read_reg(struct aspeed_spi_chip *chip,
  173. const struct spi_mem_op *op)
  174. {
  175. aspeed_spi_start_user(chip);
  176. aspeed_spi_write_to_ahb(chip->ahb_base, &op->cmd.opcode, 1);
  177. aspeed_spi_read_from_ahb(op->data.buf.in,
  178. chip->ahb_base, op->data.nbytes);
  179. aspeed_spi_stop_user(chip);
  180. return 0;
  181. }
  182. static int aspeed_spi_write_reg(struct aspeed_spi_chip *chip,
  183. const struct spi_mem_op *op)
  184. {
  185. aspeed_spi_start_user(chip);
  186. aspeed_spi_write_to_ahb(chip->ahb_base, &op->cmd.opcode, 1);
  187. aspeed_spi_write_to_ahb(chip->ahb_base, op->data.buf.out,
  188. op->data.nbytes);
  189. aspeed_spi_stop_user(chip);
  190. return 0;
  191. }
  192. static ssize_t aspeed_spi_read_user(struct aspeed_spi_chip *chip,
  193. const struct spi_mem_op *op,
  194. u64 offset, size_t len, void *buf)
  195. {
  196. int io_mode = aspeed_spi_get_io_mode(op);
  197. u8 dummy = 0xFF;
  198. int i;
  199. int ret;
  200. aspeed_spi_start_user(chip);
  201. ret = aspeed_spi_send_cmd_addr(chip, op->addr.nbytes, offset, op->cmd.opcode);
  202. if (ret < 0)
  203. return ret;
  204. if (op->dummy.buswidth && op->dummy.nbytes) {
  205. for (i = 0; i < op->dummy.nbytes / op->dummy.buswidth; i++)
  206. aspeed_spi_write_to_ahb(chip->ahb_base, &dummy, sizeof(dummy));
  207. }
  208. aspeed_spi_set_io_mode(chip, io_mode);
  209. aspeed_spi_read_from_ahb(buf, chip->ahb_base, len);
  210. aspeed_spi_stop_user(chip);
  211. return 0;
  212. }
  213. static ssize_t aspeed_spi_write_user(struct aspeed_spi_chip *chip,
  214. const struct spi_mem_op *op)
  215. {
  216. int ret;
  217. aspeed_spi_start_user(chip);
  218. ret = aspeed_spi_send_cmd_addr(chip, op->addr.nbytes, op->addr.val, op->cmd.opcode);
  219. if (ret < 0)
  220. return ret;
  221. aspeed_spi_write_to_ahb(chip->ahb_base, op->data.buf.out, op->data.nbytes);
  222. aspeed_spi_stop_user(chip);
  223. return 0;
  224. }
  225. /* support for 1-1-1, 1-1-2 or 1-1-4 */
  226. static bool aspeed_spi_supports_op(struct spi_mem *mem, const struct spi_mem_op *op)
  227. {
  228. if (op->cmd.buswidth > 1)
  229. return false;
  230. if (op->addr.nbytes != 0) {
  231. if (op->addr.buswidth > 1)
  232. return false;
  233. if (op->addr.nbytes < 3 || op->addr.nbytes > 4)
  234. return false;
  235. }
  236. if (op->dummy.nbytes != 0) {
  237. if (op->dummy.buswidth > 1 || op->dummy.nbytes > 7)
  238. return false;
  239. }
  240. if (op->data.nbytes != 0 && op->data.buswidth > 4)
  241. return false;
  242. return spi_mem_default_supports_op(mem, op);
  243. }
  244. static const struct aspeed_spi_data ast2400_spi_data;
  245. static int do_aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
  246. {
  247. struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->master);
  248. struct aspeed_spi_chip *chip = &aspi->chips[mem->spi->chip_select];
  249. u32 addr_mode, addr_mode_backup;
  250. u32 ctl_val;
  251. int ret = 0;
  252. dev_dbg(aspi->dev,
  253. "CE%d %s OP %#x mode:%d.%d.%d.%d naddr:%#x ndummies:%#x len:%#x",
  254. chip->cs, op->data.dir == SPI_MEM_DATA_IN ? "read" : "write",
  255. op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
  256. op->dummy.buswidth, op->data.buswidth,
  257. op->addr.nbytes, op->dummy.nbytes, op->data.nbytes);
  258. addr_mode = readl(aspi->regs + CE_CTRL_REG);
  259. addr_mode_backup = addr_mode;
  260. ctl_val = chip->ctl_val[ASPEED_SPI_BASE];
  261. ctl_val &= ~CTRL_IO_CMD_MASK;
  262. ctl_val |= op->cmd.opcode << CTRL_COMMAND_SHIFT;
  263. /* 4BYTE address mode */
  264. if (op->addr.nbytes) {
  265. if (op->addr.nbytes == 4)
  266. addr_mode |= (0x11 << chip->cs);
  267. else
  268. addr_mode &= ~(0x11 << chip->cs);
  269. if (op->addr.nbytes == 4 && chip->aspi->data == &ast2400_spi_data)
  270. ctl_val |= CTRL_IO_ADDRESS_4B;
  271. }
  272. if (op->dummy.nbytes)
  273. ctl_val |= CTRL_IO_DUMMY_SET(op->dummy.nbytes / op->dummy.buswidth);
  274. if (op->data.nbytes)
  275. ctl_val |= aspeed_spi_get_io_mode(op);
  276. if (op->data.dir == SPI_MEM_DATA_OUT)
  277. ctl_val |= CTRL_IO_MODE_WRITE;
  278. else
  279. ctl_val |= CTRL_IO_MODE_READ;
  280. if (addr_mode != addr_mode_backup)
  281. writel(addr_mode, aspi->regs + CE_CTRL_REG);
  282. writel(ctl_val, chip->ctl);
  283. if (op->data.dir == SPI_MEM_DATA_IN) {
  284. if (!op->addr.nbytes)
  285. ret = aspeed_spi_read_reg(chip, op);
  286. else
  287. ret = aspeed_spi_read_user(chip, op, op->addr.val,
  288. op->data.nbytes, op->data.buf.in);
  289. } else {
  290. if (!op->addr.nbytes)
  291. ret = aspeed_spi_write_reg(chip, op);
  292. else
  293. ret = aspeed_spi_write_user(chip, op);
  294. }
  295. /* Restore defaults */
  296. if (addr_mode != addr_mode_backup)
  297. writel(addr_mode_backup, aspi->regs + CE_CTRL_REG);
  298. writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
  299. return ret;
  300. }
  301. static int aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
  302. {
  303. int ret;
  304. ret = do_aspeed_spi_exec_op(mem, op);
  305. if (ret)
  306. dev_err(&mem->spi->dev, "operation failed: %d\n", ret);
  307. return ret;
  308. }
  309. static const char *aspeed_spi_get_name(struct spi_mem *mem)
  310. {
  311. struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->master);
  312. struct device *dev = aspi->dev;
  313. return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), mem->spi->chip_select);
  314. }
  315. struct aspeed_spi_window {
  316. u32 cs;
  317. u32 offset;
  318. u32 size;
  319. };
  320. static void aspeed_spi_get_windows(struct aspeed_spi *aspi,
  321. struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS])
  322. {
  323. const struct aspeed_spi_data *data = aspi->data;
  324. u32 reg_val;
  325. u32 cs;
  326. for (cs = 0; cs < aspi->data->max_cs; cs++) {
  327. reg_val = readl(aspi->regs + CE0_SEGMENT_ADDR_REG + cs * 4);
  328. windows[cs].cs = cs;
  329. windows[cs].size = data->segment_end(aspi, reg_val) -
  330. data->segment_start(aspi, reg_val);
  331. windows[cs].offset = data->segment_start(aspi, reg_val) - aspi->ahb_base_phy;
  332. dev_vdbg(aspi->dev, "CE%d offset=0x%.8x size=0x%x\n", cs,
  333. windows[cs].offset, windows[cs].size);
  334. }
  335. }
  336. /*
  337. * On the AST2600, some CE windows are closed by default at reset but
  338. * U-Boot should open all.
  339. */
  340. static int aspeed_spi_chip_set_default_window(struct aspeed_spi_chip *chip)
  341. {
  342. struct aspeed_spi *aspi = chip->aspi;
  343. struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS] = { 0 };
  344. struct aspeed_spi_window *win = &windows[chip->cs];
  345. /* No segment registers for the AST2400 SPI controller */
  346. if (aspi->data == &ast2400_spi_data) {
  347. win->offset = 0;
  348. win->size = aspi->ahb_window_size;
  349. } else {
  350. aspeed_spi_get_windows(aspi, windows);
  351. }
  352. chip->ahb_base = aspi->ahb_base + win->offset;
  353. chip->ahb_window_size = win->size;
  354. dev_dbg(aspi->dev, "CE%d default window [ 0x%.8x - 0x%.8x ] %dMB",
  355. chip->cs, aspi->ahb_base_phy + win->offset,
  356. aspi->ahb_base_phy + win->offset + win->size - 1,
  357. win->size >> 20);
  358. return chip->ahb_window_size ? 0 : -1;
  359. }
  360. static int aspeed_spi_set_window(struct aspeed_spi *aspi,
  361. const struct aspeed_spi_window *win)
  362. {
  363. u32 start = aspi->ahb_base_phy + win->offset;
  364. u32 end = start + win->size;
  365. void __iomem *seg_reg = aspi->regs + CE0_SEGMENT_ADDR_REG + win->cs * 4;
  366. u32 seg_val_backup = readl(seg_reg);
  367. u32 seg_val = aspi->data->segment_reg(aspi, start, end);
  368. if (seg_val == seg_val_backup)
  369. return 0;
  370. writel(seg_val, seg_reg);
  371. /*
  372. * Restore initial value if something goes wrong else we could
  373. * loose access to the chip.
  374. */
  375. if (seg_val != readl(seg_reg)) {
  376. dev_err(aspi->dev, "CE%d invalid window [ 0x%.8x - 0x%.8x ] %dMB",
  377. win->cs, start, end - 1, win->size >> 20);
  378. writel(seg_val_backup, seg_reg);
  379. return -EIO;
  380. }
  381. if (win->size)
  382. dev_dbg(aspi->dev, "CE%d new window [ 0x%.8x - 0x%.8x ] %dMB",
  383. win->cs, start, end - 1, win->size >> 20);
  384. else
  385. dev_dbg(aspi->dev, "CE%d window closed", win->cs);
  386. return 0;
  387. }
  388. /*
  389. * Yet to be done when possible :
  390. * - Align mappings on flash size (we don't have the info)
  391. * - ioremap each window, not strictly necessary since the overall window
  392. * is correct.
  393. */
  394. static const struct aspeed_spi_data ast2500_spi_data;
  395. static const struct aspeed_spi_data ast2600_spi_data;
  396. static const struct aspeed_spi_data ast2600_fmc_data;
  397. static int aspeed_spi_chip_adjust_window(struct aspeed_spi_chip *chip,
  398. u32 local_offset, u32 size)
  399. {
  400. struct aspeed_spi *aspi = chip->aspi;
  401. struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS] = { 0 };
  402. struct aspeed_spi_window *win = &windows[chip->cs];
  403. int ret;
  404. /* No segment registers for the AST2400 SPI controller */
  405. if (aspi->data == &ast2400_spi_data)
  406. return 0;
  407. /*
  408. * Due to an HW issue on the AST2500 SPI controller, the CE0
  409. * window size should be smaller than the maximum 128MB.
  410. */
  411. if (aspi->data == &ast2500_spi_data && chip->cs == 0 && size == SZ_128M) {
  412. size = 120 << 20;
  413. dev_info(aspi->dev, "CE%d window resized to %dMB (AST2500 HW quirk)",
  414. chip->cs, size >> 20);
  415. }
  416. /*
  417. * The decoding size of AST2600 SPI controller should set at
  418. * least 2MB.
  419. */
  420. if ((aspi->data == &ast2600_spi_data || aspi->data == &ast2600_fmc_data) &&
  421. size < SZ_2M) {
  422. size = SZ_2M;
  423. dev_info(aspi->dev, "CE%d window resized to %dMB (AST2600 Decoding)",
  424. chip->cs, size >> 20);
  425. }
  426. aspeed_spi_get_windows(aspi, windows);
  427. /* Adjust this chip window */
  428. win->offset += local_offset;
  429. win->size = size;
  430. if (win->offset + win->size > aspi->ahb_window_size) {
  431. win->size = aspi->ahb_window_size - win->offset;
  432. dev_warn(aspi->dev, "CE%d window resized to %dMB", chip->cs, win->size >> 20);
  433. }
  434. ret = aspeed_spi_set_window(aspi, win);
  435. if (ret)
  436. return ret;
  437. /* Update chip mapping info */
  438. chip->ahb_base = aspi->ahb_base + win->offset;
  439. chip->ahb_window_size = win->size;
  440. /*
  441. * Also adjust next chip window to make sure that it does not
  442. * overlap with the current window.
  443. */
  444. if (chip->cs < aspi->data->max_cs - 1) {
  445. struct aspeed_spi_window *next = &windows[chip->cs + 1];
  446. /* Change offset and size to keep the same end address */
  447. if ((next->offset + next->size) > (win->offset + win->size))
  448. next->size = (next->offset + next->size) - (win->offset + win->size);
  449. else
  450. next->size = 0;
  451. next->offset = win->offset + win->size;
  452. aspeed_spi_set_window(aspi, next);
  453. }
  454. return 0;
  455. }
  456. static int aspeed_spi_do_calibration(struct aspeed_spi_chip *chip);
  457. static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
  458. {
  459. struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
  460. struct aspeed_spi_chip *chip = &aspi->chips[desc->mem->spi->chip_select];
  461. struct spi_mem_op *op = &desc->info.op_tmpl;
  462. u32 ctl_val;
  463. int ret = 0;
  464. dev_dbg(aspi->dev,
  465. "CE%d %s dirmap [ 0x%.8llx - 0x%.8llx ] OP %#x mode:%d.%d.%d.%d naddr:%#x ndummies:%#x\n",
  466. chip->cs, op->data.dir == SPI_MEM_DATA_IN ? "read" : "write",
  467. desc->info.offset, desc->info.offset + desc->info.length,
  468. op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
  469. op->dummy.buswidth, op->data.buswidth,
  470. op->addr.nbytes, op->dummy.nbytes);
  471. chip->clk_freq = desc->mem->spi->max_speed_hz;
  472. /* Only for reads */
  473. if (op->data.dir != SPI_MEM_DATA_IN)
  474. return -EOPNOTSUPP;
  475. aspeed_spi_chip_adjust_window(chip, desc->info.offset, desc->info.length);
  476. if (desc->info.length > chip->ahb_window_size)
  477. dev_warn(aspi->dev, "CE%d window (%dMB) too small for mapping",
  478. chip->cs, chip->ahb_window_size >> 20);
  479. /* Define the default IO read settings */
  480. ctl_val = readl(chip->ctl) & ~CTRL_IO_CMD_MASK;
  481. ctl_val |= aspeed_spi_get_io_mode(op) |
  482. op->cmd.opcode << CTRL_COMMAND_SHIFT |
  483. CTRL_IO_MODE_READ;
  484. if (op->dummy.nbytes)
  485. ctl_val |= CTRL_IO_DUMMY_SET(op->dummy.nbytes / op->dummy.buswidth);
  486. /* Tune 4BYTE address mode */
  487. if (op->addr.nbytes) {
  488. u32 addr_mode = readl(aspi->regs + CE_CTRL_REG);
  489. if (op->addr.nbytes == 4)
  490. addr_mode |= (0x11 << chip->cs);
  491. else
  492. addr_mode &= ~(0x11 << chip->cs);
  493. writel(addr_mode, aspi->regs + CE_CTRL_REG);
  494. /* AST2400 SPI controller sets 4BYTE address mode in
  495. * CE0 Control Register
  496. */
  497. if (op->addr.nbytes == 4 && chip->aspi->data == &ast2400_spi_data)
  498. ctl_val |= CTRL_IO_ADDRESS_4B;
  499. }
  500. /* READ mode is the controller default setting */
  501. chip->ctl_val[ASPEED_SPI_READ] = ctl_val;
  502. writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
  503. ret = aspeed_spi_do_calibration(chip);
  504. dev_info(aspi->dev, "CE%d read buswidth:%d [0x%08x]\n",
  505. chip->cs, op->data.buswidth, chip->ctl_val[ASPEED_SPI_READ]);
  506. return ret;
  507. }
  508. static ssize_t aspeed_spi_dirmap_read(struct spi_mem_dirmap_desc *desc,
  509. u64 offset, size_t len, void *buf)
  510. {
  511. struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
  512. struct aspeed_spi_chip *chip = &aspi->chips[desc->mem->spi->chip_select];
  513. /* Switch to USER command mode if mapping window is too small */
  514. if (chip->ahb_window_size < offset + len) {
  515. int ret;
  516. ret = aspeed_spi_read_user(chip, &desc->info.op_tmpl, offset, len, buf);
  517. if (ret < 0)
  518. return ret;
  519. } else {
  520. memcpy_fromio(buf, chip->ahb_base + offset, len);
  521. }
  522. return len;
  523. }
  524. static const struct spi_controller_mem_ops aspeed_spi_mem_ops = {
  525. .supports_op = aspeed_spi_supports_op,
  526. .exec_op = aspeed_spi_exec_op,
  527. .get_name = aspeed_spi_get_name,
  528. .dirmap_create = aspeed_spi_dirmap_create,
  529. .dirmap_read = aspeed_spi_dirmap_read,
  530. };
  531. static void aspeed_spi_chip_set_type(struct aspeed_spi *aspi, unsigned int cs, int type)
  532. {
  533. u32 reg;
  534. reg = readl(aspi->regs + CONFIG_REG);
  535. reg &= ~(0x3 << (cs * 2));
  536. reg |= type << (cs * 2);
  537. writel(reg, aspi->regs + CONFIG_REG);
  538. }
  539. static void aspeed_spi_chip_enable(struct aspeed_spi *aspi, unsigned int cs, bool enable)
  540. {
  541. u32 we_bit = BIT(aspi->data->we0 + cs);
  542. u32 reg = readl(aspi->regs + CONFIG_REG);
  543. if (enable)
  544. reg |= we_bit;
  545. else
  546. reg &= ~we_bit;
  547. writel(reg, aspi->regs + CONFIG_REG);
  548. }
  549. static int aspeed_spi_setup(struct spi_device *spi)
  550. {
  551. struct aspeed_spi *aspi = spi_controller_get_devdata(spi->master);
  552. const struct aspeed_spi_data *data = aspi->data;
  553. unsigned int cs = spi->chip_select;
  554. struct aspeed_spi_chip *chip = &aspi->chips[cs];
  555. chip->aspi = aspi;
  556. chip->cs = cs;
  557. chip->ctl = aspi->regs + data->ctl0 + cs * 4;
  558. /* The driver only supports SPI type flash */
  559. if (data->hastype)
  560. aspeed_spi_chip_set_type(aspi, cs, CONFIG_TYPE_SPI);
  561. if (aspeed_spi_chip_set_default_window(chip) < 0) {
  562. dev_warn(aspi->dev, "CE%d window invalid", cs);
  563. return -EINVAL;
  564. }
  565. aspeed_spi_chip_enable(aspi, cs, true);
  566. chip->ctl_val[ASPEED_SPI_BASE] = CTRL_CE_STOP_ACTIVE | CTRL_IO_MODE_USER;
  567. dev_dbg(aspi->dev, "CE%d setup done\n", cs);
  568. return 0;
  569. }
  570. static void aspeed_spi_cleanup(struct spi_device *spi)
  571. {
  572. struct aspeed_spi *aspi = spi_controller_get_devdata(spi->master);
  573. unsigned int cs = spi->chip_select;
  574. aspeed_spi_chip_enable(aspi, cs, false);
  575. dev_dbg(aspi->dev, "CE%d cleanup done\n", cs);
  576. }
  577. static void aspeed_spi_enable(struct aspeed_spi *aspi, bool enable)
  578. {
  579. int cs;
  580. for (cs = 0; cs < aspi->data->max_cs; cs++)
  581. aspeed_spi_chip_enable(aspi, cs, enable);
  582. }
  583. static int aspeed_spi_probe(struct platform_device *pdev)
  584. {
  585. struct device *dev = &pdev->dev;
  586. const struct aspeed_spi_data *data;
  587. struct spi_controller *ctlr;
  588. struct aspeed_spi *aspi;
  589. struct resource *res;
  590. int ret;
  591. data = of_device_get_match_data(&pdev->dev);
  592. if (!data)
  593. return -ENODEV;
  594. ctlr = devm_spi_alloc_master(dev, sizeof(*aspi));
  595. if (!ctlr)
  596. return -ENOMEM;
  597. aspi = spi_controller_get_devdata(ctlr);
  598. platform_set_drvdata(pdev, aspi);
  599. aspi->data = data;
  600. aspi->dev = dev;
  601. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  602. aspi->regs = devm_ioremap_resource(dev, res);
  603. if (IS_ERR(aspi->regs))
  604. return PTR_ERR(aspi->regs);
  605. res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  606. aspi->ahb_base = devm_ioremap_resource(dev, res);
  607. if (IS_ERR(aspi->ahb_base)) {
  608. dev_err(dev, "missing AHB mapping window\n");
  609. return PTR_ERR(aspi->ahb_base);
  610. }
  611. aspi->ahb_window_size = resource_size(res);
  612. aspi->ahb_base_phy = res->start;
  613. aspi->clk = devm_clk_get(&pdev->dev, NULL);
  614. if (IS_ERR(aspi->clk)) {
  615. dev_err(dev, "missing clock\n");
  616. return PTR_ERR(aspi->clk);
  617. }
  618. aspi->clk_freq = clk_get_rate(aspi->clk);
  619. if (!aspi->clk_freq) {
  620. dev_err(dev, "invalid clock\n");
  621. return -EINVAL;
  622. }
  623. ret = clk_prepare_enable(aspi->clk);
  624. if (ret) {
  625. dev_err(dev, "can not enable the clock\n");
  626. return ret;
  627. }
  628. /* IRQ is for DMA, which the driver doesn't support yet */
  629. ctlr->mode_bits = SPI_RX_DUAL | SPI_TX_DUAL | data->mode_bits;
  630. ctlr->bus_num = pdev->id;
  631. ctlr->mem_ops = &aspeed_spi_mem_ops;
  632. ctlr->setup = aspeed_spi_setup;
  633. ctlr->cleanup = aspeed_spi_cleanup;
  634. ctlr->num_chipselect = data->max_cs;
  635. ctlr->dev.of_node = dev->of_node;
  636. ret = devm_spi_register_controller(dev, ctlr);
  637. if (ret) {
  638. dev_err(&pdev->dev, "spi_register_controller failed\n");
  639. goto disable_clk;
  640. }
  641. return 0;
  642. disable_clk:
  643. clk_disable_unprepare(aspi->clk);
  644. return ret;
  645. }
  646. static int aspeed_spi_remove(struct platform_device *pdev)
  647. {
  648. struct aspeed_spi *aspi = platform_get_drvdata(pdev);
  649. aspeed_spi_enable(aspi, false);
  650. clk_disable_unprepare(aspi->clk);
  651. return 0;
  652. }
  653. /*
  654. * AHB mappings
  655. */
  656. /*
  657. * The Segment Registers of the AST2400 and AST2500 use a 8MB unit.
  658. * The address range is encoded with absolute addresses in the overall
  659. * mapping window.
  660. */
  661. static u32 aspeed_spi_segment_start(struct aspeed_spi *aspi, u32 reg)
  662. {
  663. return ((reg >> 16) & 0xFF) << 23;
  664. }
  665. static u32 aspeed_spi_segment_end(struct aspeed_spi *aspi, u32 reg)
  666. {
  667. return ((reg >> 24) & 0xFF) << 23;
  668. }
  669. static u32 aspeed_spi_segment_reg(struct aspeed_spi *aspi, u32 start, u32 end)
  670. {
  671. return (((start >> 23) & 0xFF) << 16) | (((end >> 23) & 0xFF) << 24);
  672. }
  673. /*
  674. * The Segment Registers of the AST2600 use a 1MB unit. The address
  675. * range is encoded with offsets in the overall mapping window.
  676. */
  677. #define AST2600_SEG_ADDR_MASK 0x0ff00000
  678. static u32 aspeed_spi_segment_ast2600_start(struct aspeed_spi *aspi,
  679. u32 reg)
  680. {
  681. u32 start_offset = (reg << 16) & AST2600_SEG_ADDR_MASK;
  682. return aspi->ahb_base_phy + start_offset;
  683. }
  684. static u32 aspeed_spi_segment_ast2600_end(struct aspeed_spi *aspi,
  685. u32 reg)
  686. {
  687. u32 end_offset = reg & AST2600_SEG_ADDR_MASK;
  688. /* segment is disabled */
  689. if (!end_offset)
  690. return aspi->ahb_base_phy;
  691. return aspi->ahb_base_phy + end_offset + 0x100000;
  692. }
  693. static u32 aspeed_spi_segment_ast2600_reg(struct aspeed_spi *aspi,
  694. u32 start, u32 end)
  695. {
  696. /* disable zero size segments */
  697. if (start == end)
  698. return 0;
  699. return ((start & AST2600_SEG_ADDR_MASK) >> 16) |
  700. ((end - 1) & AST2600_SEG_ADDR_MASK);
  701. }
  702. /*
  703. * Read timing compensation sequences
  704. */
  705. #define CALIBRATE_BUF_SIZE SZ_16K
  706. static bool aspeed_spi_check_reads(struct aspeed_spi_chip *chip,
  707. const u8 *golden_buf, u8 *test_buf)
  708. {
  709. int i;
  710. for (i = 0; i < 10; i++) {
  711. memcpy_fromio(test_buf, chip->ahb_base, CALIBRATE_BUF_SIZE);
  712. if (memcmp(test_buf, golden_buf, CALIBRATE_BUF_SIZE) != 0) {
  713. #if defined(VERBOSE_DEBUG)
  714. print_hex_dump_bytes(DEVICE_NAME " fail: ", DUMP_PREFIX_NONE,
  715. test_buf, 0x100);
  716. #endif
  717. return false;
  718. }
  719. }
  720. return true;
  721. }
  722. #define FREAD_TPASS(i) (((i) / 2) | (((i) & 1) ? 0 : 8))
  723. /*
  724. * The timing register is shared by all devices. Only update for CE0.
  725. */
  726. static int aspeed_spi_calibrate(struct aspeed_spi_chip *chip, u32 hdiv,
  727. const u8 *golden_buf, u8 *test_buf)
  728. {
  729. struct aspeed_spi *aspi = chip->aspi;
  730. const struct aspeed_spi_data *data = aspi->data;
  731. int i;
  732. int good_pass = -1, pass_count = 0;
  733. u32 shift = (hdiv - 1) << 2;
  734. u32 mask = ~(0xfu << shift);
  735. u32 fread_timing_val = 0;
  736. /* Try HCLK delay 0..5, each one with/without delay and look for a
  737. * good pair.
  738. */
  739. for (i = 0; i < 12; i++) {
  740. bool pass;
  741. if (chip->cs == 0) {
  742. fread_timing_val &= mask;
  743. fread_timing_val |= FREAD_TPASS(i) << shift;
  744. writel(fread_timing_val, aspi->regs + data->timing);
  745. }
  746. pass = aspeed_spi_check_reads(chip, golden_buf, test_buf);
  747. dev_dbg(aspi->dev,
  748. " * [%08x] %d HCLK delay, %dns DI delay : %s",
  749. fread_timing_val, i / 2, (i & 1) ? 0 : 4,
  750. pass ? "PASS" : "FAIL");
  751. if (pass) {
  752. pass_count++;
  753. if (pass_count == 3) {
  754. good_pass = i - 1;
  755. break;
  756. }
  757. } else {
  758. pass_count = 0;
  759. }
  760. }
  761. /* No good setting for this frequency */
  762. if (good_pass < 0)
  763. return -1;
  764. /* We have at least one pass of margin, let's use first pass */
  765. if (chip->cs == 0) {
  766. fread_timing_val &= mask;
  767. fread_timing_val |= FREAD_TPASS(good_pass) << shift;
  768. writel(fread_timing_val, aspi->regs + data->timing);
  769. }
  770. dev_dbg(aspi->dev, " * -> good is pass %d [0x%08x]",
  771. good_pass, fread_timing_val);
  772. return 0;
  773. }
  774. static bool aspeed_spi_check_calib_data(const u8 *test_buf, u32 size)
  775. {
  776. const u32 *tb32 = (const u32 *)test_buf;
  777. u32 i, cnt = 0;
  778. /* We check if we have enough words that are neither all 0
  779. * nor all 1's so the calibration can be considered valid.
  780. *
  781. * I use an arbitrary threshold for now of 64
  782. */
  783. size >>= 2;
  784. for (i = 0; i < size; i++) {
  785. if (tb32[i] != 0 && tb32[i] != 0xffffffff)
  786. cnt++;
  787. }
  788. return cnt >= 64;
  789. }
  790. static const u32 aspeed_spi_hclk_divs[] = {
  791. 0xf, /* HCLK */
  792. 0x7, /* HCLK/2 */
  793. 0xe, /* HCLK/3 */
  794. 0x6, /* HCLK/4 */
  795. 0xd, /* HCLK/5 */
  796. };
  797. #define ASPEED_SPI_HCLK_DIV(i) \
  798. (aspeed_spi_hclk_divs[(i) - 1] << CTRL_FREQ_SEL_SHIFT)
  799. static int aspeed_spi_do_calibration(struct aspeed_spi_chip *chip)
  800. {
  801. struct aspeed_spi *aspi = chip->aspi;
  802. const struct aspeed_spi_data *data = aspi->data;
  803. u32 ahb_freq = aspi->clk_freq;
  804. u32 max_freq = chip->clk_freq;
  805. u32 ctl_val;
  806. u8 *golden_buf = NULL;
  807. u8 *test_buf = NULL;
  808. int i, rc, best_div = -1;
  809. dev_dbg(aspi->dev, "calculate timing compensation - AHB freq: %d MHz",
  810. ahb_freq / 1000000);
  811. /*
  812. * use the related low frequency to get check calibration data
  813. * and get golden data.
  814. */
  815. ctl_val = chip->ctl_val[ASPEED_SPI_READ] & data->hclk_mask;
  816. writel(ctl_val, chip->ctl);
  817. test_buf = kzalloc(CALIBRATE_BUF_SIZE * 2, GFP_KERNEL);
  818. if (!test_buf)
  819. return -ENOMEM;
  820. golden_buf = test_buf + CALIBRATE_BUF_SIZE;
  821. memcpy_fromio(golden_buf, chip->ahb_base, CALIBRATE_BUF_SIZE);
  822. if (!aspeed_spi_check_calib_data(golden_buf, CALIBRATE_BUF_SIZE)) {
  823. dev_info(aspi->dev, "Calibration area too uniform, using low speed");
  824. goto no_calib;
  825. }
  826. #if defined(VERBOSE_DEBUG)
  827. print_hex_dump_bytes(DEVICE_NAME " good: ", DUMP_PREFIX_NONE,
  828. golden_buf, 0x100);
  829. #endif
  830. /* Now we iterate the HCLK dividers until we find our breaking point */
  831. for (i = ARRAY_SIZE(aspeed_spi_hclk_divs); i > data->hdiv_max - 1; i--) {
  832. u32 tv, freq;
  833. freq = ahb_freq / i;
  834. if (freq > max_freq)
  835. continue;
  836. /* Set the timing */
  837. tv = chip->ctl_val[ASPEED_SPI_READ] | ASPEED_SPI_HCLK_DIV(i);
  838. writel(tv, chip->ctl);
  839. dev_dbg(aspi->dev, "Trying HCLK/%d [%08x] ...", i, tv);
  840. rc = data->calibrate(chip, i, golden_buf, test_buf);
  841. if (rc == 0)
  842. best_div = i;
  843. }
  844. /* Nothing found ? */
  845. if (best_div < 0) {
  846. dev_warn(aspi->dev, "No good frequency, using dumb slow");
  847. } else {
  848. dev_dbg(aspi->dev, "Found good read timings at HCLK/%d", best_div);
  849. /* Record the freq */
  850. for (i = 0; i < ASPEED_SPI_MAX; i++)
  851. chip->ctl_val[i] = (chip->ctl_val[i] & data->hclk_mask) |
  852. ASPEED_SPI_HCLK_DIV(best_div);
  853. }
  854. no_calib:
  855. writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
  856. kfree(test_buf);
  857. return 0;
  858. }
  859. #define TIMING_DELAY_DI BIT(3)
  860. #define TIMING_DELAY_HCYCLE_MAX 5
  861. #define TIMING_REG_AST2600(chip) \
  862. ((chip)->aspi->regs + (chip)->aspi->data->timing + \
  863. (chip)->cs * 4)
  864. static int aspeed_spi_ast2600_calibrate(struct aspeed_spi_chip *chip, u32 hdiv,
  865. const u8 *golden_buf, u8 *test_buf)
  866. {
  867. struct aspeed_spi *aspi = chip->aspi;
  868. int hcycle;
  869. u32 shift = (hdiv - 2) << 3;
  870. u32 mask = ~(0xfu << shift);
  871. u32 fread_timing_val = 0;
  872. for (hcycle = 0; hcycle <= TIMING_DELAY_HCYCLE_MAX; hcycle++) {
  873. int delay_ns;
  874. bool pass = false;
  875. fread_timing_val &= mask;
  876. fread_timing_val |= hcycle << shift;
  877. /* no DI input delay first */
  878. writel(fread_timing_val, TIMING_REG_AST2600(chip));
  879. pass = aspeed_spi_check_reads(chip, golden_buf, test_buf);
  880. dev_dbg(aspi->dev,
  881. " * [%08x] %d HCLK delay, DI delay none : %s",
  882. fread_timing_val, hcycle, pass ? "PASS" : "FAIL");
  883. if (pass)
  884. return 0;
  885. /* Add DI input delays */
  886. fread_timing_val &= mask;
  887. fread_timing_val |= (TIMING_DELAY_DI | hcycle) << shift;
  888. for (delay_ns = 0; delay_ns < 0x10; delay_ns++) {
  889. fread_timing_val &= ~(0xf << (4 + shift));
  890. fread_timing_val |= delay_ns << (4 + shift);
  891. writel(fread_timing_val, TIMING_REG_AST2600(chip));
  892. pass = aspeed_spi_check_reads(chip, golden_buf, test_buf);
  893. dev_dbg(aspi->dev,
  894. " * [%08x] %d HCLK delay, DI delay %d.%dns : %s",
  895. fread_timing_val, hcycle, (delay_ns + 1) / 2,
  896. (delay_ns + 1) & 1 ? 5 : 5, pass ? "PASS" : "FAIL");
  897. /*
  898. * TODO: This is optimistic. We should look
  899. * for a working interval and save the middle
  900. * value in the read timing register.
  901. */
  902. if (pass)
  903. return 0;
  904. }
  905. }
  906. /* No good setting for this frequency */
  907. return -1;
  908. }
  909. /*
  910. * Platform definitions
  911. */
  912. static const struct aspeed_spi_data ast2400_fmc_data = {
  913. .max_cs = 5,
  914. .hastype = true,
  915. .we0 = 16,
  916. .ctl0 = CE0_CTRL_REG,
  917. .timing = CE0_TIMING_COMPENSATION_REG,
  918. .hclk_mask = 0xfffff0ff,
  919. .hdiv_max = 1,
  920. .calibrate = aspeed_spi_calibrate,
  921. .segment_start = aspeed_spi_segment_start,
  922. .segment_end = aspeed_spi_segment_end,
  923. .segment_reg = aspeed_spi_segment_reg,
  924. };
  925. static const struct aspeed_spi_data ast2400_spi_data = {
  926. .max_cs = 1,
  927. .hastype = false,
  928. .we0 = 0,
  929. .ctl0 = 0x04,
  930. .timing = 0x14,
  931. .hclk_mask = 0xfffff0ff,
  932. .hdiv_max = 1,
  933. .calibrate = aspeed_spi_calibrate,
  934. /* No segment registers */
  935. };
  936. static const struct aspeed_spi_data ast2500_fmc_data = {
  937. .max_cs = 3,
  938. .hastype = true,
  939. .we0 = 16,
  940. .ctl0 = CE0_CTRL_REG,
  941. .timing = CE0_TIMING_COMPENSATION_REG,
  942. .hclk_mask = 0xffffd0ff,
  943. .hdiv_max = 1,
  944. .calibrate = aspeed_spi_calibrate,
  945. .segment_start = aspeed_spi_segment_start,
  946. .segment_end = aspeed_spi_segment_end,
  947. .segment_reg = aspeed_spi_segment_reg,
  948. };
  949. static const struct aspeed_spi_data ast2500_spi_data = {
  950. .max_cs = 2,
  951. .hastype = false,
  952. .we0 = 16,
  953. .ctl0 = CE0_CTRL_REG,
  954. .timing = CE0_TIMING_COMPENSATION_REG,
  955. .hclk_mask = 0xffffd0ff,
  956. .hdiv_max = 1,
  957. .calibrate = aspeed_spi_calibrate,
  958. .segment_start = aspeed_spi_segment_start,
  959. .segment_end = aspeed_spi_segment_end,
  960. .segment_reg = aspeed_spi_segment_reg,
  961. };
  962. static const struct aspeed_spi_data ast2600_fmc_data = {
  963. .max_cs = 3,
  964. .hastype = false,
  965. .mode_bits = SPI_RX_QUAD | SPI_TX_QUAD,
  966. .we0 = 16,
  967. .ctl0 = CE0_CTRL_REG,
  968. .timing = CE0_TIMING_COMPENSATION_REG,
  969. .hclk_mask = 0xf0fff0ff,
  970. .hdiv_max = 2,
  971. .calibrate = aspeed_spi_ast2600_calibrate,
  972. .segment_start = aspeed_spi_segment_ast2600_start,
  973. .segment_end = aspeed_spi_segment_ast2600_end,
  974. .segment_reg = aspeed_spi_segment_ast2600_reg,
  975. };
  976. static const struct aspeed_spi_data ast2600_spi_data = {
  977. .max_cs = 2,
  978. .hastype = false,
  979. .mode_bits = SPI_RX_QUAD | SPI_TX_QUAD,
  980. .we0 = 16,
  981. .ctl0 = CE0_CTRL_REG,
  982. .timing = CE0_TIMING_COMPENSATION_REG,
  983. .hclk_mask = 0xf0fff0ff,
  984. .hdiv_max = 2,
  985. .calibrate = aspeed_spi_ast2600_calibrate,
  986. .segment_start = aspeed_spi_segment_ast2600_start,
  987. .segment_end = aspeed_spi_segment_ast2600_end,
  988. .segment_reg = aspeed_spi_segment_ast2600_reg,
  989. };
  990. static const struct of_device_id aspeed_spi_matches[] = {
  991. { .compatible = "aspeed,ast2400-fmc", .data = &ast2400_fmc_data },
  992. { .compatible = "aspeed,ast2400-spi", .data = &ast2400_spi_data },
  993. { .compatible = "aspeed,ast2500-fmc", .data = &ast2500_fmc_data },
  994. { .compatible = "aspeed,ast2500-spi", .data = &ast2500_spi_data },
  995. { .compatible = "aspeed,ast2600-fmc", .data = &ast2600_fmc_data },
  996. { .compatible = "aspeed,ast2600-spi", .data = &ast2600_spi_data },
  997. { }
  998. };
  999. MODULE_DEVICE_TABLE(of, aspeed_spi_matches);
  1000. static struct platform_driver aspeed_spi_driver = {
  1001. .probe = aspeed_spi_probe,
  1002. .remove = aspeed_spi_remove,
  1003. .driver = {
  1004. .name = DEVICE_NAME,
  1005. .of_match_table = aspeed_spi_matches,
  1006. }
  1007. };
  1008. module_platform_driver(aspeed_spi_driver);
  1009. MODULE_DESCRIPTION("ASPEED Static Memory Controller Driver");
  1010. MODULE_AUTHOR("Chin-Ting Kuo <[email protected]>");
  1011. MODULE_AUTHOR("Cedric Le Goater <[email protected]>");
  1012. MODULE_LICENSE("GPL v2");