spi-ar934x.c 6.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // SPI controller driver for Qualcomm Atheros AR934x/QCA95xx SoCs
  4. //
  5. // Copyright (C) 2020 Chuanhong Guo <[email protected]>
  6. //
  7. // Based on spi-mt7621.c:
  8. // Copyright (C) 2011 Sergiy <[email protected]>
  9. // Copyright (C) 2011-2013 Gabor Juhos <[email protected]>
  10. // Copyright (C) 2014-2015 Felix Fietkau <[email protected]>
  11. #include <linux/clk.h>
  12. #include <linux/io.h>
  13. #include <linux/iopoll.h>
  14. #include <linux/kernel.h>
  15. #include <linux/module.h>
  16. #include <linux/of_device.h>
  17. #include <linux/spi/spi.h>
  18. #define DRIVER_NAME "spi-ar934x"
  19. #define AR934X_SPI_REG_FS 0x00
  20. #define AR934X_SPI_ENABLE BIT(0)
  21. #define AR934X_SPI_REG_IOC 0x08
  22. #define AR934X_SPI_IOC_INITVAL 0x70000
  23. #define AR934X_SPI_REG_CTRL 0x04
  24. #define AR934X_SPI_CLK_MASK GENMASK(5, 0)
  25. #define AR934X_SPI_DATAOUT 0x10
  26. #define AR934X_SPI_REG_SHIFT_CTRL 0x14
  27. #define AR934X_SPI_SHIFT_EN BIT(31)
  28. #define AR934X_SPI_SHIFT_CS(n) BIT(28 + (n))
  29. #define AR934X_SPI_SHIFT_TERM 26
  30. #define AR934X_SPI_SHIFT_VAL(cs, term, count) \
  31. (AR934X_SPI_SHIFT_EN | AR934X_SPI_SHIFT_CS(cs) | \
  32. (term) << AR934X_SPI_SHIFT_TERM | (count))
  33. #define AR934X_SPI_DATAIN 0x18
  34. struct ar934x_spi {
  35. struct spi_controller *ctlr;
  36. void __iomem *base;
  37. struct clk *clk;
  38. unsigned int clk_freq;
  39. };
  40. static inline int ar934x_spi_clk_div(struct ar934x_spi *sp, unsigned int freq)
  41. {
  42. int div = DIV_ROUND_UP(sp->clk_freq, freq * 2) - 1;
  43. if (div < 0)
  44. return 0;
  45. else if (div > AR934X_SPI_CLK_MASK)
  46. return -EINVAL;
  47. else
  48. return div;
  49. }
  50. static int ar934x_spi_setup(struct spi_device *spi)
  51. {
  52. struct ar934x_spi *sp = spi_controller_get_devdata(spi->master);
  53. if ((spi->max_speed_hz == 0) ||
  54. (spi->max_speed_hz > (sp->clk_freq / 2))) {
  55. spi->max_speed_hz = sp->clk_freq / 2;
  56. } else if (spi->max_speed_hz < (sp->clk_freq / 128)) {
  57. dev_err(&spi->dev, "spi clock is too low\n");
  58. return -EINVAL;
  59. }
  60. return 0;
  61. }
  62. static int ar934x_spi_transfer_one_message(struct spi_controller *master,
  63. struct spi_message *m)
  64. {
  65. struct ar934x_spi *sp = spi_controller_get_devdata(master);
  66. struct spi_transfer *t = NULL;
  67. struct spi_device *spi = m->spi;
  68. unsigned long trx_done, trx_cur;
  69. int stat = 0;
  70. u8 bpw, term = 0;
  71. int div, i;
  72. u32 reg;
  73. const u8 *tx_buf;
  74. u8 *buf;
  75. m->actual_length = 0;
  76. list_for_each_entry(t, &m->transfers, transfer_list) {
  77. if (t->bits_per_word >= 8 && t->bits_per_word < 32)
  78. bpw = t->bits_per_word >> 3;
  79. else
  80. bpw = 4;
  81. if (t->speed_hz)
  82. div = ar934x_spi_clk_div(sp, t->speed_hz);
  83. else
  84. div = ar934x_spi_clk_div(sp, spi->max_speed_hz);
  85. if (div < 0) {
  86. stat = -EIO;
  87. goto msg_done;
  88. }
  89. reg = ioread32(sp->base + AR934X_SPI_REG_CTRL);
  90. reg &= ~AR934X_SPI_CLK_MASK;
  91. reg |= div;
  92. iowrite32(reg, sp->base + AR934X_SPI_REG_CTRL);
  93. iowrite32(0, sp->base + AR934X_SPI_DATAOUT);
  94. for (trx_done = 0; trx_done < t->len; trx_done += bpw) {
  95. trx_cur = t->len - trx_done;
  96. if (trx_cur > bpw)
  97. trx_cur = bpw;
  98. else if (list_is_last(&t->transfer_list, &m->transfers))
  99. term = 1;
  100. if (t->tx_buf) {
  101. tx_buf = t->tx_buf + trx_done;
  102. reg = tx_buf[0];
  103. for (i = 1; i < trx_cur; i++)
  104. reg = reg << 8 | tx_buf[i];
  105. iowrite32(reg, sp->base + AR934X_SPI_DATAOUT);
  106. }
  107. reg = AR934X_SPI_SHIFT_VAL(spi->chip_select, term,
  108. trx_cur * 8);
  109. iowrite32(reg, sp->base + AR934X_SPI_REG_SHIFT_CTRL);
  110. stat = readl_poll_timeout(
  111. sp->base + AR934X_SPI_REG_SHIFT_CTRL, reg,
  112. !(reg & AR934X_SPI_SHIFT_EN), 0, 5);
  113. if (stat < 0)
  114. goto msg_done;
  115. if (t->rx_buf) {
  116. reg = ioread32(sp->base + AR934X_SPI_DATAIN);
  117. buf = t->rx_buf + trx_done;
  118. for (i = 0; i < trx_cur; i++) {
  119. buf[trx_cur - i - 1] = reg & 0xff;
  120. reg >>= 8;
  121. }
  122. }
  123. spi_delay_exec(&t->word_delay, t);
  124. }
  125. m->actual_length += t->len;
  126. spi_transfer_delay_exec(t);
  127. }
  128. msg_done:
  129. m->status = stat;
  130. spi_finalize_current_message(master);
  131. return 0;
  132. }
  133. static const struct of_device_id ar934x_spi_match[] = {
  134. { .compatible = "qca,ar934x-spi" },
  135. {},
  136. };
  137. MODULE_DEVICE_TABLE(of, ar934x_spi_match);
  138. static int ar934x_spi_probe(struct platform_device *pdev)
  139. {
  140. struct spi_controller *ctlr;
  141. struct ar934x_spi *sp;
  142. void __iomem *base;
  143. struct clk *clk;
  144. int ret;
  145. base = devm_platform_ioremap_resource(pdev, 0);
  146. if (IS_ERR(base))
  147. return PTR_ERR(base);
  148. clk = devm_clk_get(&pdev->dev, NULL);
  149. if (IS_ERR(clk)) {
  150. dev_err(&pdev->dev, "failed to get clock\n");
  151. return PTR_ERR(clk);
  152. }
  153. ret = clk_prepare_enable(clk);
  154. if (ret)
  155. return ret;
  156. ctlr = devm_spi_alloc_master(&pdev->dev, sizeof(*sp));
  157. if (!ctlr) {
  158. dev_info(&pdev->dev, "failed to allocate spi controller\n");
  159. ret = -ENOMEM;
  160. goto err_clk_disable;
  161. }
  162. /* disable flash mapping and expose spi controller registers */
  163. iowrite32(AR934X_SPI_ENABLE, base + AR934X_SPI_REG_FS);
  164. /* restore pins to default state: CSn=1 DO=CLK=0 */
  165. iowrite32(AR934X_SPI_IOC_INITVAL, base + AR934X_SPI_REG_IOC);
  166. ctlr->mode_bits = SPI_LSB_FIRST;
  167. ctlr->setup = ar934x_spi_setup;
  168. ctlr->transfer_one_message = ar934x_spi_transfer_one_message;
  169. ctlr->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(24) |
  170. SPI_BPW_MASK(16) | SPI_BPW_MASK(8);
  171. ctlr->dev.of_node = pdev->dev.of_node;
  172. ctlr->num_chipselect = 3;
  173. dev_set_drvdata(&pdev->dev, ctlr);
  174. sp = spi_controller_get_devdata(ctlr);
  175. sp->base = base;
  176. sp->clk = clk;
  177. sp->clk_freq = clk_get_rate(clk);
  178. sp->ctlr = ctlr;
  179. ret = spi_register_controller(ctlr);
  180. if (!ret)
  181. return 0;
  182. err_clk_disable:
  183. clk_disable_unprepare(clk);
  184. return ret;
  185. }
  186. static int ar934x_spi_remove(struct platform_device *pdev)
  187. {
  188. struct spi_controller *ctlr;
  189. struct ar934x_spi *sp;
  190. ctlr = dev_get_drvdata(&pdev->dev);
  191. sp = spi_controller_get_devdata(ctlr);
  192. spi_unregister_controller(ctlr);
  193. clk_disable_unprepare(sp->clk);
  194. return 0;
  195. }
  196. static struct platform_driver ar934x_spi_driver = {
  197. .driver = {
  198. .name = DRIVER_NAME,
  199. .of_match_table = ar934x_spi_match,
  200. },
  201. .probe = ar934x_spi_probe,
  202. .remove = ar934x_spi_remove,
  203. };
  204. module_platform_driver(ar934x_spi_driver);
  205. MODULE_DESCRIPTION("SPI controller driver for Qualcomm Atheros AR934x/QCA95xx");
  206. MODULE_AUTHOR("Chuanhong Guo <[email protected]>");
  207. MODULE_LICENSE("GPL v2");
  208. MODULE_ALIAS("platform:" DRIVER_NAME);