Kconfig 4.7 KB

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  1. # SPDX-License-Identifier: GPL-2.0-only
  2. if ARCH_TEGRA
  3. # 32-bit ARM SoCs
  4. if ARM
  5. config ARCH_TEGRA_2x_SOC
  6. bool "Enable support for Tegra20 family"
  7. select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
  8. select ARM_ERRATA_720789
  9. select ARM_ERRATA_754327 if SMP
  10. select ARM_ERRATA_764369 if SMP
  11. select PINCTRL_TEGRA20
  12. select PL310_ERRATA_727915 if CACHE_L2X0
  13. select PL310_ERRATA_769419 if CACHE_L2X0
  14. select SOC_TEGRA_FLOWCTRL
  15. select SOC_TEGRA_PMC
  16. select SOC_TEGRA20_VOLTAGE_COUPLER if REGULATOR
  17. select TEGRA_TIMER
  18. help
  19. Support for NVIDIA Tegra AP20 and T20 processors, based on the
  20. ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
  21. config ARCH_TEGRA_3x_SOC
  22. bool "Enable support for Tegra30 family"
  23. select ARM_ERRATA_754322
  24. select ARM_ERRATA_764369 if SMP
  25. select PINCTRL_TEGRA30
  26. select PL310_ERRATA_769419 if CACHE_L2X0
  27. select SOC_TEGRA_FLOWCTRL
  28. select SOC_TEGRA_PMC
  29. select SOC_TEGRA30_VOLTAGE_COUPLER if REGULATOR
  30. select TEGRA_TIMER
  31. help
  32. Support for NVIDIA Tegra T30 processor family, based on the
  33. ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
  34. config ARCH_TEGRA_114_SOC
  35. bool "Enable support for Tegra114 family"
  36. select ARM_ERRATA_798181 if SMP
  37. select HAVE_ARM_ARCH_TIMER
  38. select PINCTRL_TEGRA114
  39. select SOC_TEGRA_FLOWCTRL
  40. select SOC_TEGRA_PMC
  41. select TEGRA_TIMER
  42. help
  43. Support for NVIDIA Tegra T114 processor family, based on the
  44. ARM CortexA15MP CPU
  45. config ARCH_TEGRA_124_SOC
  46. bool "Enable support for Tegra124 family"
  47. select HAVE_ARM_ARCH_TIMER
  48. select PINCTRL_TEGRA124
  49. select SOC_TEGRA_FLOWCTRL
  50. select SOC_TEGRA_PMC
  51. select TEGRA_TIMER
  52. help
  53. Support for NVIDIA Tegra T124 processor family, based on the
  54. ARM CortexA15MP CPU
  55. endif
  56. # 64-bit ARM SoCs
  57. if ARM64
  58. config ARCH_TEGRA_132_SOC
  59. bool "NVIDIA Tegra132 SoC"
  60. select PINCTRL_TEGRA124
  61. select SOC_TEGRA_FLOWCTRL
  62. select SOC_TEGRA_PMC
  63. help
  64. Enable support for NVIDIA Tegra132 SoC, based on the Denver
  65. ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
  66. but contains an NVIDIA Denver CPU complex in place of
  67. Tegra124's "4+1" Cortex-A15 CPU complex.
  68. config ARCH_TEGRA_210_SOC
  69. bool "NVIDIA Tegra210 SoC"
  70. select PINCTRL_TEGRA210
  71. select SOC_TEGRA_FLOWCTRL
  72. select SOC_TEGRA_PMC
  73. select TEGRA_TIMER
  74. help
  75. Enable support for the NVIDIA Tegra210 SoC. Also known as Tegra X1,
  76. the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53
  77. cores in a switched configuration. It features a GPU of the Maxwell
  78. architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1
  79. and providing 256 CUDA cores. It supports hardware-accelerated en-
  80. and decoding of various video standards including H.265, H.264 and
  81. VP8 at 4K resolution and up to 60 fps.
  82. Besides the multimedia features it also comes with a variety of I/O
  83. controllers, such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to
  84. name only a few.
  85. config ARCH_TEGRA_186_SOC
  86. bool "NVIDIA Tegra186 SoC"
  87. select MAILBOX
  88. select TEGRA_BPMP
  89. select TEGRA_HSP_MBOX
  90. select TEGRA_IVC
  91. select SOC_TEGRA_PMC
  92. help
  93. Enable support for the NVIDIA Tegar186 SoC. The Tegra186 features a
  94. combination of Denver and Cortex-A57 CPU cores and a GPU based on
  95. the Pascal architecture. It contains an ADSP with a Cortex-A9 CPU
  96. used for audio processing, hardware video encoders/decoders with
  97. multi-format support, ISP for image capture processing and BPMP for
  98. power management.
  99. config ARCH_TEGRA_194_SOC
  100. bool "NVIDIA Tegra194 SoC"
  101. select MAILBOX
  102. select PINCTRL_TEGRA194
  103. select TEGRA_BPMP
  104. select TEGRA_HSP_MBOX
  105. select TEGRA_IVC
  106. select SOC_TEGRA_PMC
  107. help
  108. Enable support for the NVIDIA Tegra194 SoC.
  109. config ARCH_TEGRA_234_SOC
  110. bool "NVIDIA Tegra234 SoC"
  111. select MAILBOX
  112. select TEGRA_BPMP
  113. select TEGRA_HSP_MBOX
  114. select TEGRA_IVC
  115. select SOC_TEGRA_PMC
  116. help
  117. Enable support for the NVIDIA Tegra234 SoC.
  118. endif
  119. endif
  120. config SOC_TEGRA_FUSE
  121. def_bool y
  122. depends on ARCH_TEGRA
  123. select SOC_BUS
  124. config SOC_TEGRA_FLOWCTRL
  125. bool
  126. config SOC_TEGRA_PMC
  127. bool
  128. select GENERIC_PINCONF
  129. select PM_OPP
  130. select PM_GENERIC_DOMAINS
  131. select REGMAP
  132. config SOC_TEGRA_POWERGATE_BPMP
  133. def_bool y
  134. depends on PM_GENERIC_DOMAINS
  135. depends on TEGRA_BPMP
  136. config SOC_TEGRA20_VOLTAGE_COUPLER
  137. bool "Voltage scaling support for Tegra20 SoCs"
  138. depends on ARCH_TEGRA_2x_SOC || COMPILE_TEST
  139. depends on REGULATOR
  140. config SOC_TEGRA30_VOLTAGE_COUPLER
  141. bool "Voltage scaling support for Tegra30 SoCs"
  142. depends on ARCH_TEGRA_3x_SOC || COMPILE_TEST
  143. depends on REGULATOR
  144. config SOC_TEGRA_CBB
  145. tristate "Tegra driver to handle error from CBB"
  146. depends on ARCH_TEGRA_194_SOC || ARCH_TEGRA_234_SOC
  147. default y
  148. help
  149. Support for handling error from Tegra Control Backbone(CBB).
  150. This driver handles the errors from CBB and prints debug
  151. information about the failed transactions.