crypto-qti-hwkm.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Crypto HWKM library for storage encryption.
  4. *
  5. * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  6. */
  7. #include <linux/slab.h>
  8. #include <linux/crypto-qti-common.h>
  9. #include <linux/hwkm.h>
  10. #include <linux/module.h>
  11. #include <linux/kernel.h>
  12. #include <linux/cacheflush.h>
  13. #include <linux/qcom_scm.h>
  14. #include <linux/qtee_shmbridge.h>
  15. #include "crypto-qti-ice-regs.h"
  16. #include "crypto-qti-platform.h"
  17. #if IS_ENABLED(CONFIG_QTI_HW_KEY_MANAGER)
  18. #define KEYMANAGER_ICE_MAP_SLOT(slot) ((slot * 2))
  19. #endif
  20. #if IS_ENABLED(CONFIG_QTI_HW_KEY_MANAGER_V1)
  21. #define KEYMANAGER_ICE_MAP_SLOT(slot) ((slot * 2) + 10)
  22. #define GP_KEYSLOT 140
  23. #define RAW_SECRET_KEYSLOT 141
  24. #define TPKEY_SLOT_ICEMEM_SLAVE 0x92
  25. #define SLOT_EMPTY_ERROR 0x1000
  26. #define INLINECRYPT_CTX "inline encryption key"
  27. #define RAW_SECRET_CTX "raw secret"
  28. #define BYTE_ORDER_VAL 8
  29. #define KEY_WRAPPED_SIZE 68
  30. #endif
  31. union crypto_cfg {
  32. __le32 regval[2];
  33. struct {
  34. u8 dusize;
  35. u8 capidx;
  36. u8 nop;
  37. u8 cfge;
  38. u8 dumb[4];
  39. };
  40. };
  41. static bool qti_hwkm_init_done;
  42. static void print_key(const struct blk_crypto_key *key,
  43. unsigned int slot)
  44. {
  45. int i = 0;
  46. pr_err("%s: Printing key for slot %d\n", __func__, slot);
  47. for (i = 0; i < key->size; i++)
  48. pr_err("key->raw[%d] = 0x%x\n", i, key->raw[i]);
  49. }
  50. static int crypto_qti_program_hwkm_tz(const struct blk_crypto_key *key,
  51. unsigned int slot)
  52. {
  53. int err = 0;
  54. struct qtee_shm shm;
  55. err = qtee_shmbridge_allocate_shm(key->size, &shm);
  56. if (err)
  57. return -ENOMEM;
  58. memcpy(shm.vaddr, key->raw, key->size);
  59. qtee_shmbridge_flush_shm_buf(&shm);
  60. err = qcom_scm_config_set_ice_key(slot, shm.paddr, key->size,
  61. 0, 0, 0);
  62. if (err) {
  63. pr_err("%s:SCM call Error for get contents keyblob: 0x%x\n",
  64. __func__, err);
  65. print_key(key, slot);
  66. }
  67. qtee_shmbridge_inv_shm_buf(&shm);
  68. qtee_shmbridge_free_shm(&shm);
  69. return err;
  70. }
  71. int crypto_qti_get_hwkm_raw_secret_tz(
  72. const u8 *wrapped_key,
  73. unsigned int wrapped_key_size, u8 *secret,
  74. unsigned int secret_size)
  75. {
  76. int err = 0;
  77. struct qtee_shm shm_key, shm_secret;
  78. err = qtee_shmbridge_allocate_shm(wrapped_key_size, &shm_key);
  79. if (err)
  80. return -ENOMEM;
  81. err = qtee_shmbridge_allocate_shm(secret_size, &shm_secret);
  82. if (err) {
  83. qtee_shmbridge_free_shm(&shm_key);
  84. return -ENOMEM;
  85. }
  86. memcpy(shm_key.vaddr, wrapped_key, wrapped_key_size);
  87. qtee_shmbridge_flush_shm_buf(&shm_key);
  88. memset(shm_secret.vaddr, 0, secret_size);
  89. qtee_shmbridge_flush_shm_buf(&shm_secret);
  90. err = qcom_scm_derive_raw_secret(shm_key.paddr, wrapped_key_size,
  91. shm_secret.paddr, secret_size);
  92. if (err) {
  93. pr_err("%s:SCM call error for raw secret: 0x%x\n", __func__, err);
  94. goto exit;
  95. }
  96. qtee_shmbridge_inv_shm_buf(&shm_secret);
  97. memcpy(secret, shm_secret.vaddr, secret_size);
  98. qtee_shmbridge_inv_shm_buf(&shm_key);
  99. exit:
  100. qtee_shmbridge_free_shm(&shm_key);
  101. qtee_shmbridge_free_shm(&shm_secret);
  102. return err;
  103. }
  104. #if IS_ENABLED(CONFIG_QTI_HW_KEY_MANAGER_V1)
  105. static int crypto_qti_hwkm_evict_slot_v1(unsigned int slot, bool double_key)
  106. {
  107. struct hwkm_cmd cmd_clear;
  108. struct hwkm_rsp rsp_clear;
  109. memset(&cmd_clear, 0, sizeof(cmd_clear));
  110. cmd_clear.op = KEY_SLOT_CLEAR;
  111. cmd_clear.clear.dks = slot;
  112. if (double_key)
  113. cmd_clear.clear.is_double_key = true;
  114. return qti_hwkm_handle_cmd(&cmd_clear, &rsp_clear);
  115. }
  116. #endif
  117. #if IS_ENABLED(CONFIG_QTI_HW_KEY_MANAGER)
  118. static int crypto_qti_hwkm_evict_slot(unsigned int slot)
  119. {
  120. int err = 0;
  121. err = qcom_scm_clear_ice_key(slot, 0);
  122. if (err)
  123. pr_err("%s:SCM call Error: 0x%x\n", __func__, err);
  124. return err;
  125. }
  126. #endif
  127. #if IS_ENABLED(CONFIG_QTI_HW_KEY_MANAGER_V1)
  128. static int crypto_qti_program_key_v1(const struct ice_mmio_data *mmio_data,
  129. const struct blk_crypto_key *key, unsigned int slot,
  130. unsigned int data_unit_mask, int capid)
  131. {
  132. int err_program;
  133. int err_clear;
  134. struct hwkm_cmd cmd_unwrap;
  135. struct hwkm_cmd cmd_kdf;
  136. struct hwkm_rsp rsp_unwrap;
  137. struct hwkm_rsp rsp_kdf;
  138. struct hwkm_key_policy policy_kdf = {
  139. .security_lvl = MANAGED_KEY,
  140. .hw_destination = ICEMEM_SLAVE,
  141. .key_type = GENERIC_KEY,
  142. .enc_allowed = true,
  143. .dec_allowed = true,
  144. .alg_allowed = AES256_XTS,
  145. .km_by_nsec_allowed = true,
  146. };
  147. struct hwkm_bsve bsve_kdf = {
  148. .enabled = true,
  149. .km_swc_en = true,
  150. .km_child_key_policy_en = true,
  151. };
  152. union crypto_cfg cfg;
  153. err_program = qti_hwkm_clocks(true);
  154. if (err_program) {
  155. pr_err("%s: Error enabling clocks %d\n", __func__,
  156. err_program);
  157. return err_program;
  158. }
  159. /* Failsafe, clear GP_KEYSLOT incase it is not empty for any reason */
  160. err_clear = crypto_qti_hwkm_evict_slot_v1(GP_KEYSLOT, false);
  161. if (err_clear && (err_clear != SLOT_EMPTY_ERROR)) {
  162. pr_err("%s: Error clearing ICE slot %d, err %d\n",
  163. __func__, GP_KEYSLOT, err_clear);
  164. qti_hwkm_clocks(false);
  165. return -EINVAL;
  166. }
  167. /* Unwrap keyblob into a non ICE slot using TP key */
  168. cmd_unwrap.op = KEY_UNWRAP_IMPORT;
  169. cmd_unwrap.unwrap.dks = GP_KEYSLOT;
  170. cmd_unwrap.unwrap.kwk = TPKEY_SLOT_ICEMEM_SLAVE;
  171. if ((key->size) == KEY_WRAPPED_SIZE) {
  172. cmd_unwrap.unwrap.sz = key->size;
  173. memcpy(cmd_unwrap.unwrap.wkb, key->raw,
  174. cmd_unwrap.unwrap.sz);
  175. } else {
  176. cmd_unwrap.unwrap.sz = (key->size) - RAW_SECRET_SIZE;
  177. memcpy(cmd_unwrap.unwrap.wkb, (key->raw) + RAW_SECRET_SIZE,
  178. cmd_unwrap.unwrap.sz);
  179. }
  180. err_program = qti_hwkm_handle_cmd(&cmd_unwrap, &rsp_unwrap);
  181. if (err_program) {
  182. pr_err("%s: Error with key unwrap %d\n", __func__,
  183. err_program);
  184. qti_hwkm_clocks(false);
  185. return -EINVAL;
  186. }
  187. /* Failsafe, clear ICE keyslot incase it is not empty for any reason */
  188. err_clear = crypto_qti_hwkm_evict_slot_v1(KEYMANAGER_ICE_MAP_SLOT(slot),
  189. true);
  190. if (err_clear && (err_clear != SLOT_EMPTY_ERROR)) {
  191. pr_err("%s: Error clearing ICE slot %d, err %d\n",
  192. __func__, KEYMANAGER_ICE_MAP_SLOT(slot), err_clear);
  193. qti_hwkm_clocks(false);
  194. return -EINVAL;
  195. }
  196. /* Derive a 512-bit key which will be the key to encrypt/decrypt data */
  197. cmd_kdf.op = SYSTEM_KDF;
  198. cmd_kdf.kdf.dks = KEYMANAGER_ICE_MAP_SLOT(slot);
  199. cmd_kdf.kdf.kdk = GP_KEYSLOT;
  200. cmd_kdf.kdf.policy = policy_kdf;
  201. cmd_kdf.kdf.bsve = bsve_kdf;
  202. cmd_kdf.kdf.sz = round_up(strlen(INLINECRYPT_CTX), BYTE_ORDER_VAL);
  203. memset(cmd_kdf.kdf.ctx, 0, HWKM_MAX_CTX_SIZE);
  204. memcpy(cmd_kdf.kdf.ctx, INLINECRYPT_CTX, strlen(INLINECRYPT_CTX));
  205. memset(&cfg, 0, sizeof(cfg));
  206. cfg.dusize = data_unit_mask;
  207. cfg.capidx = capid;
  208. cfg.cfge = 0x80;
  209. ice_writel(mmio_data->ice_base_mmio, 0x0, (ICE_LUT_KEYS_CRYPTOCFG_R_16 +
  210. ICE_LUT_KEYS_CRYPTOCFG_OFFSET*slot));
  211. /* Make sure CFGE is cleared */
  212. wmb();
  213. err_program = qti_hwkm_handle_cmd(&cmd_kdf, &rsp_kdf);
  214. if (err_program) {
  215. pr_err("%s: Error programming key %d, slot %d\n", __func__,
  216. err_program, slot);
  217. err_clear = crypto_qti_hwkm_evict_slot_v1(GP_KEYSLOT, false);
  218. if (err_clear) {
  219. pr_err("%s: Error clearing slot %d err %d\n",
  220. __func__, GP_KEYSLOT, err_clear);
  221. }
  222. qti_hwkm_clocks(false);
  223. return -EINVAL;
  224. }
  225. err_clear = crypto_qti_hwkm_evict_slot_v1(GP_KEYSLOT, false);
  226. if (err_clear) {
  227. pr_err("%s: Error unwrapped slot clear %d\n", __func__,
  228. err_clear);
  229. qti_hwkm_clocks(false);
  230. return -EINVAL;
  231. }
  232. ice_writel(mmio_data->ice_base_mmio, cfg.regval[0], (ICE_LUT_KEYS_CRYPTOCFG_R_16 +
  233. ICE_LUT_KEYS_CRYPTOCFG_OFFSET*slot));
  234. /* Make sure CFGE is enabled before moving forward */
  235. wmb();
  236. qti_hwkm_clocks(false);
  237. return err_program;
  238. }
  239. #endif
  240. int crypto_qti_program_key(const struct ice_mmio_data *mmio_data,
  241. const struct blk_crypto_key *key, unsigned int slot,
  242. unsigned int data_unit_mask, int capid, int storage_type)
  243. {
  244. int err = 0;
  245. union crypto_cfg cfg;
  246. if ((key->size) <= RAW_SECRET_SIZE) {
  247. pr_err("%s: Incorrect key size %d\n", __func__, key->size);
  248. return -EINVAL;
  249. }
  250. if (!qti_hwkm_init_done) {
  251. err = qti_hwkm_init(mmio_data);
  252. if (err) {
  253. pr_err("%s: Error with HWKM init %d\n", __func__, err);
  254. return -EINVAL;
  255. }
  256. qti_hwkm_init_done = true;
  257. }
  258. #if IS_ENABLED(CONFIG_QTI_HW_KEY_MANAGER_V1)
  259. /* Call to support Program Key for HWKM v1 */
  260. return crypto_qti_program_key_v1(mmio_data, key, slot, data_unit_mask, capid);
  261. #endif
  262. memset(&cfg, 0, sizeof(cfg));
  263. cfg.dusize = data_unit_mask;
  264. cfg.capidx = capid;
  265. cfg.cfge = 0x80;
  266. ice_writel(mmio_data->ice_base_mmio, 0x0, (ICE_LUT_KEYS_CRYPTOCFG_R_16 +
  267. ICE_LUT_KEYS_CRYPTOCFG_OFFSET*slot));
  268. /* Make sure CFGE is cleared */
  269. wmb();
  270. /*
  271. * Call TZ to get a contents keyblob
  272. * TZ unwraps the derivation key, derives a 512 bit XTS key
  273. * and wraps it with the TP Key. It then unwraps to the ICE slot.
  274. */
  275. err = crypto_qti_program_hwkm_tz(key, KEYMANAGER_ICE_MAP_SLOT(slot));
  276. if (err) {
  277. pr_err("%s: Error programming hwkm keyblob , err = %d\n",
  278. __func__, err);
  279. goto exit;
  280. }
  281. ice_writel(mmio_data->ice_base_mmio, cfg.regval[0],
  282. (ICE_LUT_KEYS_CRYPTOCFG_R_16 + ICE_LUT_KEYS_CRYPTOCFG_OFFSET*slot));
  283. /* Make sure CFGE is enabled before moving forward */
  284. wmb();
  285. exit:
  286. return err;
  287. }
  288. EXPORT_SYMBOL(crypto_qti_program_key);
  289. int crypto_qti_invalidate_key(const struct ice_mmio_data *mmio_data,
  290. unsigned int slot, int storage_type)
  291. {
  292. int err = 0;
  293. if (!qti_hwkm_init_done)
  294. return 0;
  295. /* Clear key from ICE keyslot */
  296. #if IS_ENABLED(CONFIG_QTI_HW_KEY_MANAGER)
  297. err = crypto_qti_hwkm_evict_slot(KEYMANAGER_ICE_MAP_SLOT(slot));
  298. if (err)
  299. pr_err("%s: Error with key clear %d, slot %d\n", __func__, err, slot);
  300. #endif
  301. #if IS_ENABLED(CONFIG_QTI_HW_KEY_MANAGER_V1)
  302. err = qti_hwkm_clocks(true);
  303. if (err) {
  304. pr_err("%s: Error enabling clocks %d\n", __func__, err);
  305. return err;
  306. }
  307. err = crypto_qti_hwkm_evict_slot_v1(KEYMANAGER_ICE_MAP_SLOT(slot), true);
  308. if (err && (err != SLOT_EMPTY_ERROR)) {
  309. pr_err("%s: Error clearing slot %d, err %d\n",
  310. __func__, slot, err);
  311. qti_hwkm_clocks(false);
  312. return -EINVAL;
  313. }
  314. qti_hwkm_clocks(false);
  315. #endif
  316. return err;
  317. }
  318. EXPORT_SYMBOL(crypto_qti_invalidate_key);
  319. void crypto_qti_disable_platform(void)
  320. {
  321. qti_hwkm_init_done = false;
  322. }
  323. EXPORT_SYMBOL(crypto_qti_disable_platform);
  324. #if IS_ENABLED(CONFIG_QTI_HW_KEY_MANAGER_V1)
  325. static int crypto_qti_derive_raw_secret_platform_v1(
  326. const u8 *wrapped_key,
  327. unsigned int wrapped_key_size, u8 *secret,
  328. unsigned int secret_size)
  329. {
  330. int err_program;
  331. int err_clear;
  332. struct hwkm_cmd cmd_unwrap;
  333. struct hwkm_cmd cmd_kdf;
  334. struct hwkm_cmd cmd_read;
  335. struct hwkm_rsp rsp_unwrap;
  336. struct hwkm_rsp rsp_kdf;
  337. struct hwkm_rsp rsp_read;
  338. struct hwkm_key_policy policy_kdf = {
  339. .security_lvl = SW_KEY,
  340. .hw_destination = ICEMEM_SLAVE,
  341. .key_type = GENERIC_KEY,
  342. .enc_allowed = true,
  343. .dec_allowed = true,
  344. .alg_allowed = AES256_CBC,
  345. .km_by_nsec_allowed = true,
  346. };
  347. struct hwkm_bsve bsve_kdf = {
  348. .enabled = true,
  349. .km_swc_en = true,
  350. .km_child_key_policy_en = true,
  351. };
  352. if (wrapped_key_size != KEY_WRAPPED_SIZE) {
  353. memcpy(secret, wrapped_key, secret_size);
  354. return 0;
  355. }
  356. err_program = qti_hwkm_clocks(true);
  357. if (err_program) {
  358. pr_err("%s: Error enabling clocks %d\n", __func__,
  359. err_program);
  360. return err_program;
  361. }
  362. /* Failsafe, clear GP_KEYSLOT incase it is not empty for any reason */
  363. err_clear = crypto_qti_hwkm_evict_slot_v1(GP_KEYSLOT, false);
  364. if (err_clear && (err_clear != SLOT_EMPTY_ERROR)) {
  365. pr_err("%s: Error clearing GP slot %d, err %d\n",
  366. __func__, GP_KEYSLOT, err_clear);
  367. qti_hwkm_clocks(false);
  368. return -EINVAL;
  369. }
  370. /* Unwrap keyblob into a non ICE slot using TP key */
  371. cmd_unwrap.op = KEY_UNWRAP_IMPORT;
  372. cmd_unwrap.unwrap.dks = GP_KEYSLOT;
  373. cmd_unwrap.unwrap.kwk = TPKEY_SLOT_ICEMEM_SLAVE;
  374. cmd_unwrap.unwrap.sz = wrapped_key_size;
  375. memcpy(cmd_unwrap.unwrap.wkb, wrapped_key,
  376. cmd_unwrap.unwrap.sz);
  377. err_program = qti_hwkm_handle_cmd(&cmd_unwrap, &rsp_unwrap);
  378. if (err_program) {
  379. pr_err("%s: Error with key unwrap %d\n", __func__,
  380. err_program);
  381. qti_hwkm_clocks(false);
  382. return -EINVAL;
  383. }
  384. /* Failsafe, clear RAW_SECRET_KEYSLOT incase it is not empty */
  385. err_clear = crypto_qti_hwkm_evict_slot_v1(RAW_SECRET_KEYSLOT, false);
  386. if (err_clear && (err_clear != SLOT_EMPTY_ERROR)) {
  387. pr_err("%s: Error clearing raw secret slot %d, err %d\n",
  388. __func__, RAW_SECRET_KEYSLOT, err_clear);
  389. qti_hwkm_clocks(false);
  390. return -EINVAL;
  391. }
  392. /* Derive a 512-bit key which will be the key to encrypt/decrypt data */
  393. cmd_kdf.op = SYSTEM_KDF;
  394. cmd_kdf.kdf.dks = RAW_SECRET_KEYSLOT;
  395. cmd_kdf.kdf.kdk = GP_KEYSLOT;
  396. cmd_kdf.kdf.policy = policy_kdf;
  397. cmd_kdf.kdf.bsve = bsve_kdf;
  398. cmd_kdf.kdf.sz = round_up(strlen(RAW_SECRET_CTX), BYTE_ORDER_VAL);
  399. memset(cmd_kdf.kdf.ctx, 0, HWKM_MAX_CTX_SIZE);
  400. memcpy(cmd_kdf.kdf.ctx, RAW_SECRET_CTX, strlen(RAW_SECRET_CTX));
  401. err_program = qti_hwkm_handle_cmd(&cmd_kdf, &rsp_kdf);
  402. if (err_program) {
  403. pr_err("%s: Error deriving secret %d, slot %d\n", __func__,
  404. err_program, RAW_SECRET_KEYSLOT);
  405. err_program = -EINVAL;
  406. }
  407. /* Read the KDF key for raw secret */
  408. cmd_read.op = KEY_SLOT_RDWR;
  409. cmd_read.rdwr.slot = RAW_SECRET_KEYSLOT;
  410. cmd_read.rdwr.is_write = false;
  411. err_program = qti_hwkm_handle_cmd(&cmd_read, &rsp_read);
  412. if (err_program) {
  413. pr_err("%s: Error with key read %d\n", __func__, err_program);
  414. err_program = -EINVAL;
  415. }
  416. memcpy(secret, rsp_read.rdwr.key, rsp_read.rdwr.sz);
  417. err_clear = crypto_qti_hwkm_evict_slot_v1(GP_KEYSLOT, false);
  418. if (err_clear)
  419. pr_err("%s: GP slot clear %d\n", __func__, err_clear);
  420. err_clear = crypto_qti_hwkm_evict_slot_v1(RAW_SECRET_KEYSLOT, false);
  421. if (err_clear)
  422. pr_err("%s: raw secret slot clear %d\n", __func__, err_clear);
  423. qti_hwkm_clocks(false);
  424. return err_program;
  425. }
  426. #endif
  427. int crypto_qti_derive_raw_secret_platform(const struct ice_mmio_data *mmio_data,
  428. const u8 *wrapped_key,
  429. unsigned int wrapped_key_size, u8 *secret,
  430. unsigned int secret_size)
  431. {
  432. int err = 0;
  433. #if IS_ENABLED(CONFIG_QTI_HW_KEY_MANAGER_V1)
  434. return crypto_qti_derive_raw_secret_platform_v1(wrapped_key,
  435. wrapped_key_size, secret, secret_size);
  436. #endif
  437. if (!qti_hwkm_init_done) {
  438. err = qti_hwkm_init(mmio_data);
  439. if (err) {
  440. pr_err("%s: Error with HWKM init %d\n", __func__, err);
  441. return -EINVAL;
  442. }
  443. qti_hwkm_init_done = true;
  444. }
  445. /*
  446. * Call TZ to get a raw secret
  447. * TZ unwraps the derivation key, derives a CMAC key
  448. * and then another derivation to get 32 bytes of key data.
  449. */
  450. err = crypto_qti_get_hwkm_raw_secret_tz(wrapped_key, wrapped_key_size,
  451. secret, secret_size);
  452. if (err) {
  453. pr_err("%s: Error with getting derived contents keyblob , err = %d\n",
  454. __func__, err);
  455. }
  456. return err;
  457. }
  458. EXPORT_SYMBOL(crypto_qti_derive_raw_secret_platform);
  459. MODULE_LICENSE("GPL");
  460. MODULE_DESCRIPTION("Crypto HWKM library for storage encryption");