smartpqi_init.c 290 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * driver for Microchip PQI-based storage controllers
  4. * Copyright (c) 2019-2022 Microchip Technology Inc. and its subsidiaries
  5. * Copyright (c) 2016-2018 Microsemi Corporation
  6. * Copyright (c) 2016 PMC-Sierra, Inc.
  7. *
  8. * Questions/Comments/Bugfixes to [email protected]
  9. *
  10. */
  11. #include <linux/module.h>
  12. #include <linux/kernel.h>
  13. #include <linux/pci.h>
  14. #include <linux/delay.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/sched.h>
  17. #include <linux/rtc.h>
  18. #include <linux/bcd.h>
  19. #include <linux/reboot.h>
  20. #include <linux/cciss_ioctl.h>
  21. #include <linux/blk-mq-pci.h>
  22. #include <scsi/scsi_host.h>
  23. #include <scsi/scsi_cmnd.h>
  24. #include <scsi/scsi_device.h>
  25. #include <scsi/scsi_eh.h>
  26. #include <scsi/scsi_transport_sas.h>
  27. #include <asm/unaligned.h>
  28. #include "smartpqi.h"
  29. #include "smartpqi_sis.h"
  30. #if !defined(BUILD_TIMESTAMP)
  31. #define BUILD_TIMESTAMP
  32. #endif
  33. #define DRIVER_VERSION "2.1.18-045"
  34. #define DRIVER_MAJOR 2
  35. #define DRIVER_MINOR 1
  36. #define DRIVER_RELEASE 18
  37. #define DRIVER_REVISION 45
  38. #define DRIVER_NAME "Microchip SmartPQI Driver (v" \
  39. DRIVER_VERSION BUILD_TIMESTAMP ")"
  40. #define DRIVER_NAME_SHORT "smartpqi"
  41. #define PQI_EXTRA_SGL_MEMORY (12 * sizeof(struct pqi_sg_descriptor))
  42. #define PQI_POST_RESET_DELAY_SECS 5
  43. #define PQI_POST_OFA_RESET_DELAY_UPON_TIMEOUT_SECS 10
  44. MODULE_AUTHOR("Microchip");
  45. MODULE_DESCRIPTION("Driver for Microchip Smart Family Controller version "
  46. DRIVER_VERSION);
  47. MODULE_VERSION(DRIVER_VERSION);
  48. MODULE_LICENSE("GPL");
  49. struct pqi_cmd_priv {
  50. int this_residual;
  51. };
  52. static struct pqi_cmd_priv *pqi_cmd_priv(struct scsi_cmnd *cmd)
  53. {
  54. return scsi_cmd_priv(cmd);
  55. }
  56. static void pqi_verify_structures(void);
  57. static void pqi_take_ctrl_offline(struct pqi_ctrl_info *ctrl_info,
  58. enum pqi_ctrl_shutdown_reason ctrl_shutdown_reason);
  59. static void pqi_ctrl_offline_worker(struct work_struct *work);
  60. static int pqi_scan_scsi_devices(struct pqi_ctrl_info *ctrl_info);
  61. static void pqi_scan_start(struct Scsi_Host *shost);
  62. static void pqi_start_io(struct pqi_ctrl_info *ctrl_info,
  63. struct pqi_queue_group *queue_group, enum pqi_io_path path,
  64. struct pqi_io_request *io_request);
  65. static int pqi_submit_raid_request_synchronous(struct pqi_ctrl_info *ctrl_info,
  66. struct pqi_iu_header *request, unsigned int flags,
  67. struct pqi_raid_error_info *error_info);
  68. static int pqi_aio_submit_io(struct pqi_ctrl_info *ctrl_info,
  69. struct scsi_cmnd *scmd, u32 aio_handle, u8 *cdb,
  70. unsigned int cdb_length, struct pqi_queue_group *queue_group,
  71. struct pqi_encryption_info *encryption_info, bool raid_bypass, bool io_high_prio);
  72. static int pqi_aio_submit_r1_write_io(struct pqi_ctrl_info *ctrl_info,
  73. struct scsi_cmnd *scmd, struct pqi_queue_group *queue_group,
  74. struct pqi_encryption_info *encryption_info, struct pqi_scsi_dev *device,
  75. struct pqi_scsi_dev_raid_map_data *rmd);
  76. static int pqi_aio_submit_r56_write_io(struct pqi_ctrl_info *ctrl_info,
  77. struct scsi_cmnd *scmd, struct pqi_queue_group *queue_group,
  78. struct pqi_encryption_info *encryption_info, struct pqi_scsi_dev *device,
  79. struct pqi_scsi_dev_raid_map_data *rmd);
  80. static void pqi_ofa_ctrl_quiesce(struct pqi_ctrl_info *ctrl_info);
  81. static void pqi_ofa_ctrl_unquiesce(struct pqi_ctrl_info *ctrl_info);
  82. static int pqi_ofa_ctrl_restart(struct pqi_ctrl_info *ctrl_info, unsigned int delay_secs);
  83. static void pqi_ofa_setup_host_buffer(struct pqi_ctrl_info *ctrl_info);
  84. static void pqi_ofa_free_host_buffer(struct pqi_ctrl_info *ctrl_info);
  85. static int pqi_ofa_host_memory_update(struct pqi_ctrl_info *ctrl_info);
  86. static int pqi_device_wait_for_pending_io(struct pqi_ctrl_info *ctrl_info,
  87. struct pqi_scsi_dev *device, u8 lun, unsigned long timeout_msecs);
  88. static void pqi_fail_all_outstanding_requests(struct pqi_ctrl_info *ctrl_info);
  89. /* for flags argument to pqi_submit_raid_request_synchronous() */
  90. #define PQI_SYNC_FLAGS_INTERRUPTABLE 0x1
  91. static struct scsi_transport_template *pqi_sas_transport_template;
  92. static atomic_t pqi_controller_count = ATOMIC_INIT(0);
  93. enum pqi_lockup_action {
  94. NONE,
  95. REBOOT,
  96. PANIC
  97. };
  98. static enum pqi_lockup_action pqi_lockup_action = NONE;
  99. static struct {
  100. enum pqi_lockup_action action;
  101. char *name;
  102. } pqi_lockup_actions[] = {
  103. {
  104. .action = NONE,
  105. .name = "none",
  106. },
  107. {
  108. .action = REBOOT,
  109. .name = "reboot",
  110. },
  111. {
  112. .action = PANIC,
  113. .name = "panic",
  114. },
  115. };
  116. static unsigned int pqi_supported_event_types[] = {
  117. PQI_EVENT_TYPE_HOTPLUG,
  118. PQI_EVENT_TYPE_HARDWARE,
  119. PQI_EVENT_TYPE_PHYSICAL_DEVICE,
  120. PQI_EVENT_TYPE_LOGICAL_DEVICE,
  121. PQI_EVENT_TYPE_OFA,
  122. PQI_EVENT_TYPE_AIO_STATE_CHANGE,
  123. PQI_EVENT_TYPE_AIO_CONFIG_CHANGE,
  124. };
  125. static int pqi_disable_device_id_wildcards;
  126. module_param_named(disable_device_id_wildcards,
  127. pqi_disable_device_id_wildcards, int, 0644);
  128. MODULE_PARM_DESC(disable_device_id_wildcards,
  129. "Disable device ID wildcards.");
  130. static int pqi_disable_heartbeat;
  131. module_param_named(disable_heartbeat,
  132. pqi_disable_heartbeat, int, 0644);
  133. MODULE_PARM_DESC(disable_heartbeat,
  134. "Disable heartbeat.");
  135. static int pqi_disable_ctrl_shutdown;
  136. module_param_named(disable_ctrl_shutdown,
  137. pqi_disable_ctrl_shutdown, int, 0644);
  138. MODULE_PARM_DESC(disable_ctrl_shutdown,
  139. "Disable controller shutdown when controller locked up.");
  140. static char *pqi_lockup_action_param;
  141. module_param_named(lockup_action,
  142. pqi_lockup_action_param, charp, 0644);
  143. MODULE_PARM_DESC(lockup_action, "Action to take when controller locked up.\n"
  144. "\t\tSupported: none, reboot, panic\n"
  145. "\t\tDefault: none");
  146. static int pqi_expose_ld_first;
  147. module_param_named(expose_ld_first,
  148. pqi_expose_ld_first, int, 0644);
  149. MODULE_PARM_DESC(expose_ld_first, "Expose logical drives before physical drives.");
  150. static int pqi_hide_vsep;
  151. module_param_named(hide_vsep,
  152. pqi_hide_vsep, int, 0644);
  153. MODULE_PARM_DESC(hide_vsep, "Hide the virtual SEP for direct attached drives.");
  154. static int pqi_disable_managed_interrupts;
  155. module_param_named(disable_managed_interrupts,
  156. pqi_disable_managed_interrupts, int, 0644);
  157. MODULE_PARM_DESC(disable_managed_interrupts,
  158. "Disable the kernel automatically assigning SMP affinity to IRQs.");
  159. static unsigned int pqi_ctrl_ready_timeout_secs;
  160. module_param_named(ctrl_ready_timeout,
  161. pqi_ctrl_ready_timeout_secs, uint, 0644);
  162. MODULE_PARM_DESC(ctrl_ready_timeout,
  163. "Timeout in seconds for driver to wait for controller ready.");
  164. static char *raid_levels[] = {
  165. "RAID-0",
  166. "RAID-4",
  167. "RAID-1(1+0)",
  168. "RAID-5",
  169. "RAID-5+1",
  170. "RAID-6",
  171. "RAID-1(Triple)",
  172. };
  173. static char *pqi_raid_level_to_string(u8 raid_level)
  174. {
  175. if (raid_level < ARRAY_SIZE(raid_levels))
  176. return raid_levels[raid_level];
  177. return "RAID UNKNOWN";
  178. }
  179. #define SA_RAID_0 0
  180. #define SA_RAID_4 1
  181. #define SA_RAID_1 2 /* also used for RAID 10 */
  182. #define SA_RAID_5 3 /* also used for RAID 50 */
  183. #define SA_RAID_51 4
  184. #define SA_RAID_6 5 /* also used for RAID 60 */
  185. #define SA_RAID_TRIPLE 6 /* also used for RAID 1+0 Triple */
  186. #define SA_RAID_MAX SA_RAID_TRIPLE
  187. #define SA_RAID_UNKNOWN 0xff
  188. static inline void pqi_scsi_done(struct scsi_cmnd *scmd)
  189. {
  190. pqi_prep_for_scsi_done(scmd);
  191. scsi_done(scmd);
  192. }
  193. static inline void pqi_disable_write_same(struct scsi_device *sdev)
  194. {
  195. sdev->no_write_same = 1;
  196. }
  197. static inline bool pqi_scsi3addr_equal(u8 *scsi3addr1, u8 *scsi3addr2)
  198. {
  199. return memcmp(scsi3addr1, scsi3addr2, 8) == 0;
  200. }
  201. static inline bool pqi_is_logical_device(struct pqi_scsi_dev *device)
  202. {
  203. return !device->is_physical_device;
  204. }
  205. static inline bool pqi_is_external_raid_addr(u8 *scsi3addr)
  206. {
  207. return scsi3addr[2] != 0;
  208. }
  209. static inline bool pqi_ctrl_offline(struct pqi_ctrl_info *ctrl_info)
  210. {
  211. return !ctrl_info->controller_online;
  212. }
  213. static inline void pqi_check_ctrl_health(struct pqi_ctrl_info *ctrl_info)
  214. {
  215. if (ctrl_info->controller_online)
  216. if (!sis_is_firmware_running(ctrl_info))
  217. pqi_take_ctrl_offline(ctrl_info, PQI_FIRMWARE_KERNEL_NOT_UP);
  218. }
  219. static inline bool pqi_is_hba_lunid(u8 *scsi3addr)
  220. {
  221. return pqi_scsi3addr_equal(scsi3addr, RAID_CTLR_LUNID);
  222. }
  223. #define PQI_DRIVER_SCRATCH_PQI_MODE 0x1
  224. #define PQI_DRIVER_SCRATCH_FW_TRIAGE_SUPPORTED 0x2
  225. static inline enum pqi_ctrl_mode pqi_get_ctrl_mode(struct pqi_ctrl_info *ctrl_info)
  226. {
  227. return sis_read_driver_scratch(ctrl_info) & PQI_DRIVER_SCRATCH_PQI_MODE ? PQI_MODE : SIS_MODE;
  228. }
  229. static inline void pqi_save_ctrl_mode(struct pqi_ctrl_info *ctrl_info,
  230. enum pqi_ctrl_mode mode)
  231. {
  232. u32 driver_scratch;
  233. driver_scratch = sis_read_driver_scratch(ctrl_info);
  234. if (mode == PQI_MODE)
  235. driver_scratch |= PQI_DRIVER_SCRATCH_PQI_MODE;
  236. else
  237. driver_scratch &= ~PQI_DRIVER_SCRATCH_PQI_MODE;
  238. sis_write_driver_scratch(ctrl_info, driver_scratch);
  239. }
  240. static inline bool pqi_is_fw_triage_supported(struct pqi_ctrl_info *ctrl_info)
  241. {
  242. return (sis_read_driver_scratch(ctrl_info) & PQI_DRIVER_SCRATCH_FW_TRIAGE_SUPPORTED) != 0;
  243. }
  244. static inline void pqi_save_fw_triage_setting(struct pqi_ctrl_info *ctrl_info, bool is_supported)
  245. {
  246. u32 driver_scratch;
  247. driver_scratch = sis_read_driver_scratch(ctrl_info);
  248. if (is_supported)
  249. driver_scratch |= PQI_DRIVER_SCRATCH_FW_TRIAGE_SUPPORTED;
  250. else
  251. driver_scratch &= ~PQI_DRIVER_SCRATCH_FW_TRIAGE_SUPPORTED;
  252. sis_write_driver_scratch(ctrl_info, driver_scratch);
  253. }
  254. static inline void pqi_ctrl_block_scan(struct pqi_ctrl_info *ctrl_info)
  255. {
  256. ctrl_info->scan_blocked = true;
  257. mutex_lock(&ctrl_info->scan_mutex);
  258. }
  259. static inline void pqi_ctrl_unblock_scan(struct pqi_ctrl_info *ctrl_info)
  260. {
  261. ctrl_info->scan_blocked = false;
  262. mutex_unlock(&ctrl_info->scan_mutex);
  263. }
  264. static inline bool pqi_ctrl_scan_blocked(struct pqi_ctrl_info *ctrl_info)
  265. {
  266. return ctrl_info->scan_blocked;
  267. }
  268. static inline void pqi_ctrl_block_device_reset(struct pqi_ctrl_info *ctrl_info)
  269. {
  270. mutex_lock(&ctrl_info->lun_reset_mutex);
  271. }
  272. static inline void pqi_ctrl_unblock_device_reset(struct pqi_ctrl_info *ctrl_info)
  273. {
  274. mutex_unlock(&ctrl_info->lun_reset_mutex);
  275. }
  276. static inline void pqi_scsi_block_requests(struct pqi_ctrl_info *ctrl_info)
  277. {
  278. struct Scsi_Host *shost;
  279. unsigned int num_loops;
  280. int msecs_sleep;
  281. shost = ctrl_info->scsi_host;
  282. scsi_block_requests(shost);
  283. num_loops = 0;
  284. msecs_sleep = 20;
  285. while (scsi_host_busy(shost)) {
  286. num_loops++;
  287. if (num_loops == 10)
  288. msecs_sleep = 500;
  289. msleep(msecs_sleep);
  290. }
  291. }
  292. static inline void pqi_scsi_unblock_requests(struct pqi_ctrl_info *ctrl_info)
  293. {
  294. scsi_unblock_requests(ctrl_info->scsi_host);
  295. }
  296. static inline void pqi_ctrl_busy(struct pqi_ctrl_info *ctrl_info)
  297. {
  298. atomic_inc(&ctrl_info->num_busy_threads);
  299. }
  300. static inline void pqi_ctrl_unbusy(struct pqi_ctrl_info *ctrl_info)
  301. {
  302. atomic_dec(&ctrl_info->num_busy_threads);
  303. }
  304. static inline bool pqi_ctrl_blocked(struct pqi_ctrl_info *ctrl_info)
  305. {
  306. return ctrl_info->block_requests;
  307. }
  308. static inline void pqi_ctrl_block_requests(struct pqi_ctrl_info *ctrl_info)
  309. {
  310. ctrl_info->block_requests = true;
  311. }
  312. static inline void pqi_ctrl_unblock_requests(struct pqi_ctrl_info *ctrl_info)
  313. {
  314. ctrl_info->block_requests = false;
  315. wake_up_all(&ctrl_info->block_requests_wait);
  316. }
  317. static void pqi_wait_if_ctrl_blocked(struct pqi_ctrl_info *ctrl_info)
  318. {
  319. if (!pqi_ctrl_blocked(ctrl_info))
  320. return;
  321. atomic_inc(&ctrl_info->num_blocked_threads);
  322. wait_event(ctrl_info->block_requests_wait,
  323. !pqi_ctrl_blocked(ctrl_info));
  324. atomic_dec(&ctrl_info->num_blocked_threads);
  325. }
  326. #define PQI_QUIESCE_WARNING_TIMEOUT_SECS 10
  327. static inline void pqi_ctrl_wait_until_quiesced(struct pqi_ctrl_info *ctrl_info)
  328. {
  329. unsigned long start_jiffies;
  330. unsigned long warning_timeout;
  331. bool displayed_warning;
  332. displayed_warning = false;
  333. start_jiffies = jiffies;
  334. warning_timeout = (PQI_QUIESCE_WARNING_TIMEOUT_SECS * HZ) + start_jiffies;
  335. while (atomic_read(&ctrl_info->num_busy_threads) >
  336. atomic_read(&ctrl_info->num_blocked_threads)) {
  337. if (time_after(jiffies, warning_timeout)) {
  338. dev_warn(&ctrl_info->pci_dev->dev,
  339. "waiting %u seconds for driver activity to quiesce\n",
  340. jiffies_to_msecs(jiffies - start_jiffies) / 1000);
  341. displayed_warning = true;
  342. warning_timeout = (PQI_QUIESCE_WARNING_TIMEOUT_SECS * HZ) + jiffies;
  343. }
  344. usleep_range(1000, 2000);
  345. }
  346. if (displayed_warning)
  347. dev_warn(&ctrl_info->pci_dev->dev,
  348. "driver activity quiesced after waiting for %u seconds\n",
  349. jiffies_to_msecs(jiffies - start_jiffies) / 1000);
  350. }
  351. static inline bool pqi_device_offline(struct pqi_scsi_dev *device)
  352. {
  353. return device->device_offline;
  354. }
  355. static inline void pqi_ctrl_ofa_start(struct pqi_ctrl_info *ctrl_info)
  356. {
  357. mutex_lock(&ctrl_info->ofa_mutex);
  358. }
  359. static inline void pqi_ctrl_ofa_done(struct pqi_ctrl_info *ctrl_info)
  360. {
  361. mutex_unlock(&ctrl_info->ofa_mutex);
  362. }
  363. static inline void pqi_wait_until_ofa_finished(struct pqi_ctrl_info *ctrl_info)
  364. {
  365. mutex_lock(&ctrl_info->ofa_mutex);
  366. mutex_unlock(&ctrl_info->ofa_mutex);
  367. }
  368. static inline bool pqi_ofa_in_progress(struct pqi_ctrl_info *ctrl_info)
  369. {
  370. return mutex_is_locked(&ctrl_info->ofa_mutex);
  371. }
  372. static inline void pqi_device_remove_start(struct pqi_scsi_dev *device)
  373. {
  374. device->in_remove = true;
  375. }
  376. static inline bool pqi_device_in_remove(struct pqi_scsi_dev *device)
  377. {
  378. return device->in_remove;
  379. }
  380. static inline int pqi_event_type_to_event_index(unsigned int event_type)
  381. {
  382. int index;
  383. for (index = 0; index < ARRAY_SIZE(pqi_supported_event_types); index++)
  384. if (event_type == pqi_supported_event_types[index])
  385. return index;
  386. return -1;
  387. }
  388. static inline bool pqi_is_supported_event(unsigned int event_type)
  389. {
  390. return pqi_event_type_to_event_index(event_type) != -1;
  391. }
  392. static inline void pqi_schedule_rescan_worker_with_delay(struct pqi_ctrl_info *ctrl_info,
  393. unsigned long delay)
  394. {
  395. if (pqi_ctrl_offline(ctrl_info))
  396. return;
  397. schedule_delayed_work(&ctrl_info->rescan_work, delay);
  398. }
  399. static inline void pqi_schedule_rescan_worker(struct pqi_ctrl_info *ctrl_info)
  400. {
  401. pqi_schedule_rescan_worker_with_delay(ctrl_info, 0);
  402. }
  403. #define PQI_RESCAN_WORK_DELAY (10 * HZ)
  404. static inline void pqi_schedule_rescan_worker_delayed(struct pqi_ctrl_info *ctrl_info)
  405. {
  406. pqi_schedule_rescan_worker_with_delay(ctrl_info, PQI_RESCAN_WORK_DELAY);
  407. }
  408. static inline void pqi_cancel_rescan_worker(struct pqi_ctrl_info *ctrl_info)
  409. {
  410. cancel_delayed_work_sync(&ctrl_info->rescan_work);
  411. }
  412. static inline u32 pqi_read_heartbeat_counter(struct pqi_ctrl_info *ctrl_info)
  413. {
  414. if (!ctrl_info->heartbeat_counter)
  415. return 0;
  416. return readl(ctrl_info->heartbeat_counter);
  417. }
  418. static inline u8 pqi_read_soft_reset_status(struct pqi_ctrl_info *ctrl_info)
  419. {
  420. return readb(ctrl_info->soft_reset_status);
  421. }
  422. static inline void pqi_clear_soft_reset_status(struct pqi_ctrl_info *ctrl_info)
  423. {
  424. u8 status;
  425. status = pqi_read_soft_reset_status(ctrl_info);
  426. status &= ~PQI_SOFT_RESET_ABORT;
  427. writeb(status, ctrl_info->soft_reset_status);
  428. }
  429. static int pqi_map_single(struct pci_dev *pci_dev,
  430. struct pqi_sg_descriptor *sg_descriptor, void *buffer,
  431. size_t buffer_length, enum dma_data_direction data_direction)
  432. {
  433. dma_addr_t bus_address;
  434. if (!buffer || buffer_length == 0 || data_direction == DMA_NONE)
  435. return 0;
  436. bus_address = dma_map_single(&pci_dev->dev, buffer, buffer_length,
  437. data_direction);
  438. if (dma_mapping_error(&pci_dev->dev, bus_address))
  439. return -ENOMEM;
  440. put_unaligned_le64((u64)bus_address, &sg_descriptor->address);
  441. put_unaligned_le32(buffer_length, &sg_descriptor->length);
  442. put_unaligned_le32(CISS_SG_LAST, &sg_descriptor->flags);
  443. return 0;
  444. }
  445. static void pqi_pci_unmap(struct pci_dev *pci_dev,
  446. struct pqi_sg_descriptor *descriptors, int num_descriptors,
  447. enum dma_data_direction data_direction)
  448. {
  449. int i;
  450. if (data_direction == DMA_NONE)
  451. return;
  452. for (i = 0; i < num_descriptors; i++)
  453. dma_unmap_single(&pci_dev->dev,
  454. (dma_addr_t)get_unaligned_le64(&descriptors[i].address),
  455. get_unaligned_le32(&descriptors[i].length),
  456. data_direction);
  457. }
  458. static int pqi_build_raid_path_request(struct pqi_ctrl_info *ctrl_info,
  459. struct pqi_raid_path_request *request, u8 cmd,
  460. u8 *scsi3addr, void *buffer, size_t buffer_length,
  461. u16 vpd_page, enum dma_data_direction *dir)
  462. {
  463. u8 *cdb;
  464. size_t cdb_length = buffer_length;
  465. memset(request, 0, sizeof(*request));
  466. request->header.iu_type = PQI_REQUEST_IU_RAID_PATH_IO;
  467. put_unaligned_le16(offsetof(struct pqi_raid_path_request,
  468. sg_descriptors[1]) - PQI_REQUEST_HEADER_LENGTH,
  469. &request->header.iu_length);
  470. put_unaligned_le32(buffer_length, &request->buffer_length);
  471. memcpy(request->lun_number, scsi3addr, sizeof(request->lun_number));
  472. request->task_attribute = SOP_TASK_ATTRIBUTE_SIMPLE;
  473. request->additional_cdb_bytes_usage = SOP_ADDITIONAL_CDB_BYTES_0;
  474. cdb = request->cdb;
  475. switch (cmd) {
  476. case TEST_UNIT_READY:
  477. request->data_direction = SOP_READ_FLAG;
  478. cdb[0] = TEST_UNIT_READY;
  479. break;
  480. case INQUIRY:
  481. request->data_direction = SOP_READ_FLAG;
  482. cdb[0] = INQUIRY;
  483. if (vpd_page & VPD_PAGE) {
  484. cdb[1] = 0x1;
  485. cdb[2] = (u8)vpd_page;
  486. }
  487. cdb[4] = (u8)cdb_length;
  488. break;
  489. case CISS_REPORT_LOG:
  490. case CISS_REPORT_PHYS:
  491. request->data_direction = SOP_READ_FLAG;
  492. cdb[0] = cmd;
  493. if (cmd == CISS_REPORT_PHYS) {
  494. if (ctrl_info->rpl_extended_format_4_5_supported)
  495. cdb[1] = CISS_REPORT_PHYS_FLAG_EXTENDED_FORMAT_4;
  496. else
  497. cdb[1] = CISS_REPORT_PHYS_FLAG_EXTENDED_FORMAT_2;
  498. } else {
  499. cdb[1] = ctrl_info->ciss_report_log_flags;
  500. }
  501. put_unaligned_be32(cdb_length, &cdb[6]);
  502. break;
  503. case CISS_GET_RAID_MAP:
  504. request->data_direction = SOP_READ_FLAG;
  505. cdb[0] = CISS_READ;
  506. cdb[1] = CISS_GET_RAID_MAP;
  507. put_unaligned_be32(cdb_length, &cdb[6]);
  508. break;
  509. case SA_FLUSH_CACHE:
  510. request->header.driver_flags = PQI_DRIVER_NONBLOCKABLE_REQUEST;
  511. request->data_direction = SOP_WRITE_FLAG;
  512. cdb[0] = BMIC_WRITE;
  513. cdb[6] = BMIC_FLUSH_CACHE;
  514. put_unaligned_be16(cdb_length, &cdb[7]);
  515. break;
  516. case BMIC_SENSE_DIAG_OPTIONS:
  517. cdb_length = 0;
  518. fallthrough;
  519. case BMIC_IDENTIFY_CONTROLLER:
  520. case BMIC_IDENTIFY_PHYSICAL_DEVICE:
  521. case BMIC_SENSE_SUBSYSTEM_INFORMATION:
  522. case BMIC_SENSE_FEATURE:
  523. request->data_direction = SOP_READ_FLAG;
  524. cdb[0] = BMIC_READ;
  525. cdb[6] = cmd;
  526. put_unaligned_be16(cdb_length, &cdb[7]);
  527. break;
  528. case BMIC_SET_DIAG_OPTIONS:
  529. cdb_length = 0;
  530. fallthrough;
  531. case BMIC_WRITE_HOST_WELLNESS:
  532. request->data_direction = SOP_WRITE_FLAG;
  533. cdb[0] = BMIC_WRITE;
  534. cdb[6] = cmd;
  535. put_unaligned_be16(cdb_length, &cdb[7]);
  536. break;
  537. case BMIC_CSMI_PASSTHRU:
  538. request->data_direction = SOP_BIDIRECTIONAL;
  539. cdb[0] = BMIC_WRITE;
  540. cdb[5] = CSMI_CC_SAS_SMP_PASSTHRU;
  541. cdb[6] = cmd;
  542. put_unaligned_be16(cdb_length, &cdb[7]);
  543. break;
  544. default:
  545. dev_err(&ctrl_info->pci_dev->dev, "unknown command 0x%c\n", cmd);
  546. break;
  547. }
  548. switch (request->data_direction) {
  549. case SOP_READ_FLAG:
  550. *dir = DMA_FROM_DEVICE;
  551. break;
  552. case SOP_WRITE_FLAG:
  553. *dir = DMA_TO_DEVICE;
  554. break;
  555. case SOP_NO_DIRECTION_FLAG:
  556. *dir = DMA_NONE;
  557. break;
  558. default:
  559. *dir = DMA_BIDIRECTIONAL;
  560. break;
  561. }
  562. return pqi_map_single(ctrl_info->pci_dev, &request->sg_descriptors[0],
  563. buffer, buffer_length, *dir);
  564. }
  565. static inline void pqi_reinit_io_request(struct pqi_io_request *io_request)
  566. {
  567. io_request->scmd = NULL;
  568. io_request->status = 0;
  569. io_request->error_info = NULL;
  570. io_request->raid_bypass = false;
  571. }
  572. static struct pqi_io_request *pqi_alloc_io_request(
  573. struct pqi_ctrl_info *ctrl_info)
  574. {
  575. struct pqi_io_request *io_request;
  576. u16 i = ctrl_info->next_io_request_slot; /* benignly racy */
  577. while (1) {
  578. io_request = &ctrl_info->io_request_pool[i];
  579. if (atomic_inc_return(&io_request->refcount) == 1)
  580. break;
  581. atomic_dec(&io_request->refcount);
  582. i = (i + 1) % ctrl_info->max_io_slots;
  583. }
  584. /* benignly racy */
  585. ctrl_info->next_io_request_slot = (i + 1) % ctrl_info->max_io_slots;
  586. pqi_reinit_io_request(io_request);
  587. return io_request;
  588. }
  589. static void pqi_free_io_request(struct pqi_io_request *io_request)
  590. {
  591. atomic_dec(&io_request->refcount);
  592. }
  593. static int pqi_send_scsi_raid_request(struct pqi_ctrl_info *ctrl_info, u8 cmd,
  594. u8 *scsi3addr, void *buffer, size_t buffer_length, u16 vpd_page,
  595. struct pqi_raid_error_info *error_info)
  596. {
  597. int rc;
  598. struct pqi_raid_path_request request;
  599. enum dma_data_direction dir;
  600. rc = pqi_build_raid_path_request(ctrl_info, &request, cmd, scsi3addr,
  601. buffer, buffer_length, vpd_page, &dir);
  602. if (rc)
  603. return rc;
  604. rc = pqi_submit_raid_request_synchronous(ctrl_info, &request.header, 0, error_info);
  605. pqi_pci_unmap(ctrl_info->pci_dev, request.sg_descriptors, 1, dir);
  606. return rc;
  607. }
  608. /* helper functions for pqi_send_scsi_raid_request */
  609. static inline int pqi_send_ctrl_raid_request(struct pqi_ctrl_info *ctrl_info,
  610. u8 cmd, void *buffer, size_t buffer_length)
  611. {
  612. return pqi_send_scsi_raid_request(ctrl_info, cmd, RAID_CTLR_LUNID,
  613. buffer, buffer_length, 0, NULL);
  614. }
  615. static inline int pqi_send_ctrl_raid_with_error(struct pqi_ctrl_info *ctrl_info,
  616. u8 cmd, void *buffer, size_t buffer_length,
  617. struct pqi_raid_error_info *error_info)
  618. {
  619. return pqi_send_scsi_raid_request(ctrl_info, cmd, RAID_CTLR_LUNID,
  620. buffer, buffer_length, 0, error_info);
  621. }
  622. static inline int pqi_identify_controller(struct pqi_ctrl_info *ctrl_info,
  623. struct bmic_identify_controller *buffer)
  624. {
  625. return pqi_send_ctrl_raid_request(ctrl_info, BMIC_IDENTIFY_CONTROLLER,
  626. buffer, sizeof(*buffer));
  627. }
  628. static inline int pqi_sense_subsystem_info(struct pqi_ctrl_info *ctrl_info,
  629. struct bmic_sense_subsystem_info *sense_info)
  630. {
  631. return pqi_send_ctrl_raid_request(ctrl_info,
  632. BMIC_SENSE_SUBSYSTEM_INFORMATION, sense_info,
  633. sizeof(*sense_info));
  634. }
  635. static inline int pqi_scsi_inquiry(struct pqi_ctrl_info *ctrl_info,
  636. u8 *scsi3addr, u16 vpd_page, void *buffer, size_t buffer_length)
  637. {
  638. return pqi_send_scsi_raid_request(ctrl_info, INQUIRY, scsi3addr,
  639. buffer, buffer_length, vpd_page, NULL);
  640. }
  641. static int pqi_identify_physical_device(struct pqi_ctrl_info *ctrl_info,
  642. struct pqi_scsi_dev *device,
  643. struct bmic_identify_physical_device *buffer, size_t buffer_length)
  644. {
  645. int rc;
  646. enum dma_data_direction dir;
  647. u16 bmic_device_index;
  648. struct pqi_raid_path_request request;
  649. rc = pqi_build_raid_path_request(ctrl_info, &request,
  650. BMIC_IDENTIFY_PHYSICAL_DEVICE, RAID_CTLR_LUNID, buffer,
  651. buffer_length, 0, &dir);
  652. if (rc)
  653. return rc;
  654. bmic_device_index = CISS_GET_DRIVE_NUMBER(device->scsi3addr);
  655. request.cdb[2] = (u8)bmic_device_index;
  656. request.cdb[9] = (u8)(bmic_device_index >> 8);
  657. rc = pqi_submit_raid_request_synchronous(ctrl_info, &request.header, 0, NULL);
  658. pqi_pci_unmap(ctrl_info->pci_dev, request.sg_descriptors, 1, dir);
  659. return rc;
  660. }
  661. static inline u32 pqi_aio_limit_to_bytes(__le16 *limit)
  662. {
  663. u32 bytes;
  664. bytes = get_unaligned_le16(limit);
  665. if (bytes == 0)
  666. bytes = ~0;
  667. else
  668. bytes *= 1024;
  669. return bytes;
  670. }
  671. #pragma pack(1)
  672. struct bmic_sense_feature_buffer {
  673. struct bmic_sense_feature_buffer_header header;
  674. struct bmic_sense_feature_io_page_aio_subpage aio_subpage;
  675. };
  676. #pragma pack()
  677. #define MINIMUM_AIO_SUBPAGE_BUFFER_LENGTH \
  678. offsetofend(struct bmic_sense_feature_buffer, \
  679. aio_subpage.max_write_raid_1_10_3drive)
  680. #define MINIMUM_AIO_SUBPAGE_LENGTH \
  681. (offsetofend(struct bmic_sense_feature_io_page_aio_subpage, \
  682. max_write_raid_1_10_3drive) - \
  683. sizeof_field(struct bmic_sense_feature_io_page_aio_subpage, header))
  684. static int pqi_get_advanced_raid_bypass_config(struct pqi_ctrl_info *ctrl_info)
  685. {
  686. int rc;
  687. enum dma_data_direction dir;
  688. struct pqi_raid_path_request request;
  689. struct bmic_sense_feature_buffer *buffer;
  690. buffer = kmalloc(sizeof(*buffer), GFP_KERNEL);
  691. if (!buffer)
  692. return -ENOMEM;
  693. rc = pqi_build_raid_path_request(ctrl_info, &request, BMIC_SENSE_FEATURE, RAID_CTLR_LUNID,
  694. buffer, sizeof(*buffer), 0, &dir);
  695. if (rc)
  696. goto error;
  697. request.cdb[2] = BMIC_SENSE_FEATURE_IO_PAGE;
  698. request.cdb[3] = BMIC_SENSE_FEATURE_IO_PAGE_AIO_SUBPAGE;
  699. rc = pqi_submit_raid_request_synchronous(ctrl_info, &request.header, 0, NULL);
  700. pqi_pci_unmap(ctrl_info->pci_dev, request.sg_descriptors, 1, dir);
  701. if (rc)
  702. goto error;
  703. if (buffer->header.page_code != BMIC_SENSE_FEATURE_IO_PAGE ||
  704. buffer->header.subpage_code !=
  705. BMIC_SENSE_FEATURE_IO_PAGE_AIO_SUBPAGE ||
  706. get_unaligned_le16(&buffer->header.buffer_length) <
  707. MINIMUM_AIO_SUBPAGE_BUFFER_LENGTH ||
  708. buffer->aio_subpage.header.page_code !=
  709. BMIC_SENSE_FEATURE_IO_PAGE ||
  710. buffer->aio_subpage.header.subpage_code !=
  711. BMIC_SENSE_FEATURE_IO_PAGE_AIO_SUBPAGE ||
  712. get_unaligned_le16(&buffer->aio_subpage.header.page_length) <
  713. MINIMUM_AIO_SUBPAGE_LENGTH) {
  714. goto error;
  715. }
  716. ctrl_info->max_transfer_encrypted_sas_sata =
  717. pqi_aio_limit_to_bytes(
  718. &buffer->aio_subpage.max_transfer_encrypted_sas_sata);
  719. ctrl_info->max_transfer_encrypted_nvme =
  720. pqi_aio_limit_to_bytes(
  721. &buffer->aio_subpage.max_transfer_encrypted_nvme);
  722. ctrl_info->max_write_raid_5_6 =
  723. pqi_aio_limit_to_bytes(
  724. &buffer->aio_subpage.max_write_raid_5_6);
  725. ctrl_info->max_write_raid_1_10_2drive =
  726. pqi_aio_limit_to_bytes(
  727. &buffer->aio_subpage.max_write_raid_1_10_2drive);
  728. ctrl_info->max_write_raid_1_10_3drive =
  729. pqi_aio_limit_to_bytes(
  730. &buffer->aio_subpage.max_write_raid_1_10_3drive);
  731. error:
  732. kfree(buffer);
  733. return rc;
  734. }
  735. static int pqi_flush_cache(struct pqi_ctrl_info *ctrl_info,
  736. enum bmic_flush_cache_shutdown_event shutdown_event)
  737. {
  738. int rc;
  739. struct bmic_flush_cache *flush_cache;
  740. flush_cache = kzalloc(sizeof(*flush_cache), GFP_KERNEL);
  741. if (!flush_cache)
  742. return -ENOMEM;
  743. flush_cache->shutdown_event = shutdown_event;
  744. rc = pqi_send_ctrl_raid_request(ctrl_info, SA_FLUSH_CACHE, flush_cache,
  745. sizeof(*flush_cache));
  746. kfree(flush_cache);
  747. return rc;
  748. }
  749. int pqi_csmi_smp_passthru(struct pqi_ctrl_info *ctrl_info,
  750. struct bmic_csmi_smp_passthru_buffer *buffer, size_t buffer_length,
  751. struct pqi_raid_error_info *error_info)
  752. {
  753. return pqi_send_ctrl_raid_with_error(ctrl_info, BMIC_CSMI_PASSTHRU,
  754. buffer, buffer_length, error_info);
  755. }
  756. #define PQI_FETCH_PTRAID_DATA (1 << 31)
  757. static int pqi_set_diag_rescan(struct pqi_ctrl_info *ctrl_info)
  758. {
  759. int rc;
  760. struct bmic_diag_options *diag;
  761. diag = kzalloc(sizeof(*diag), GFP_KERNEL);
  762. if (!diag)
  763. return -ENOMEM;
  764. rc = pqi_send_ctrl_raid_request(ctrl_info, BMIC_SENSE_DIAG_OPTIONS,
  765. diag, sizeof(*diag));
  766. if (rc)
  767. goto out;
  768. diag->options |= cpu_to_le32(PQI_FETCH_PTRAID_DATA);
  769. rc = pqi_send_ctrl_raid_request(ctrl_info, BMIC_SET_DIAG_OPTIONS, diag,
  770. sizeof(*diag));
  771. out:
  772. kfree(diag);
  773. return rc;
  774. }
  775. static inline int pqi_write_host_wellness(struct pqi_ctrl_info *ctrl_info,
  776. void *buffer, size_t buffer_length)
  777. {
  778. return pqi_send_ctrl_raid_request(ctrl_info, BMIC_WRITE_HOST_WELLNESS,
  779. buffer, buffer_length);
  780. }
  781. #pragma pack(1)
  782. struct bmic_host_wellness_driver_version {
  783. u8 start_tag[4];
  784. u8 driver_version_tag[2];
  785. __le16 driver_version_length;
  786. char driver_version[32];
  787. u8 dont_write_tag[2];
  788. u8 end_tag[2];
  789. };
  790. #pragma pack()
  791. static int pqi_write_driver_version_to_host_wellness(
  792. struct pqi_ctrl_info *ctrl_info)
  793. {
  794. int rc;
  795. struct bmic_host_wellness_driver_version *buffer;
  796. size_t buffer_length;
  797. buffer_length = sizeof(*buffer);
  798. buffer = kmalloc(buffer_length, GFP_KERNEL);
  799. if (!buffer)
  800. return -ENOMEM;
  801. buffer->start_tag[0] = '<';
  802. buffer->start_tag[1] = 'H';
  803. buffer->start_tag[2] = 'W';
  804. buffer->start_tag[3] = '>';
  805. buffer->driver_version_tag[0] = 'D';
  806. buffer->driver_version_tag[1] = 'V';
  807. put_unaligned_le16(sizeof(buffer->driver_version),
  808. &buffer->driver_version_length);
  809. strncpy(buffer->driver_version, "Linux " DRIVER_VERSION,
  810. sizeof(buffer->driver_version) - 1);
  811. buffer->driver_version[sizeof(buffer->driver_version) - 1] = '\0';
  812. buffer->dont_write_tag[0] = 'D';
  813. buffer->dont_write_tag[1] = 'W';
  814. buffer->end_tag[0] = 'Z';
  815. buffer->end_tag[1] = 'Z';
  816. rc = pqi_write_host_wellness(ctrl_info, buffer, buffer_length);
  817. kfree(buffer);
  818. return rc;
  819. }
  820. #pragma pack(1)
  821. struct bmic_host_wellness_time {
  822. u8 start_tag[4];
  823. u8 time_tag[2];
  824. __le16 time_length;
  825. u8 time[8];
  826. u8 dont_write_tag[2];
  827. u8 end_tag[2];
  828. };
  829. #pragma pack()
  830. static int pqi_write_current_time_to_host_wellness(
  831. struct pqi_ctrl_info *ctrl_info)
  832. {
  833. int rc;
  834. struct bmic_host_wellness_time *buffer;
  835. size_t buffer_length;
  836. time64_t local_time;
  837. unsigned int year;
  838. struct tm tm;
  839. buffer_length = sizeof(*buffer);
  840. buffer = kmalloc(buffer_length, GFP_KERNEL);
  841. if (!buffer)
  842. return -ENOMEM;
  843. buffer->start_tag[0] = '<';
  844. buffer->start_tag[1] = 'H';
  845. buffer->start_tag[2] = 'W';
  846. buffer->start_tag[3] = '>';
  847. buffer->time_tag[0] = 'T';
  848. buffer->time_tag[1] = 'D';
  849. put_unaligned_le16(sizeof(buffer->time),
  850. &buffer->time_length);
  851. local_time = ktime_get_real_seconds();
  852. time64_to_tm(local_time, -sys_tz.tz_minuteswest * 60, &tm);
  853. year = tm.tm_year + 1900;
  854. buffer->time[0] = bin2bcd(tm.tm_hour);
  855. buffer->time[1] = bin2bcd(tm.tm_min);
  856. buffer->time[2] = bin2bcd(tm.tm_sec);
  857. buffer->time[3] = 0;
  858. buffer->time[4] = bin2bcd(tm.tm_mon + 1);
  859. buffer->time[5] = bin2bcd(tm.tm_mday);
  860. buffer->time[6] = bin2bcd(year / 100);
  861. buffer->time[7] = bin2bcd(year % 100);
  862. buffer->dont_write_tag[0] = 'D';
  863. buffer->dont_write_tag[1] = 'W';
  864. buffer->end_tag[0] = 'Z';
  865. buffer->end_tag[1] = 'Z';
  866. rc = pqi_write_host_wellness(ctrl_info, buffer, buffer_length);
  867. kfree(buffer);
  868. return rc;
  869. }
  870. #define PQI_UPDATE_TIME_WORK_INTERVAL (24UL * 60 * 60 * HZ)
  871. static void pqi_update_time_worker(struct work_struct *work)
  872. {
  873. int rc;
  874. struct pqi_ctrl_info *ctrl_info;
  875. ctrl_info = container_of(to_delayed_work(work), struct pqi_ctrl_info,
  876. update_time_work);
  877. rc = pqi_write_current_time_to_host_wellness(ctrl_info);
  878. if (rc)
  879. dev_warn(&ctrl_info->pci_dev->dev,
  880. "error updating time on controller\n");
  881. schedule_delayed_work(&ctrl_info->update_time_work,
  882. PQI_UPDATE_TIME_WORK_INTERVAL);
  883. }
  884. static inline void pqi_schedule_update_time_worker(struct pqi_ctrl_info *ctrl_info)
  885. {
  886. schedule_delayed_work(&ctrl_info->update_time_work, 0);
  887. }
  888. static inline void pqi_cancel_update_time_worker(struct pqi_ctrl_info *ctrl_info)
  889. {
  890. cancel_delayed_work_sync(&ctrl_info->update_time_work);
  891. }
  892. static inline int pqi_report_luns(struct pqi_ctrl_info *ctrl_info, u8 cmd, void *buffer,
  893. size_t buffer_length)
  894. {
  895. return pqi_send_ctrl_raid_request(ctrl_info, cmd, buffer, buffer_length);
  896. }
  897. static int pqi_report_phys_logical_luns(struct pqi_ctrl_info *ctrl_info, u8 cmd, void **buffer)
  898. {
  899. int rc;
  900. size_t lun_list_length;
  901. size_t lun_data_length;
  902. size_t new_lun_list_length;
  903. void *lun_data = NULL;
  904. struct report_lun_header *report_lun_header;
  905. report_lun_header = kmalloc(sizeof(*report_lun_header), GFP_KERNEL);
  906. if (!report_lun_header) {
  907. rc = -ENOMEM;
  908. goto out;
  909. }
  910. rc = pqi_report_luns(ctrl_info, cmd, report_lun_header, sizeof(*report_lun_header));
  911. if (rc)
  912. goto out;
  913. lun_list_length = get_unaligned_be32(&report_lun_header->list_length);
  914. again:
  915. lun_data_length = sizeof(struct report_lun_header) + lun_list_length;
  916. lun_data = kmalloc(lun_data_length, GFP_KERNEL);
  917. if (!lun_data) {
  918. rc = -ENOMEM;
  919. goto out;
  920. }
  921. if (lun_list_length == 0) {
  922. memcpy(lun_data, report_lun_header, sizeof(*report_lun_header));
  923. goto out;
  924. }
  925. rc = pqi_report_luns(ctrl_info, cmd, lun_data, lun_data_length);
  926. if (rc)
  927. goto out;
  928. new_lun_list_length =
  929. get_unaligned_be32(&((struct report_lun_header *)lun_data)->list_length);
  930. if (new_lun_list_length > lun_list_length) {
  931. lun_list_length = new_lun_list_length;
  932. kfree(lun_data);
  933. goto again;
  934. }
  935. out:
  936. kfree(report_lun_header);
  937. if (rc) {
  938. kfree(lun_data);
  939. lun_data = NULL;
  940. }
  941. *buffer = lun_data;
  942. return rc;
  943. }
  944. static inline int pqi_report_phys_luns(struct pqi_ctrl_info *ctrl_info, void **buffer)
  945. {
  946. int rc;
  947. unsigned int i;
  948. u8 rpl_response_format;
  949. u32 num_physicals;
  950. size_t rpl_16byte_wwid_list_length;
  951. void *rpl_list;
  952. struct report_lun_header *rpl_header;
  953. struct report_phys_lun_8byte_wwid_list *rpl_8byte_wwid_list;
  954. struct report_phys_lun_16byte_wwid_list *rpl_16byte_wwid_list;
  955. rc = pqi_report_phys_logical_luns(ctrl_info, CISS_REPORT_PHYS, &rpl_list);
  956. if (rc)
  957. return rc;
  958. if (ctrl_info->rpl_extended_format_4_5_supported) {
  959. rpl_header = rpl_list;
  960. rpl_response_format = rpl_header->flags & CISS_REPORT_PHYS_FLAG_EXTENDED_FORMAT_MASK;
  961. if (rpl_response_format == CISS_REPORT_PHYS_FLAG_EXTENDED_FORMAT_4) {
  962. *buffer = rpl_list;
  963. return 0;
  964. } else if (rpl_response_format != CISS_REPORT_PHYS_FLAG_EXTENDED_FORMAT_2) {
  965. dev_err(&ctrl_info->pci_dev->dev,
  966. "RPL returned unsupported data format %u\n",
  967. rpl_response_format);
  968. return -EINVAL;
  969. } else {
  970. dev_warn(&ctrl_info->pci_dev->dev,
  971. "RPL returned extended format 2 instead of 4\n");
  972. }
  973. }
  974. rpl_8byte_wwid_list = rpl_list;
  975. num_physicals = get_unaligned_be32(&rpl_8byte_wwid_list->header.list_length) / sizeof(rpl_8byte_wwid_list->lun_entries[0]);
  976. rpl_16byte_wwid_list_length = sizeof(struct report_lun_header) + (num_physicals * sizeof(struct report_phys_lun_16byte_wwid));
  977. rpl_16byte_wwid_list = kmalloc(rpl_16byte_wwid_list_length, GFP_KERNEL);
  978. if (!rpl_16byte_wwid_list)
  979. return -ENOMEM;
  980. put_unaligned_be32(num_physicals * sizeof(struct report_phys_lun_16byte_wwid),
  981. &rpl_16byte_wwid_list->header.list_length);
  982. rpl_16byte_wwid_list->header.flags = rpl_8byte_wwid_list->header.flags;
  983. for (i = 0; i < num_physicals; i++) {
  984. memcpy(&rpl_16byte_wwid_list->lun_entries[i].lunid, &rpl_8byte_wwid_list->lun_entries[i].lunid, sizeof(rpl_8byte_wwid_list->lun_entries[i].lunid));
  985. memcpy(&rpl_16byte_wwid_list->lun_entries[i].wwid[0], &rpl_8byte_wwid_list->lun_entries[i].wwid, sizeof(rpl_8byte_wwid_list->lun_entries[i].wwid));
  986. memset(&rpl_16byte_wwid_list->lun_entries[i].wwid[8], 0, 8);
  987. rpl_16byte_wwid_list->lun_entries[i].device_type = rpl_8byte_wwid_list->lun_entries[i].device_type;
  988. rpl_16byte_wwid_list->lun_entries[i].device_flags = rpl_8byte_wwid_list->lun_entries[i].device_flags;
  989. rpl_16byte_wwid_list->lun_entries[i].lun_count = rpl_8byte_wwid_list->lun_entries[i].lun_count;
  990. rpl_16byte_wwid_list->lun_entries[i].redundant_paths = rpl_8byte_wwid_list->lun_entries[i].redundant_paths;
  991. rpl_16byte_wwid_list->lun_entries[i].aio_handle = rpl_8byte_wwid_list->lun_entries[i].aio_handle;
  992. }
  993. kfree(rpl_8byte_wwid_list);
  994. *buffer = rpl_16byte_wwid_list;
  995. return 0;
  996. }
  997. static inline int pqi_report_logical_luns(struct pqi_ctrl_info *ctrl_info, void **buffer)
  998. {
  999. return pqi_report_phys_logical_luns(ctrl_info, CISS_REPORT_LOG, buffer);
  1000. }
  1001. static int pqi_get_device_lists(struct pqi_ctrl_info *ctrl_info,
  1002. struct report_phys_lun_16byte_wwid_list **physdev_list,
  1003. struct report_log_lun_list **logdev_list)
  1004. {
  1005. int rc;
  1006. size_t logdev_list_length;
  1007. size_t logdev_data_length;
  1008. struct report_log_lun_list *internal_logdev_list;
  1009. struct report_log_lun_list *logdev_data;
  1010. struct report_lun_header report_lun_header;
  1011. rc = pqi_report_phys_luns(ctrl_info, (void **)physdev_list);
  1012. if (rc)
  1013. dev_err(&ctrl_info->pci_dev->dev,
  1014. "report physical LUNs failed\n");
  1015. rc = pqi_report_logical_luns(ctrl_info, (void **)logdev_list);
  1016. if (rc)
  1017. dev_err(&ctrl_info->pci_dev->dev,
  1018. "report logical LUNs failed\n");
  1019. /*
  1020. * Tack the controller itself onto the end of the logical device list.
  1021. */
  1022. logdev_data = *logdev_list;
  1023. if (logdev_data) {
  1024. logdev_list_length =
  1025. get_unaligned_be32(&logdev_data->header.list_length);
  1026. } else {
  1027. memset(&report_lun_header, 0, sizeof(report_lun_header));
  1028. logdev_data =
  1029. (struct report_log_lun_list *)&report_lun_header;
  1030. logdev_list_length = 0;
  1031. }
  1032. logdev_data_length = sizeof(struct report_lun_header) +
  1033. logdev_list_length;
  1034. internal_logdev_list = kmalloc(logdev_data_length +
  1035. sizeof(struct report_log_lun), GFP_KERNEL);
  1036. if (!internal_logdev_list) {
  1037. kfree(*logdev_list);
  1038. *logdev_list = NULL;
  1039. return -ENOMEM;
  1040. }
  1041. memcpy(internal_logdev_list, logdev_data, logdev_data_length);
  1042. memset((u8 *)internal_logdev_list + logdev_data_length, 0,
  1043. sizeof(struct report_log_lun));
  1044. put_unaligned_be32(logdev_list_length +
  1045. sizeof(struct report_log_lun),
  1046. &internal_logdev_list->header.list_length);
  1047. kfree(*logdev_list);
  1048. *logdev_list = internal_logdev_list;
  1049. return 0;
  1050. }
  1051. static inline void pqi_set_bus_target_lun(struct pqi_scsi_dev *device,
  1052. int bus, int target, int lun)
  1053. {
  1054. device->bus = bus;
  1055. device->target = target;
  1056. device->lun = lun;
  1057. }
  1058. static void pqi_assign_bus_target_lun(struct pqi_scsi_dev *device)
  1059. {
  1060. u8 *scsi3addr;
  1061. u32 lunid;
  1062. int bus;
  1063. int target;
  1064. int lun;
  1065. scsi3addr = device->scsi3addr;
  1066. lunid = get_unaligned_le32(scsi3addr);
  1067. if (pqi_is_hba_lunid(scsi3addr)) {
  1068. /* The specified device is the controller. */
  1069. pqi_set_bus_target_lun(device, PQI_HBA_BUS, 0, lunid & 0x3fff);
  1070. device->target_lun_valid = true;
  1071. return;
  1072. }
  1073. if (pqi_is_logical_device(device)) {
  1074. if (device->is_external_raid_device) {
  1075. bus = PQI_EXTERNAL_RAID_VOLUME_BUS;
  1076. target = (lunid >> 16) & 0x3fff;
  1077. lun = lunid & 0xff;
  1078. } else {
  1079. bus = PQI_RAID_VOLUME_BUS;
  1080. target = 0;
  1081. lun = lunid & 0x3fff;
  1082. }
  1083. pqi_set_bus_target_lun(device, bus, target, lun);
  1084. device->target_lun_valid = true;
  1085. return;
  1086. }
  1087. /*
  1088. * Defer target and LUN assignment for non-controller physical devices
  1089. * because the SAS transport layer will make these assignments later.
  1090. */
  1091. pqi_set_bus_target_lun(device, PQI_PHYSICAL_DEVICE_BUS, 0, 0);
  1092. }
  1093. static void pqi_get_raid_level(struct pqi_ctrl_info *ctrl_info,
  1094. struct pqi_scsi_dev *device)
  1095. {
  1096. int rc;
  1097. u8 raid_level;
  1098. u8 *buffer;
  1099. raid_level = SA_RAID_UNKNOWN;
  1100. buffer = kmalloc(64, GFP_KERNEL);
  1101. if (buffer) {
  1102. rc = pqi_scsi_inquiry(ctrl_info, device->scsi3addr,
  1103. VPD_PAGE | CISS_VPD_LV_DEVICE_GEOMETRY, buffer, 64);
  1104. if (rc == 0) {
  1105. raid_level = buffer[8];
  1106. if (raid_level > SA_RAID_MAX)
  1107. raid_level = SA_RAID_UNKNOWN;
  1108. }
  1109. kfree(buffer);
  1110. }
  1111. device->raid_level = raid_level;
  1112. }
  1113. static int pqi_validate_raid_map(struct pqi_ctrl_info *ctrl_info,
  1114. struct pqi_scsi_dev *device, struct raid_map *raid_map)
  1115. {
  1116. char *err_msg;
  1117. u32 raid_map_size;
  1118. u32 r5or6_blocks_per_row;
  1119. raid_map_size = get_unaligned_le32(&raid_map->structure_size);
  1120. if (raid_map_size < offsetof(struct raid_map, disk_data)) {
  1121. err_msg = "RAID map too small";
  1122. goto bad_raid_map;
  1123. }
  1124. if (device->raid_level == SA_RAID_1) {
  1125. if (get_unaligned_le16(&raid_map->layout_map_count) != 2) {
  1126. err_msg = "invalid RAID-1 map";
  1127. goto bad_raid_map;
  1128. }
  1129. } else if (device->raid_level == SA_RAID_TRIPLE) {
  1130. if (get_unaligned_le16(&raid_map->layout_map_count) != 3) {
  1131. err_msg = "invalid RAID-1(Triple) map";
  1132. goto bad_raid_map;
  1133. }
  1134. } else if ((device->raid_level == SA_RAID_5 ||
  1135. device->raid_level == SA_RAID_6) &&
  1136. get_unaligned_le16(&raid_map->layout_map_count) > 1) {
  1137. /* RAID 50/60 */
  1138. r5or6_blocks_per_row =
  1139. get_unaligned_le16(&raid_map->strip_size) *
  1140. get_unaligned_le16(&raid_map->data_disks_per_row);
  1141. if (r5or6_blocks_per_row == 0) {
  1142. err_msg = "invalid RAID-5 or RAID-6 map";
  1143. goto bad_raid_map;
  1144. }
  1145. }
  1146. return 0;
  1147. bad_raid_map:
  1148. dev_warn(&ctrl_info->pci_dev->dev,
  1149. "logical device %08x%08x %s\n",
  1150. *((u32 *)&device->scsi3addr),
  1151. *((u32 *)&device->scsi3addr[4]), err_msg);
  1152. return -EINVAL;
  1153. }
  1154. static int pqi_get_raid_map(struct pqi_ctrl_info *ctrl_info,
  1155. struct pqi_scsi_dev *device)
  1156. {
  1157. int rc;
  1158. u32 raid_map_size;
  1159. struct raid_map *raid_map;
  1160. raid_map = kmalloc(sizeof(*raid_map), GFP_KERNEL);
  1161. if (!raid_map)
  1162. return -ENOMEM;
  1163. rc = pqi_send_scsi_raid_request(ctrl_info, CISS_GET_RAID_MAP,
  1164. device->scsi3addr, raid_map, sizeof(*raid_map), 0, NULL);
  1165. if (rc)
  1166. goto error;
  1167. raid_map_size = get_unaligned_le32(&raid_map->structure_size);
  1168. if (raid_map_size > sizeof(*raid_map)) {
  1169. kfree(raid_map);
  1170. raid_map = kmalloc(raid_map_size, GFP_KERNEL);
  1171. if (!raid_map)
  1172. return -ENOMEM;
  1173. rc = pqi_send_scsi_raid_request(ctrl_info, CISS_GET_RAID_MAP,
  1174. device->scsi3addr, raid_map, raid_map_size, 0, NULL);
  1175. if (rc)
  1176. goto error;
  1177. if (get_unaligned_le32(&raid_map->structure_size)
  1178. != raid_map_size) {
  1179. dev_warn(&ctrl_info->pci_dev->dev,
  1180. "requested %u bytes, received %u bytes\n",
  1181. raid_map_size,
  1182. get_unaligned_le32(&raid_map->structure_size));
  1183. rc = -EINVAL;
  1184. goto error;
  1185. }
  1186. }
  1187. rc = pqi_validate_raid_map(ctrl_info, device, raid_map);
  1188. if (rc)
  1189. goto error;
  1190. device->raid_map = raid_map;
  1191. return 0;
  1192. error:
  1193. kfree(raid_map);
  1194. return rc;
  1195. }
  1196. static void pqi_set_max_transfer_encrypted(struct pqi_ctrl_info *ctrl_info,
  1197. struct pqi_scsi_dev *device)
  1198. {
  1199. if (!ctrl_info->lv_drive_type_mix_valid) {
  1200. device->max_transfer_encrypted = ~0;
  1201. return;
  1202. }
  1203. switch (LV_GET_DRIVE_TYPE_MIX(device->scsi3addr)) {
  1204. case LV_DRIVE_TYPE_MIX_SAS_HDD_ONLY:
  1205. case LV_DRIVE_TYPE_MIX_SATA_HDD_ONLY:
  1206. case LV_DRIVE_TYPE_MIX_SAS_OR_SATA_SSD_ONLY:
  1207. case LV_DRIVE_TYPE_MIX_SAS_SSD_ONLY:
  1208. case LV_DRIVE_TYPE_MIX_SATA_SSD_ONLY:
  1209. case LV_DRIVE_TYPE_MIX_SAS_ONLY:
  1210. case LV_DRIVE_TYPE_MIX_SATA_ONLY:
  1211. device->max_transfer_encrypted =
  1212. ctrl_info->max_transfer_encrypted_sas_sata;
  1213. break;
  1214. case LV_DRIVE_TYPE_MIX_NVME_ONLY:
  1215. device->max_transfer_encrypted =
  1216. ctrl_info->max_transfer_encrypted_nvme;
  1217. break;
  1218. case LV_DRIVE_TYPE_MIX_UNKNOWN:
  1219. case LV_DRIVE_TYPE_MIX_NO_RESTRICTION:
  1220. default:
  1221. device->max_transfer_encrypted =
  1222. min(ctrl_info->max_transfer_encrypted_sas_sata,
  1223. ctrl_info->max_transfer_encrypted_nvme);
  1224. break;
  1225. }
  1226. }
  1227. static void pqi_get_raid_bypass_status(struct pqi_ctrl_info *ctrl_info,
  1228. struct pqi_scsi_dev *device)
  1229. {
  1230. int rc;
  1231. u8 *buffer;
  1232. u8 bypass_status;
  1233. buffer = kmalloc(64, GFP_KERNEL);
  1234. if (!buffer)
  1235. return;
  1236. rc = pqi_scsi_inquiry(ctrl_info, device->scsi3addr,
  1237. VPD_PAGE | CISS_VPD_LV_BYPASS_STATUS, buffer, 64);
  1238. if (rc)
  1239. goto out;
  1240. #define RAID_BYPASS_STATUS 4
  1241. #define RAID_BYPASS_CONFIGURED 0x1
  1242. #define RAID_BYPASS_ENABLED 0x2
  1243. bypass_status = buffer[RAID_BYPASS_STATUS];
  1244. device->raid_bypass_configured =
  1245. (bypass_status & RAID_BYPASS_CONFIGURED) != 0;
  1246. if (device->raid_bypass_configured &&
  1247. (bypass_status & RAID_BYPASS_ENABLED) &&
  1248. pqi_get_raid_map(ctrl_info, device) == 0) {
  1249. device->raid_bypass_enabled = true;
  1250. if (get_unaligned_le16(&device->raid_map->flags) &
  1251. RAID_MAP_ENCRYPTION_ENABLED)
  1252. pqi_set_max_transfer_encrypted(ctrl_info, device);
  1253. }
  1254. out:
  1255. kfree(buffer);
  1256. }
  1257. /*
  1258. * Use vendor-specific VPD to determine online/offline status of a volume.
  1259. */
  1260. static void pqi_get_volume_status(struct pqi_ctrl_info *ctrl_info,
  1261. struct pqi_scsi_dev *device)
  1262. {
  1263. int rc;
  1264. size_t page_length;
  1265. u8 volume_status = CISS_LV_STATUS_UNAVAILABLE;
  1266. bool volume_offline = true;
  1267. u32 volume_flags;
  1268. struct ciss_vpd_logical_volume_status *vpd;
  1269. vpd = kmalloc(sizeof(*vpd), GFP_KERNEL);
  1270. if (!vpd)
  1271. goto no_buffer;
  1272. rc = pqi_scsi_inquiry(ctrl_info, device->scsi3addr,
  1273. VPD_PAGE | CISS_VPD_LV_STATUS, vpd, sizeof(*vpd));
  1274. if (rc)
  1275. goto out;
  1276. if (vpd->page_code != CISS_VPD_LV_STATUS)
  1277. goto out;
  1278. page_length = offsetof(struct ciss_vpd_logical_volume_status,
  1279. volume_status) + vpd->page_length;
  1280. if (page_length < sizeof(*vpd))
  1281. goto out;
  1282. volume_status = vpd->volume_status;
  1283. volume_flags = get_unaligned_be32(&vpd->flags);
  1284. volume_offline = (volume_flags & CISS_LV_FLAGS_NO_HOST_IO) != 0;
  1285. out:
  1286. kfree(vpd);
  1287. no_buffer:
  1288. device->volume_status = volume_status;
  1289. device->volume_offline = volume_offline;
  1290. }
  1291. #define PQI_DEVICE_NCQ_PRIO_SUPPORTED 0x01
  1292. #define PQI_DEVICE_PHY_MAP_SUPPORTED 0x10
  1293. static int pqi_get_physical_device_info(struct pqi_ctrl_info *ctrl_info,
  1294. struct pqi_scsi_dev *device,
  1295. struct bmic_identify_physical_device *id_phys)
  1296. {
  1297. int rc;
  1298. memset(id_phys, 0, sizeof(*id_phys));
  1299. rc = pqi_identify_physical_device(ctrl_info, device,
  1300. id_phys, sizeof(*id_phys));
  1301. if (rc) {
  1302. device->queue_depth = PQI_PHYSICAL_DISK_DEFAULT_MAX_QUEUE_DEPTH;
  1303. return rc;
  1304. }
  1305. scsi_sanitize_inquiry_string(&id_phys->model[0], 8);
  1306. scsi_sanitize_inquiry_string(&id_phys->model[8], 16);
  1307. memcpy(device->vendor, &id_phys->model[0], sizeof(device->vendor));
  1308. memcpy(device->model, &id_phys->model[8], sizeof(device->model));
  1309. device->box_index = id_phys->box_index;
  1310. device->phys_box_on_bus = id_phys->phys_box_on_bus;
  1311. device->phy_connected_dev_type = id_phys->phy_connected_dev_type[0];
  1312. device->queue_depth =
  1313. get_unaligned_le16(&id_phys->current_queue_depth_limit);
  1314. device->active_path_index = id_phys->active_path_number;
  1315. device->path_map = id_phys->redundant_path_present_map;
  1316. memcpy(&device->box,
  1317. &id_phys->alternate_paths_phys_box_on_port,
  1318. sizeof(device->box));
  1319. memcpy(&device->phys_connector,
  1320. &id_phys->alternate_paths_phys_connector,
  1321. sizeof(device->phys_connector));
  1322. device->bay = id_phys->phys_bay_in_box;
  1323. device->lun_count = id_phys->multi_lun_device_lun_count;
  1324. if ((id_phys->even_more_flags & PQI_DEVICE_PHY_MAP_SUPPORTED) &&
  1325. id_phys->phy_count)
  1326. device->phy_id =
  1327. id_phys->phy_to_phy_map[device->active_path_index];
  1328. else
  1329. device->phy_id = 0xFF;
  1330. device->ncq_prio_support =
  1331. ((get_unaligned_le32(&id_phys->misc_drive_flags) >> 16) &
  1332. PQI_DEVICE_NCQ_PRIO_SUPPORTED);
  1333. return 0;
  1334. }
  1335. static int pqi_get_logical_device_info(struct pqi_ctrl_info *ctrl_info,
  1336. struct pqi_scsi_dev *device)
  1337. {
  1338. int rc;
  1339. u8 *buffer;
  1340. buffer = kmalloc(64, GFP_KERNEL);
  1341. if (!buffer)
  1342. return -ENOMEM;
  1343. /* Send an inquiry to the device to see what it is. */
  1344. rc = pqi_scsi_inquiry(ctrl_info, device->scsi3addr, 0, buffer, 64);
  1345. if (rc)
  1346. goto out;
  1347. scsi_sanitize_inquiry_string(&buffer[8], 8);
  1348. scsi_sanitize_inquiry_string(&buffer[16], 16);
  1349. device->devtype = buffer[0] & 0x1f;
  1350. memcpy(device->vendor, &buffer[8], sizeof(device->vendor));
  1351. memcpy(device->model, &buffer[16], sizeof(device->model));
  1352. if (device->devtype == TYPE_DISK) {
  1353. if (device->is_external_raid_device) {
  1354. device->raid_level = SA_RAID_UNKNOWN;
  1355. device->volume_status = CISS_LV_OK;
  1356. device->volume_offline = false;
  1357. } else {
  1358. pqi_get_raid_level(ctrl_info, device);
  1359. pqi_get_raid_bypass_status(ctrl_info, device);
  1360. pqi_get_volume_status(ctrl_info, device);
  1361. }
  1362. }
  1363. out:
  1364. kfree(buffer);
  1365. return rc;
  1366. }
  1367. /*
  1368. * Prevent adding drive to OS for some corner cases such as a drive
  1369. * undergoing a sanitize operation. Some OSes will continue to poll
  1370. * the drive until the sanitize completes, which can take hours,
  1371. * resulting in long bootup delays. Commands such as TUR, READ_CAP
  1372. * are allowed, but READ/WRITE cause check condition. So the OS
  1373. * cannot check/read the partition table.
  1374. * Note: devices that have completed sanitize must be re-enabled
  1375. * using the management utility.
  1376. */
  1377. static bool pqi_keep_device_offline(struct pqi_ctrl_info *ctrl_info,
  1378. struct pqi_scsi_dev *device)
  1379. {
  1380. u8 scsi_status;
  1381. int rc;
  1382. enum dma_data_direction dir;
  1383. char *buffer;
  1384. int buffer_length = 64;
  1385. size_t sense_data_length;
  1386. struct scsi_sense_hdr sshdr;
  1387. struct pqi_raid_path_request request;
  1388. struct pqi_raid_error_info error_info;
  1389. bool offline = false; /* Assume keep online */
  1390. /* Do not check controllers. */
  1391. if (pqi_is_hba_lunid(device->scsi3addr))
  1392. return false;
  1393. /* Do not check LVs. */
  1394. if (pqi_is_logical_device(device))
  1395. return false;
  1396. buffer = kmalloc(buffer_length, GFP_KERNEL);
  1397. if (!buffer)
  1398. return false; /* Assume not offline */
  1399. /* Check for SANITIZE in progress using TUR */
  1400. rc = pqi_build_raid_path_request(ctrl_info, &request,
  1401. TEST_UNIT_READY, RAID_CTLR_LUNID, buffer,
  1402. buffer_length, 0, &dir);
  1403. if (rc)
  1404. goto out; /* Assume not offline */
  1405. memcpy(request.lun_number, device->scsi3addr, sizeof(request.lun_number));
  1406. rc = pqi_submit_raid_request_synchronous(ctrl_info, &request.header, 0, &error_info);
  1407. if (rc)
  1408. goto out; /* Assume not offline */
  1409. scsi_status = error_info.status;
  1410. sense_data_length = get_unaligned_le16(&error_info.sense_data_length);
  1411. if (sense_data_length == 0)
  1412. sense_data_length =
  1413. get_unaligned_le16(&error_info.response_data_length);
  1414. if (sense_data_length) {
  1415. if (sense_data_length > sizeof(error_info.data))
  1416. sense_data_length = sizeof(error_info.data);
  1417. /*
  1418. * Check for sanitize in progress: asc:0x04, ascq: 0x1b
  1419. */
  1420. if (scsi_status == SAM_STAT_CHECK_CONDITION &&
  1421. scsi_normalize_sense(error_info.data,
  1422. sense_data_length, &sshdr) &&
  1423. sshdr.sense_key == NOT_READY &&
  1424. sshdr.asc == 0x04 &&
  1425. sshdr.ascq == 0x1b) {
  1426. device->device_offline = true;
  1427. offline = true;
  1428. goto out; /* Keep device offline */
  1429. }
  1430. }
  1431. out:
  1432. kfree(buffer);
  1433. return offline;
  1434. }
  1435. static int pqi_get_device_info_phys_logical(struct pqi_ctrl_info *ctrl_info,
  1436. struct pqi_scsi_dev *device,
  1437. struct bmic_identify_physical_device *id_phys)
  1438. {
  1439. int rc;
  1440. if (device->is_expander_smp_device)
  1441. return 0;
  1442. if (pqi_is_logical_device(device))
  1443. rc = pqi_get_logical_device_info(ctrl_info, device);
  1444. else
  1445. rc = pqi_get_physical_device_info(ctrl_info, device, id_phys);
  1446. return rc;
  1447. }
  1448. static int pqi_get_device_info(struct pqi_ctrl_info *ctrl_info,
  1449. struct pqi_scsi_dev *device,
  1450. struct bmic_identify_physical_device *id_phys)
  1451. {
  1452. int rc;
  1453. rc = pqi_get_device_info_phys_logical(ctrl_info, device, id_phys);
  1454. if (rc == 0 && device->lun_count == 0)
  1455. device->lun_count = 1;
  1456. return rc;
  1457. }
  1458. static void pqi_show_volume_status(struct pqi_ctrl_info *ctrl_info,
  1459. struct pqi_scsi_dev *device)
  1460. {
  1461. char *status;
  1462. static const char unknown_state_str[] =
  1463. "Volume is in an unknown state (%u)";
  1464. char unknown_state_buffer[sizeof(unknown_state_str) + 10];
  1465. switch (device->volume_status) {
  1466. case CISS_LV_OK:
  1467. status = "Volume online";
  1468. break;
  1469. case CISS_LV_FAILED:
  1470. status = "Volume failed";
  1471. break;
  1472. case CISS_LV_NOT_CONFIGURED:
  1473. status = "Volume not configured";
  1474. break;
  1475. case CISS_LV_DEGRADED:
  1476. status = "Volume degraded";
  1477. break;
  1478. case CISS_LV_READY_FOR_RECOVERY:
  1479. status = "Volume ready for recovery operation";
  1480. break;
  1481. case CISS_LV_UNDERGOING_RECOVERY:
  1482. status = "Volume undergoing recovery";
  1483. break;
  1484. case CISS_LV_WRONG_PHYSICAL_DRIVE_REPLACED:
  1485. status = "Wrong physical drive was replaced";
  1486. break;
  1487. case CISS_LV_PHYSICAL_DRIVE_CONNECTION_PROBLEM:
  1488. status = "A physical drive not properly connected";
  1489. break;
  1490. case CISS_LV_HARDWARE_OVERHEATING:
  1491. status = "Hardware is overheating";
  1492. break;
  1493. case CISS_LV_HARDWARE_HAS_OVERHEATED:
  1494. status = "Hardware has overheated";
  1495. break;
  1496. case CISS_LV_UNDERGOING_EXPANSION:
  1497. status = "Volume undergoing expansion";
  1498. break;
  1499. case CISS_LV_NOT_AVAILABLE:
  1500. status = "Volume waiting for transforming volume";
  1501. break;
  1502. case CISS_LV_QUEUED_FOR_EXPANSION:
  1503. status = "Volume queued for expansion";
  1504. break;
  1505. case CISS_LV_DISABLED_SCSI_ID_CONFLICT:
  1506. status = "Volume disabled due to SCSI ID conflict";
  1507. break;
  1508. case CISS_LV_EJECTED:
  1509. status = "Volume has been ejected";
  1510. break;
  1511. case CISS_LV_UNDERGOING_ERASE:
  1512. status = "Volume undergoing background erase";
  1513. break;
  1514. case CISS_LV_READY_FOR_PREDICTIVE_SPARE_REBUILD:
  1515. status = "Volume ready for predictive spare rebuild";
  1516. break;
  1517. case CISS_LV_UNDERGOING_RPI:
  1518. status = "Volume undergoing rapid parity initialization";
  1519. break;
  1520. case CISS_LV_PENDING_RPI:
  1521. status = "Volume queued for rapid parity initialization";
  1522. break;
  1523. case CISS_LV_ENCRYPTED_NO_KEY:
  1524. status = "Encrypted volume inaccessible - key not present";
  1525. break;
  1526. case CISS_LV_UNDERGOING_ENCRYPTION:
  1527. status = "Volume undergoing encryption process";
  1528. break;
  1529. case CISS_LV_UNDERGOING_ENCRYPTION_REKEYING:
  1530. status = "Volume undergoing encryption re-keying process";
  1531. break;
  1532. case CISS_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
  1533. status = "Volume encrypted but encryption is disabled";
  1534. break;
  1535. case CISS_LV_PENDING_ENCRYPTION:
  1536. status = "Volume pending migration to encrypted state";
  1537. break;
  1538. case CISS_LV_PENDING_ENCRYPTION_REKEYING:
  1539. status = "Volume pending encryption rekeying";
  1540. break;
  1541. case CISS_LV_NOT_SUPPORTED:
  1542. status = "Volume not supported on this controller";
  1543. break;
  1544. case CISS_LV_STATUS_UNAVAILABLE:
  1545. status = "Volume status not available";
  1546. break;
  1547. default:
  1548. snprintf(unknown_state_buffer, sizeof(unknown_state_buffer),
  1549. unknown_state_str, device->volume_status);
  1550. status = unknown_state_buffer;
  1551. break;
  1552. }
  1553. dev_info(&ctrl_info->pci_dev->dev,
  1554. "scsi %d:%d:%d:%d %s\n",
  1555. ctrl_info->scsi_host->host_no,
  1556. device->bus, device->target, device->lun, status);
  1557. }
  1558. static void pqi_rescan_worker(struct work_struct *work)
  1559. {
  1560. struct pqi_ctrl_info *ctrl_info;
  1561. ctrl_info = container_of(to_delayed_work(work), struct pqi_ctrl_info,
  1562. rescan_work);
  1563. pqi_scan_scsi_devices(ctrl_info);
  1564. }
  1565. static int pqi_add_device(struct pqi_ctrl_info *ctrl_info,
  1566. struct pqi_scsi_dev *device)
  1567. {
  1568. int rc;
  1569. if (pqi_is_logical_device(device))
  1570. rc = scsi_add_device(ctrl_info->scsi_host, device->bus,
  1571. device->target, device->lun);
  1572. else
  1573. rc = pqi_add_sas_device(ctrl_info->sas_host, device);
  1574. return rc;
  1575. }
  1576. #define PQI_REMOVE_DEVICE_PENDING_IO_TIMEOUT_MSECS (20 * 1000)
  1577. static inline void pqi_remove_device(struct pqi_ctrl_info *ctrl_info, struct pqi_scsi_dev *device)
  1578. {
  1579. int rc;
  1580. int lun;
  1581. for (lun = 0; lun < device->lun_count; lun++) {
  1582. rc = pqi_device_wait_for_pending_io(ctrl_info, device, lun,
  1583. PQI_REMOVE_DEVICE_PENDING_IO_TIMEOUT_MSECS);
  1584. if (rc)
  1585. dev_err(&ctrl_info->pci_dev->dev,
  1586. "scsi %d:%d:%d:%d removing device with %d outstanding command(s)\n",
  1587. ctrl_info->scsi_host->host_no, device->bus,
  1588. device->target, lun,
  1589. atomic_read(&device->scsi_cmds_outstanding[lun]));
  1590. }
  1591. if (pqi_is_logical_device(device))
  1592. scsi_remove_device(device->sdev);
  1593. else
  1594. pqi_remove_sas_device(device);
  1595. pqi_device_remove_start(device);
  1596. }
  1597. /* Assumes the SCSI device list lock is held. */
  1598. static struct pqi_scsi_dev *pqi_find_scsi_dev(struct pqi_ctrl_info *ctrl_info,
  1599. int bus, int target, int lun)
  1600. {
  1601. struct pqi_scsi_dev *device;
  1602. list_for_each_entry(device, &ctrl_info->scsi_device_list, scsi_device_list_entry)
  1603. if (device->bus == bus && device->target == target && device->lun == lun)
  1604. return device;
  1605. return NULL;
  1606. }
  1607. static inline bool pqi_device_equal(struct pqi_scsi_dev *dev1, struct pqi_scsi_dev *dev2)
  1608. {
  1609. if (dev1->is_physical_device != dev2->is_physical_device)
  1610. return false;
  1611. if (dev1->is_physical_device)
  1612. return memcmp(dev1->wwid, dev2->wwid, sizeof(dev1->wwid)) == 0;
  1613. return memcmp(dev1->volume_id, dev2->volume_id, sizeof(dev1->volume_id)) == 0;
  1614. }
  1615. enum pqi_find_result {
  1616. DEVICE_NOT_FOUND,
  1617. DEVICE_CHANGED,
  1618. DEVICE_SAME,
  1619. };
  1620. static enum pqi_find_result pqi_scsi_find_entry(struct pqi_ctrl_info *ctrl_info,
  1621. struct pqi_scsi_dev *device_to_find, struct pqi_scsi_dev **matching_device)
  1622. {
  1623. struct pqi_scsi_dev *device;
  1624. list_for_each_entry(device, &ctrl_info->scsi_device_list, scsi_device_list_entry) {
  1625. if (pqi_scsi3addr_equal(device_to_find->scsi3addr, device->scsi3addr)) {
  1626. *matching_device = device;
  1627. if (pqi_device_equal(device_to_find, device)) {
  1628. if (device_to_find->volume_offline)
  1629. return DEVICE_CHANGED;
  1630. return DEVICE_SAME;
  1631. }
  1632. return DEVICE_CHANGED;
  1633. }
  1634. }
  1635. return DEVICE_NOT_FOUND;
  1636. }
  1637. static inline const char *pqi_device_type(struct pqi_scsi_dev *device)
  1638. {
  1639. if (device->is_expander_smp_device)
  1640. return "Enclosure SMP ";
  1641. return scsi_device_type(device->devtype);
  1642. }
  1643. #define PQI_DEV_INFO_BUFFER_LENGTH 128
  1644. static void pqi_dev_info(struct pqi_ctrl_info *ctrl_info,
  1645. char *action, struct pqi_scsi_dev *device)
  1646. {
  1647. ssize_t count;
  1648. char buffer[PQI_DEV_INFO_BUFFER_LENGTH];
  1649. count = scnprintf(buffer, PQI_DEV_INFO_BUFFER_LENGTH,
  1650. "%d:%d:", ctrl_info->scsi_host->host_no, device->bus);
  1651. if (device->target_lun_valid)
  1652. count += scnprintf(buffer + count,
  1653. PQI_DEV_INFO_BUFFER_LENGTH - count,
  1654. "%d:%d",
  1655. device->target,
  1656. device->lun);
  1657. else
  1658. count += scnprintf(buffer + count,
  1659. PQI_DEV_INFO_BUFFER_LENGTH - count,
  1660. "-:-");
  1661. if (pqi_is_logical_device(device))
  1662. count += scnprintf(buffer + count,
  1663. PQI_DEV_INFO_BUFFER_LENGTH - count,
  1664. " %08x%08x",
  1665. *((u32 *)&device->scsi3addr),
  1666. *((u32 *)&device->scsi3addr[4]));
  1667. else
  1668. count += scnprintf(buffer + count,
  1669. PQI_DEV_INFO_BUFFER_LENGTH - count,
  1670. " %016llx%016llx",
  1671. get_unaligned_be64(&device->wwid[0]),
  1672. get_unaligned_be64(&device->wwid[8]));
  1673. count += scnprintf(buffer + count, PQI_DEV_INFO_BUFFER_LENGTH - count,
  1674. " %s %.8s %.16s ",
  1675. pqi_device_type(device),
  1676. device->vendor,
  1677. device->model);
  1678. if (pqi_is_logical_device(device)) {
  1679. if (device->devtype == TYPE_DISK)
  1680. count += scnprintf(buffer + count,
  1681. PQI_DEV_INFO_BUFFER_LENGTH - count,
  1682. "SSDSmartPathCap%c En%c %-12s",
  1683. device->raid_bypass_configured ? '+' : '-',
  1684. device->raid_bypass_enabled ? '+' : '-',
  1685. pqi_raid_level_to_string(device->raid_level));
  1686. } else {
  1687. count += scnprintf(buffer + count,
  1688. PQI_DEV_INFO_BUFFER_LENGTH - count,
  1689. "AIO%c", device->aio_enabled ? '+' : '-');
  1690. if (device->devtype == TYPE_DISK ||
  1691. device->devtype == TYPE_ZBC)
  1692. count += scnprintf(buffer + count,
  1693. PQI_DEV_INFO_BUFFER_LENGTH - count,
  1694. " qd=%-6d", device->queue_depth);
  1695. }
  1696. dev_info(&ctrl_info->pci_dev->dev, "%s %s\n", action, buffer);
  1697. }
  1698. static bool pqi_raid_maps_equal(struct raid_map *raid_map1, struct raid_map *raid_map2)
  1699. {
  1700. u32 raid_map1_size;
  1701. u32 raid_map2_size;
  1702. if (raid_map1 == NULL || raid_map2 == NULL)
  1703. return raid_map1 == raid_map2;
  1704. raid_map1_size = get_unaligned_le32(&raid_map1->structure_size);
  1705. raid_map2_size = get_unaligned_le32(&raid_map2->structure_size);
  1706. if (raid_map1_size != raid_map2_size)
  1707. return false;
  1708. return memcmp(raid_map1, raid_map2, raid_map1_size) == 0;
  1709. }
  1710. /* Assumes the SCSI device list lock is held. */
  1711. static void pqi_scsi_update_device(struct pqi_ctrl_info *ctrl_info,
  1712. struct pqi_scsi_dev *existing_device, struct pqi_scsi_dev *new_device)
  1713. {
  1714. existing_device->device_type = new_device->device_type;
  1715. existing_device->bus = new_device->bus;
  1716. if (new_device->target_lun_valid) {
  1717. existing_device->target = new_device->target;
  1718. existing_device->lun = new_device->lun;
  1719. existing_device->target_lun_valid = true;
  1720. }
  1721. /* By definition, the scsi3addr and wwid fields are already the same. */
  1722. existing_device->is_physical_device = new_device->is_physical_device;
  1723. memcpy(existing_device->vendor, new_device->vendor, sizeof(existing_device->vendor));
  1724. memcpy(existing_device->model, new_device->model, sizeof(existing_device->model));
  1725. existing_device->sas_address = new_device->sas_address;
  1726. existing_device->queue_depth = new_device->queue_depth;
  1727. existing_device->device_offline = false;
  1728. existing_device->lun_count = new_device->lun_count;
  1729. if (pqi_is_logical_device(existing_device)) {
  1730. existing_device->is_external_raid_device = new_device->is_external_raid_device;
  1731. if (existing_device->devtype == TYPE_DISK) {
  1732. existing_device->raid_level = new_device->raid_level;
  1733. existing_device->volume_status = new_device->volume_status;
  1734. if (ctrl_info->logical_volume_rescan_needed)
  1735. existing_device->rescan = true;
  1736. memset(existing_device->next_bypass_group, 0, sizeof(existing_device->next_bypass_group));
  1737. if (!pqi_raid_maps_equal(existing_device->raid_map, new_device->raid_map)) {
  1738. kfree(existing_device->raid_map);
  1739. existing_device->raid_map = new_device->raid_map;
  1740. /* To prevent this from being freed later. */
  1741. new_device->raid_map = NULL;
  1742. }
  1743. existing_device->raid_bypass_configured = new_device->raid_bypass_configured;
  1744. existing_device->raid_bypass_enabled = new_device->raid_bypass_enabled;
  1745. }
  1746. } else {
  1747. existing_device->aio_enabled = new_device->aio_enabled;
  1748. existing_device->aio_handle = new_device->aio_handle;
  1749. existing_device->is_expander_smp_device = new_device->is_expander_smp_device;
  1750. existing_device->active_path_index = new_device->active_path_index;
  1751. existing_device->phy_id = new_device->phy_id;
  1752. existing_device->path_map = new_device->path_map;
  1753. existing_device->bay = new_device->bay;
  1754. existing_device->box_index = new_device->box_index;
  1755. existing_device->phys_box_on_bus = new_device->phys_box_on_bus;
  1756. existing_device->phy_connected_dev_type = new_device->phy_connected_dev_type;
  1757. memcpy(existing_device->box, new_device->box, sizeof(existing_device->box));
  1758. memcpy(existing_device->phys_connector, new_device->phys_connector, sizeof(existing_device->phys_connector));
  1759. }
  1760. }
  1761. static inline void pqi_free_device(struct pqi_scsi_dev *device)
  1762. {
  1763. if (device) {
  1764. kfree(device->raid_map);
  1765. kfree(device);
  1766. }
  1767. }
  1768. /*
  1769. * Called when exposing a new device to the OS fails in order to re-adjust
  1770. * our internal SCSI device list to match the SCSI ML's view.
  1771. */
  1772. static inline void pqi_fixup_botched_add(struct pqi_ctrl_info *ctrl_info,
  1773. struct pqi_scsi_dev *device)
  1774. {
  1775. unsigned long flags;
  1776. spin_lock_irqsave(&ctrl_info->scsi_device_list_lock, flags);
  1777. list_del(&device->scsi_device_list_entry);
  1778. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  1779. /* Allow the device structure to be freed later. */
  1780. device->keep_device = false;
  1781. }
  1782. static inline bool pqi_is_device_added(struct pqi_scsi_dev *device)
  1783. {
  1784. if (device->is_expander_smp_device)
  1785. return device->sas_port != NULL;
  1786. return device->sdev != NULL;
  1787. }
  1788. static void pqi_update_device_list(struct pqi_ctrl_info *ctrl_info,
  1789. struct pqi_scsi_dev *new_device_list[], unsigned int num_new_devices)
  1790. {
  1791. int rc;
  1792. unsigned int i;
  1793. unsigned long flags;
  1794. enum pqi_find_result find_result;
  1795. struct pqi_scsi_dev *device;
  1796. struct pqi_scsi_dev *next;
  1797. struct pqi_scsi_dev *matching_device;
  1798. LIST_HEAD(add_list);
  1799. LIST_HEAD(delete_list);
  1800. /*
  1801. * The idea here is to do as little work as possible while holding the
  1802. * spinlock. That's why we go to great pains to defer anything other
  1803. * than updating the internal device list until after we release the
  1804. * spinlock.
  1805. */
  1806. spin_lock_irqsave(&ctrl_info->scsi_device_list_lock, flags);
  1807. /* Assume that all devices in the existing list have gone away. */
  1808. list_for_each_entry(device, &ctrl_info->scsi_device_list, scsi_device_list_entry)
  1809. device->device_gone = true;
  1810. for (i = 0; i < num_new_devices; i++) {
  1811. device = new_device_list[i];
  1812. find_result = pqi_scsi_find_entry(ctrl_info, device,
  1813. &matching_device);
  1814. switch (find_result) {
  1815. case DEVICE_SAME:
  1816. /*
  1817. * The newly found device is already in the existing
  1818. * device list.
  1819. */
  1820. device->new_device = false;
  1821. matching_device->device_gone = false;
  1822. pqi_scsi_update_device(ctrl_info, matching_device, device);
  1823. break;
  1824. case DEVICE_NOT_FOUND:
  1825. /*
  1826. * The newly found device is NOT in the existing device
  1827. * list.
  1828. */
  1829. device->new_device = true;
  1830. break;
  1831. case DEVICE_CHANGED:
  1832. /*
  1833. * The original device has gone away and we need to add
  1834. * the new device.
  1835. */
  1836. device->new_device = true;
  1837. break;
  1838. }
  1839. }
  1840. /* Process all devices that have gone away. */
  1841. list_for_each_entry_safe(device, next, &ctrl_info->scsi_device_list,
  1842. scsi_device_list_entry) {
  1843. if (device->device_gone) {
  1844. list_del(&device->scsi_device_list_entry);
  1845. list_add_tail(&device->delete_list_entry, &delete_list);
  1846. }
  1847. }
  1848. /* Process all new devices. */
  1849. for (i = 0; i < num_new_devices; i++) {
  1850. device = new_device_list[i];
  1851. if (!device->new_device)
  1852. continue;
  1853. if (device->volume_offline)
  1854. continue;
  1855. list_add_tail(&device->scsi_device_list_entry,
  1856. &ctrl_info->scsi_device_list);
  1857. list_add_tail(&device->add_list_entry, &add_list);
  1858. /* To prevent this device structure from being freed later. */
  1859. device->keep_device = true;
  1860. }
  1861. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  1862. /*
  1863. * If OFA is in progress and there are devices that need to be deleted,
  1864. * allow any pending reset operations to continue and unblock any SCSI
  1865. * requests before removal.
  1866. */
  1867. if (pqi_ofa_in_progress(ctrl_info)) {
  1868. list_for_each_entry_safe(device, next, &delete_list, delete_list_entry)
  1869. if (pqi_is_device_added(device))
  1870. pqi_device_remove_start(device);
  1871. pqi_ctrl_unblock_device_reset(ctrl_info);
  1872. pqi_scsi_unblock_requests(ctrl_info);
  1873. }
  1874. /* Remove all devices that have gone away. */
  1875. list_for_each_entry_safe(device, next, &delete_list, delete_list_entry) {
  1876. if (device->volume_offline) {
  1877. pqi_dev_info(ctrl_info, "offline", device);
  1878. pqi_show_volume_status(ctrl_info, device);
  1879. } else {
  1880. pqi_dev_info(ctrl_info, "removed", device);
  1881. }
  1882. if (pqi_is_device_added(device))
  1883. pqi_remove_device(ctrl_info, device);
  1884. list_del(&device->delete_list_entry);
  1885. pqi_free_device(device);
  1886. }
  1887. /*
  1888. * Notify the SML of any existing device changes such as;
  1889. * queue depth, device size.
  1890. */
  1891. list_for_each_entry(device, &ctrl_info->scsi_device_list, scsi_device_list_entry) {
  1892. if (device->sdev && device->queue_depth != device->advertised_queue_depth) {
  1893. device->advertised_queue_depth = device->queue_depth;
  1894. scsi_change_queue_depth(device->sdev, device->advertised_queue_depth);
  1895. if (device->rescan) {
  1896. scsi_rescan_device(device->sdev);
  1897. device->rescan = false;
  1898. }
  1899. }
  1900. }
  1901. /* Expose any new devices. */
  1902. list_for_each_entry_safe(device, next, &add_list, add_list_entry) {
  1903. if (!pqi_is_device_added(device)) {
  1904. rc = pqi_add_device(ctrl_info, device);
  1905. if (rc == 0) {
  1906. pqi_dev_info(ctrl_info, "added", device);
  1907. } else {
  1908. dev_warn(&ctrl_info->pci_dev->dev,
  1909. "scsi %d:%d:%d:%d addition failed, device not added\n",
  1910. ctrl_info->scsi_host->host_no,
  1911. device->bus, device->target,
  1912. device->lun);
  1913. pqi_fixup_botched_add(ctrl_info, device);
  1914. }
  1915. }
  1916. }
  1917. ctrl_info->logical_volume_rescan_needed = false;
  1918. }
  1919. static inline bool pqi_is_supported_device(struct pqi_scsi_dev *device)
  1920. {
  1921. /*
  1922. * Only support the HBA controller itself as a RAID
  1923. * controller. If it's a RAID controller other than
  1924. * the HBA itself (an external RAID controller, for
  1925. * example), we don't support it.
  1926. */
  1927. if (device->device_type == SA_DEVICE_TYPE_CONTROLLER &&
  1928. !pqi_is_hba_lunid(device->scsi3addr))
  1929. return false;
  1930. return true;
  1931. }
  1932. static inline bool pqi_skip_device(u8 *scsi3addr)
  1933. {
  1934. /* Ignore all masked devices. */
  1935. if (MASKED_DEVICE(scsi3addr))
  1936. return true;
  1937. return false;
  1938. }
  1939. static inline void pqi_mask_device(u8 *scsi3addr)
  1940. {
  1941. scsi3addr[3] |= 0xc0;
  1942. }
  1943. static inline bool pqi_is_multipath_device(struct pqi_scsi_dev *device)
  1944. {
  1945. if (pqi_is_logical_device(device))
  1946. return false;
  1947. return (device->path_map & (device->path_map - 1)) != 0;
  1948. }
  1949. static inline bool pqi_expose_device(struct pqi_scsi_dev *device)
  1950. {
  1951. return !device->is_physical_device || !pqi_skip_device(device->scsi3addr);
  1952. }
  1953. static int pqi_update_scsi_devices(struct pqi_ctrl_info *ctrl_info)
  1954. {
  1955. int i;
  1956. int rc;
  1957. LIST_HEAD(new_device_list_head);
  1958. struct report_phys_lun_16byte_wwid_list *physdev_list = NULL;
  1959. struct report_log_lun_list *logdev_list = NULL;
  1960. struct report_phys_lun_16byte_wwid *phys_lun;
  1961. struct report_log_lun *log_lun;
  1962. struct bmic_identify_physical_device *id_phys = NULL;
  1963. u32 num_physicals;
  1964. u32 num_logicals;
  1965. struct pqi_scsi_dev **new_device_list = NULL;
  1966. struct pqi_scsi_dev *device;
  1967. struct pqi_scsi_dev *next;
  1968. unsigned int num_new_devices;
  1969. unsigned int num_valid_devices;
  1970. bool is_physical_device;
  1971. u8 *scsi3addr;
  1972. unsigned int physical_index;
  1973. unsigned int logical_index;
  1974. static char *out_of_memory_msg =
  1975. "failed to allocate memory, device discovery stopped";
  1976. rc = pqi_get_device_lists(ctrl_info, &physdev_list, &logdev_list);
  1977. if (rc)
  1978. goto out;
  1979. if (physdev_list)
  1980. num_physicals =
  1981. get_unaligned_be32(&physdev_list->header.list_length)
  1982. / sizeof(physdev_list->lun_entries[0]);
  1983. else
  1984. num_physicals = 0;
  1985. if (logdev_list)
  1986. num_logicals =
  1987. get_unaligned_be32(&logdev_list->header.list_length)
  1988. / sizeof(logdev_list->lun_entries[0]);
  1989. else
  1990. num_logicals = 0;
  1991. if (num_physicals) {
  1992. /*
  1993. * We need this buffer for calls to pqi_get_physical_disk_info()
  1994. * below. We allocate it here instead of inside
  1995. * pqi_get_physical_disk_info() because it's a fairly large
  1996. * buffer.
  1997. */
  1998. id_phys = kmalloc(sizeof(*id_phys), GFP_KERNEL);
  1999. if (!id_phys) {
  2000. dev_warn(&ctrl_info->pci_dev->dev, "%s\n",
  2001. out_of_memory_msg);
  2002. rc = -ENOMEM;
  2003. goto out;
  2004. }
  2005. if (pqi_hide_vsep) {
  2006. for (i = num_physicals - 1; i >= 0; i--) {
  2007. phys_lun = &physdev_list->lun_entries[i];
  2008. if (CISS_GET_DRIVE_NUMBER(phys_lun->lunid) == PQI_VSEP_CISS_BTL) {
  2009. pqi_mask_device(phys_lun->lunid);
  2010. break;
  2011. }
  2012. }
  2013. }
  2014. }
  2015. if (num_logicals &&
  2016. (logdev_list->header.flags & CISS_REPORT_LOG_FLAG_DRIVE_TYPE_MIX))
  2017. ctrl_info->lv_drive_type_mix_valid = true;
  2018. num_new_devices = num_physicals + num_logicals;
  2019. new_device_list = kmalloc_array(num_new_devices,
  2020. sizeof(*new_device_list),
  2021. GFP_KERNEL);
  2022. if (!new_device_list) {
  2023. dev_warn(&ctrl_info->pci_dev->dev, "%s\n", out_of_memory_msg);
  2024. rc = -ENOMEM;
  2025. goto out;
  2026. }
  2027. for (i = 0; i < num_new_devices; i++) {
  2028. device = kzalloc(sizeof(*device), GFP_KERNEL);
  2029. if (!device) {
  2030. dev_warn(&ctrl_info->pci_dev->dev, "%s\n",
  2031. out_of_memory_msg);
  2032. rc = -ENOMEM;
  2033. goto out;
  2034. }
  2035. list_add_tail(&device->new_device_list_entry,
  2036. &new_device_list_head);
  2037. }
  2038. device = NULL;
  2039. num_valid_devices = 0;
  2040. physical_index = 0;
  2041. logical_index = 0;
  2042. for (i = 0; i < num_new_devices; i++) {
  2043. if ((!pqi_expose_ld_first && i < num_physicals) ||
  2044. (pqi_expose_ld_first && i >= num_logicals)) {
  2045. is_physical_device = true;
  2046. phys_lun = &physdev_list->lun_entries[physical_index++];
  2047. log_lun = NULL;
  2048. scsi3addr = phys_lun->lunid;
  2049. } else {
  2050. is_physical_device = false;
  2051. phys_lun = NULL;
  2052. log_lun = &logdev_list->lun_entries[logical_index++];
  2053. scsi3addr = log_lun->lunid;
  2054. }
  2055. if (is_physical_device && pqi_skip_device(scsi3addr))
  2056. continue;
  2057. if (device)
  2058. device = list_next_entry(device, new_device_list_entry);
  2059. else
  2060. device = list_first_entry(&new_device_list_head,
  2061. struct pqi_scsi_dev, new_device_list_entry);
  2062. memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr));
  2063. device->is_physical_device = is_physical_device;
  2064. if (is_physical_device) {
  2065. device->device_type = phys_lun->device_type;
  2066. if (device->device_type == SA_DEVICE_TYPE_EXPANDER_SMP)
  2067. device->is_expander_smp_device = true;
  2068. } else {
  2069. device->is_external_raid_device =
  2070. pqi_is_external_raid_addr(scsi3addr);
  2071. }
  2072. if (!pqi_is_supported_device(device))
  2073. continue;
  2074. /* Do not present disks that the OS cannot fully probe */
  2075. if (pqi_keep_device_offline(ctrl_info, device))
  2076. continue;
  2077. /* Gather information about the device. */
  2078. rc = pqi_get_device_info(ctrl_info, device, id_phys);
  2079. if (rc == -ENOMEM) {
  2080. dev_warn(&ctrl_info->pci_dev->dev, "%s\n",
  2081. out_of_memory_msg);
  2082. goto out;
  2083. }
  2084. if (rc) {
  2085. if (device->is_physical_device)
  2086. dev_warn(&ctrl_info->pci_dev->dev,
  2087. "obtaining device info failed, skipping physical device %016llx%016llx\n",
  2088. get_unaligned_be64(&phys_lun->wwid[0]),
  2089. get_unaligned_be64(&phys_lun->wwid[8]));
  2090. else
  2091. dev_warn(&ctrl_info->pci_dev->dev,
  2092. "obtaining device info failed, skipping logical device %08x%08x\n",
  2093. *((u32 *)&device->scsi3addr),
  2094. *((u32 *)&device->scsi3addr[4]));
  2095. rc = 0;
  2096. continue;
  2097. }
  2098. pqi_assign_bus_target_lun(device);
  2099. if (device->is_physical_device) {
  2100. memcpy(device->wwid, phys_lun->wwid, sizeof(device->wwid));
  2101. if ((phys_lun->device_flags &
  2102. CISS_REPORT_PHYS_DEV_FLAG_AIO_ENABLED) &&
  2103. phys_lun->aio_handle) {
  2104. device->aio_enabled = true;
  2105. device->aio_handle =
  2106. phys_lun->aio_handle;
  2107. }
  2108. } else {
  2109. memcpy(device->volume_id, log_lun->volume_id,
  2110. sizeof(device->volume_id));
  2111. }
  2112. device->sas_address = get_unaligned_be64(&device->wwid[0]);
  2113. new_device_list[num_valid_devices++] = device;
  2114. }
  2115. pqi_update_device_list(ctrl_info, new_device_list, num_valid_devices);
  2116. out:
  2117. list_for_each_entry_safe(device, next, &new_device_list_head,
  2118. new_device_list_entry) {
  2119. if (device->keep_device)
  2120. continue;
  2121. list_del(&device->new_device_list_entry);
  2122. pqi_free_device(device);
  2123. }
  2124. kfree(new_device_list);
  2125. kfree(physdev_list);
  2126. kfree(logdev_list);
  2127. kfree(id_phys);
  2128. return rc;
  2129. }
  2130. static int pqi_scan_scsi_devices(struct pqi_ctrl_info *ctrl_info)
  2131. {
  2132. int rc;
  2133. int mutex_acquired;
  2134. if (pqi_ctrl_offline(ctrl_info))
  2135. return -ENXIO;
  2136. mutex_acquired = mutex_trylock(&ctrl_info->scan_mutex);
  2137. if (!mutex_acquired) {
  2138. if (pqi_ctrl_scan_blocked(ctrl_info))
  2139. return -EBUSY;
  2140. pqi_schedule_rescan_worker_delayed(ctrl_info);
  2141. return -EINPROGRESS;
  2142. }
  2143. rc = pqi_update_scsi_devices(ctrl_info);
  2144. if (rc && !pqi_ctrl_scan_blocked(ctrl_info))
  2145. pqi_schedule_rescan_worker_delayed(ctrl_info);
  2146. mutex_unlock(&ctrl_info->scan_mutex);
  2147. return rc;
  2148. }
  2149. static void pqi_scan_start(struct Scsi_Host *shost)
  2150. {
  2151. struct pqi_ctrl_info *ctrl_info;
  2152. ctrl_info = shost_to_hba(shost);
  2153. pqi_scan_scsi_devices(ctrl_info);
  2154. }
  2155. /* Returns TRUE if scan is finished. */
  2156. static int pqi_scan_finished(struct Scsi_Host *shost,
  2157. unsigned long elapsed_time)
  2158. {
  2159. struct pqi_ctrl_info *ctrl_info;
  2160. ctrl_info = shost_priv(shost);
  2161. return !mutex_is_locked(&ctrl_info->scan_mutex);
  2162. }
  2163. static inline void pqi_set_encryption_info(struct pqi_encryption_info *encryption_info,
  2164. struct raid_map *raid_map, u64 first_block)
  2165. {
  2166. u32 volume_blk_size;
  2167. /*
  2168. * Set the encryption tweak values based on logical block address.
  2169. * If the block size is 512, the tweak value is equal to the LBA.
  2170. * For other block sizes, tweak value is (LBA * block size) / 512.
  2171. */
  2172. volume_blk_size = get_unaligned_le32(&raid_map->volume_blk_size);
  2173. if (volume_blk_size != 512)
  2174. first_block = (first_block * volume_blk_size) / 512;
  2175. encryption_info->data_encryption_key_index =
  2176. get_unaligned_le16(&raid_map->data_encryption_key_index);
  2177. encryption_info->encrypt_tweak_lower = lower_32_bits(first_block);
  2178. encryption_info->encrypt_tweak_upper = upper_32_bits(first_block);
  2179. }
  2180. /*
  2181. * Attempt to perform RAID bypass mapping for a logical volume I/O.
  2182. */
  2183. static bool pqi_aio_raid_level_supported(struct pqi_ctrl_info *ctrl_info,
  2184. struct pqi_scsi_dev_raid_map_data *rmd)
  2185. {
  2186. bool is_supported = true;
  2187. switch (rmd->raid_level) {
  2188. case SA_RAID_0:
  2189. break;
  2190. case SA_RAID_1:
  2191. if (rmd->is_write && (!ctrl_info->enable_r1_writes ||
  2192. rmd->data_length > ctrl_info->max_write_raid_1_10_2drive))
  2193. is_supported = false;
  2194. break;
  2195. case SA_RAID_TRIPLE:
  2196. if (rmd->is_write && (!ctrl_info->enable_r1_writes ||
  2197. rmd->data_length > ctrl_info->max_write_raid_1_10_3drive))
  2198. is_supported = false;
  2199. break;
  2200. case SA_RAID_5:
  2201. if (rmd->is_write && (!ctrl_info->enable_r5_writes ||
  2202. rmd->data_length > ctrl_info->max_write_raid_5_6))
  2203. is_supported = false;
  2204. break;
  2205. case SA_RAID_6:
  2206. if (rmd->is_write && (!ctrl_info->enable_r6_writes ||
  2207. rmd->data_length > ctrl_info->max_write_raid_5_6))
  2208. is_supported = false;
  2209. break;
  2210. default:
  2211. is_supported = false;
  2212. break;
  2213. }
  2214. return is_supported;
  2215. }
  2216. #define PQI_RAID_BYPASS_INELIGIBLE 1
  2217. static int pqi_get_aio_lba_and_block_count(struct scsi_cmnd *scmd,
  2218. struct pqi_scsi_dev_raid_map_data *rmd)
  2219. {
  2220. /* Check for valid opcode, get LBA and block count. */
  2221. switch (scmd->cmnd[0]) {
  2222. case WRITE_6:
  2223. rmd->is_write = true;
  2224. fallthrough;
  2225. case READ_6:
  2226. rmd->first_block = (u64)(((scmd->cmnd[1] & 0x1f) << 16) |
  2227. (scmd->cmnd[2] << 8) | scmd->cmnd[3]);
  2228. rmd->block_cnt = (u32)scmd->cmnd[4];
  2229. if (rmd->block_cnt == 0)
  2230. rmd->block_cnt = 256;
  2231. break;
  2232. case WRITE_10:
  2233. rmd->is_write = true;
  2234. fallthrough;
  2235. case READ_10:
  2236. rmd->first_block = (u64)get_unaligned_be32(&scmd->cmnd[2]);
  2237. rmd->block_cnt = (u32)get_unaligned_be16(&scmd->cmnd[7]);
  2238. break;
  2239. case WRITE_12:
  2240. rmd->is_write = true;
  2241. fallthrough;
  2242. case READ_12:
  2243. rmd->first_block = (u64)get_unaligned_be32(&scmd->cmnd[2]);
  2244. rmd->block_cnt = get_unaligned_be32(&scmd->cmnd[6]);
  2245. break;
  2246. case WRITE_16:
  2247. rmd->is_write = true;
  2248. fallthrough;
  2249. case READ_16:
  2250. rmd->first_block = get_unaligned_be64(&scmd->cmnd[2]);
  2251. rmd->block_cnt = get_unaligned_be32(&scmd->cmnd[10]);
  2252. break;
  2253. default:
  2254. /* Process via normal I/O path. */
  2255. return PQI_RAID_BYPASS_INELIGIBLE;
  2256. }
  2257. put_unaligned_le32(scsi_bufflen(scmd), &rmd->data_length);
  2258. return 0;
  2259. }
  2260. static int pci_get_aio_common_raid_map_values(struct pqi_ctrl_info *ctrl_info,
  2261. struct pqi_scsi_dev_raid_map_data *rmd, struct raid_map *raid_map)
  2262. {
  2263. #if BITS_PER_LONG == 32
  2264. u64 tmpdiv;
  2265. #endif
  2266. rmd->last_block = rmd->first_block + rmd->block_cnt - 1;
  2267. /* Check for invalid block or wraparound. */
  2268. if (rmd->last_block >=
  2269. get_unaligned_le64(&raid_map->volume_blk_cnt) ||
  2270. rmd->last_block < rmd->first_block)
  2271. return PQI_RAID_BYPASS_INELIGIBLE;
  2272. rmd->data_disks_per_row =
  2273. get_unaligned_le16(&raid_map->data_disks_per_row);
  2274. rmd->strip_size = get_unaligned_le16(&raid_map->strip_size);
  2275. rmd->layout_map_count = get_unaligned_le16(&raid_map->layout_map_count);
  2276. /* Calculate stripe information for the request. */
  2277. rmd->blocks_per_row = rmd->data_disks_per_row * rmd->strip_size;
  2278. if (rmd->blocks_per_row == 0) /* Used as a divisor in many calculations */
  2279. return PQI_RAID_BYPASS_INELIGIBLE;
  2280. #if BITS_PER_LONG == 32
  2281. tmpdiv = rmd->first_block;
  2282. do_div(tmpdiv, rmd->blocks_per_row);
  2283. rmd->first_row = tmpdiv;
  2284. tmpdiv = rmd->last_block;
  2285. do_div(tmpdiv, rmd->blocks_per_row);
  2286. rmd->last_row = tmpdiv;
  2287. rmd->first_row_offset = (u32)(rmd->first_block - (rmd->first_row * rmd->blocks_per_row));
  2288. rmd->last_row_offset = (u32)(rmd->last_block - (rmd->last_row * rmd->blocks_per_row));
  2289. tmpdiv = rmd->first_row_offset;
  2290. do_div(tmpdiv, rmd->strip_size);
  2291. rmd->first_column = tmpdiv;
  2292. tmpdiv = rmd->last_row_offset;
  2293. do_div(tmpdiv, rmd->strip_size);
  2294. rmd->last_column = tmpdiv;
  2295. #else
  2296. rmd->first_row = rmd->first_block / rmd->blocks_per_row;
  2297. rmd->last_row = rmd->last_block / rmd->blocks_per_row;
  2298. rmd->first_row_offset = (u32)(rmd->first_block -
  2299. (rmd->first_row * rmd->blocks_per_row));
  2300. rmd->last_row_offset = (u32)(rmd->last_block - (rmd->last_row *
  2301. rmd->blocks_per_row));
  2302. rmd->first_column = rmd->first_row_offset / rmd->strip_size;
  2303. rmd->last_column = rmd->last_row_offset / rmd->strip_size;
  2304. #endif
  2305. /* If this isn't a single row/column then give to the controller. */
  2306. if (rmd->first_row != rmd->last_row ||
  2307. rmd->first_column != rmd->last_column)
  2308. return PQI_RAID_BYPASS_INELIGIBLE;
  2309. /* Proceeding with driver mapping. */
  2310. rmd->total_disks_per_row = rmd->data_disks_per_row +
  2311. get_unaligned_le16(&raid_map->metadata_disks_per_row);
  2312. rmd->map_row = ((u32)(rmd->first_row >>
  2313. raid_map->parity_rotation_shift)) %
  2314. get_unaligned_le16(&raid_map->row_cnt);
  2315. rmd->map_index = (rmd->map_row * rmd->total_disks_per_row) +
  2316. rmd->first_column;
  2317. return 0;
  2318. }
  2319. static int pqi_calc_aio_r5_or_r6(struct pqi_scsi_dev_raid_map_data *rmd,
  2320. struct raid_map *raid_map)
  2321. {
  2322. #if BITS_PER_LONG == 32
  2323. u64 tmpdiv;
  2324. #endif
  2325. if (rmd->blocks_per_row == 0) /* Used as a divisor in many calculations */
  2326. return PQI_RAID_BYPASS_INELIGIBLE;
  2327. /* RAID 50/60 */
  2328. /* Verify first and last block are in same RAID group. */
  2329. rmd->stripesize = rmd->blocks_per_row * rmd->layout_map_count;
  2330. #if BITS_PER_LONG == 32
  2331. tmpdiv = rmd->first_block;
  2332. rmd->first_group = do_div(tmpdiv, rmd->stripesize);
  2333. tmpdiv = rmd->first_group;
  2334. do_div(tmpdiv, rmd->blocks_per_row);
  2335. rmd->first_group = tmpdiv;
  2336. tmpdiv = rmd->last_block;
  2337. rmd->last_group = do_div(tmpdiv, rmd->stripesize);
  2338. tmpdiv = rmd->last_group;
  2339. do_div(tmpdiv, rmd->blocks_per_row);
  2340. rmd->last_group = tmpdiv;
  2341. #else
  2342. rmd->first_group = (rmd->first_block % rmd->stripesize) / rmd->blocks_per_row;
  2343. rmd->last_group = (rmd->last_block % rmd->stripesize) / rmd->blocks_per_row;
  2344. #endif
  2345. if (rmd->first_group != rmd->last_group)
  2346. return PQI_RAID_BYPASS_INELIGIBLE;
  2347. /* Verify request is in a single row of RAID 5/6. */
  2348. #if BITS_PER_LONG == 32
  2349. tmpdiv = rmd->first_block;
  2350. do_div(tmpdiv, rmd->stripesize);
  2351. rmd->first_row = tmpdiv;
  2352. rmd->r5or6_first_row = tmpdiv;
  2353. tmpdiv = rmd->last_block;
  2354. do_div(tmpdiv, rmd->stripesize);
  2355. rmd->r5or6_last_row = tmpdiv;
  2356. #else
  2357. rmd->first_row = rmd->r5or6_first_row =
  2358. rmd->first_block / rmd->stripesize;
  2359. rmd->r5or6_last_row = rmd->last_block / rmd->stripesize;
  2360. #endif
  2361. if (rmd->r5or6_first_row != rmd->r5or6_last_row)
  2362. return PQI_RAID_BYPASS_INELIGIBLE;
  2363. /* Verify request is in a single column. */
  2364. #if BITS_PER_LONG == 32
  2365. tmpdiv = rmd->first_block;
  2366. rmd->first_row_offset = do_div(tmpdiv, rmd->stripesize);
  2367. tmpdiv = rmd->first_row_offset;
  2368. rmd->first_row_offset = (u32)do_div(tmpdiv, rmd->blocks_per_row);
  2369. rmd->r5or6_first_row_offset = rmd->first_row_offset;
  2370. tmpdiv = rmd->last_block;
  2371. rmd->r5or6_last_row_offset = do_div(tmpdiv, rmd->stripesize);
  2372. tmpdiv = rmd->r5or6_last_row_offset;
  2373. rmd->r5or6_last_row_offset = do_div(tmpdiv, rmd->blocks_per_row);
  2374. tmpdiv = rmd->r5or6_first_row_offset;
  2375. do_div(tmpdiv, rmd->strip_size);
  2376. rmd->first_column = rmd->r5or6_first_column = tmpdiv;
  2377. tmpdiv = rmd->r5or6_last_row_offset;
  2378. do_div(tmpdiv, rmd->strip_size);
  2379. rmd->r5or6_last_column = tmpdiv;
  2380. #else
  2381. rmd->first_row_offset = rmd->r5or6_first_row_offset =
  2382. (u32)((rmd->first_block % rmd->stripesize) %
  2383. rmd->blocks_per_row);
  2384. rmd->r5or6_last_row_offset =
  2385. (u32)((rmd->last_block % rmd->stripesize) %
  2386. rmd->blocks_per_row);
  2387. rmd->first_column =
  2388. rmd->r5or6_first_row_offset / rmd->strip_size;
  2389. rmd->r5or6_first_column = rmd->first_column;
  2390. rmd->r5or6_last_column = rmd->r5or6_last_row_offset / rmd->strip_size;
  2391. #endif
  2392. if (rmd->r5or6_first_column != rmd->r5or6_last_column)
  2393. return PQI_RAID_BYPASS_INELIGIBLE;
  2394. /* Request is eligible. */
  2395. rmd->map_row =
  2396. ((u32)(rmd->first_row >> raid_map->parity_rotation_shift)) %
  2397. get_unaligned_le16(&raid_map->row_cnt);
  2398. rmd->map_index = (rmd->first_group *
  2399. (get_unaligned_le16(&raid_map->row_cnt) *
  2400. rmd->total_disks_per_row)) +
  2401. (rmd->map_row * rmd->total_disks_per_row) + rmd->first_column;
  2402. if (rmd->is_write) {
  2403. u32 index;
  2404. /*
  2405. * p_parity_it_nexus and q_parity_it_nexus are pointers to the
  2406. * parity entries inside the device's raid_map.
  2407. *
  2408. * A device's RAID map is bounded by: number of RAID disks squared.
  2409. *
  2410. * The devices RAID map size is checked during device
  2411. * initialization.
  2412. */
  2413. index = DIV_ROUND_UP(rmd->map_index + 1, rmd->total_disks_per_row);
  2414. index *= rmd->total_disks_per_row;
  2415. index -= get_unaligned_le16(&raid_map->metadata_disks_per_row);
  2416. rmd->p_parity_it_nexus = raid_map->disk_data[index].aio_handle;
  2417. if (rmd->raid_level == SA_RAID_6) {
  2418. rmd->q_parity_it_nexus = raid_map->disk_data[index + 1].aio_handle;
  2419. rmd->xor_mult = raid_map->disk_data[rmd->map_index].xor_mult[1];
  2420. }
  2421. #if BITS_PER_LONG == 32
  2422. tmpdiv = rmd->first_block;
  2423. do_div(tmpdiv, rmd->blocks_per_row);
  2424. rmd->row = tmpdiv;
  2425. #else
  2426. rmd->row = rmd->first_block / rmd->blocks_per_row;
  2427. #endif
  2428. }
  2429. return 0;
  2430. }
  2431. static void pqi_set_aio_cdb(struct pqi_scsi_dev_raid_map_data *rmd)
  2432. {
  2433. /* Build the new CDB for the physical disk I/O. */
  2434. if (rmd->disk_block > 0xffffffff) {
  2435. rmd->cdb[0] = rmd->is_write ? WRITE_16 : READ_16;
  2436. rmd->cdb[1] = 0;
  2437. put_unaligned_be64(rmd->disk_block, &rmd->cdb[2]);
  2438. put_unaligned_be32(rmd->disk_block_cnt, &rmd->cdb[10]);
  2439. rmd->cdb[14] = 0;
  2440. rmd->cdb[15] = 0;
  2441. rmd->cdb_length = 16;
  2442. } else {
  2443. rmd->cdb[0] = rmd->is_write ? WRITE_10 : READ_10;
  2444. rmd->cdb[1] = 0;
  2445. put_unaligned_be32((u32)rmd->disk_block, &rmd->cdb[2]);
  2446. rmd->cdb[6] = 0;
  2447. put_unaligned_be16((u16)rmd->disk_block_cnt, &rmd->cdb[7]);
  2448. rmd->cdb[9] = 0;
  2449. rmd->cdb_length = 10;
  2450. }
  2451. }
  2452. static void pqi_calc_aio_r1_nexus(struct raid_map *raid_map,
  2453. struct pqi_scsi_dev_raid_map_data *rmd)
  2454. {
  2455. u32 index;
  2456. u32 group;
  2457. group = rmd->map_index / rmd->data_disks_per_row;
  2458. index = rmd->map_index - (group * rmd->data_disks_per_row);
  2459. rmd->it_nexus[0] = raid_map->disk_data[index].aio_handle;
  2460. index += rmd->data_disks_per_row;
  2461. rmd->it_nexus[1] = raid_map->disk_data[index].aio_handle;
  2462. if (rmd->layout_map_count > 2) {
  2463. index += rmd->data_disks_per_row;
  2464. rmd->it_nexus[2] = raid_map->disk_data[index].aio_handle;
  2465. }
  2466. rmd->num_it_nexus_entries = rmd->layout_map_count;
  2467. }
  2468. static int pqi_raid_bypass_submit_scsi_cmd(struct pqi_ctrl_info *ctrl_info,
  2469. struct pqi_scsi_dev *device, struct scsi_cmnd *scmd,
  2470. struct pqi_queue_group *queue_group)
  2471. {
  2472. int rc;
  2473. struct raid_map *raid_map;
  2474. u32 group;
  2475. u32 next_bypass_group;
  2476. struct pqi_encryption_info *encryption_info_ptr;
  2477. struct pqi_encryption_info encryption_info;
  2478. struct pqi_scsi_dev_raid_map_data rmd = { 0 };
  2479. rc = pqi_get_aio_lba_and_block_count(scmd, &rmd);
  2480. if (rc)
  2481. return PQI_RAID_BYPASS_INELIGIBLE;
  2482. rmd.raid_level = device->raid_level;
  2483. if (!pqi_aio_raid_level_supported(ctrl_info, &rmd))
  2484. return PQI_RAID_BYPASS_INELIGIBLE;
  2485. if (unlikely(rmd.block_cnt == 0))
  2486. return PQI_RAID_BYPASS_INELIGIBLE;
  2487. raid_map = device->raid_map;
  2488. rc = pci_get_aio_common_raid_map_values(ctrl_info, &rmd, raid_map);
  2489. if (rc)
  2490. return PQI_RAID_BYPASS_INELIGIBLE;
  2491. if (device->raid_level == SA_RAID_1 ||
  2492. device->raid_level == SA_RAID_TRIPLE) {
  2493. if (rmd.is_write) {
  2494. pqi_calc_aio_r1_nexus(raid_map, &rmd);
  2495. } else {
  2496. group = device->next_bypass_group[rmd.map_index];
  2497. next_bypass_group = group + 1;
  2498. if (next_bypass_group >= rmd.layout_map_count)
  2499. next_bypass_group = 0;
  2500. device->next_bypass_group[rmd.map_index] = next_bypass_group;
  2501. rmd.map_index += group * rmd.data_disks_per_row;
  2502. }
  2503. } else if ((device->raid_level == SA_RAID_5 ||
  2504. device->raid_level == SA_RAID_6) &&
  2505. (rmd.layout_map_count > 1 || rmd.is_write)) {
  2506. rc = pqi_calc_aio_r5_or_r6(&rmd, raid_map);
  2507. if (rc)
  2508. return PQI_RAID_BYPASS_INELIGIBLE;
  2509. }
  2510. if (unlikely(rmd.map_index >= RAID_MAP_MAX_ENTRIES))
  2511. return PQI_RAID_BYPASS_INELIGIBLE;
  2512. rmd.aio_handle = raid_map->disk_data[rmd.map_index].aio_handle;
  2513. rmd.disk_block = get_unaligned_le64(&raid_map->disk_starting_blk) +
  2514. rmd.first_row * rmd.strip_size +
  2515. (rmd.first_row_offset - rmd.first_column * rmd.strip_size);
  2516. rmd.disk_block_cnt = rmd.block_cnt;
  2517. /* Handle differing logical/physical block sizes. */
  2518. if (raid_map->phys_blk_shift) {
  2519. rmd.disk_block <<= raid_map->phys_blk_shift;
  2520. rmd.disk_block_cnt <<= raid_map->phys_blk_shift;
  2521. }
  2522. if (unlikely(rmd.disk_block_cnt > 0xffff))
  2523. return PQI_RAID_BYPASS_INELIGIBLE;
  2524. pqi_set_aio_cdb(&rmd);
  2525. if (get_unaligned_le16(&raid_map->flags) & RAID_MAP_ENCRYPTION_ENABLED) {
  2526. if (rmd.data_length > device->max_transfer_encrypted)
  2527. return PQI_RAID_BYPASS_INELIGIBLE;
  2528. pqi_set_encryption_info(&encryption_info, raid_map, rmd.first_block);
  2529. encryption_info_ptr = &encryption_info;
  2530. } else {
  2531. encryption_info_ptr = NULL;
  2532. }
  2533. if (rmd.is_write) {
  2534. switch (device->raid_level) {
  2535. case SA_RAID_1:
  2536. case SA_RAID_TRIPLE:
  2537. return pqi_aio_submit_r1_write_io(ctrl_info, scmd, queue_group,
  2538. encryption_info_ptr, device, &rmd);
  2539. case SA_RAID_5:
  2540. case SA_RAID_6:
  2541. return pqi_aio_submit_r56_write_io(ctrl_info, scmd, queue_group,
  2542. encryption_info_ptr, device, &rmd);
  2543. }
  2544. }
  2545. return pqi_aio_submit_io(ctrl_info, scmd, rmd.aio_handle,
  2546. rmd.cdb, rmd.cdb_length, queue_group,
  2547. encryption_info_ptr, true, false);
  2548. }
  2549. #define PQI_STATUS_IDLE 0x0
  2550. #define PQI_CREATE_ADMIN_QUEUE_PAIR 1
  2551. #define PQI_DELETE_ADMIN_QUEUE_PAIR 2
  2552. #define PQI_DEVICE_STATE_POWER_ON_AND_RESET 0x0
  2553. #define PQI_DEVICE_STATE_STATUS_AVAILABLE 0x1
  2554. #define PQI_DEVICE_STATE_ALL_REGISTERS_READY 0x2
  2555. #define PQI_DEVICE_STATE_ADMIN_QUEUE_PAIR_READY 0x3
  2556. #define PQI_DEVICE_STATE_ERROR 0x4
  2557. #define PQI_MODE_READY_TIMEOUT_SECS 30
  2558. #define PQI_MODE_READY_POLL_INTERVAL_MSECS 1
  2559. static int pqi_wait_for_pqi_mode_ready(struct pqi_ctrl_info *ctrl_info)
  2560. {
  2561. struct pqi_device_registers __iomem *pqi_registers;
  2562. unsigned long timeout;
  2563. u64 signature;
  2564. u8 status;
  2565. pqi_registers = ctrl_info->pqi_registers;
  2566. timeout = (PQI_MODE_READY_TIMEOUT_SECS * HZ) + jiffies;
  2567. while (1) {
  2568. signature = readq(&pqi_registers->signature);
  2569. if (memcmp(&signature, PQI_DEVICE_SIGNATURE,
  2570. sizeof(signature)) == 0)
  2571. break;
  2572. if (time_after(jiffies, timeout)) {
  2573. dev_err(&ctrl_info->pci_dev->dev,
  2574. "timed out waiting for PQI signature\n");
  2575. return -ETIMEDOUT;
  2576. }
  2577. msleep(PQI_MODE_READY_POLL_INTERVAL_MSECS);
  2578. }
  2579. while (1) {
  2580. status = readb(&pqi_registers->function_and_status_code);
  2581. if (status == PQI_STATUS_IDLE)
  2582. break;
  2583. if (time_after(jiffies, timeout)) {
  2584. dev_err(&ctrl_info->pci_dev->dev,
  2585. "timed out waiting for PQI IDLE\n");
  2586. return -ETIMEDOUT;
  2587. }
  2588. msleep(PQI_MODE_READY_POLL_INTERVAL_MSECS);
  2589. }
  2590. while (1) {
  2591. if (readl(&pqi_registers->device_status) ==
  2592. PQI_DEVICE_STATE_ALL_REGISTERS_READY)
  2593. break;
  2594. if (time_after(jiffies, timeout)) {
  2595. dev_err(&ctrl_info->pci_dev->dev,
  2596. "timed out waiting for PQI all registers ready\n");
  2597. return -ETIMEDOUT;
  2598. }
  2599. msleep(PQI_MODE_READY_POLL_INTERVAL_MSECS);
  2600. }
  2601. return 0;
  2602. }
  2603. static inline void pqi_aio_path_disabled(struct pqi_io_request *io_request)
  2604. {
  2605. struct pqi_scsi_dev *device;
  2606. device = io_request->scmd->device->hostdata;
  2607. device->raid_bypass_enabled = false;
  2608. device->aio_enabled = false;
  2609. }
  2610. static inline void pqi_take_device_offline(struct scsi_device *sdev, char *path)
  2611. {
  2612. struct pqi_ctrl_info *ctrl_info;
  2613. struct pqi_scsi_dev *device;
  2614. device = sdev->hostdata;
  2615. if (device->device_offline)
  2616. return;
  2617. device->device_offline = true;
  2618. ctrl_info = shost_to_hba(sdev->host);
  2619. pqi_schedule_rescan_worker(ctrl_info);
  2620. dev_err(&ctrl_info->pci_dev->dev, "re-scanning %s scsi %d:%d:%d:%d\n",
  2621. path, ctrl_info->scsi_host->host_no, device->bus,
  2622. device->target, device->lun);
  2623. }
  2624. static void pqi_process_raid_io_error(struct pqi_io_request *io_request)
  2625. {
  2626. u8 scsi_status;
  2627. u8 host_byte;
  2628. struct scsi_cmnd *scmd;
  2629. struct pqi_raid_error_info *error_info;
  2630. size_t sense_data_length;
  2631. int residual_count;
  2632. int xfer_count;
  2633. struct scsi_sense_hdr sshdr;
  2634. scmd = io_request->scmd;
  2635. if (!scmd)
  2636. return;
  2637. error_info = io_request->error_info;
  2638. scsi_status = error_info->status;
  2639. host_byte = DID_OK;
  2640. switch (error_info->data_out_result) {
  2641. case PQI_DATA_IN_OUT_GOOD:
  2642. break;
  2643. case PQI_DATA_IN_OUT_UNDERFLOW:
  2644. xfer_count =
  2645. get_unaligned_le32(&error_info->data_out_transferred);
  2646. residual_count = scsi_bufflen(scmd) - xfer_count;
  2647. scsi_set_resid(scmd, residual_count);
  2648. if (xfer_count < scmd->underflow)
  2649. host_byte = DID_SOFT_ERROR;
  2650. break;
  2651. case PQI_DATA_IN_OUT_UNSOLICITED_ABORT:
  2652. case PQI_DATA_IN_OUT_ABORTED:
  2653. host_byte = DID_ABORT;
  2654. break;
  2655. case PQI_DATA_IN_OUT_TIMEOUT:
  2656. host_byte = DID_TIME_OUT;
  2657. break;
  2658. case PQI_DATA_IN_OUT_BUFFER_OVERFLOW:
  2659. case PQI_DATA_IN_OUT_PROTOCOL_ERROR:
  2660. case PQI_DATA_IN_OUT_BUFFER_ERROR:
  2661. case PQI_DATA_IN_OUT_BUFFER_OVERFLOW_DESCRIPTOR_AREA:
  2662. case PQI_DATA_IN_OUT_BUFFER_OVERFLOW_BRIDGE:
  2663. case PQI_DATA_IN_OUT_ERROR:
  2664. case PQI_DATA_IN_OUT_HARDWARE_ERROR:
  2665. case PQI_DATA_IN_OUT_PCIE_FABRIC_ERROR:
  2666. case PQI_DATA_IN_OUT_PCIE_COMPLETION_TIMEOUT:
  2667. case PQI_DATA_IN_OUT_PCIE_COMPLETER_ABORT_RECEIVED:
  2668. case PQI_DATA_IN_OUT_PCIE_UNSUPPORTED_REQUEST_RECEIVED:
  2669. case PQI_DATA_IN_OUT_PCIE_ECRC_CHECK_FAILED:
  2670. case PQI_DATA_IN_OUT_PCIE_UNSUPPORTED_REQUEST:
  2671. case PQI_DATA_IN_OUT_PCIE_ACS_VIOLATION:
  2672. case PQI_DATA_IN_OUT_PCIE_TLP_PREFIX_BLOCKED:
  2673. case PQI_DATA_IN_OUT_PCIE_POISONED_MEMORY_READ:
  2674. default:
  2675. host_byte = DID_ERROR;
  2676. break;
  2677. }
  2678. sense_data_length = get_unaligned_le16(&error_info->sense_data_length);
  2679. if (sense_data_length == 0)
  2680. sense_data_length =
  2681. get_unaligned_le16(&error_info->response_data_length);
  2682. if (sense_data_length) {
  2683. if (sense_data_length > sizeof(error_info->data))
  2684. sense_data_length = sizeof(error_info->data);
  2685. if (scsi_status == SAM_STAT_CHECK_CONDITION &&
  2686. scsi_normalize_sense(error_info->data,
  2687. sense_data_length, &sshdr) &&
  2688. sshdr.sense_key == HARDWARE_ERROR &&
  2689. sshdr.asc == 0x3e) {
  2690. struct pqi_ctrl_info *ctrl_info = shost_to_hba(scmd->device->host);
  2691. struct pqi_scsi_dev *device = scmd->device->hostdata;
  2692. switch (sshdr.ascq) {
  2693. case 0x1: /* LOGICAL UNIT FAILURE */
  2694. if (printk_ratelimit())
  2695. scmd_printk(KERN_ERR, scmd, "received 'logical unit failure' from controller for scsi %d:%d:%d:%d\n",
  2696. ctrl_info->scsi_host->host_no, device->bus, device->target, device->lun);
  2697. pqi_take_device_offline(scmd->device, "RAID");
  2698. host_byte = DID_NO_CONNECT;
  2699. break;
  2700. default: /* See http://www.t10.org/lists/asc-num.htm#ASC_3E */
  2701. if (printk_ratelimit())
  2702. scmd_printk(KERN_ERR, scmd, "received unhandled error %d from controller for scsi %d:%d:%d:%d\n",
  2703. sshdr.ascq, ctrl_info->scsi_host->host_no, device->bus, device->target, device->lun);
  2704. break;
  2705. }
  2706. }
  2707. if (sense_data_length > SCSI_SENSE_BUFFERSIZE)
  2708. sense_data_length = SCSI_SENSE_BUFFERSIZE;
  2709. memcpy(scmd->sense_buffer, error_info->data,
  2710. sense_data_length);
  2711. }
  2712. scmd->result = scsi_status;
  2713. set_host_byte(scmd, host_byte);
  2714. }
  2715. static void pqi_process_aio_io_error(struct pqi_io_request *io_request)
  2716. {
  2717. u8 scsi_status;
  2718. u8 host_byte;
  2719. struct scsi_cmnd *scmd;
  2720. struct pqi_aio_error_info *error_info;
  2721. size_t sense_data_length;
  2722. int residual_count;
  2723. int xfer_count;
  2724. bool device_offline;
  2725. struct pqi_scsi_dev *device;
  2726. scmd = io_request->scmd;
  2727. error_info = io_request->error_info;
  2728. host_byte = DID_OK;
  2729. sense_data_length = 0;
  2730. device_offline = false;
  2731. device = scmd->device->hostdata;
  2732. switch (error_info->service_response) {
  2733. case PQI_AIO_SERV_RESPONSE_COMPLETE:
  2734. scsi_status = error_info->status;
  2735. break;
  2736. case PQI_AIO_SERV_RESPONSE_FAILURE:
  2737. switch (error_info->status) {
  2738. case PQI_AIO_STATUS_IO_ABORTED:
  2739. scsi_status = SAM_STAT_TASK_ABORTED;
  2740. break;
  2741. case PQI_AIO_STATUS_UNDERRUN:
  2742. scsi_status = SAM_STAT_GOOD;
  2743. residual_count = get_unaligned_le32(
  2744. &error_info->residual_count);
  2745. scsi_set_resid(scmd, residual_count);
  2746. xfer_count = scsi_bufflen(scmd) - residual_count;
  2747. if (xfer_count < scmd->underflow)
  2748. host_byte = DID_SOFT_ERROR;
  2749. break;
  2750. case PQI_AIO_STATUS_OVERRUN:
  2751. scsi_status = SAM_STAT_GOOD;
  2752. break;
  2753. case PQI_AIO_STATUS_AIO_PATH_DISABLED:
  2754. pqi_aio_path_disabled(io_request);
  2755. if (pqi_is_multipath_device(device)) {
  2756. pqi_device_remove_start(device);
  2757. host_byte = DID_NO_CONNECT;
  2758. scsi_status = SAM_STAT_CHECK_CONDITION;
  2759. } else {
  2760. scsi_status = SAM_STAT_GOOD;
  2761. io_request->status = -EAGAIN;
  2762. }
  2763. break;
  2764. case PQI_AIO_STATUS_NO_PATH_TO_DEVICE:
  2765. case PQI_AIO_STATUS_INVALID_DEVICE:
  2766. if (!io_request->raid_bypass) {
  2767. device_offline = true;
  2768. pqi_take_device_offline(scmd->device, "AIO");
  2769. host_byte = DID_NO_CONNECT;
  2770. }
  2771. scsi_status = SAM_STAT_CHECK_CONDITION;
  2772. break;
  2773. case PQI_AIO_STATUS_IO_ERROR:
  2774. default:
  2775. scsi_status = SAM_STAT_CHECK_CONDITION;
  2776. break;
  2777. }
  2778. break;
  2779. case PQI_AIO_SERV_RESPONSE_TMF_COMPLETE:
  2780. case PQI_AIO_SERV_RESPONSE_TMF_SUCCEEDED:
  2781. scsi_status = SAM_STAT_GOOD;
  2782. break;
  2783. case PQI_AIO_SERV_RESPONSE_TMF_REJECTED:
  2784. case PQI_AIO_SERV_RESPONSE_TMF_INCORRECT_LUN:
  2785. default:
  2786. scsi_status = SAM_STAT_CHECK_CONDITION;
  2787. break;
  2788. }
  2789. if (error_info->data_present) {
  2790. sense_data_length =
  2791. get_unaligned_le16(&error_info->data_length);
  2792. if (sense_data_length) {
  2793. if (sense_data_length > sizeof(error_info->data))
  2794. sense_data_length = sizeof(error_info->data);
  2795. if (sense_data_length > SCSI_SENSE_BUFFERSIZE)
  2796. sense_data_length = SCSI_SENSE_BUFFERSIZE;
  2797. memcpy(scmd->sense_buffer, error_info->data,
  2798. sense_data_length);
  2799. }
  2800. }
  2801. if (device_offline && sense_data_length == 0)
  2802. scsi_build_sense(scmd, 0, HARDWARE_ERROR, 0x3e, 0x1);
  2803. scmd->result = scsi_status;
  2804. set_host_byte(scmd, host_byte);
  2805. }
  2806. static void pqi_process_io_error(unsigned int iu_type,
  2807. struct pqi_io_request *io_request)
  2808. {
  2809. switch (iu_type) {
  2810. case PQI_RESPONSE_IU_RAID_PATH_IO_ERROR:
  2811. pqi_process_raid_io_error(io_request);
  2812. break;
  2813. case PQI_RESPONSE_IU_AIO_PATH_IO_ERROR:
  2814. pqi_process_aio_io_error(io_request);
  2815. break;
  2816. }
  2817. }
  2818. static int pqi_interpret_task_management_response(struct pqi_ctrl_info *ctrl_info,
  2819. struct pqi_task_management_response *response)
  2820. {
  2821. int rc;
  2822. switch (response->response_code) {
  2823. case SOP_TMF_COMPLETE:
  2824. case SOP_TMF_FUNCTION_SUCCEEDED:
  2825. rc = 0;
  2826. break;
  2827. case SOP_TMF_REJECTED:
  2828. rc = -EAGAIN;
  2829. break;
  2830. case SOP_RC_INCORRECT_LOGICAL_UNIT:
  2831. rc = -ENODEV;
  2832. break;
  2833. default:
  2834. rc = -EIO;
  2835. break;
  2836. }
  2837. if (rc)
  2838. dev_err(&ctrl_info->pci_dev->dev,
  2839. "Task Management Function error: %d (response code: %u)\n", rc, response->response_code);
  2840. return rc;
  2841. }
  2842. static inline void pqi_invalid_response(struct pqi_ctrl_info *ctrl_info,
  2843. enum pqi_ctrl_shutdown_reason ctrl_shutdown_reason)
  2844. {
  2845. pqi_take_ctrl_offline(ctrl_info, ctrl_shutdown_reason);
  2846. }
  2847. static int pqi_process_io_intr(struct pqi_ctrl_info *ctrl_info, struct pqi_queue_group *queue_group)
  2848. {
  2849. int num_responses;
  2850. pqi_index_t oq_pi;
  2851. pqi_index_t oq_ci;
  2852. struct pqi_io_request *io_request;
  2853. struct pqi_io_response *response;
  2854. u16 request_id;
  2855. num_responses = 0;
  2856. oq_ci = queue_group->oq_ci_copy;
  2857. while (1) {
  2858. oq_pi = readl(queue_group->oq_pi);
  2859. if (oq_pi >= ctrl_info->num_elements_per_oq) {
  2860. pqi_invalid_response(ctrl_info, PQI_IO_PI_OUT_OF_RANGE);
  2861. dev_err(&ctrl_info->pci_dev->dev,
  2862. "I/O interrupt: producer index (%u) out of range (0-%u): consumer index: %u\n",
  2863. oq_pi, ctrl_info->num_elements_per_oq - 1, oq_ci);
  2864. return -1;
  2865. }
  2866. if (oq_pi == oq_ci)
  2867. break;
  2868. num_responses++;
  2869. response = queue_group->oq_element_array +
  2870. (oq_ci * PQI_OPERATIONAL_OQ_ELEMENT_LENGTH);
  2871. request_id = get_unaligned_le16(&response->request_id);
  2872. if (request_id >= ctrl_info->max_io_slots) {
  2873. pqi_invalid_response(ctrl_info, PQI_INVALID_REQ_ID);
  2874. dev_err(&ctrl_info->pci_dev->dev,
  2875. "request ID in response (%u) out of range (0-%u): producer index: %u consumer index: %u\n",
  2876. request_id, ctrl_info->max_io_slots - 1, oq_pi, oq_ci);
  2877. return -1;
  2878. }
  2879. io_request = &ctrl_info->io_request_pool[request_id];
  2880. if (atomic_read(&io_request->refcount) == 0) {
  2881. pqi_invalid_response(ctrl_info, PQI_UNMATCHED_REQ_ID);
  2882. dev_err(&ctrl_info->pci_dev->dev,
  2883. "request ID in response (%u) does not match an outstanding I/O request: producer index: %u consumer index: %u\n",
  2884. request_id, oq_pi, oq_ci);
  2885. return -1;
  2886. }
  2887. switch (response->header.iu_type) {
  2888. case PQI_RESPONSE_IU_RAID_PATH_IO_SUCCESS:
  2889. case PQI_RESPONSE_IU_AIO_PATH_IO_SUCCESS:
  2890. if (io_request->scmd)
  2891. io_request->scmd->result = 0;
  2892. fallthrough;
  2893. case PQI_RESPONSE_IU_GENERAL_MANAGEMENT:
  2894. break;
  2895. case PQI_RESPONSE_IU_VENDOR_GENERAL:
  2896. io_request->status =
  2897. get_unaligned_le16(
  2898. &((struct pqi_vendor_general_response *)response)->status);
  2899. break;
  2900. case PQI_RESPONSE_IU_TASK_MANAGEMENT:
  2901. io_request->status = pqi_interpret_task_management_response(ctrl_info,
  2902. (void *)response);
  2903. break;
  2904. case PQI_RESPONSE_IU_AIO_PATH_DISABLED:
  2905. pqi_aio_path_disabled(io_request);
  2906. io_request->status = -EAGAIN;
  2907. break;
  2908. case PQI_RESPONSE_IU_RAID_PATH_IO_ERROR:
  2909. case PQI_RESPONSE_IU_AIO_PATH_IO_ERROR:
  2910. io_request->error_info = ctrl_info->error_buffer +
  2911. (get_unaligned_le16(&response->error_index) *
  2912. PQI_ERROR_BUFFER_ELEMENT_LENGTH);
  2913. pqi_process_io_error(response->header.iu_type, io_request);
  2914. break;
  2915. default:
  2916. pqi_invalid_response(ctrl_info, PQI_UNEXPECTED_IU_TYPE);
  2917. dev_err(&ctrl_info->pci_dev->dev,
  2918. "unexpected IU type: 0x%x: producer index: %u consumer index: %u\n",
  2919. response->header.iu_type, oq_pi, oq_ci);
  2920. return -1;
  2921. }
  2922. io_request->io_complete_callback(io_request, io_request->context);
  2923. /*
  2924. * Note that the I/O request structure CANNOT BE TOUCHED after
  2925. * returning from the I/O completion callback!
  2926. */
  2927. oq_ci = (oq_ci + 1) % ctrl_info->num_elements_per_oq;
  2928. }
  2929. if (num_responses) {
  2930. queue_group->oq_ci_copy = oq_ci;
  2931. writel(oq_ci, queue_group->oq_ci);
  2932. }
  2933. return num_responses;
  2934. }
  2935. static inline unsigned int pqi_num_elements_free(unsigned int pi,
  2936. unsigned int ci, unsigned int elements_in_queue)
  2937. {
  2938. unsigned int num_elements_used;
  2939. if (pi >= ci)
  2940. num_elements_used = pi - ci;
  2941. else
  2942. num_elements_used = elements_in_queue - ci + pi;
  2943. return elements_in_queue - num_elements_used - 1;
  2944. }
  2945. static void pqi_send_event_ack(struct pqi_ctrl_info *ctrl_info,
  2946. struct pqi_event_acknowledge_request *iu, size_t iu_length)
  2947. {
  2948. pqi_index_t iq_pi;
  2949. pqi_index_t iq_ci;
  2950. unsigned long flags;
  2951. void *next_element;
  2952. struct pqi_queue_group *queue_group;
  2953. queue_group = &ctrl_info->queue_groups[PQI_DEFAULT_QUEUE_GROUP];
  2954. put_unaligned_le16(queue_group->oq_id, &iu->header.response_queue_id);
  2955. while (1) {
  2956. spin_lock_irqsave(&queue_group->submit_lock[RAID_PATH], flags);
  2957. iq_pi = queue_group->iq_pi_copy[RAID_PATH];
  2958. iq_ci = readl(queue_group->iq_ci[RAID_PATH]);
  2959. if (pqi_num_elements_free(iq_pi, iq_ci,
  2960. ctrl_info->num_elements_per_iq))
  2961. break;
  2962. spin_unlock_irqrestore(
  2963. &queue_group->submit_lock[RAID_PATH], flags);
  2964. if (pqi_ctrl_offline(ctrl_info))
  2965. return;
  2966. }
  2967. next_element = queue_group->iq_element_array[RAID_PATH] +
  2968. (iq_pi * PQI_OPERATIONAL_IQ_ELEMENT_LENGTH);
  2969. memcpy(next_element, iu, iu_length);
  2970. iq_pi = (iq_pi + 1) % ctrl_info->num_elements_per_iq;
  2971. queue_group->iq_pi_copy[RAID_PATH] = iq_pi;
  2972. /*
  2973. * This write notifies the controller that an IU is available to be
  2974. * processed.
  2975. */
  2976. writel(iq_pi, queue_group->iq_pi[RAID_PATH]);
  2977. spin_unlock_irqrestore(&queue_group->submit_lock[RAID_PATH], flags);
  2978. }
  2979. static void pqi_acknowledge_event(struct pqi_ctrl_info *ctrl_info,
  2980. struct pqi_event *event)
  2981. {
  2982. struct pqi_event_acknowledge_request request;
  2983. memset(&request, 0, sizeof(request));
  2984. request.header.iu_type = PQI_REQUEST_IU_ACKNOWLEDGE_VENDOR_EVENT;
  2985. put_unaligned_le16(sizeof(request) - PQI_REQUEST_HEADER_LENGTH,
  2986. &request.header.iu_length);
  2987. request.event_type = event->event_type;
  2988. put_unaligned_le16(event->event_id, &request.event_id);
  2989. put_unaligned_le32(event->additional_event_id, &request.additional_event_id);
  2990. pqi_send_event_ack(ctrl_info, &request, sizeof(request));
  2991. }
  2992. #define PQI_SOFT_RESET_STATUS_TIMEOUT_SECS 30
  2993. #define PQI_SOFT_RESET_STATUS_POLL_INTERVAL_SECS 1
  2994. static enum pqi_soft_reset_status pqi_poll_for_soft_reset_status(
  2995. struct pqi_ctrl_info *ctrl_info)
  2996. {
  2997. u8 status;
  2998. unsigned long timeout;
  2999. timeout = (PQI_SOFT_RESET_STATUS_TIMEOUT_SECS * HZ) + jiffies;
  3000. while (1) {
  3001. status = pqi_read_soft_reset_status(ctrl_info);
  3002. if (status & PQI_SOFT_RESET_INITIATE)
  3003. return RESET_INITIATE_DRIVER;
  3004. if (status & PQI_SOFT_RESET_ABORT)
  3005. return RESET_ABORT;
  3006. if (!sis_is_firmware_running(ctrl_info))
  3007. return RESET_NORESPONSE;
  3008. if (time_after(jiffies, timeout)) {
  3009. dev_warn(&ctrl_info->pci_dev->dev,
  3010. "timed out waiting for soft reset status\n");
  3011. return RESET_TIMEDOUT;
  3012. }
  3013. ssleep(PQI_SOFT_RESET_STATUS_POLL_INTERVAL_SECS);
  3014. }
  3015. }
  3016. static void pqi_process_soft_reset(struct pqi_ctrl_info *ctrl_info)
  3017. {
  3018. int rc;
  3019. unsigned int delay_secs;
  3020. enum pqi_soft_reset_status reset_status;
  3021. if (ctrl_info->soft_reset_handshake_supported)
  3022. reset_status = pqi_poll_for_soft_reset_status(ctrl_info);
  3023. else
  3024. reset_status = RESET_INITIATE_FIRMWARE;
  3025. delay_secs = PQI_POST_RESET_DELAY_SECS;
  3026. switch (reset_status) {
  3027. case RESET_TIMEDOUT:
  3028. delay_secs = PQI_POST_OFA_RESET_DELAY_UPON_TIMEOUT_SECS;
  3029. fallthrough;
  3030. case RESET_INITIATE_DRIVER:
  3031. dev_info(&ctrl_info->pci_dev->dev,
  3032. "Online Firmware Activation: resetting controller\n");
  3033. sis_soft_reset(ctrl_info);
  3034. fallthrough;
  3035. case RESET_INITIATE_FIRMWARE:
  3036. ctrl_info->pqi_mode_enabled = false;
  3037. pqi_save_ctrl_mode(ctrl_info, SIS_MODE);
  3038. rc = pqi_ofa_ctrl_restart(ctrl_info, delay_secs);
  3039. pqi_ofa_free_host_buffer(ctrl_info);
  3040. pqi_ctrl_ofa_done(ctrl_info);
  3041. dev_info(&ctrl_info->pci_dev->dev,
  3042. "Online Firmware Activation: %s\n",
  3043. rc == 0 ? "SUCCESS" : "FAILED");
  3044. break;
  3045. case RESET_ABORT:
  3046. dev_info(&ctrl_info->pci_dev->dev,
  3047. "Online Firmware Activation ABORTED\n");
  3048. if (ctrl_info->soft_reset_handshake_supported)
  3049. pqi_clear_soft_reset_status(ctrl_info);
  3050. pqi_ofa_free_host_buffer(ctrl_info);
  3051. pqi_ctrl_ofa_done(ctrl_info);
  3052. pqi_ofa_ctrl_unquiesce(ctrl_info);
  3053. break;
  3054. case RESET_NORESPONSE:
  3055. fallthrough;
  3056. default:
  3057. dev_err(&ctrl_info->pci_dev->dev,
  3058. "unexpected Online Firmware Activation reset status: 0x%x\n",
  3059. reset_status);
  3060. pqi_ofa_free_host_buffer(ctrl_info);
  3061. pqi_ctrl_ofa_done(ctrl_info);
  3062. pqi_ofa_ctrl_unquiesce(ctrl_info);
  3063. pqi_take_ctrl_offline(ctrl_info, PQI_OFA_RESPONSE_TIMEOUT);
  3064. break;
  3065. }
  3066. }
  3067. static void pqi_ofa_memory_alloc_worker(struct work_struct *work)
  3068. {
  3069. struct pqi_ctrl_info *ctrl_info;
  3070. ctrl_info = container_of(work, struct pqi_ctrl_info, ofa_memory_alloc_work);
  3071. pqi_ctrl_ofa_start(ctrl_info);
  3072. pqi_ofa_setup_host_buffer(ctrl_info);
  3073. pqi_ofa_host_memory_update(ctrl_info);
  3074. }
  3075. static void pqi_ofa_quiesce_worker(struct work_struct *work)
  3076. {
  3077. struct pqi_ctrl_info *ctrl_info;
  3078. struct pqi_event *event;
  3079. ctrl_info = container_of(work, struct pqi_ctrl_info, ofa_quiesce_work);
  3080. event = &ctrl_info->events[pqi_event_type_to_event_index(PQI_EVENT_TYPE_OFA)];
  3081. pqi_ofa_ctrl_quiesce(ctrl_info);
  3082. pqi_acknowledge_event(ctrl_info, event);
  3083. pqi_process_soft_reset(ctrl_info);
  3084. }
  3085. static bool pqi_ofa_process_event(struct pqi_ctrl_info *ctrl_info,
  3086. struct pqi_event *event)
  3087. {
  3088. bool ack_event;
  3089. ack_event = true;
  3090. switch (event->event_id) {
  3091. case PQI_EVENT_OFA_MEMORY_ALLOCATION:
  3092. dev_info(&ctrl_info->pci_dev->dev,
  3093. "received Online Firmware Activation memory allocation request\n");
  3094. schedule_work(&ctrl_info->ofa_memory_alloc_work);
  3095. break;
  3096. case PQI_EVENT_OFA_QUIESCE:
  3097. dev_info(&ctrl_info->pci_dev->dev,
  3098. "received Online Firmware Activation quiesce request\n");
  3099. schedule_work(&ctrl_info->ofa_quiesce_work);
  3100. ack_event = false;
  3101. break;
  3102. case PQI_EVENT_OFA_CANCELED:
  3103. dev_info(&ctrl_info->pci_dev->dev,
  3104. "received Online Firmware Activation cancel request: reason: %u\n",
  3105. ctrl_info->ofa_cancel_reason);
  3106. pqi_ofa_free_host_buffer(ctrl_info);
  3107. pqi_ctrl_ofa_done(ctrl_info);
  3108. break;
  3109. default:
  3110. dev_err(&ctrl_info->pci_dev->dev,
  3111. "received unknown Online Firmware Activation request: event ID: %u\n",
  3112. event->event_id);
  3113. break;
  3114. }
  3115. return ack_event;
  3116. }
  3117. static void pqi_disable_raid_bypass(struct pqi_ctrl_info *ctrl_info)
  3118. {
  3119. unsigned long flags;
  3120. struct pqi_scsi_dev *device;
  3121. spin_lock_irqsave(&ctrl_info->scsi_device_list_lock, flags);
  3122. list_for_each_entry(device, &ctrl_info->scsi_device_list, scsi_device_list_entry)
  3123. if (device->raid_bypass_enabled)
  3124. device->raid_bypass_enabled = false;
  3125. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  3126. }
  3127. static void pqi_event_worker(struct work_struct *work)
  3128. {
  3129. unsigned int i;
  3130. bool rescan_needed;
  3131. struct pqi_ctrl_info *ctrl_info;
  3132. struct pqi_event *event;
  3133. bool ack_event;
  3134. ctrl_info = container_of(work, struct pqi_ctrl_info, event_work);
  3135. pqi_ctrl_busy(ctrl_info);
  3136. pqi_wait_if_ctrl_blocked(ctrl_info);
  3137. if (pqi_ctrl_offline(ctrl_info))
  3138. goto out;
  3139. rescan_needed = false;
  3140. event = ctrl_info->events;
  3141. for (i = 0; i < PQI_NUM_SUPPORTED_EVENTS; i++) {
  3142. if (event->pending) {
  3143. event->pending = false;
  3144. if (event->event_type == PQI_EVENT_TYPE_OFA) {
  3145. ack_event = pqi_ofa_process_event(ctrl_info, event);
  3146. } else {
  3147. ack_event = true;
  3148. rescan_needed = true;
  3149. if (event->event_type == PQI_EVENT_TYPE_LOGICAL_DEVICE)
  3150. ctrl_info->logical_volume_rescan_needed = true;
  3151. else if (event->event_type == PQI_EVENT_TYPE_AIO_STATE_CHANGE)
  3152. pqi_disable_raid_bypass(ctrl_info);
  3153. }
  3154. if (ack_event)
  3155. pqi_acknowledge_event(ctrl_info, event);
  3156. }
  3157. event++;
  3158. }
  3159. #define PQI_RESCAN_WORK_FOR_EVENT_DELAY (5 * HZ)
  3160. if (rescan_needed)
  3161. pqi_schedule_rescan_worker_with_delay(ctrl_info,
  3162. PQI_RESCAN_WORK_FOR_EVENT_DELAY);
  3163. out:
  3164. pqi_ctrl_unbusy(ctrl_info);
  3165. }
  3166. #define PQI_HEARTBEAT_TIMER_INTERVAL (10 * HZ)
  3167. static void pqi_heartbeat_timer_handler(struct timer_list *t)
  3168. {
  3169. int num_interrupts;
  3170. u32 heartbeat_count;
  3171. struct pqi_ctrl_info *ctrl_info = from_timer(ctrl_info, t, heartbeat_timer);
  3172. pqi_check_ctrl_health(ctrl_info);
  3173. if (pqi_ctrl_offline(ctrl_info))
  3174. return;
  3175. num_interrupts = atomic_read(&ctrl_info->num_interrupts);
  3176. heartbeat_count = pqi_read_heartbeat_counter(ctrl_info);
  3177. if (num_interrupts == ctrl_info->previous_num_interrupts) {
  3178. if (heartbeat_count == ctrl_info->previous_heartbeat_count) {
  3179. dev_err(&ctrl_info->pci_dev->dev,
  3180. "no heartbeat detected - last heartbeat count: %u\n",
  3181. heartbeat_count);
  3182. pqi_take_ctrl_offline(ctrl_info, PQI_NO_HEARTBEAT);
  3183. return;
  3184. }
  3185. } else {
  3186. ctrl_info->previous_num_interrupts = num_interrupts;
  3187. }
  3188. ctrl_info->previous_heartbeat_count = heartbeat_count;
  3189. mod_timer(&ctrl_info->heartbeat_timer,
  3190. jiffies + PQI_HEARTBEAT_TIMER_INTERVAL);
  3191. }
  3192. static void pqi_start_heartbeat_timer(struct pqi_ctrl_info *ctrl_info)
  3193. {
  3194. if (!ctrl_info->heartbeat_counter)
  3195. return;
  3196. ctrl_info->previous_num_interrupts =
  3197. atomic_read(&ctrl_info->num_interrupts);
  3198. ctrl_info->previous_heartbeat_count =
  3199. pqi_read_heartbeat_counter(ctrl_info);
  3200. ctrl_info->heartbeat_timer.expires =
  3201. jiffies + PQI_HEARTBEAT_TIMER_INTERVAL;
  3202. add_timer(&ctrl_info->heartbeat_timer);
  3203. }
  3204. static inline void pqi_stop_heartbeat_timer(struct pqi_ctrl_info *ctrl_info)
  3205. {
  3206. del_timer_sync(&ctrl_info->heartbeat_timer);
  3207. }
  3208. static void pqi_ofa_capture_event_payload(struct pqi_ctrl_info *ctrl_info,
  3209. struct pqi_event *event, struct pqi_event_response *response)
  3210. {
  3211. switch (event->event_id) {
  3212. case PQI_EVENT_OFA_MEMORY_ALLOCATION:
  3213. ctrl_info->ofa_bytes_requested =
  3214. get_unaligned_le32(&response->data.ofa_memory_allocation.bytes_requested);
  3215. break;
  3216. case PQI_EVENT_OFA_CANCELED:
  3217. ctrl_info->ofa_cancel_reason =
  3218. get_unaligned_le16(&response->data.ofa_cancelled.reason);
  3219. break;
  3220. }
  3221. }
  3222. static int pqi_process_event_intr(struct pqi_ctrl_info *ctrl_info)
  3223. {
  3224. int num_events;
  3225. pqi_index_t oq_pi;
  3226. pqi_index_t oq_ci;
  3227. struct pqi_event_queue *event_queue;
  3228. struct pqi_event_response *response;
  3229. struct pqi_event *event;
  3230. int event_index;
  3231. event_queue = &ctrl_info->event_queue;
  3232. num_events = 0;
  3233. oq_ci = event_queue->oq_ci_copy;
  3234. while (1) {
  3235. oq_pi = readl(event_queue->oq_pi);
  3236. if (oq_pi >= PQI_NUM_EVENT_QUEUE_ELEMENTS) {
  3237. pqi_invalid_response(ctrl_info, PQI_EVENT_PI_OUT_OF_RANGE);
  3238. dev_err(&ctrl_info->pci_dev->dev,
  3239. "event interrupt: producer index (%u) out of range (0-%u): consumer index: %u\n",
  3240. oq_pi, PQI_NUM_EVENT_QUEUE_ELEMENTS - 1, oq_ci);
  3241. return -1;
  3242. }
  3243. if (oq_pi == oq_ci)
  3244. break;
  3245. num_events++;
  3246. response = event_queue->oq_element_array + (oq_ci * PQI_EVENT_OQ_ELEMENT_LENGTH);
  3247. event_index = pqi_event_type_to_event_index(response->event_type);
  3248. if (event_index >= 0 && response->request_acknowledge) {
  3249. event = &ctrl_info->events[event_index];
  3250. event->pending = true;
  3251. event->event_type = response->event_type;
  3252. event->event_id = get_unaligned_le16(&response->event_id);
  3253. event->additional_event_id =
  3254. get_unaligned_le32(&response->additional_event_id);
  3255. if (event->event_type == PQI_EVENT_TYPE_OFA)
  3256. pqi_ofa_capture_event_payload(ctrl_info, event, response);
  3257. }
  3258. oq_ci = (oq_ci + 1) % PQI_NUM_EVENT_QUEUE_ELEMENTS;
  3259. }
  3260. if (num_events) {
  3261. event_queue->oq_ci_copy = oq_ci;
  3262. writel(oq_ci, event_queue->oq_ci);
  3263. schedule_work(&ctrl_info->event_work);
  3264. }
  3265. return num_events;
  3266. }
  3267. #define PQI_LEGACY_INTX_MASK 0x1
  3268. static inline void pqi_configure_legacy_intx(struct pqi_ctrl_info *ctrl_info, bool enable_intx)
  3269. {
  3270. u32 intx_mask;
  3271. struct pqi_device_registers __iomem *pqi_registers;
  3272. volatile void __iomem *register_addr;
  3273. pqi_registers = ctrl_info->pqi_registers;
  3274. if (enable_intx)
  3275. register_addr = &pqi_registers->legacy_intx_mask_clear;
  3276. else
  3277. register_addr = &pqi_registers->legacy_intx_mask_set;
  3278. intx_mask = readl(register_addr);
  3279. intx_mask |= PQI_LEGACY_INTX_MASK;
  3280. writel(intx_mask, register_addr);
  3281. }
  3282. static void pqi_change_irq_mode(struct pqi_ctrl_info *ctrl_info,
  3283. enum pqi_irq_mode new_mode)
  3284. {
  3285. switch (ctrl_info->irq_mode) {
  3286. case IRQ_MODE_MSIX:
  3287. switch (new_mode) {
  3288. case IRQ_MODE_MSIX:
  3289. break;
  3290. case IRQ_MODE_INTX:
  3291. pqi_configure_legacy_intx(ctrl_info, true);
  3292. sis_enable_intx(ctrl_info);
  3293. break;
  3294. case IRQ_MODE_NONE:
  3295. break;
  3296. }
  3297. break;
  3298. case IRQ_MODE_INTX:
  3299. switch (new_mode) {
  3300. case IRQ_MODE_MSIX:
  3301. pqi_configure_legacy_intx(ctrl_info, false);
  3302. sis_enable_msix(ctrl_info);
  3303. break;
  3304. case IRQ_MODE_INTX:
  3305. break;
  3306. case IRQ_MODE_NONE:
  3307. pqi_configure_legacy_intx(ctrl_info, false);
  3308. break;
  3309. }
  3310. break;
  3311. case IRQ_MODE_NONE:
  3312. switch (new_mode) {
  3313. case IRQ_MODE_MSIX:
  3314. sis_enable_msix(ctrl_info);
  3315. break;
  3316. case IRQ_MODE_INTX:
  3317. pqi_configure_legacy_intx(ctrl_info, true);
  3318. sis_enable_intx(ctrl_info);
  3319. break;
  3320. case IRQ_MODE_NONE:
  3321. break;
  3322. }
  3323. break;
  3324. }
  3325. ctrl_info->irq_mode = new_mode;
  3326. }
  3327. #define PQI_LEGACY_INTX_PENDING 0x1
  3328. static inline bool pqi_is_valid_irq(struct pqi_ctrl_info *ctrl_info)
  3329. {
  3330. bool valid_irq;
  3331. u32 intx_status;
  3332. switch (ctrl_info->irq_mode) {
  3333. case IRQ_MODE_MSIX:
  3334. valid_irq = true;
  3335. break;
  3336. case IRQ_MODE_INTX:
  3337. intx_status = readl(&ctrl_info->pqi_registers->legacy_intx_status);
  3338. if (intx_status & PQI_LEGACY_INTX_PENDING)
  3339. valid_irq = true;
  3340. else
  3341. valid_irq = false;
  3342. break;
  3343. case IRQ_MODE_NONE:
  3344. default:
  3345. valid_irq = false;
  3346. break;
  3347. }
  3348. return valid_irq;
  3349. }
  3350. static irqreturn_t pqi_irq_handler(int irq, void *data)
  3351. {
  3352. struct pqi_ctrl_info *ctrl_info;
  3353. struct pqi_queue_group *queue_group;
  3354. int num_io_responses_handled;
  3355. int num_events_handled;
  3356. queue_group = data;
  3357. ctrl_info = queue_group->ctrl_info;
  3358. if (!pqi_is_valid_irq(ctrl_info))
  3359. return IRQ_NONE;
  3360. num_io_responses_handled = pqi_process_io_intr(ctrl_info, queue_group);
  3361. if (num_io_responses_handled < 0)
  3362. goto out;
  3363. if (irq == ctrl_info->event_irq) {
  3364. num_events_handled = pqi_process_event_intr(ctrl_info);
  3365. if (num_events_handled < 0)
  3366. goto out;
  3367. } else {
  3368. num_events_handled = 0;
  3369. }
  3370. if (num_io_responses_handled + num_events_handled > 0)
  3371. atomic_inc(&ctrl_info->num_interrupts);
  3372. pqi_start_io(ctrl_info, queue_group, RAID_PATH, NULL);
  3373. pqi_start_io(ctrl_info, queue_group, AIO_PATH, NULL);
  3374. out:
  3375. return IRQ_HANDLED;
  3376. }
  3377. static int pqi_request_irqs(struct pqi_ctrl_info *ctrl_info)
  3378. {
  3379. struct pci_dev *pci_dev = ctrl_info->pci_dev;
  3380. int i;
  3381. int rc;
  3382. ctrl_info->event_irq = pci_irq_vector(pci_dev, 0);
  3383. for (i = 0; i < ctrl_info->num_msix_vectors_enabled; i++) {
  3384. rc = request_irq(pci_irq_vector(pci_dev, i), pqi_irq_handler, 0,
  3385. DRIVER_NAME_SHORT, &ctrl_info->queue_groups[i]);
  3386. if (rc) {
  3387. dev_err(&pci_dev->dev,
  3388. "irq %u init failed with error %d\n",
  3389. pci_irq_vector(pci_dev, i), rc);
  3390. return rc;
  3391. }
  3392. ctrl_info->num_msix_vectors_initialized++;
  3393. }
  3394. return 0;
  3395. }
  3396. static void pqi_free_irqs(struct pqi_ctrl_info *ctrl_info)
  3397. {
  3398. int i;
  3399. for (i = 0; i < ctrl_info->num_msix_vectors_initialized; i++)
  3400. free_irq(pci_irq_vector(ctrl_info->pci_dev, i),
  3401. &ctrl_info->queue_groups[i]);
  3402. ctrl_info->num_msix_vectors_initialized = 0;
  3403. }
  3404. static int pqi_enable_msix_interrupts(struct pqi_ctrl_info *ctrl_info)
  3405. {
  3406. int num_vectors_enabled;
  3407. unsigned int flags = PCI_IRQ_MSIX;
  3408. if (!pqi_disable_managed_interrupts)
  3409. flags |= PCI_IRQ_AFFINITY;
  3410. num_vectors_enabled = pci_alloc_irq_vectors(ctrl_info->pci_dev,
  3411. PQI_MIN_MSIX_VECTORS, ctrl_info->num_queue_groups,
  3412. flags);
  3413. if (num_vectors_enabled < 0) {
  3414. dev_err(&ctrl_info->pci_dev->dev,
  3415. "MSI-X init failed with error %d\n",
  3416. num_vectors_enabled);
  3417. return num_vectors_enabled;
  3418. }
  3419. ctrl_info->num_msix_vectors_enabled = num_vectors_enabled;
  3420. ctrl_info->irq_mode = IRQ_MODE_MSIX;
  3421. return 0;
  3422. }
  3423. static void pqi_disable_msix_interrupts(struct pqi_ctrl_info *ctrl_info)
  3424. {
  3425. if (ctrl_info->num_msix_vectors_enabled) {
  3426. pci_free_irq_vectors(ctrl_info->pci_dev);
  3427. ctrl_info->num_msix_vectors_enabled = 0;
  3428. }
  3429. }
  3430. static int pqi_alloc_operational_queues(struct pqi_ctrl_info *ctrl_info)
  3431. {
  3432. unsigned int i;
  3433. size_t alloc_length;
  3434. size_t element_array_length_per_iq;
  3435. size_t element_array_length_per_oq;
  3436. void *element_array;
  3437. void __iomem *next_queue_index;
  3438. void *aligned_pointer;
  3439. unsigned int num_inbound_queues;
  3440. unsigned int num_outbound_queues;
  3441. unsigned int num_queue_indexes;
  3442. struct pqi_queue_group *queue_group;
  3443. element_array_length_per_iq =
  3444. PQI_OPERATIONAL_IQ_ELEMENT_LENGTH *
  3445. ctrl_info->num_elements_per_iq;
  3446. element_array_length_per_oq =
  3447. PQI_OPERATIONAL_OQ_ELEMENT_LENGTH *
  3448. ctrl_info->num_elements_per_oq;
  3449. num_inbound_queues = ctrl_info->num_queue_groups * 2;
  3450. num_outbound_queues = ctrl_info->num_queue_groups;
  3451. num_queue_indexes = (ctrl_info->num_queue_groups * 3) + 1;
  3452. aligned_pointer = NULL;
  3453. for (i = 0; i < num_inbound_queues; i++) {
  3454. aligned_pointer = PTR_ALIGN(aligned_pointer,
  3455. PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT);
  3456. aligned_pointer += element_array_length_per_iq;
  3457. }
  3458. for (i = 0; i < num_outbound_queues; i++) {
  3459. aligned_pointer = PTR_ALIGN(aligned_pointer,
  3460. PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT);
  3461. aligned_pointer += element_array_length_per_oq;
  3462. }
  3463. aligned_pointer = PTR_ALIGN(aligned_pointer,
  3464. PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT);
  3465. aligned_pointer += PQI_NUM_EVENT_QUEUE_ELEMENTS *
  3466. PQI_EVENT_OQ_ELEMENT_LENGTH;
  3467. for (i = 0; i < num_queue_indexes; i++) {
  3468. aligned_pointer = PTR_ALIGN(aligned_pointer,
  3469. PQI_OPERATIONAL_INDEX_ALIGNMENT);
  3470. aligned_pointer += sizeof(pqi_index_t);
  3471. }
  3472. alloc_length = (size_t)aligned_pointer +
  3473. PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT;
  3474. alloc_length += PQI_EXTRA_SGL_MEMORY;
  3475. ctrl_info->queue_memory_base =
  3476. dma_alloc_coherent(&ctrl_info->pci_dev->dev, alloc_length,
  3477. &ctrl_info->queue_memory_base_dma_handle,
  3478. GFP_KERNEL);
  3479. if (!ctrl_info->queue_memory_base)
  3480. return -ENOMEM;
  3481. ctrl_info->queue_memory_length = alloc_length;
  3482. element_array = PTR_ALIGN(ctrl_info->queue_memory_base,
  3483. PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT);
  3484. for (i = 0; i < ctrl_info->num_queue_groups; i++) {
  3485. queue_group = &ctrl_info->queue_groups[i];
  3486. queue_group->iq_element_array[RAID_PATH] = element_array;
  3487. queue_group->iq_element_array_bus_addr[RAID_PATH] =
  3488. ctrl_info->queue_memory_base_dma_handle +
  3489. (element_array - ctrl_info->queue_memory_base);
  3490. element_array += element_array_length_per_iq;
  3491. element_array = PTR_ALIGN(element_array,
  3492. PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT);
  3493. queue_group->iq_element_array[AIO_PATH] = element_array;
  3494. queue_group->iq_element_array_bus_addr[AIO_PATH] =
  3495. ctrl_info->queue_memory_base_dma_handle +
  3496. (element_array - ctrl_info->queue_memory_base);
  3497. element_array += element_array_length_per_iq;
  3498. element_array = PTR_ALIGN(element_array,
  3499. PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT);
  3500. }
  3501. for (i = 0; i < ctrl_info->num_queue_groups; i++) {
  3502. queue_group = &ctrl_info->queue_groups[i];
  3503. queue_group->oq_element_array = element_array;
  3504. queue_group->oq_element_array_bus_addr =
  3505. ctrl_info->queue_memory_base_dma_handle +
  3506. (element_array - ctrl_info->queue_memory_base);
  3507. element_array += element_array_length_per_oq;
  3508. element_array = PTR_ALIGN(element_array,
  3509. PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT);
  3510. }
  3511. ctrl_info->event_queue.oq_element_array = element_array;
  3512. ctrl_info->event_queue.oq_element_array_bus_addr =
  3513. ctrl_info->queue_memory_base_dma_handle +
  3514. (element_array - ctrl_info->queue_memory_base);
  3515. element_array += PQI_NUM_EVENT_QUEUE_ELEMENTS *
  3516. PQI_EVENT_OQ_ELEMENT_LENGTH;
  3517. next_queue_index = (void __iomem *)PTR_ALIGN(element_array,
  3518. PQI_OPERATIONAL_INDEX_ALIGNMENT);
  3519. for (i = 0; i < ctrl_info->num_queue_groups; i++) {
  3520. queue_group = &ctrl_info->queue_groups[i];
  3521. queue_group->iq_ci[RAID_PATH] = next_queue_index;
  3522. queue_group->iq_ci_bus_addr[RAID_PATH] =
  3523. ctrl_info->queue_memory_base_dma_handle +
  3524. (next_queue_index -
  3525. (void __iomem *)ctrl_info->queue_memory_base);
  3526. next_queue_index += sizeof(pqi_index_t);
  3527. next_queue_index = PTR_ALIGN(next_queue_index,
  3528. PQI_OPERATIONAL_INDEX_ALIGNMENT);
  3529. queue_group->iq_ci[AIO_PATH] = next_queue_index;
  3530. queue_group->iq_ci_bus_addr[AIO_PATH] =
  3531. ctrl_info->queue_memory_base_dma_handle +
  3532. (next_queue_index -
  3533. (void __iomem *)ctrl_info->queue_memory_base);
  3534. next_queue_index += sizeof(pqi_index_t);
  3535. next_queue_index = PTR_ALIGN(next_queue_index,
  3536. PQI_OPERATIONAL_INDEX_ALIGNMENT);
  3537. queue_group->oq_pi = next_queue_index;
  3538. queue_group->oq_pi_bus_addr =
  3539. ctrl_info->queue_memory_base_dma_handle +
  3540. (next_queue_index -
  3541. (void __iomem *)ctrl_info->queue_memory_base);
  3542. next_queue_index += sizeof(pqi_index_t);
  3543. next_queue_index = PTR_ALIGN(next_queue_index,
  3544. PQI_OPERATIONAL_INDEX_ALIGNMENT);
  3545. }
  3546. ctrl_info->event_queue.oq_pi = next_queue_index;
  3547. ctrl_info->event_queue.oq_pi_bus_addr =
  3548. ctrl_info->queue_memory_base_dma_handle +
  3549. (next_queue_index -
  3550. (void __iomem *)ctrl_info->queue_memory_base);
  3551. return 0;
  3552. }
  3553. static void pqi_init_operational_queues(struct pqi_ctrl_info *ctrl_info)
  3554. {
  3555. unsigned int i;
  3556. u16 next_iq_id = PQI_MIN_OPERATIONAL_QUEUE_ID;
  3557. u16 next_oq_id = PQI_MIN_OPERATIONAL_QUEUE_ID;
  3558. /*
  3559. * Initialize the backpointers to the controller structure in
  3560. * each operational queue group structure.
  3561. */
  3562. for (i = 0; i < ctrl_info->num_queue_groups; i++)
  3563. ctrl_info->queue_groups[i].ctrl_info = ctrl_info;
  3564. /*
  3565. * Assign IDs to all operational queues. Note that the IDs
  3566. * assigned to operational IQs are independent of the IDs
  3567. * assigned to operational OQs.
  3568. */
  3569. ctrl_info->event_queue.oq_id = next_oq_id++;
  3570. for (i = 0; i < ctrl_info->num_queue_groups; i++) {
  3571. ctrl_info->queue_groups[i].iq_id[RAID_PATH] = next_iq_id++;
  3572. ctrl_info->queue_groups[i].iq_id[AIO_PATH] = next_iq_id++;
  3573. ctrl_info->queue_groups[i].oq_id = next_oq_id++;
  3574. }
  3575. /*
  3576. * Assign MSI-X table entry indexes to all queues. Note that the
  3577. * interrupt for the event queue is shared with the first queue group.
  3578. */
  3579. ctrl_info->event_queue.int_msg_num = 0;
  3580. for (i = 0; i < ctrl_info->num_queue_groups; i++)
  3581. ctrl_info->queue_groups[i].int_msg_num = i;
  3582. for (i = 0; i < ctrl_info->num_queue_groups; i++) {
  3583. spin_lock_init(&ctrl_info->queue_groups[i].submit_lock[0]);
  3584. spin_lock_init(&ctrl_info->queue_groups[i].submit_lock[1]);
  3585. INIT_LIST_HEAD(&ctrl_info->queue_groups[i].request_list[0]);
  3586. INIT_LIST_HEAD(&ctrl_info->queue_groups[i].request_list[1]);
  3587. }
  3588. }
  3589. static int pqi_alloc_admin_queues(struct pqi_ctrl_info *ctrl_info)
  3590. {
  3591. size_t alloc_length;
  3592. struct pqi_admin_queues_aligned *admin_queues_aligned;
  3593. struct pqi_admin_queues *admin_queues;
  3594. alloc_length = sizeof(struct pqi_admin_queues_aligned) +
  3595. PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT;
  3596. ctrl_info->admin_queue_memory_base =
  3597. dma_alloc_coherent(&ctrl_info->pci_dev->dev, alloc_length,
  3598. &ctrl_info->admin_queue_memory_base_dma_handle,
  3599. GFP_KERNEL);
  3600. if (!ctrl_info->admin_queue_memory_base)
  3601. return -ENOMEM;
  3602. ctrl_info->admin_queue_memory_length = alloc_length;
  3603. admin_queues = &ctrl_info->admin_queues;
  3604. admin_queues_aligned = PTR_ALIGN(ctrl_info->admin_queue_memory_base,
  3605. PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT);
  3606. admin_queues->iq_element_array =
  3607. &admin_queues_aligned->iq_element_array;
  3608. admin_queues->oq_element_array =
  3609. &admin_queues_aligned->oq_element_array;
  3610. admin_queues->iq_ci =
  3611. (pqi_index_t __iomem *)&admin_queues_aligned->iq_ci;
  3612. admin_queues->oq_pi =
  3613. (pqi_index_t __iomem *)&admin_queues_aligned->oq_pi;
  3614. admin_queues->iq_element_array_bus_addr =
  3615. ctrl_info->admin_queue_memory_base_dma_handle +
  3616. (admin_queues->iq_element_array -
  3617. ctrl_info->admin_queue_memory_base);
  3618. admin_queues->oq_element_array_bus_addr =
  3619. ctrl_info->admin_queue_memory_base_dma_handle +
  3620. (admin_queues->oq_element_array -
  3621. ctrl_info->admin_queue_memory_base);
  3622. admin_queues->iq_ci_bus_addr =
  3623. ctrl_info->admin_queue_memory_base_dma_handle +
  3624. ((void __iomem *)admin_queues->iq_ci -
  3625. (void __iomem *)ctrl_info->admin_queue_memory_base);
  3626. admin_queues->oq_pi_bus_addr =
  3627. ctrl_info->admin_queue_memory_base_dma_handle +
  3628. ((void __iomem *)admin_queues->oq_pi -
  3629. (void __iomem *)ctrl_info->admin_queue_memory_base);
  3630. return 0;
  3631. }
  3632. #define PQI_ADMIN_QUEUE_CREATE_TIMEOUT_JIFFIES HZ
  3633. #define PQI_ADMIN_QUEUE_CREATE_POLL_INTERVAL_MSECS 1
  3634. static int pqi_create_admin_queues(struct pqi_ctrl_info *ctrl_info)
  3635. {
  3636. struct pqi_device_registers __iomem *pqi_registers;
  3637. struct pqi_admin_queues *admin_queues;
  3638. unsigned long timeout;
  3639. u8 status;
  3640. u32 reg;
  3641. pqi_registers = ctrl_info->pqi_registers;
  3642. admin_queues = &ctrl_info->admin_queues;
  3643. writeq((u64)admin_queues->iq_element_array_bus_addr,
  3644. &pqi_registers->admin_iq_element_array_addr);
  3645. writeq((u64)admin_queues->oq_element_array_bus_addr,
  3646. &pqi_registers->admin_oq_element_array_addr);
  3647. writeq((u64)admin_queues->iq_ci_bus_addr,
  3648. &pqi_registers->admin_iq_ci_addr);
  3649. writeq((u64)admin_queues->oq_pi_bus_addr,
  3650. &pqi_registers->admin_oq_pi_addr);
  3651. reg = PQI_ADMIN_IQ_NUM_ELEMENTS |
  3652. (PQI_ADMIN_OQ_NUM_ELEMENTS << 8) |
  3653. (admin_queues->int_msg_num << 16);
  3654. writel(reg, &pqi_registers->admin_iq_num_elements);
  3655. writel(PQI_CREATE_ADMIN_QUEUE_PAIR,
  3656. &pqi_registers->function_and_status_code);
  3657. timeout = PQI_ADMIN_QUEUE_CREATE_TIMEOUT_JIFFIES + jiffies;
  3658. while (1) {
  3659. msleep(PQI_ADMIN_QUEUE_CREATE_POLL_INTERVAL_MSECS);
  3660. status = readb(&pqi_registers->function_and_status_code);
  3661. if (status == PQI_STATUS_IDLE)
  3662. break;
  3663. if (time_after(jiffies, timeout))
  3664. return -ETIMEDOUT;
  3665. }
  3666. /*
  3667. * The offset registers are not initialized to the correct
  3668. * offsets until *after* the create admin queue pair command
  3669. * completes successfully.
  3670. */
  3671. admin_queues->iq_pi = ctrl_info->iomem_base +
  3672. PQI_DEVICE_REGISTERS_OFFSET +
  3673. readq(&pqi_registers->admin_iq_pi_offset);
  3674. admin_queues->oq_ci = ctrl_info->iomem_base +
  3675. PQI_DEVICE_REGISTERS_OFFSET +
  3676. readq(&pqi_registers->admin_oq_ci_offset);
  3677. return 0;
  3678. }
  3679. static void pqi_submit_admin_request(struct pqi_ctrl_info *ctrl_info,
  3680. struct pqi_general_admin_request *request)
  3681. {
  3682. struct pqi_admin_queues *admin_queues;
  3683. void *next_element;
  3684. pqi_index_t iq_pi;
  3685. admin_queues = &ctrl_info->admin_queues;
  3686. iq_pi = admin_queues->iq_pi_copy;
  3687. next_element = admin_queues->iq_element_array +
  3688. (iq_pi * PQI_ADMIN_IQ_ELEMENT_LENGTH);
  3689. memcpy(next_element, request, sizeof(*request));
  3690. iq_pi = (iq_pi + 1) % PQI_ADMIN_IQ_NUM_ELEMENTS;
  3691. admin_queues->iq_pi_copy = iq_pi;
  3692. /*
  3693. * This write notifies the controller that an IU is available to be
  3694. * processed.
  3695. */
  3696. writel(iq_pi, admin_queues->iq_pi);
  3697. }
  3698. #define PQI_ADMIN_REQUEST_TIMEOUT_SECS 60
  3699. static int pqi_poll_for_admin_response(struct pqi_ctrl_info *ctrl_info,
  3700. struct pqi_general_admin_response *response)
  3701. {
  3702. struct pqi_admin_queues *admin_queues;
  3703. pqi_index_t oq_pi;
  3704. pqi_index_t oq_ci;
  3705. unsigned long timeout;
  3706. admin_queues = &ctrl_info->admin_queues;
  3707. oq_ci = admin_queues->oq_ci_copy;
  3708. timeout = (PQI_ADMIN_REQUEST_TIMEOUT_SECS * HZ) + jiffies;
  3709. while (1) {
  3710. oq_pi = readl(admin_queues->oq_pi);
  3711. if (oq_pi != oq_ci)
  3712. break;
  3713. if (time_after(jiffies, timeout)) {
  3714. dev_err(&ctrl_info->pci_dev->dev,
  3715. "timed out waiting for admin response\n");
  3716. return -ETIMEDOUT;
  3717. }
  3718. if (!sis_is_firmware_running(ctrl_info))
  3719. return -ENXIO;
  3720. usleep_range(1000, 2000);
  3721. }
  3722. memcpy(response, admin_queues->oq_element_array +
  3723. (oq_ci * PQI_ADMIN_OQ_ELEMENT_LENGTH), sizeof(*response));
  3724. oq_ci = (oq_ci + 1) % PQI_ADMIN_OQ_NUM_ELEMENTS;
  3725. admin_queues->oq_ci_copy = oq_ci;
  3726. writel(oq_ci, admin_queues->oq_ci);
  3727. return 0;
  3728. }
  3729. static void pqi_start_io(struct pqi_ctrl_info *ctrl_info,
  3730. struct pqi_queue_group *queue_group, enum pqi_io_path path,
  3731. struct pqi_io_request *io_request)
  3732. {
  3733. struct pqi_io_request *next;
  3734. void *next_element;
  3735. pqi_index_t iq_pi;
  3736. pqi_index_t iq_ci;
  3737. size_t iu_length;
  3738. unsigned long flags;
  3739. unsigned int num_elements_needed;
  3740. unsigned int num_elements_to_end_of_queue;
  3741. size_t copy_count;
  3742. struct pqi_iu_header *request;
  3743. spin_lock_irqsave(&queue_group->submit_lock[path], flags);
  3744. if (io_request) {
  3745. io_request->queue_group = queue_group;
  3746. list_add_tail(&io_request->request_list_entry,
  3747. &queue_group->request_list[path]);
  3748. }
  3749. iq_pi = queue_group->iq_pi_copy[path];
  3750. list_for_each_entry_safe(io_request, next,
  3751. &queue_group->request_list[path], request_list_entry) {
  3752. request = io_request->iu;
  3753. iu_length = get_unaligned_le16(&request->iu_length) +
  3754. PQI_REQUEST_HEADER_LENGTH;
  3755. num_elements_needed =
  3756. DIV_ROUND_UP(iu_length,
  3757. PQI_OPERATIONAL_IQ_ELEMENT_LENGTH);
  3758. iq_ci = readl(queue_group->iq_ci[path]);
  3759. if (num_elements_needed > pqi_num_elements_free(iq_pi, iq_ci,
  3760. ctrl_info->num_elements_per_iq))
  3761. break;
  3762. put_unaligned_le16(queue_group->oq_id,
  3763. &request->response_queue_id);
  3764. next_element = queue_group->iq_element_array[path] +
  3765. (iq_pi * PQI_OPERATIONAL_IQ_ELEMENT_LENGTH);
  3766. num_elements_to_end_of_queue =
  3767. ctrl_info->num_elements_per_iq - iq_pi;
  3768. if (num_elements_needed <= num_elements_to_end_of_queue) {
  3769. memcpy(next_element, request, iu_length);
  3770. } else {
  3771. copy_count = num_elements_to_end_of_queue *
  3772. PQI_OPERATIONAL_IQ_ELEMENT_LENGTH;
  3773. memcpy(next_element, request, copy_count);
  3774. memcpy(queue_group->iq_element_array[path],
  3775. (u8 *)request + copy_count,
  3776. iu_length - copy_count);
  3777. }
  3778. iq_pi = (iq_pi + num_elements_needed) %
  3779. ctrl_info->num_elements_per_iq;
  3780. list_del(&io_request->request_list_entry);
  3781. }
  3782. if (iq_pi != queue_group->iq_pi_copy[path]) {
  3783. queue_group->iq_pi_copy[path] = iq_pi;
  3784. /*
  3785. * This write notifies the controller that one or more IUs are
  3786. * available to be processed.
  3787. */
  3788. writel(iq_pi, queue_group->iq_pi[path]);
  3789. }
  3790. spin_unlock_irqrestore(&queue_group->submit_lock[path], flags);
  3791. }
  3792. #define PQI_WAIT_FOR_COMPLETION_IO_TIMEOUT_SECS 10
  3793. static int pqi_wait_for_completion_io(struct pqi_ctrl_info *ctrl_info,
  3794. struct completion *wait)
  3795. {
  3796. int rc;
  3797. while (1) {
  3798. if (wait_for_completion_io_timeout(wait,
  3799. PQI_WAIT_FOR_COMPLETION_IO_TIMEOUT_SECS * HZ)) {
  3800. rc = 0;
  3801. break;
  3802. }
  3803. pqi_check_ctrl_health(ctrl_info);
  3804. if (pqi_ctrl_offline(ctrl_info)) {
  3805. rc = -ENXIO;
  3806. break;
  3807. }
  3808. }
  3809. return rc;
  3810. }
  3811. static void pqi_raid_synchronous_complete(struct pqi_io_request *io_request,
  3812. void *context)
  3813. {
  3814. struct completion *waiting = context;
  3815. complete(waiting);
  3816. }
  3817. static int pqi_process_raid_io_error_synchronous(
  3818. struct pqi_raid_error_info *error_info)
  3819. {
  3820. int rc = -EIO;
  3821. switch (error_info->data_out_result) {
  3822. case PQI_DATA_IN_OUT_GOOD:
  3823. if (error_info->status == SAM_STAT_GOOD)
  3824. rc = 0;
  3825. break;
  3826. case PQI_DATA_IN_OUT_UNDERFLOW:
  3827. if (error_info->status == SAM_STAT_GOOD ||
  3828. error_info->status == SAM_STAT_CHECK_CONDITION)
  3829. rc = 0;
  3830. break;
  3831. case PQI_DATA_IN_OUT_ABORTED:
  3832. rc = PQI_CMD_STATUS_ABORTED;
  3833. break;
  3834. }
  3835. return rc;
  3836. }
  3837. static inline bool pqi_is_blockable_request(struct pqi_iu_header *request)
  3838. {
  3839. return (request->driver_flags & PQI_DRIVER_NONBLOCKABLE_REQUEST) == 0;
  3840. }
  3841. static int pqi_submit_raid_request_synchronous(struct pqi_ctrl_info *ctrl_info,
  3842. struct pqi_iu_header *request, unsigned int flags,
  3843. struct pqi_raid_error_info *error_info)
  3844. {
  3845. int rc = 0;
  3846. struct pqi_io_request *io_request;
  3847. size_t iu_length;
  3848. DECLARE_COMPLETION_ONSTACK(wait);
  3849. if (flags & PQI_SYNC_FLAGS_INTERRUPTABLE) {
  3850. if (down_interruptible(&ctrl_info->sync_request_sem))
  3851. return -ERESTARTSYS;
  3852. } else {
  3853. down(&ctrl_info->sync_request_sem);
  3854. }
  3855. pqi_ctrl_busy(ctrl_info);
  3856. /*
  3857. * Wait for other admin queue updates such as;
  3858. * config table changes, OFA memory updates, ...
  3859. */
  3860. if (pqi_is_blockable_request(request))
  3861. pqi_wait_if_ctrl_blocked(ctrl_info);
  3862. if (pqi_ctrl_offline(ctrl_info)) {
  3863. rc = -ENXIO;
  3864. goto out;
  3865. }
  3866. io_request = pqi_alloc_io_request(ctrl_info);
  3867. put_unaligned_le16(io_request->index,
  3868. &(((struct pqi_raid_path_request *)request)->request_id));
  3869. if (request->iu_type == PQI_REQUEST_IU_RAID_PATH_IO)
  3870. ((struct pqi_raid_path_request *)request)->error_index =
  3871. ((struct pqi_raid_path_request *)request)->request_id;
  3872. iu_length = get_unaligned_le16(&request->iu_length) +
  3873. PQI_REQUEST_HEADER_LENGTH;
  3874. memcpy(io_request->iu, request, iu_length);
  3875. io_request->io_complete_callback = pqi_raid_synchronous_complete;
  3876. io_request->context = &wait;
  3877. pqi_start_io(ctrl_info, &ctrl_info->queue_groups[PQI_DEFAULT_QUEUE_GROUP], RAID_PATH,
  3878. io_request);
  3879. pqi_wait_for_completion_io(ctrl_info, &wait);
  3880. if (error_info) {
  3881. if (io_request->error_info)
  3882. memcpy(error_info, io_request->error_info, sizeof(*error_info));
  3883. else
  3884. memset(error_info, 0, sizeof(*error_info));
  3885. } else if (rc == 0 && io_request->error_info) {
  3886. rc = pqi_process_raid_io_error_synchronous(io_request->error_info);
  3887. }
  3888. pqi_free_io_request(io_request);
  3889. out:
  3890. pqi_ctrl_unbusy(ctrl_info);
  3891. up(&ctrl_info->sync_request_sem);
  3892. return rc;
  3893. }
  3894. static int pqi_validate_admin_response(
  3895. struct pqi_general_admin_response *response, u8 expected_function_code)
  3896. {
  3897. if (response->header.iu_type != PQI_RESPONSE_IU_GENERAL_ADMIN)
  3898. return -EINVAL;
  3899. if (get_unaligned_le16(&response->header.iu_length) !=
  3900. PQI_GENERAL_ADMIN_IU_LENGTH)
  3901. return -EINVAL;
  3902. if (response->function_code != expected_function_code)
  3903. return -EINVAL;
  3904. if (response->status != PQI_GENERAL_ADMIN_STATUS_SUCCESS)
  3905. return -EINVAL;
  3906. return 0;
  3907. }
  3908. static int pqi_submit_admin_request_synchronous(
  3909. struct pqi_ctrl_info *ctrl_info,
  3910. struct pqi_general_admin_request *request,
  3911. struct pqi_general_admin_response *response)
  3912. {
  3913. int rc;
  3914. pqi_submit_admin_request(ctrl_info, request);
  3915. rc = pqi_poll_for_admin_response(ctrl_info, response);
  3916. if (rc == 0)
  3917. rc = pqi_validate_admin_response(response, request->function_code);
  3918. return rc;
  3919. }
  3920. static int pqi_report_device_capability(struct pqi_ctrl_info *ctrl_info)
  3921. {
  3922. int rc;
  3923. struct pqi_general_admin_request request;
  3924. struct pqi_general_admin_response response;
  3925. struct pqi_device_capability *capability;
  3926. struct pqi_iu_layer_descriptor *sop_iu_layer_descriptor;
  3927. capability = kmalloc(sizeof(*capability), GFP_KERNEL);
  3928. if (!capability)
  3929. return -ENOMEM;
  3930. memset(&request, 0, sizeof(request));
  3931. request.header.iu_type = PQI_REQUEST_IU_GENERAL_ADMIN;
  3932. put_unaligned_le16(PQI_GENERAL_ADMIN_IU_LENGTH,
  3933. &request.header.iu_length);
  3934. request.function_code =
  3935. PQI_GENERAL_ADMIN_FUNCTION_REPORT_DEVICE_CAPABILITY;
  3936. put_unaligned_le32(sizeof(*capability),
  3937. &request.data.report_device_capability.buffer_length);
  3938. rc = pqi_map_single(ctrl_info->pci_dev,
  3939. &request.data.report_device_capability.sg_descriptor,
  3940. capability, sizeof(*capability),
  3941. DMA_FROM_DEVICE);
  3942. if (rc)
  3943. goto out;
  3944. rc = pqi_submit_admin_request_synchronous(ctrl_info, &request, &response);
  3945. pqi_pci_unmap(ctrl_info->pci_dev,
  3946. &request.data.report_device_capability.sg_descriptor, 1,
  3947. DMA_FROM_DEVICE);
  3948. if (rc)
  3949. goto out;
  3950. if (response.status != PQI_GENERAL_ADMIN_STATUS_SUCCESS) {
  3951. rc = -EIO;
  3952. goto out;
  3953. }
  3954. ctrl_info->max_inbound_queues =
  3955. get_unaligned_le16(&capability->max_inbound_queues);
  3956. ctrl_info->max_elements_per_iq =
  3957. get_unaligned_le16(&capability->max_elements_per_iq);
  3958. ctrl_info->max_iq_element_length =
  3959. get_unaligned_le16(&capability->max_iq_element_length)
  3960. * 16;
  3961. ctrl_info->max_outbound_queues =
  3962. get_unaligned_le16(&capability->max_outbound_queues);
  3963. ctrl_info->max_elements_per_oq =
  3964. get_unaligned_le16(&capability->max_elements_per_oq);
  3965. ctrl_info->max_oq_element_length =
  3966. get_unaligned_le16(&capability->max_oq_element_length)
  3967. * 16;
  3968. sop_iu_layer_descriptor =
  3969. &capability->iu_layer_descriptors[PQI_PROTOCOL_SOP];
  3970. ctrl_info->max_inbound_iu_length_per_firmware =
  3971. get_unaligned_le16(
  3972. &sop_iu_layer_descriptor->max_inbound_iu_length);
  3973. ctrl_info->inbound_spanning_supported =
  3974. sop_iu_layer_descriptor->inbound_spanning_supported;
  3975. ctrl_info->outbound_spanning_supported =
  3976. sop_iu_layer_descriptor->outbound_spanning_supported;
  3977. out:
  3978. kfree(capability);
  3979. return rc;
  3980. }
  3981. static int pqi_validate_device_capability(struct pqi_ctrl_info *ctrl_info)
  3982. {
  3983. if (ctrl_info->max_iq_element_length <
  3984. PQI_OPERATIONAL_IQ_ELEMENT_LENGTH) {
  3985. dev_err(&ctrl_info->pci_dev->dev,
  3986. "max. inbound queue element length of %d is less than the required length of %d\n",
  3987. ctrl_info->max_iq_element_length,
  3988. PQI_OPERATIONAL_IQ_ELEMENT_LENGTH);
  3989. return -EINVAL;
  3990. }
  3991. if (ctrl_info->max_oq_element_length <
  3992. PQI_OPERATIONAL_OQ_ELEMENT_LENGTH) {
  3993. dev_err(&ctrl_info->pci_dev->dev,
  3994. "max. outbound queue element length of %d is less than the required length of %d\n",
  3995. ctrl_info->max_oq_element_length,
  3996. PQI_OPERATIONAL_OQ_ELEMENT_LENGTH);
  3997. return -EINVAL;
  3998. }
  3999. if (ctrl_info->max_inbound_iu_length_per_firmware <
  4000. PQI_OPERATIONAL_IQ_ELEMENT_LENGTH) {
  4001. dev_err(&ctrl_info->pci_dev->dev,
  4002. "max. inbound IU length of %u is less than the min. required length of %d\n",
  4003. ctrl_info->max_inbound_iu_length_per_firmware,
  4004. PQI_OPERATIONAL_IQ_ELEMENT_LENGTH);
  4005. return -EINVAL;
  4006. }
  4007. if (!ctrl_info->inbound_spanning_supported) {
  4008. dev_err(&ctrl_info->pci_dev->dev,
  4009. "the controller does not support inbound spanning\n");
  4010. return -EINVAL;
  4011. }
  4012. if (ctrl_info->outbound_spanning_supported) {
  4013. dev_err(&ctrl_info->pci_dev->dev,
  4014. "the controller supports outbound spanning but this driver does not\n");
  4015. return -EINVAL;
  4016. }
  4017. return 0;
  4018. }
  4019. static int pqi_create_event_queue(struct pqi_ctrl_info *ctrl_info)
  4020. {
  4021. int rc;
  4022. struct pqi_event_queue *event_queue;
  4023. struct pqi_general_admin_request request;
  4024. struct pqi_general_admin_response response;
  4025. event_queue = &ctrl_info->event_queue;
  4026. /*
  4027. * Create OQ (Outbound Queue - device to host queue) to dedicate
  4028. * to events.
  4029. */
  4030. memset(&request, 0, sizeof(request));
  4031. request.header.iu_type = PQI_REQUEST_IU_GENERAL_ADMIN;
  4032. put_unaligned_le16(PQI_GENERAL_ADMIN_IU_LENGTH,
  4033. &request.header.iu_length);
  4034. request.function_code = PQI_GENERAL_ADMIN_FUNCTION_CREATE_OQ;
  4035. put_unaligned_le16(event_queue->oq_id,
  4036. &request.data.create_operational_oq.queue_id);
  4037. put_unaligned_le64((u64)event_queue->oq_element_array_bus_addr,
  4038. &request.data.create_operational_oq.element_array_addr);
  4039. put_unaligned_le64((u64)event_queue->oq_pi_bus_addr,
  4040. &request.data.create_operational_oq.pi_addr);
  4041. put_unaligned_le16(PQI_NUM_EVENT_QUEUE_ELEMENTS,
  4042. &request.data.create_operational_oq.num_elements);
  4043. put_unaligned_le16(PQI_EVENT_OQ_ELEMENT_LENGTH / 16,
  4044. &request.data.create_operational_oq.element_length);
  4045. request.data.create_operational_oq.queue_protocol = PQI_PROTOCOL_SOP;
  4046. put_unaligned_le16(event_queue->int_msg_num,
  4047. &request.data.create_operational_oq.int_msg_num);
  4048. rc = pqi_submit_admin_request_synchronous(ctrl_info, &request,
  4049. &response);
  4050. if (rc)
  4051. return rc;
  4052. event_queue->oq_ci = ctrl_info->iomem_base +
  4053. PQI_DEVICE_REGISTERS_OFFSET +
  4054. get_unaligned_le64(
  4055. &response.data.create_operational_oq.oq_ci_offset);
  4056. return 0;
  4057. }
  4058. static int pqi_create_queue_group(struct pqi_ctrl_info *ctrl_info,
  4059. unsigned int group_number)
  4060. {
  4061. int rc;
  4062. struct pqi_queue_group *queue_group;
  4063. struct pqi_general_admin_request request;
  4064. struct pqi_general_admin_response response;
  4065. queue_group = &ctrl_info->queue_groups[group_number];
  4066. /*
  4067. * Create IQ (Inbound Queue - host to device queue) for
  4068. * RAID path.
  4069. */
  4070. memset(&request, 0, sizeof(request));
  4071. request.header.iu_type = PQI_REQUEST_IU_GENERAL_ADMIN;
  4072. put_unaligned_le16(PQI_GENERAL_ADMIN_IU_LENGTH,
  4073. &request.header.iu_length);
  4074. request.function_code = PQI_GENERAL_ADMIN_FUNCTION_CREATE_IQ;
  4075. put_unaligned_le16(queue_group->iq_id[RAID_PATH],
  4076. &request.data.create_operational_iq.queue_id);
  4077. put_unaligned_le64(
  4078. (u64)queue_group->iq_element_array_bus_addr[RAID_PATH],
  4079. &request.data.create_operational_iq.element_array_addr);
  4080. put_unaligned_le64((u64)queue_group->iq_ci_bus_addr[RAID_PATH],
  4081. &request.data.create_operational_iq.ci_addr);
  4082. put_unaligned_le16(ctrl_info->num_elements_per_iq,
  4083. &request.data.create_operational_iq.num_elements);
  4084. put_unaligned_le16(PQI_OPERATIONAL_IQ_ELEMENT_LENGTH / 16,
  4085. &request.data.create_operational_iq.element_length);
  4086. request.data.create_operational_iq.queue_protocol = PQI_PROTOCOL_SOP;
  4087. rc = pqi_submit_admin_request_synchronous(ctrl_info, &request,
  4088. &response);
  4089. if (rc) {
  4090. dev_err(&ctrl_info->pci_dev->dev,
  4091. "error creating inbound RAID queue\n");
  4092. return rc;
  4093. }
  4094. queue_group->iq_pi[RAID_PATH] = ctrl_info->iomem_base +
  4095. PQI_DEVICE_REGISTERS_OFFSET +
  4096. get_unaligned_le64(
  4097. &response.data.create_operational_iq.iq_pi_offset);
  4098. /*
  4099. * Create IQ (Inbound Queue - host to device queue) for
  4100. * Advanced I/O (AIO) path.
  4101. */
  4102. memset(&request, 0, sizeof(request));
  4103. request.header.iu_type = PQI_REQUEST_IU_GENERAL_ADMIN;
  4104. put_unaligned_le16(PQI_GENERAL_ADMIN_IU_LENGTH,
  4105. &request.header.iu_length);
  4106. request.function_code = PQI_GENERAL_ADMIN_FUNCTION_CREATE_IQ;
  4107. put_unaligned_le16(queue_group->iq_id[AIO_PATH],
  4108. &request.data.create_operational_iq.queue_id);
  4109. put_unaligned_le64((u64)queue_group->
  4110. iq_element_array_bus_addr[AIO_PATH],
  4111. &request.data.create_operational_iq.element_array_addr);
  4112. put_unaligned_le64((u64)queue_group->iq_ci_bus_addr[AIO_PATH],
  4113. &request.data.create_operational_iq.ci_addr);
  4114. put_unaligned_le16(ctrl_info->num_elements_per_iq,
  4115. &request.data.create_operational_iq.num_elements);
  4116. put_unaligned_le16(PQI_OPERATIONAL_IQ_ELEMENT_LENGTH / 16,
  4117. &request.data.create_operational_iq.element_length);
  4118. request.data.create_operational_iq.queue_protocol = PQI_PROTOCOL_SOP;
  4119. rc = pqi_submit_admin_request_synchronous(ctrl_info, &request,
  4120. &response);
  4121. if (rc) {
  4122. dev_err(&ctrl_info->pci_dev->dev,
  4123. "error creating inbound AIO queue\n");
  4124. return rc;
  4125. }
  4126. queue_group->iq_pi[AIO_PATH] = ctrl_info->iomem_base +
  4127. PQI_DEVICE_REGISTERS_OFFSET +
  4128. get_unaligned_le64(
  4129. &response.data.create_operational_iq.iq_pi_offset);
  4130. /*
  4131. * Designate the 2nd IQ as the AIO path. By default, all IQs are
  4132. * assumed to be for RAID path I/O unless we change the queue's
  4133. * property.
  4134. */
  4135. memset(&request, 0, sizeof(request));
  4136. request.header.iu_type = PQI_REQUEST_IU_GENERAL_ADMIN;
  4137. put_unaligned_le16(PQI_GENERAL_ADMIN_IU_LENGTH,
  4138. &request.header.iu_length);
  4139. request.function_code = PQI_GENERAL_ADMIN_FUNCTION_CHANGE_IQ_PROPERTY;
  4140. put_unaligned_le16(queue_group->iq_id[AIO_PATH],
  4141. &request.data.change_operational_iq_properties.queue_id);
  4142. put_unaligned_le32(PQI_IQ_PROPERTY_IS_AIO_QUEUE,
  4143. &request.data.change_operational_iq_properties.vendor_specific);
  4144. rc = pqi_submit_admin_request_synchronous(ctrl_info, &request,
  4145. &response);
  4146. if (rc) {
  4147. dev_err(&ctrl_info->pci_dev->dev,
  4148. "error changing queue property\n");
  4149. return rc;
  4150. }
  4151. /*
  4152. * Create OQ (Outbound Queue - device to host queue).
  4153. */
  4154. memset(&request, 0, sizeof(request));
  4155. request.header.iu_type = PQI_REQUEST_IU_GENERAL_ADMIN;
  4156. put_unaligned_le16(PQI_GENERAL_ADMIN_IU_LENGTH,
  4157. &request.header.iu_length);
  4158. request.function_code = PQI_GENERAL_ADMIN_FUNCTION_CREATE_OQ;
  4159. put_unaligned_le16(queue_group->oq_id,
  4160. &request.data.create_operational_oq.queue_id);
  4161. put_unaligned_le64((u64)queue_group->oq_element_array_bus_addr,
  4162. &request.data.create_operational_oq.element_array_addr);
  4163. put_unaligned_le64((u64)queue_group->oq_pi_bus_addr,
  4164. &request.data.create_operational_oq.pi_addr);
  4165. put_unaligned_le16(ctrl_info->num_elements_per_oq,
  4166. &request.data.create_operational_oq.num_elements);
  4167. put_unaligned_le16(PQI_OPERATIONAL_OQ_ELEMENT_LENGTH / 16,
  4168. &request.data.create_operational_oq.element_length);
  4169. request.data.create_operational_oq.queue_protocol = PQI_PROTOCOL_SOP;
  4170. put_unaligned_le16(queue_group->int_msg_num,
  4171. &request.data.create_operational_oq.int_msg_num);
  4172. rc = pqi_submit_admin_request_synchronous(ctrl_info, &request,
  4173. &response);
  4174. if (rc) {
  4175. dev_err(&ctrl_info->pci_dev->dev,
  4176. "error creating outbound queue\n");
  4177. return rc;
  4178. }
  4179. queue_group->oq_ci = ctrl_info->iomem_base +
  4180. PQI_DEVICE_REGISTERS_OFFSET +
  4181. get_unaligned_le64(
  4182. &response.data.create_operational_oq.oq_ci_offset);
  4183. return 0;
  4184. }
  4185. static int pqi_create_queues(struct pqi_ctrl_info *ctrl_info)
  4186. {
  4187. int rc;
  4188. unsigned int i;
  4189. rc = pqi_create_event_queue(ctrl_info);
  4190. if (rc) {
  4191. dev_err(&ctrl_info->pci_dev->dev,
  4192. "error creating event queue\n");
  4193. return rc;
  4194. }
  4195. for (i = 0; i < ctrl_info->num_queue_groups; i++) {
  4196. rc = pqi_create_queue_group(ctrl_info, i);
  4197. if (rc) {
  4198. dev_err(&ctrl_info->pci_dev->dev,
  4199. "error creating queue group number %u/%u\n",
  4200. i, ctrl_info->num_queue_groups);
  4201. return rc;
  4202. }
  4203. }
  4204. return 0;
  4205. }
  4206. #define PQI_REPORT_EVENT_CONFIG_BUFFER_LENGTH \
  4207. struct_size((struct pqi_event_config *)0, descriptors, PQI_MAX_EVENT_DESCRIPTORS)
  4208. static int pqi_configure_events(struct pqi_ctrl_info *ctrl_info,
  4209. bool enable_events)
  4210. {
  4211. int rc;
  4212. unsigned int i;
  4213. struct pqi_event_config *event_config;
  4214. struct pqi_event_descriptor *event_descriptor;
  4215. struct pqi_general_management_request request;
  4216. event_config = kmalloc(PQI_REPORT_EVENT_CONFIG_BUFFER_LENGTH,
  4217. GFP_KERNEL);
  4218. if (!event_config)
  4219. return -ENOMEM;
  4220. memset(&request, 0, sizeof(request));
  4221. request.header.iu_type = PQI_REQUEST_IU_REPORT_VENDOR_EVENT_CONFIG;
  4222. put_unaligned_le16(offsetof(struct pqi_general_management_request,
  4223. data.report_event_configuration.sg_descriptors[1]) -
  4224. PQI_REQUEST_HEADER_LENGTH, &request.header.iu_length);
  4225. put_unaligned_le32(PQI_REPORT_EVENT_CONFIG_BUFFER_LENGTH,
  4226. &request.data.report_event_configuration.buffer_length);
  4227. rc = pqi_map_single(ctrl_info->pci_dev,
  4228. request.data.report_event_configuration.sg_descriptors,
  4229. event_config, PQI_REPORT_EVENT_CONFIG_BUFFER_LENGTH,
  4230. DMA_FROM_DEVICE);
  4231. if (rc)
  4232. goto out;
  4233. rc = pqi_submit_raid_request_synchronous(ctrl_info, &request.header, 0, NULL);
  4234. pqi_pci_unmap(ctrl_info->pci_dev,
  4235. request.data.report_event_configuration.sg_descriptors, 1,
  4236. DMA_FROM_DEVICE);
  4237. if (rc)
  4238. goto out;
  4239. for (i = 0; i < event_config->num_event_descriptors; i++) {
  4240. event_descriptor = &event_config->descriptors[i];
  4241. if (enable_events &&
  4242. pqi_is_supported_event(event_descriptor->event_type))
  4243. put_unaligned_le16(ctrl_info->event_queue.oq_id,
  4244. &event_descriptor->oq_id);
  4245. else
  4246. put_unaligned_le16(0, &event_descriptor->oq_id);
  4247. }
  4248. memset(&request, 0, sizeof(request));
  4249. request.header.iu_type = PQI_REQUEST_IU_SET_VENDOR_EVENT_CONFIG;
  4250. put_unaligned_le16(offsetof(struct pqi_general_management_request,
  4251. data.report_event_configuration.sg_descriptors[1]) -
  4252. PQI_REQUEST_HEADER_LENGTH, &request.header.iu_length);
  4253. put_unaligned_le32(PQI_REPORT_EVENT_CONFIG_BUFFER_LENGTH,
  4254. &request.data.report_event_configuration.buffer_length);
  4255. rc = pqi_map_single(ctrl_info->pci_dev,
  4256. request.data.report_event_configuration.sg_descriptors,
  4257. event_config, PQI_REPORT_EVENT_CONFIG_BUFFER_LENGTH,
  4258. DMA_TO_DEVICE);
  4259. if (rc)
  4260. goto out;
  4261. rc = pqi_submit_raid_request_synchronous(ctrl_info, &request.header, 0, NULL);
  4262. pqi_pci_unmap(ctrl_info->pci_dev,
  4263. request.data.report_event_configuration.sg_descriptors, 1,
  4264. DMA_TO_DEVICE);
  4265. out:
  4266. kfree(event_config);
  4267. return rc;
  4268. }
  4269. static inline int pqi_enable_events(struct pqi_ctrl_info *ctrl_info)
  4270. {
  4271. return pqi_configure_events(ctrl_info, true);
  4272. }
  4273. static void pqi_free_all_io_requests(struct pqi_ctrl_info *ctrl_info)
  4274. {
  4275. unsigned int i;
  4276. struct device *dev;
  4277. size_t sg_chain_buffer_length;
  4278. struct pqi_io_request *io_request;
  4279. if (!ctrl_info->io_request_pool)
  4280. return;
  4281. dev = &ctrl_info->pci_dev->dev;
  4282. sg_chain_buffer_length = ctrl_info->sg_chain_buffer_length;
  4283. io_request = ctrl_info->io_request_pool;
  4284. for (i = 0; i < ctrl_info->max_io_slots; i++) {
  4285. kfree(io_request->iu);
  4286. if (!io_request->sg_chain_buffer)
  4287. break;
  4288. dma_free_coherent(dev, sg_chain_buffer_length,
  4289. io_request->sg_chain_buffer,
  4290. io_request->sg_chain_buffer_dma_handle);
  4291. io_request++;
  4292. }
  4293. kfree(ctrl_info->io_request_pool);
  4294. ctrl_info->io_request_pool = NULL;
  4295. }
  4296. static inline int pqi_alloc_error_buffer(struct pqi_ctrl_info *ctrl_info)
  4297. {
  4298. ctrl_info->error_buffer = dma_alloc_coherent(&ctrl_info->pci_dev->dev,
  4299. ctrl_info->error_buffer_length,
  4300. &ctrl_info->error_buffer_dma_handle,
  4301. GFP_KERNEL);
  4302. if (!ctrl_info->error_buffer)
  4303. return -ENOMEM;
  4304. return 0;
  4305. }
  4306. static int pqi_alloc_io_resources(struct pqi_ctrl_info *ctrl_info)
  4307. {
  4308. unsigned int i;
  4309. void *sg_chain_buffer;
  4310. size_t sg_chain_buffer_length;
  4311. dma_addr_t sg_chain_buffer_dma_handle;
  4312. struct device *dev;
  4313. struct pqi_io_request *io_request;
  4314. ctrl_info->io_request_pool = kcalloc(ctrl_info->max_io_slots,
  4315. sizeof(ctrl_info->io_request_pool[0]), GFP_KERNEL);
  4316. if (!ctrl_info->io_request_pool) {
  4317. dev_err(&ctrl_info->pci_dev->dev,
  4318. "failed to allocate I/O request pool\n");
  4319. goto error;
  4320. }
  4321. dev = &ctrl_info->pci_dev->dev;
  4322. sg_chain_buffer_length = ctrl_info->sg_chain_buffer_length;
  4323. io_request = ctrl_info->io_request_pool;
  4324. for (i = 0; i < ctrl_info->max_io_slots; i++) {
  4325. io_request->iu = kmalloc(ctrl_info->max_inbound_iu_length, GFP_KERNEL);
  4326. if (!io_request->iu) {
  4327. dev_err(&ctrl_info->pci_dev->dev,
  4328. "failed to allocate IU buffers\n");
  4329. goto error;
  4330. }
  4331. sg_chain_buffer = dma_alloc_coherent(dev,
  4332. sg_chain_buffer_length, &sg_chain_buffer_dma_handle,
  4333. GFP_KERNEL);
  4334. if (!sg_chain_buffer) {
  4335. dev_err(&ctrl_info->pci_dev->dev,
  4336. "failed to allocate PQI scatter-gather chain buffers\n");
  4337. goto error;
  4338. }
  4339. io_request->index = i;
  4340. io_request->sg_chain_buffer = sg_chain_buffer;
  4341. io_request->sg_chain_buffer_dma_handle = sg_chain_buffer_dma_handle;
  4342. io_request++;
  4343. }
  4344. return 0;
  4345. error:
  4346. pqi_free_all_io_requests(ctrl_info);
  4347. return -ENOMEM;
  4348. }
  4349. /*
  4350. * Calculate required resources that are sized based on max. outstanding
  4351. * requests and max. transfer size.
  4352. */
  4353. static void pqi_calculate_io_resources(struct pqi_ctrl_info *ctrl_info)
  4354. {
  4355. u32 max_transfer_size;
  4356. u32 max_sg_entries;
  4357. ctrl_info->scsi_ml_can_queue =
  4358. ctrl_info->max_outstanding_requests - PQI_RESERVED_IO_SLOTS;
  4359. ctrl_info->max_io_slots = ctrl_info->max_outstanding_requests;
  4360. ctrl_info->error_buffer_length =
  4361. ctrl_info->max_io_slots * PQI_ERROR_BUFFER_ELEMENT_LENGTH;
  4362. if (reset_devices)
  4363. max_transfer_size = min(ctrl_info->max_transfer_size,
  4364. PQI_MAX_TRANSFER_SIZE_KDUMP);
  4365. else
  4366. max_transfer_size = min(ctrl_info->max_transfer_size,
  4367. PQI_MAX_TRANSFER_SIZE);
  4368. max_sg_entries = max_transfer_size / PAGE_SIZE;
  4369. /* +1 to cover when the buffer is not page-aligned. */
  4370. max_sg_entries++;
  4371. max_sg_entries = min(ctrl_info->max_sg_entries, max_sg_entries);
  4372. max_transfer_size = (max_sg_entries - 1) * PAGE_SIZE;
  4373. ctrl_info->sg_chain_buffer_length =
  4374. (max_sg_entries * sizeof(struct pqi_sg_descriptor)) +
  4375. PQI_EXTRA_SGL_MEMORY;
  4376. ctrl_info->sg_tablesize = max_sg_entries;
  4377. ctrl_info->max_sectors = max_transfer_size / 512;
  4378. }
  4379. static void pqi_calculate_queue_resources(struct pqi_ctrl_info *ctrl_info)
  4380. {
  4381. int num_queue_groups;
  4382. u16 num_elements_per_iq;
  4383. u16 num_elements_per_oq;
  4384. if (reset_devices) {
  4385. num_queue_groups = 1;
  4386. } else {
  4387. int num_cpus;
  4388. int max_queue_groups;
  4389. max_queue_groups = min(ctrl_info->max_inbound_queues / 2,
  4390. ctrl_info->max_outbound_queues - 1);
  4391. max_queue_groups = min(max_queue_groups, PQI_MAX_QUEUE_GROUPS);
  4392. num_cpus = num_online_cpus();
  4393. num_queue_groups = min(num_cpus, ctrl_info->max_msix_vectors);
  4394. num_queue_groups = min(num_queue_groups, max_queue_groups);
  4395. }
  4396. ctrl_info->num_queue_groups = num_queue_groups;
  4397. ctrl_info->max_hw_queue_index = num_queue_groups - 1;
  4398. /*
  4399. * Make sure that the max. inbound IU length is an even multiple
  4400. * of our inbound element length.
  4401. */
  4402. ctrl_info->max_inbound_iu_length =
  4403. (ctrl_info->max_inbound_iu_length_per_firmware /
  4404. PQI_OPERATIONAL_IQ_ELEMENT_LENGTH) *
  4405. PQI_OPERATIONAL_IQ_ELEMENT_LENGTH;
  4406. num_elements_per_iq =
  4407. (ctrl_info->max_inbound_iu_length /
  4408. PQI_OPERATIONAL_IQ_ELEMENT_LENGTH);
  4409. /* Add one because one element in each queue is unusable. */
  4410. num_elements_per_iq++;
  4411. num_elements_per_iq = min(num_elements_per_iq,
  4412. ctrl_info->max_elements_per_iq);
  4413. num_elements_per_oq = ((num_elements_per_iq - 1) * 2) + 1;
  4414. num_elements_per_oq = min(num_elements_per_oq,
  4415. ctrl_info->max_elements_per_oq);
  4416. ctrl_info->num_elements_per_iq = num_elements_per_iq;
  4417. ctrl_info->num_elements_per_oq = num_elements_per_oq;
  4418. ctrl_info->max_sg_per_iu =
  4419. ((ctrl_info->max_inbound_iu_length -
  4420. PQI_OPERATIONAL_IQ_ELEMENT_LENGTH) /
  4421. sizeof(struct pqi_sg_descriptor)) +
  4422. PQI_MAX_EMBEDDED_SG_DESCRIPTORS;
  4423. ctrl_info->max_sg_per_r56_iu =
  4424. ((ctrl_info->max_inbound_iu_length -
  4425. PQI_OPERATIONAL_IQ_ELEMENT_LENGTH) /
  4426. sizeof(struct pqi_sg_descriptor)) +
  4427. PQI_MAX_EMBEDDED_R56_SG_DESCRIPTORS;
  4428. }
  4429. static inline void pqi_set_sg_descriptor(struct pqi_sg_descriptor *sg_descriptor,
  4430. struct scatterlist *sg)
  4431. {
  4432. u64 address = (u64)sg_dma_address(sg);
  4433. unsigned int length = sg_dma_len(sg);
  4434. put_unaligned_le64(address, &sg_descriptor->address);
  4435. put_unaligned_le32(length, &sg_descriptor->length);
  4436. put_unaligned_le32(0, &sg_descriptor->flags);
  4437. }
  4438. static unsigned int pqi_build_sg_list(struct pqi_sg_descriptor *sg_descriptor,
  4439. struct scatterlist *sg, int sg_count, struct pqi_io_request *io_request,
  4440. int max_sg_per_iu, bool *chained)
  4441. {
  4442. int i;
  4443. unsigned int num_sg_in_iu;
  4444. *chained = false;
  4445. i = 0;
  4446. num_sg_in_iu = 0;
  4447. max_sg_per_iu--; /* Subtract 1 to leave room for chain marker. */
  4448. while (1) {
  4449. pqi_set_sg_descriptor(sg_descriptor, sg);
  4450. if (!*chained)
  4451. num_sg_in_iu++;
  4452. i++;
  4453. if (i == sg_count)
  4454. break;
  4455. sg_descriptor++;
  4456. if (i == max_sg_per_iu) {
  4457. put_unaligned_le64((u64)io_request->sg_chain_buffer_dma_handle,
  4458. &sg_descriptor->address);
  4459. put_unaligned_le32((sg_count - num_sg_in_iu) * sizeof(*sg_descriptor),
  4460. &sg_descriptor->length);
  4461. put_unaligned_le32(CISS_SG_CHAIN, &sg_descriptor->flags);
  4462. *chained = true;
  4463. num_sg_in_iu++;
  4464. sg_descriptor = io_request->sg_chain_buffer;
  4465. }
  4466. sg = sg_next(sg);
  4467. }
  4468. put_unaligned_le32(CISS_SG_LAST, &sg_descriptor->flags);
  4469. return num_sg_in_iu;
  4470. }
  4471. static int pqi_build_raid_sg_list(struct pqi_ctrl_info *ctrl_info,
  4472. struct pqi_raid_path_request *request, struct scsi_cmnd *scmd,
  4473. struct pqi_io_request *io_request)
  4474. {
  4475. u16 iu_length;
  4476. int sg_count;
  4477. bool chained;
  4478. unsigned int num_sg_in_iu;
  4479. struct scatterlist *sg;
  4480. struct pqi_sg_descriptor *sg_descriptor;
  4481. sg_count = scsi_dma_map(scmd);
  4482. if (sg_count < 0)
  4483. return sg_count;
  4484. iu_length = offsetof(struct pqi_raid_path_request, sg_descriptors) -
  4485. PQI_REQUEST_HEADER_LENGTH;
  4486. if (sg_count == 0)
  4487. goto out;
  4488. sg = scsi_sglist(scmd);
  4489. sg_descriptor = request->sg_descriptors;
  4490. num_sg_in_iu = pqi_build_sg_list(sg_descriptor, sg, sg_count, io_request,
  4491. ctrl_info->max_sg_per_iu, &chained);
  4492. request->partial = chained;
  4493. iu_length += num_sg_in_iu * sizeof(*sg_descriptor);
  4494. out:
  4495. put_unaligned_le16(iu_length, &request->header.iu_length);
  4496. return 0;
  4497. }
  4498. static int pqi_build_aio_r1_sg_list(struct pqi_ctrl_info *ctrl_info,
  4499. struct pqi_aio_r1_path_request *request, struct scsi_cmnd *scmd,
  4500. struct pqi_io_request *io_request)
  4501. {
  4502. u16 iu_length;
  4503. int sg_count;
  4504. bool chained;
  4505. unsigned int num_sg_in_iu;
  4506. struct scatterlist *sg;
  4507. struct pqi_sg_descriptor *sg_descriptor;
  4508. sg_count = scsi_dma_map(scmd);
  4509. if (sg_count < 0)
  4510. return sg_count;
  4511. iu_length = offsetof(struct pqi_aio_r1_path_request, sg_descriptors) -
  4512. PQI_REQUEST_HEADER_LENGTH;
  4513. num_sg_in_iu = 0;
  4514. if (sg_count == 0)
  4515. goto out;
  4516. sg = scsi_sglist(scmd);
  4517. sg_descriptor = request->sg_descriptors;
  4518. num_sg_in_iu = pqi_build_sg_list(sg_descriptor, sg, sg_count, io_request,
  4519. ctrl_info->max_sg_per_iu, &chained);
  4520. request->partial = chained;
  4521. iu_length += num_sg_in_iu * sizeof(*sg_descriptor);
  4522. out:
  4523. put_unaligned_le16(iu_length, &request->header.iu_length);
  4524. request->num_sg_descriptors = num_sg_in_iu;
  4525. return 0;
  4526. }
  4527. static int pqi_build_aio_r56_sg_list(struct pqi_ctrl_info *ctrl_info,
  4528. struct pqi_aio_r56_path_request *request, struct scsi_cmnd *scmd,
  4529. struct pqi_io_request *io_request)
  4530. {
  4531. u16 iu_length;
  4532. int sg_count;
  4533. bool chained;
  4534. unsigned int num_sg_in_iu;
  4535. struct scatterlist *sg;
  4536. struct pqi_sg_descriptor *sg_descriptor;
  4537. sg_count = scsi_dma_map(scmd);
  4538. if (sg_count < 0)
  4539. return sg_count;
  4540. iu_length = offsetof(struct pqi_aio_r56_path_request, sg_descriptors) -
  4541. PQI_REQUEST_HEADER_LENGTH;
  4542. num_sg_in_iu = 0;
  4543. if (sg_count != 0) {
  4544. sg = scsi_sglist(scmd);
  4545. sg_descriptor = request->sg_descriptors;
  4546. num_sg_in_iu = pqi_build_sg_list(sg_descriptor, sg, sg_count, io_request,
  4547. ctrl_info->max_sg_per_r56_iu, &chained);
  4548. request->partial = chained;
  4549. iu_length += num_sg_in_iu * sizeof(*sg_descriptor);
  4550. }
  4551. put_unaligned_le16(iu_length, &request->header.iu_length);
  4552. request->num_sg_descriptors = num_sg_in_iu;
  4553. return 0;
  4554. }
  4555. static int pqi_build_aio_sg_list(struct pqi_ctrl_info *ctrl_info,
  4556. struct pqi_aio_path_request *request, struct scsi_cmnd *scmd,
  4557. struct pqi_io_request *io_request)
  4558. {
  4559. u16 iu_length;
  4560. int sg_count;
  4561. bool chained;
  4562. unsigned int num_sg_in_iu;
  4563. struct scatterlist *sg;
  4564. struct pqi_sg_descriptor *sg_descriptor;
  4565. sg_count = scsi_dma_map(scmd);
  4566. if (sg_count < 0)
  4567. return sg_count;
  4568. iu_length = offsetof(struct pqi_aio_path_request, sg_descriptors) -
  4569. PQI_REQUEST_HEADER_LENGTH;
  4570. num_sg_in_iu = 0;
  4571. if (sg_count == 0)
  4572. goto out;
  4573. sg = scsi_sglist(scmd);
  4574. sg_descriptor = request->sg_descriptors;
  4575. num_sg_in_iu = pqi_build_sg_list(sg_descriptor, sg, sg_count, io_request,
  4576. ctrl_info->max_sg_per_iu, &chained);
  4577. request->partial = chained;
  4578. iu_length += num_sg_in_iu * sizeof(*sg_descriptor);
  4579. out:
  4580. put_unaligned_le16(iu_length, &request->header.iu_length);
  4581. request->num_sg_descriptors = num_sg_in_iu;
  4582. return 0;
  4583. }
  4584. static void pqi_raid_io_complete(struct pqi_io_request *io_request,
  4585. void *context)
  4586. {
  4587. struct scsi_cmnd *scmd;
  4588. scmd = io_request->scmd;
  4589. pqi_free_io_request(io_request);
  4590. scsi_dma_unmap(scmd);
  4591. pqi_scsi_done(scmd);
  4592. }
  4593. static int pqi_raid_submit_scsi_cmd_with_io_request(
  4594. struct pqi_ctrl_info *ctrl_info, struct pqi_io_request *io_request,
  4595. struct pqi_scsi_dev *device, struct scsi_cmnd *scmd,
  4596. struct pqi_queue_group *queue_group)
  4597. {
  4598. int rc;
  4599. size_t cdb_length;
  4600. struct pqi_raid_path_request *request;
  4601. io_request->io_complete_callback = pqi_raid_io_complete;
  4602. io_request->scmd = scmd;
  4603. request = io_request->iu;
  4604. memset(request, 0, offsetof(struct pqi_raid_path_request, sg_descriptors));
  4605. request->header.iu_type = PQI_REQUEST_IU_RAID_PATH_IO;
  4606. put_unaligned_le32(scsi_bufflen(scmd), &request->buffer_length);
  4607. request->task_attribute = SOP_TASK_ATTRIBUTE_SIMPLE;
  4608. put_unaligned_le16(io_request->index, &request->request_id);
  4609. request->error_index = request->request_id;
  4610. memcpy(request->lun_number, device->scsi3addr, sizeof(request->lun_number));
  4611. request->ml_device_lun_number = (u8)scmd->device->lun;
  4612. cdb_length = min_t(size_t, scmd->cmd_len, sizeof(request->cdb));
  4613. memcpy(request->cdb, scmd->cmnd, cdb_length);
  4614. switch (cdb_length) {
  4615. case 6:
  4616. case 10:
  4617. case 12:
  4618. case 16:
  4619. request->additional_cdb_bytes_usage = SOP_ADDITIONAL_CDB_BYTES_0;
  4620. break;
  4621. case 20:
  4622. request->additional_cdb_bytes_usage = SOP_ADDITIONAL_CDB_BYTES_4;
  4623. break;
  4624. case 24:
  4625. request->additional_cdb_bytes_usage = SOP_ADDITIONAL_CDB_BYTES_8;
  4626. break;
  4627. case 28:
  4628. request->additional_cdb_bytes_usage = SOP_ADDITIONAL_CDB_BYTES_12;
  4629. break;
  4630. case 32:
  4631. default:
  4632. request->additional_cdb_bytes_usage = SOP_ADDITIONAL_CDB_BYTES_16;
  4633. break;
  4634. }
  4635. switch (scmd->sc_data_direction) {
  4636. case DMA_FROM_DEVICE:
  4637. request->data_direction = SOP_READ_FLAG;
  4638. break;
  4639. case DMA_TO_DEVICE:
  4640. request->data_direction = SOP_WRITE_FLAG;
  4641. break;
  4642. case DMA_NONE:
  4643. request->data_direction = SOP_NO_DIRECTION_FLAG;
  4644. break;
  4645. case DMA_BIDIRECTIONAL:
  4646. request->data_direction = SOP_BIDIRECTIONAL;
  4647. break;
  4648. default:
  4649. dev_err(&ctrl_info->pci_dev->dev,
  4650. "unknown data direction: %d\n",
  4651. scmd->sc_data_direction);
  4652. break;
  4653. }
  4654. rc = pqi_build_raid_sg_list(ctrl_info, request, scmd, io_request);
  4655. if (rc) {
  4656. pqi_free_io_request(io_request);
  4657. return SCSI_MLQUEUE_HOST_BUSY;
  4658. }
  4659. pqi_start_io(ctrl_info, queue_group, RAID_PATH, io_request);
  4660. return 0;
  4661. }
  4662. static inline int pqi_raid_submit_scsi_cmd(struct pqi_ctrl_info *ctrl_info,
  4663. struct pqi_scsi_dev *device, struct scsi_cmnd *scmd,
  4664. struct pqi_queue_group *queue_group)
  4665. {
  4666. struct pqi_io_request *io_request;
  4667. io_request = pqi_alloc_io_request(ctrl_info);
  4668. return pqi_raid_submit_scsi_cmd_with_io_request(ctrl_info, io_request,
  4669. device, scmd, queue_group);
  4670. }
  4671. static bool pqi_raid_bypass_retry_needed(struct pqi_io_request *io_request)
  4672. {
  4673. struct scsi_cmnd *scmd;
  4674. struct pqi_scsi_dev *device;
  4675. struct pqi_ctrl_info *ctrl_info;
  4676. if (!io_request->raid_bypass)
  4677. return false;
  4678. scmd = io_request->scmd;
  4679. if ((scmd->result & 0xff) == SAM_STAT_GOOD)
  4680. return false;
  4681. if (host_byte(scmd->result) == DID_NO_CONNECT)
  4682. return false;
  4683. device = scmd->device->hostdata;
  4684. if (pqi_device_offline(device) || pqi_device_in_remove(device))
  4685. return false;
  4686. ctrl_info = shost_to_hba(scmd->device->host);
  4687. if (pqi_ctrl_offline(ctrl_info))
  4688. return false;
  4689. return true;
  4690. }
  4691. static void pqi_aio_io_complete(struct pqi_io_request *io_request,
  4692. void *context)
  4693. {
  4694. struct scsi_cmnd *scmd;
  4695. scmd = io_request->scmd;
  4696. scsi_dma_unmap(scmd);
  4697. if (io_request->status == -EAGAIN || pqi_raid_bypass_retry_needed(io_request)) {
  4698. set_host_byte(scmd, DID_IMM_RETRY);
  4699. pqi_cmd_priv(scmd)->this_residual++;
  4700. }
  4701. pqi_free_io_request(io_request);
  4702. pqi_scsi_done(scmd);
  4703. }
  4704. static inline bool pqi_is_io_high_priority(struct pqi_ctrl_info *ctrl_info,
  4705. struct pqi_scsi_dev *device, struct scsi_cmnd *scmd)
  4706. {
  4707. bool io_high_prio;
  4708. int priority_class;
  4709. io_high_prio = false;
  4710. if (device->ncq_prio_enable) {
  4711. priority_class =
  4712. IOPRIO_PRIO_CLASS(req_get_ioprio(scsi_cmd_to_rq(scmd)));
  4713. if (priority_class == IOPRIO_CLASS_RT) {
  4714. /* Set NCQ priority for read/write commands. */
  4715. switch (scmd->cmnd[0]) {
  4716. case WRITE_16:
  4717. case READ_16:
  4718. case WRITE_12:
  4719. case READ_12:
  4720. case WRITE_10:
  4721. case READ_10:
  4722. case WRITE_6:
  4723. case READ_6:
  4724. io_high_prio = true;
  4725. break;
  4726. }
  4727. }
  4728. }
  4729. return io_high_prio;
  4730. }
  4731. static inline int pqi_aio_submit_scsi_cmd(struct pqi_ctrl_info *ctrl_info,
  4732. struct pqi_scsi_dev *device, struct scsi_cmnd *scmd,
  4733. struct pqi_queue_group *queue_group)
  4734. {
  4735. bool io_high_prio;
  4736. io_high_prio = pqi_is_io_high_priority(ctrl_info, device, scmd);
  4737. return pqi_aio_submit_io(ctrl_info, scmd, device->aio_handle,
  4738. scmd->cmnd, scmd->cmd_len, queue_group, NULL,
  4739. false, io_high_prio);
  4740. }
  4741. static int pqi_aio_submit_io(struct pqi_ctrl_info *ctrl_info,
  4742. struct scsi_cmnd *scmd, u32 aio_handle, u8 *cdb,
  4743. unsigned int cdb_length, struct pqi_queue_group *queue_group,
  4744. struct pqi_encryption_info *encryption_info, bool raid_bypass,
  4745. bool io_high_prio)
  4746. {
  4747. int rc;
  4748. struct pqi_io_request *io_request;
  4749. struct pqi_aio_path_request *request;
  4750. struct pqi_scsi_dev *device;
  4751. device = scmd->device->hostdata;
  4752. io_request = pqi_alloc_io_request(ctrl_info);
  4753. io_request->io_complete_callback = pqi_aio_io_complete;
  4754. io_request->scmd = scmd;
  4755. io_request->raid_bypass = raid_bypass;
  4756. request = io_request->iu;
  4757. memset(request, 0, offsetof(struct pqi_aio_path_request, sg_descriptors));
  4758. request->header.iu_type = PQI_REQUEST_IU_AIO_PATH_IO;
  4759. put_unaligned_le32(aio_handle, &request->nexus_id);
  4760. put_unaligned_le32(scsi_bufflen(scmd), &request->buffer_length);
  4761. request->task_attribute = SOP_TASK_ATTRIBUTE_SIMPLE;
  4762. request->command_priority = io_high_prio;
  4763. put_unaligned_le16(io_request->index, &request->request_id);
  4764. request->error_index = request->request_id;
  4765. if (!pqi_is_logical_device(device) && ctrl_info->multi_lun_device_supported)
  4766. put_unaligned_le64(((scmd->device->lun) << 8), &request->lun_number);
  4767. if (cdb_length > sizeof(request->cdb))
  4768. cdb_length = sizeof(request->cdb);
  4769. request->cdb_length = cdb_length;
  4770. memcpy(request->cdb, cdb, cdb_length);
  4771. switch (scmd->sc_data_direction) {
  4772. case DMA_TO_DEVICE:
  4773. request->data_direction = SOP_READ_FLAG;
  4774. break;
  4775. case DMA_FROM_DEVICE:
  4776. request->data_direction = SOP_WRITE_FLAG;
  4777. break;
  4778. case DMA_NONE:
  4779. request->data_direction = SOP_NO_DIRECTION_FLAG;
  4780. break;
  4781. case DMA_BIDIRECTIONAL:
  4782. request->data_direction = SOP_BIDIRECTIONAL;
  4783. break;
  4784. default:
  4785. dev_err(&ctrl_info->pci_dev->dev,
  4786. "unknown data direction: %d\n",
  4787. scmd->sc_data_direction);
  4788. break;
  4789. }
  4790. if (encryption_info) {
  4791. request->encryption_enable = true;
  4792. put_unaligned_le16(encryption_info->data_encryption_key_index,
  4793. &request->data_encryption_key_index);
  4794. put_unaligned_le32(encryption_info->encrypt_tweak_lower,
  4795. &request->encrypt_tweak_lower);
  4796. put_unaligned_le32(encryption_info->encrypt_tweak_upper,
  4797. &request->encrypt_tweak_upper);
  4798. }
  4799. rc = pqi_build_aio_sg_list(ctrl_info, request, scmd, io_request);
  4800. if (rc) {
  4801. pqi_free_io_request(io_request);
  4802. return SCSI_MLQUEUE_HOST_BUSY;
  4803. }
  4804. pqi_start_io(ctrl_info, queue_group, AIO_PATH, io_request);
  4805. return 0;
  4806. }
  4807. static int pqi_aio_submit_r1_write_io(struct pqi_ctrl_info *ctrl_info,
  4808. struct scsi_cmnd *scmd, struct pqi_queue_group *queue_group,
  4809. struct pqi_encryption_info *encryption_info, struct pqi_scsi_dev *device,
  4810. struct pqi_scsi_dev_raid_map_data *rmd)
  4811. {
  4812. int rc;
  4813. struct pqi_io_request *io_request;
  4814. struct pqi_aio_r1_path_request *r1_request;
  4815. io_request = pqi_alloc_io_request(ctrl_info);
  4816. io_request->io_complete_callback = pqi_aio_io_complete;
  4817. io_request->scmd = scmd;
  4818. io_request->raid_bypass = true;
  4819. r1_request = io_request->iu;
  4820. memset(r1_request, 0, offsetof(struct pqi_aio_r1_path_request, sg_descriptors));
  4821. r1_request->header.iu_type = PQI_REQUEST_IU_AIO_PATH_RAID1_IO;
  4822. put_unaligned_le16(*(u16 *)device->scsi3addr & 0x3fff, &r1_request->volume_id);
  4823. r1_request->num_drives = rmd->num_it_nexus_entries;
  4824. put_unaligned_le32(rmd->it_nexus[0], &r1_request->it_nexus_1);
  4825. put_unaligned_le32(rmd->it_nexus[1], &r1_request->it_nexus_2);
  4826. if (rmd->num_it_nexus_entries == 3)
  4827. put_unaligned_le32(rmd->it_nexus[2], &r1_request->it_nexus_3);
  4828. put_unaligned_le32(scsi_bufflen(scmd), &r1_request->data_length);
  4829. r1_request->task_attribute = SOP_TASK_ATTRIBUTE_SIMPLE;
  4830. put_unaligned_le16(io_request->index, &r1_request->request_id);
  4831. r1_request->error_index = r1_request->request_id;
  4832. if (rmd->cdb_length > sizeof(r1_request->cdb))
  4833. rmd->cdb_length = sizeof(r1_request->cdb);
  4834. r1_request->cdb_length = rmd->cdb_length;
  4835. memcpy(r1_request->cdb, rmd->cdb, rmd->cdb_length);
  4836. /* The direction is always write. */
  4837. r1_request->data_direction = SOP_READ_FLAG;
  4838. if (encryption_info) {
  4839. r1_request->encryption_enable = true;
  4840. put_unaligned_le16(encryption_info->data_encryption_key_index,
  4841. &r1_request->data_encryption_key_index);
  4842. put_unaligned_le32(encryption_info->encrypt_tweak_lower,
  4843. &r1_request->encrypt_tweak_lower);
  4844. put_unaligned_le32(encryption_info->encrypt_tweak_upper,
  4845. &r1_request->encrypt_tweak_upper);
  4846. }
  4847. rc = pqi_build_aio_r1_sg_list(ctrl_info, r1_request, scmd, io_request);
  4848. if (rc) {
  4849. pqi_free_io_request(io_request);
  4850. return SCSI_MLQUEUE_HOST_BUSY;
  4851. }
  4852. pqi_start_io(ctrl_info, queue_group, AIO_PATH, io_request);
  4853. return 0;
  4854. }
  4855. static int pqi_aio_submit_r56_write_io(struct pqi_ctrl_info *ctrl_info,
  4856. struct scsi_cmnd *scmd, struct pqi_queue_group *queue_group,
  4857. struct pqi_encryption_info *encryption_info, struct pqi_scsi_dev *device,
  4858. struct pqi_scsi_dev_raid_map_data *rmd)
  4859. {
  4860. int rc;
  4861. struct pqi_io_request *io_request;
  4862. struct pqi_aio_r56_path_request *r56_request;
  4863. io_request = pqi_alloc_io_request(ctrl_info);
  4864. io_request->io_complete_callback = pqi_aio_io_complete;
  4865. io_request->scmd = scmd;
  4866. io_request->raid_bypass = true;
  4867. r56_request = io_request->iu;
  4868. memset(r56_request, 0, offsetof(struct pqi_aio_r56_path_request, sg_descriptors));
  4869. if (device->raid_level == SA_RAID_5 || device->raid_level == SA_RAID_51)
  4870. r56_request->header.iu_type = PQI_REQUEST_IU_AIO_PATH_RAID5_IO;
  4871. else
  4872. r56_request->header.iu_type = PQI_REQUEST_IU_AIO_PATH_RAID6_IO;
  4873. put_unaligned_le16(*(u16 *)device->scsi3addr & 0x3fff, &r56_request->volume_id);
  4874. put_unaligned_le32(rmd->aio_handle, &r56_request->data_it_nexus);
  4875. put_unaligned_le32(rmd->p_parity_it_nexus, &r56_request->p_parity_it_nexus);
  4876. if (rmd->raid_level == SA_RAID_6) {
  4877. put_unaligned_le32(rmd->q_parity_it_nexus, &r56_request->q_parity_it_nexus);
  4878. r56_request->xor_multiplier = rmd->xor_mult;
  4879. }
  4880. put_unaligned_le32(scsi_bufflen(scmd), &r56_request->data_length);
  4881. r56_request->task_attribute = SOP_TASK_ATTRIBUTE_SIMPLE;
  4882. put_unaligned_le64(rmd->row, &r56_request->row);
  4883. put_unaligned_le16(io_request->index, &r56_request->request_id);
  4884. r56_request->error_index = r56_request->request_id;
  4885. if (rmd->cdb_length > sizeof(r56_request->cdb))
  4886. rmd->cdb_length = sizeof(r56_request->cdb);
  4887. r56_request->cdb_length = rmd->cdb_length;
  4888. memcpy(r56_request->cdb, rmd->cdb, rmd->cdb_length);
  4889. /* The direction is always write. */
  4890. r56_request->data_direction = SOP_READ_FLAG;
  4891. if (encryption_info) {
  4892. r56_request->encryption_enable = true;
  4893. put_unaligned_le16(encryption_info->data_encryption_key_index,
  4894. &r56_request->data_encryption_key_index);
  4895. put_unaligned_le32(encryption_info->encrypt_tweak_lower,
  4896. &r56_request->encrypt_tweak_lower);
  4897. put_unaligned_le32(encryption_info->encrypt_tweak_upper,
  4898. &r56_request->encrypt_tweak_upper);
  4899. }
  4900. rc = pqi_build_aio_r56_sg_list(ctrl_info, r56_request, scmd, io_request);
  4901. if (rc) {
  4902. pqi_free_io_request(io_request);
  4903. return SCSI_MLQUEUE_HOST_BUSY;
  4904. }
  4905. pqi_start_io(ctrl_info, queue_group, AIO_PATH, io_request);
  4906. return 0;
  4907. }
  4908. static inline u16 pqi_get_hw_queue(struct pqi_ctrl_info *ctrl_info,
  4909. struct scsi_cmnd *scmd)
  4910. {
  4911. u16 hw_queue;
  4912. hw_queue = blk_mq_unique_tag_to_hwq(blk_mq_unique_tag(scsi_cmd_to_rq(scmd)));
  4913. if (hw_queue > ctrl_info->max_hw_queue_index)
  4914. hw_queue = 0;
  4915. return hw_queue;
  4916. }
  4917. static inline bool pqi_is_bypass_eligible_request(struct scsi_cmnd *scmd)
  4918. {
  4919. if (blk_rq_is_passthrough(scsi_cmd_to_rq(scmd)))
  4920. return false;
  4921. return pqi_cmd_priv(scmd)->this_residual == 0;
  4922. }
  4923. /*
  4924. * This function gets called just before we hand the completed SCSI request
  4925. * back to the SML.
  4926. */
  4927. void pqi_prep_for_scsi_done(struct scsi_cmnd *scmd)
  4928. {
  4929. struct pqi_scsi_dev *device;
  4930. if (!scmd->device) {
  4931. set_host_byte(scmd, DID_NO_CONNECT);
  4932. return;
  4933. }
  4934. device = scmd->device->hostdata;
  4935. if (!device) {
  4936. set_host_byte(scmd, DID_NO_CONNECT);
  4937. return;
  4938. }
  4939. atomic_dec(&device->scsi_cmds_outstanding[scmd->device->lun]);
  4940. }
  4941. static bool pqi_is_parity_write_stream(struct pqi_ctrl_info *ctrl_info,
  4942. struct scsi_cmnd *scmd)
  4943. {
  4944. u32 oldest_jiffies;
  4945. u8 lru_index;
  4946. int i;
  4947. int rc;
  4948. struct pqi_scsi_dev *device;
  4949. struct pqi_stream_data *pqi_stream_data;
  4950. struct pqi_scsi_dev_raid_map_data rmd;
  4951. if (!ctrl_info->enable_stream_detection)
  4952. return false;
  4953. rc = pqi_get_aio_lba_and_block_count(scmd, &rmd);
  4954. if (rc)
  4955. return false;
  4956. /* Check writes only. */
  4957. if (!rmd.is_write)
  4958. return false;
  4959. device = scmd->device->hostdata;
  4960. /* Check for RAID 5/6 streams. */
  4961. if (device->raid_level != SA_RAID_5 && device->raid_level != SA_RAID_6)
  4962. return false;
  4963. /*
  4964. * If controller does not support AIO RAID{5,6} writes, need to send
  4965. * requests down non-AIO path.
  4966. */
  4967. if ((device->raid_level == SA_RAID_5 && !ctrl_info->enable_r5_writes) ||
  4968. (device->raid_level == SA_RAID_6 && !ctrl_info->enable_r6_writes))
  4969. return true;
  4970. lru_index = 0;
  4971. oldest_jiffies = INT_MAX;
  4972. for (i = 0; i < NUM_STREAMS_PER_LUN; i++) {
  4973. pqi_stream_data = &device->stream_data[i];
  4974. /*
  4975. * Check for adjacent request or request is within
  4976. * the previous request.
  4977. */
  4978. if ((pqi_stream_data->next_lba &&
  4979. rmd.first_block >= pqi_stream_data->next_lba) &&
  4980. rmd.first_block <= pqi_stream_data->next_lba +
  4981. rmd.block_cnt) {
  4982. pqi_stream_data->next_lba = rmd.first_block +
  4983. rmd.block_cnt;
  4984. pqi_stream_data->last_accessed = jiffies;
  4985. return true;
  4986. }
  4987. /* unused entry */
  4988. if (pqi_stream_data->last_accessed == 0) {
  4989. lru_index = i;
  4990. break;
  4991. }
  4992. /* Find entry with oldest last accessed time. */
  4993. if (pqi_stream_data->last_accessed <= oldest_jiffies) {
  4994. oldest_jiffies = pqi_stream_data->last_accessed;
  4995. lru_index = i;
  4996. }
  4997. }
  4998. /* Set LRU entry. */
  4999. pqi_stream_data = &device->stream_data[lru_index];
  5000. pqi_stream_data->last_accessed = jiffies;
  5001. pqi_stream_data->next_lba = rmd.first_block + rmd.block_cnt;
  5002. return false;
  5003. }
  5004. static int pqi_scsi_queue_command(struct Scsi_Host *shost, struct scsi_cmnd *scmd)
  5005. {
  5006. int rc;
  5007. struct pqi_ctrl_info *ctrl_info;
  5008. struct pqi_scsi_dev *device;
  5009. u16 hw_queue;
  5010. struct pqi_queue_group *queue_group;
  5011. bool raid_bypassed;
  5012. device = scmd->device->hostdata;
  5013. if (!device) {
  5014. set_host_byte(scmd, DID_NO_CONNECT);
  5015. pqi_scsi_done(scmd);
  5016. return 0;
  5017. }
  5018. atomic_inc(&device->scsi_cmds_outstanding[scmd->device->lun]);
  5019. ctrl_info = shost_to_hba(shost);
  5020. if (pqi_ctrl_offline(ctrl_info) || pqi_device_in_remove(device)) {
  5021. set_host_byte(scmd, DID_NO_CONNECT);
  5022. pqi_scsi_done(scmd);
  5023. return 0;
  5024. }
  5025. if (pqi_ctrl_blocked(ctrl_info)) {
  5026. rc = SCSI_MLQUEUE_HOST_BUSY;
  5027. goto out;
  5028. }
  5029. /*
  5030. * This is necessary because the SML doesn't zero out this field during
  5031. * error recovery.
  5032. */
  5033. scmd->result = 0;
  5034. hw_queue = pqi_get_hw_queue(ctrl_info, scmd);
  5035. queue_group = &ctrl_info->queue_groups[hw_queue];
  5036. if (pqi_is_logical_device(device)) {
  5037. raid_bypassed = false;
  5038. if (device->raid_bypass_enabled &&
  5039. pqi_is_bypass_eligible_request(scmd) &&
  5040. !pqi_is_parity_write_stream(ctrl_info, scmd)) {
  5041. rc = pqi_raid_bypass_submit_scsi_cmd(ctrl_info, device, scmd, queue_group);
  5042. if (rc == 0 || rc == SCSI_MLQUEUE_HOST_BUSY) {
  5043. raid_bypassed = true;
  5044. atomic_inc(&device->raid_bypass_cnt);
  5045. }
  5046. }
  5047. if (!raid_bypassed)
  5048. rc = pqi_raid_submit_scsi_cmd(ctrl_info, device, scmd, queue_group);
  5049. } else {
  5050. if (device->aio_enabled)
  5051. rc = pqi_aio_submit_scsi_cmd(ctrl_info, device, scmd, queue_group);
  5052. else
  5053. rc = pqi_raid_submit_scsi_cmd(ctrl_info, device, scmd, queue_group);
  5054. }
  5055. out:
  5056. if (rc)
  5057. atomic_dec(&device->scsi_cmds_outstanding[scmd->device->lun]);
  5058. return rc;
  5059. }
  5060. static unsigned int pqi_queued_io_count(struct pqi_ctrl_info *ctrl_info)
  5061. {
  5062. unsigned int i;
  5063. unsigned int path;
  5064. unsigned long flags;
  5065. unsigned int queued_io_count;
  5066. struct pqi_queue_group *queue_group;
  5067. struct pqi_io_request *io_request;
  5068. queued_io_count = 0;
  5069. for (i = 0; i < ctrl_info->num_queue_groups; i++) {
  5070. queue_group = &ctrl_info->queue_groups[i];
  5071. for (path = 0; path < 2; path++) {
  5072. spin_lock_irqsave(&queue_group->submit_lock[path], flags);
  5073. list_for_each_entry(io_request, &queue_group->request_list[path], request_list_entry)
  5074. queued_io_count++;
  5075. spin_unlock_irqrestore(&queue_group->submit_lock[path], flags);
  5076. }
  5077. }
  5078. return queued_io_count;
  5079. }
  5080. static unsigned int pqi_nonempty_inbound_queue_count(struct pqi_ctrl_info *ctrl_info)
  5081. {
  5082. unsigned int i;
  5083. unsigned int path;
  5084. unsigned int nonempty_inbound_queue_count;
  5085. struct pqi_queue_group *queue_group;
  5086. pqi_index_t iq_pi;
  5087. pqi_index_t iq_ci;
  5088. nonempty_inbound_queue_count = 0;
  5089. for (i = 0; i < ctrl_info->num_queue_groups; i++) {
  5090. queue_group = &ctrl_info->queue_groups[i];
  5091. for (path = 0; path < 2; path++) {
  5092. iq_pi = queue_group->iq_pi_copy[path];
  5093. iq_ci = readl(queue_group->iq_ci[path]);
  5094. if (iq_ci != iq_pi)
  5095. nonempty_inbound_queue_count++;
  5096. }
  5097. }
  5098. return nonempty_inbound_queue_count;
  5099. }
  5100. #define PQI_INBOUND_QUEUES_NONEMPTY_WARNING_TIMEOUT_SECS 10
  5101. static int pqi_wait_until_inbound_queues_empty(struct pqi_ctrl_info *ctrl_info)
  5102. {
  5103. unsigned long start_jiffies;
  5104. unsigned long warning_timeout;
  5105. unsigned int queued_io_count;
  5106. unsigned int nonempty_inbound_queue_count;
  5107. bool displayed_warning;
  5108. displayed_warning = false;
  5109. start_jiffies = jiffies;
  5110. warning_timeout = (PQI_INBOUND_QUEUES_NONEMPTY_WARNING_TIMEOUT_SECS * HZ) + start_jiffies;
  5111. while (1) {
  5112. queued_io_count = pqi_queued_io_count(ctrl_info);
  5113. nonempty_inbound_queue_count = pqi_nonempty_inbound_queue_count(ctrl_info);
  5114. if (queued_io_count == 0 && nonempty_inbound_queue_count == 0)
  5115. break;
  5116. pqi_check_ctrl_health(ctrl_info);
  5117. if (pqi_ctrl_offline(ctrl_info))
  5118. return -ENXIO;
  5119. if (time_after(jiffies, warning_timeout)) {
  5120. dev_warn(&ctrl_info->pci_dev->dev,
  5121. "waiting %u seconds for queued I/O to drain (queued I/O count: %u; non-empty inbound queue count: %u)\n",
  5122. jiffies_to_msecs(jiffies - start_jiffies) / 1000, queued_io_count, nonempty_inbound_queue_count);
  5123. displayed_warning = true;
  5124. warning_timeout = (PQI_INBOUND_QUEUES_NONEMPTY_WARNING_TIMEOUT_SECS * HZ) + jiffies;
  5125. }
  5126. usleep_range(1000, 2000);
  5127. }
  5128. if (displayed_warning)
  5129. dev_warn(&ctrl_info->pci_dev->dev,
  5130. "queued I/O drained after waiting for %u seconds\n",
  5131. jiffies_to_msecs(jiffies - start_jiffies) / 1000);
  5132. return 0;
  5133. }
  5134. static void pqi_fail_io_queued_for_device(struct pqi_ctrl_info *ctrl_info,
  5135. struct pqi_scsi_dev *device)
  5136. {
  5137. unsigned int i;
  5138. unsigned int path;
  5139. struct pqi_queue_group *queue_group;
  5140. unsigned long flags;
  5141. struct pqi_io_request *io_request;
  5142. struct pqi_io_request *next;
  5143. struct scsi_cmnd *scmd;
  5144. struct pqi_scsi_dev *scsi_device;
  5145. for (i = 0; i < ctrl_info->num_queue_groups; i++) {
  5146. queue_group = &ctrl_info->queue_groups[i];
  5147. for (path = 0; path < 2; path++) {
  5148. spin_lock_irqsave(
  5149. &queue_group->submit_lock[path], flags);
  5150. list_for_each_entry_safe(io_request, next,
  5151. &queue_group->request_list[path],
  5152. request_list_entry) {
  5153. scmd = io_request->scmd;
  5154. if (!scmd)
  5155. continue;
  5156. scsi_device = scmd->device->hostdata;
  5157. if (scsi_device != device)
  5158. continue;
  5159. list_del(&io_request->request_list_entry);
  5160. set_host_byte(scmd, DID_RESET);
  5161. pqi_free_io_request(io_request);
  5162. scsi_dma_unmap(scmd);
  5163. pqi_scsi_done(scmd);
  5164. }
  5165. spin_unlock_irqrestore(
  5166. &queue_group->submit_lock[path], flags);
  5167. }
  5168. }
  5169. }
  5170. #define PQI_PENDING_IO_WARNING_TIMEOUT_SECS 10
  5171. static int pqi_device_wait_for_pending_io(struct pqi_ctrl_info *ctrl_info,
  5172. struct pqi_scsi_dev *device, u8 lun, unsigned long timeout_msecs)
  5173. {
  5174. int cmds_outstanding;
  5175. unsigned long start_jiffies;
  5176. unsigned long warning_timeout;
  5177. unsigned long msecs_waiting;
  5178. start_jiffies = jiffies;
  5179. warning_timeout = (PQI_PENDING_IO_WARNING_TIMEOUT_SECS * HZ) + start_jiffies;
  5180. while ((cmds_outstanding = atomic_read(&device->scsi_cmds_outstanding[lun])) > 0) {
  5181. if (ctrl_info->ctrl_removal_state != PQI_CTRL_GRACEFUL_REMOVAL) {
  5182. pqi_check_ctrl_health(ctrl_info);
  5183. if (pqi_ctrl_offline(ctrl_info))
  5184. return -ENXIO;
  5185. }
  5186. msecs_waiting = jiffies_to_msecs(jiffies - start_jiffies);
  5187. if (msecs_waiting >= timeout_msecs) {
  5188. dev_err(&ctrl_info->pci_dev->dev,
  5189. "scsi %d:%d:%d:%d: timed out after %lu seconds waiting for %d outstanding command(s)\n",
  5190. ctrl_info->scsi_host->host_no, device->bus, device->target,
  5191. lun, msecs_waiting / 1000, cmds_outstanding);
  5192. return -ETIMEDOUT;
  5193. }
  5194. if (time_after(jiffies, warning_timeout)) {
  5195. dev_warn(&ctrl_info->pci_dev->dev,
  5196. "scsi %d:%d:%d:%d: waiting %lu seconds for %d outstanding command(s)\n",
  5197. ctrl_info->scsi_host->host_no, device->bus, device->target,
  5198. lun, msecs_waiting / 1000, cmds_outstanding);
  5199. warning_timeout = (PQI_PENDING_IO_WARNING_TIMEOUT_SECS * HZ) + jiffies;
  5200. }
  5201. usleep_range(1000, 2000);
  5202. }
  5203. return 0;
  5204. }
  5205. static void pqi_lun_reset_complete(struct pqi_io_request *io_request,
  5206. void *context)
  5207. {
  5208. struct completion *waiting = context;
  5209. complete(waiting);
  5210. }
  5211. #define PQI_LUN_RESET_POLL_COMPLETION_SECS 10
  5212. static int pqi_wait_for_lun_reset_completion(struct pqi_ctrl_info *ctrl_info,
  5213. struct pqi_scsi_dev *device, u8 lun, struct completion *wait)
  5214. {
  5215. int rc;
  5216. unsigned int wait_secs;
  5217. int cmds_outstanding;
  5218. wait_secs = 0;
  5219. while (1) {
  5220. if (wait_for_completion_io_timeout(wait,
  5221. PQI_LUN_RESET_POLL_COMPLETION_SECS * HZ)) {
  5222. rc = 0;
  5223. break;
  5224. }
  5225. pqi_check_ctrl_health(ctrl_info);
  5226. if (pqi_ctrl_offline(ctrl_info)) {
  5227. rc = -ENXIO;
  5228. break;
  5229. }
  5230. wait_secs += PQI_LUN_RESET_POLL_COMPLETION_SECS;
  5231. cmds_outstanding = atomic_read(&device->scsi_cmds_outstanding[lun]);
  5232. dev_warn(&ctrl_info->pci_dev->dev,
  5233. "scsi %d:%d:%d:%d: waiting %u seconds for LUN reset to complete (%d command(s) outstanding)\n",
  5234. ctrl_info->scsi_host->host_no, device->bus, device->target, lun, wait_secs, cmds_outstanding);
  5235. }
  5236. return rc;
  5237. }
  5238. #define PQI_LUN_RESET_FIRMWARE_TIMEOUT_SECS 30
  5239. static int pqi_lun_reset(struct pqi_ctrl_info *ctrl_info, struct scsi_cmnd *scmd)
  5240. {
  5241. int rc;
  5242. struct pqi_io_request *io_request;
  5243. DECLARE_COMPLETION_ONSTACK(wait);
  5244. struct pqi_task_management_request *request;
  5245. struct pqi_scsi_dev *device;
  5246. device = scmd->device->hostdata;
  5247. io_request = pqi_alloc_io_request(ctrl_info);
  5248. io_request->io_complete_callback = pqi_lun_reset_complete;
  5249. io_request->context = &wait;
  5250. request = io_request->iu;
  5251. memset(request, 0, sizeof(*request));
  5252. request->header.iu_type = PQI_REQUEST_IU_TASK_MANAGEMENT;
  5253. put_unaligned_le16(sizeof(*request) - PQI_REQUEST_HEADER_LENGTH,
  5254. &request->header.iu_length);
  5255. put_unaligned_le16(io_request->index, &request->request_id);
  5256. memcpy(request->lun_number, device->scsi3addr,
  5257. sizeof(request->lun_number));
  5258. if (!pqi_is_logical_device(device) && ctrl_info->multi_lun_device_supported)
  5259. request->ml_device_lun_number = (u8)scmd->device->lun;
  5260. request->task_management_function = SOP_TASK_MANAGEMENT_LUN_RESET;
  5261. if (ctrl_info->tmf_iu_timeout_supported)
  5262. put_unaligned_le16(PQI_LUN_RESET_FIRMWARE_TIMEOUT_SECS, &request->timeout);
  5263. pqi_start_io(ctrl_info, &ctrl_info->queue_groups[PQI_DEFAULT_QUEUE_GROUP], RAID_PATH,
  5264. io_request);
  5265. rc = pqi_wait_for_lun_reset_completion(ctrl_info, device, (u8)scmd->device->lun, &wait);
  5266. if (rc == 0)
  5267. rc = io_request->status;
  5268. pqi_free_io_request(io_request);
  5269. return rc;
  5270. }
  5271. #define PQI_LUN_RESET_RETRIES 3
  5272. #define PQI_LUN_RESET_RETRY_INTERVAL_MSECS (10 * 1000)
  5273. #define PQI_LUN_RESET_PENDING_IO_TIMEOUT_MSECS (10 * 60 * 1000)
  5274. #define PQI_LUN_RESET_FAILED_PENDING_IO_TIMEOUT_MSECS (2 * 60 * 1000)
  5275. static int pqi_lun_reset_with_retries(struct pqi_ctrl_info *ctrl_info, struct scsi_cmnd *scmd)
  5276. {
  5277. int reset_rc;
  5278. int wait_rc;
  5279. unsigned int retries;
  5280. unsigned long timeout_msecs;
  5281. struct pqi_scsi_dev *device;
  5282. device = scmd->device->hostdata;
  5283. for (retries = 0;;) {
  5284. reset_rc = pqi_lun_reset(ctrl_info, scmd);
  5285. if (reset_rc == 0 || reset_rc == -ENODEV || ++retries > PQI_LUN_RESET_RETRIES)
  5286. break;
  5287. msleep(PQI_LUN_RESET_RETRY_INTERVAL_MSECS);
  5288. }
  5289. timeout_msecs = reset_rc ? PQI_LUN_RESET_FAILED_PENDING_IO_TIMEOUT_MSECS :
  5290. PQI_LUN_RESET_PENDING_IO_TIMEOUT_MSECS;
  5291. wait_rc = pqi_device_wait_for_pending_io(ctrl_info, device, scmd->device->lun, timeout_msecs);
  5292. if (wait_rc && reset_rc == 0)
  5293. reset_rc = wait_rc;
  5294. return reset_rc == 0 ? SUCCESS : FAILED;
  5295. }
  5296. static int pqi_device_reset(struct pqi_ctrl_info *ctrl_info, struct scsi_cmnd *scmd)
  5297. {
  5298. int rc;
  5299. struct pqi_scsi_dev *device;
  5300. device = scmd->device->hostdata;
  5301. pqi_ctrl_block_requests(ctrl_info);
  5302. pqi_ctrl_wait_until_quiesced(ctrl_info);
  5303. pqi_fail_io_queued_for_device(ctrl_info, device);
  5304. rc = pqi_wait_until_inbound_queues_empty(ctrl_info);
  5305. if (rc)
  5306. rc = FAILED;
  5307. else
  5308. rc = pqi_lun_reset_with_retries(ctrl_info, scmd);
  5309. pqi_ctrl_unblock_requests(ctrl_info);
  5310. return rc;
  5311. }
  5312. static int pqi_eh_device_reset_handler(struct scsi_cmnd *scmd)
  5313. {
  5314. int rc;
  5315. struct Scsi_Host *shost;
  5316. struct pqi_ctrl_info *ctrl_info;
  5317. struct pqi_scsi_dev *device;
  5318. shost = scmd->device->host;
  5319. ctrl_info = shost_to_hba(shost);
  5320. device = scmd->device->hostdata;
  5321. mutex_lock(&ctrl_info->lun_reset_mutex);
  5322. dev_err(&ctrl_info->pci_dev->dev,
  5323. "resetting scsi %d:%d:%d:%d due to cmd 0x%02x\n",
  5324. shost->host_no,
  5325. device->bus, device->target, (u32)scmd->device->lun,
  5326. scmd->cmd_len > 0 ? scmd->cmnd[0] : 0xff);
  5327. pqi_check_ctrl_health(ctrl_info);
  5328. if (pqi_ctrl_offline(ctrl_info))
  5329. rc = FAILED;
  5330. else
  5331. rc = pqi_device_reset(ctrl_info, scmd);
  5332. dev_err(&ctrl_info->pci_dev->dev,
  5333. "reset of scsi %d:%d:%d:%d: %s\n",
  5334. shost->host_no, device->bus, device->target, (u32)scmd->device->lun,
  5335. rc == SUCCESS ? "SUCCESS" : "FAILED");
  5336. mutex_unlock(&ctrl_info->lun_reset_mutex);
  5337. return rc;
  5338. }
  5339. static int pqi_slave_alloc(struct scsi_device *sdev)
  5340. {
  5341. struct pqi_scsi_dev *device;
  5342. unsigned long flags;
  5343. struct pqi_ctrl_info *ctrl_info;
  5344. struct scsi_target *starget;
  5345. struct sas_rphy *rphy;
  5346. ctrl_info = shost_to_hba(sdev->host);
  5347. spin_lock_irqsave(&ctrl_info->scsi_device_list_lock, flags);
  5348. if (sdev_channel(sdev) == PQI_PHYSICAL_DEVICE_BUS) {
  5349. starget = scsi_target(sdev);
  5350. rphy = target_to_rphy(starget);
  5351. device = pqi_find_device_by_sas_rphy(ctrl_info, rphy);
  5352. if (device) {
  5353. if (device->target_lun_valid) {
  5354. device->ignore_device = true;
  5355. } else {
  5356. device->target = sdev_id(sdev);
  5357. device->lun = sdev->lun;
  5358. device->target_lun_valid = true;
  5359. }
  5360. }
  5361. } else {
  5362. device = pqi_find_scsi_dev(ctrl_info, sdev_channel(sdev),
  5363. sdev_id(sdev), sdev->lun);
  5364. }
  5365. if (device) {
  5366. sdev->hostdata = device;
  5367. device->sdev = sdev;
  5368. if (device->queue_depth) {
  5369. device->advertised_queue_depth = device->queue_depth;
  5370. scsi_change_queue_depth(sdev,
  5371. device->advertised_queue_depth);
  5372. }
  5373. if (pqi_is_logical_device(device)) {
  5374. pqi_disable_write_same(sdev);
  5375. } else {
  5376. sdev->allow_restart = 1;
  5377. if (device->device_type == SA_DEVICE_TYPE_NVME)
  5378. pqi_disable_write_same(sdev);
  5379. }
  5380. }
  5381. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  5382. return 0;
  5383. }
  5384. static void pqi_map_queues(struct Scsi_Host *shost)
  5385. {
  5386. struct pqi_ctrl_info *ctrl_info = shost_to_hba(shost);
  5387. blk_mq_pci_map_queues(&shost->tag_set.map[HCTX_TYPE_DEFAULT],
  5388. ctrl_info->pci_dev, 0);
  5389. }
  5390. static inline bool pqi_is_tape_changer_device(struct pqi_scsi_dev *device)
  5391. {
  5392. return device->devtype == TYPE_TAPE || device->devtype == TYPE_MEDIUM_CHANGER;
  5393. }
  5394. static int pqi_slave_configure(struct scsi_device *sdev)
  5395. {
  5396. int rc = 0;
  5397. struct pqi_scsi_dev *device;
  5398. device = sdev->hostdata;
  5399. device->devtype = sdev->type;
  5400. if (pqi_is_tape_changer_device(device) && device->ignore_device) {
  5401. rc = -ENXIO;
  5402. device->ignore_device = false;
  5403. }
  5404. return rc;
  5405. }
  5406. static void pqi_slave_destroy(struct scsi_device *sdev)
  5407. {
  5408. struct pqi_ctrl_info *ctrl_info;
  5409. struct pqi_scsi_dev *device;
  5410. int mutex_acquired;
  5411. unsigned long flags;
  5412. ctrl_info = shost_to_hba(sdev->host);
  5413. mutex_acquired = mutex_trylock(&ctrl_info->scan_mutex);
  5414. if (!mutex_acquired)
  5415. return;
  5416. device = sdev->hostdata;
  5417. if (!device) {
  5418. mutex_unlock(&ctrl_info->scan_mutex);
  5419. return;
  5420. }
  5421. device->lun_count--;
  5422. if (device->lun_count > 0) {
  5423. mutex_unlock(&ctrl_info->scan_mutex);
  5424. return;
  5425. }
  5426. spin_lock_irqsave(&ctrl_info->scsi_device_list_lock, flags);
  5427. list_del(&device->scsi_device_list_entry);
  5428. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  5429. mutex_unlock(&ctrl_info->scan_mutex);
  5430. pqi_dev_info(ctrl_info, "removed", device);
  5431. pqi_free_device(device);
  5432. }
  5433. static int pqi_getpciinfo_ioctl(struct pqi_ctrl_info *ctrl_info, void __user *arg)
  5434. {
  5435. struct pci_dev *pci_dev;
  5436. u32 subsystem_vendor;
  5437. u32 subsystem_device;
  5438. cciss_pci_info_struct pciinfo;
  5439. if (!arg)
  5440. return -EINVAL;
  5441. pci_dev = ctrl_info->pci_dev;
  5442. pciinfo.domain = pci_domain_nr(pci_dev->bus);
  5443. pciinfo.bus = pci_dev->bus->number;
  5444. pciinfo.dev_fn = pci_dev->devfn;
  5445. subsystem_vendor = pci_dev->subsystem_vendor;
  5446. subsystem_device = pci_dev->subsystem_device;
  5447. pciinfo.board_id = ((subsystem_device << 16) & 0xffff0000) | subsystem_vendor;
  5448. if (copy_to_user(arg, &pciinfo, sizeof(pciinfo)))
  5449. return -EFAULT;
  5450. return 0;
  5451. }
  5452. static int pqi_getdrivver_ioctl(void __user *arg)
  5453. {
  5454. u32 version;
  5455. if (!arg)
  5456. return -EINVAL;
  5457. version = (DRIVER_MAJOR << 28) | (DRIVER_MINOR << 24) |
  5458. (DRIVER_RELEASE << 16) | DRIVER_REVISION;
  5459. if (copy_to_user(arg, &version, sizeof(version)))
  5460. return -EFAULT;
  5461. return 0;
  5462. }
  5463. struct ciss_error_info {
  5464. u8 scsi_status;
  5465. int command_status;
  5466. size_t sense_data_length;
  5467. };
  5468. static void pqi_error_info_to_ciss(struct pqi_raid_error_info *pqi_error_info,
  5469. struct ciss_error_info *ciss_error_info)
  5470. {
  5471. int ciss_cmd_status;
  5472. size_t sense_data_length;
  5473. switch (pqi_error_info->data_out_result) {
  5474. case PQI_DATA_IN_OUT_GOOD:
  5475. ciss_cmd_status = CISS_CMD_STATUS_SUCCESS;
  5476. break;
  5477. case PQI_DATA_IN_OUT_UNDERFLOW:
  5478. ciss_cmd_status = CISS_CMD_STATUS_DATA_UNDERRUN;
  5479. break;
  5480. case PQI_DATA_IN_OUT_BUFFER_OVERFLOW:
  5481. ciss_cmd_status = CISS_CMD_STATUS_DATA_OVERRUN;
  5482. break;
  5483. case PQI_DATA_IN_OUT_PROTOCOL_ERROR:
  5484. case PQI_DATA_IN_OUT_BUFFER_ERROR:
  5485. case PQI_DATA_IN_OUT_BUFFER_OVERFLOW_DESCRIPTOR_AREA:
  5486. case PQI_DATA_IN_OUT_BUFFER_OVERFLOW_BRIDGE:
  5487. case PQI_DATA_IN_OUT_ERROR:
  5488. ciss_cmd_status = CISS_CMD_STATUS_PROTOCOL_ERROR;
  5489. break;
  5490. case PQI_DATA_IN_OUT_HARDWARE_ERROR:
  5491. case PQI_DATA_IN_OUT_PCIE_FABRIC_ERROR:
  5492. case PQI_DATA_IN_OUT_PCIE_COMPLETION_TIMEOUT:
  5493. case PQI_DATA_IN_OUT_PCIE_COMPLETER_ABORT_RECEIVED:
  5494. case PQI_DATA_IN_OUT_PCIE_UNSUPPORTED_REQUEST_RECEIVED:
  5495. case PQI_DATA_IN_OUT_PCIE_ECRC_CHECK_FAILED:
  5496. case PQI_DATA_IN_OUT_PCIE_UNSUPPORTED_REQUEST:
  5497. case PQI_DATA_IN_OUT_PCIE_ACS_VIOLATION:
  5498. case PQI_DATA_IN_OUT_PCIE_TLP_PREFIX_BLOCKED:
  5499. case PQI_DATA_IN_OUT_PCIE_POISONED_MEMORY_READ:
  5500. ciss_cmd_status = CISS_CMD_STATUS_HARDWARE_ERROR;
  5501. break;
  5502. case PQI_DATA_IN_OUT_UNSOLICITED_ABORT:
  5503. ciss_cmd_status = CISS_CMD_STATUS_UNSOLICITED_ABORT;
  5504. break;
  5505. case PQI_DATA_IN_OUT_ABORTED:
  5506. ciss_cmd_status = CISS_CMD_STATUS_ABORTED;
  5507. break;
  5508. case PQI_DATA_IN_OUT_TIMEOUT:
  5509. ciss_cmd_status = CISS_CMD_STATUS_TIMEOUT;
  5510. break;
  5511. default:
  5512. ciss_cmd_status = CISS_CMD_STATUS_TARGET_STATUS;
  5513. break;
  5514. }
  5515. sense_data_length =
  5516. get_unaligned_le16(&pqi_error_info->sense_data_length);
  5517. if (sense_data_length == 0)
  5518. sense_data_length =
  5519. get_unaligned_le16(&pqi_error_info->response_data_length);
  5520. if (sense_data_length)
  5521. if (sense_data_length > sizeof(pqi_error_info->data))
  5522. sense_data_length = sizeof(pqi_error_info->data);
  5523. ciss_error_info->scsi_status = pqi_error_info->status;
  5524. ciss_error_info->command_status = ciss_cmd_status;
  5525. ciss_error_info->sense_data_length = sense_data_length;
  5526. }
  5527. static int pqi_passthru_ioctl(struct pqi_ctrl_info *ctrl_info, void __user *arg)
  5528. {
  5529. int rc;
  5530. char *kernel_buffer = NULL;
  5531. u16 iu_length;
  5532. size_t sense_data_length;
  5533. IOCTL_Command_struct iocommand;
  5534. struct pqi_raid_path_request request;
  5535. struct pqi_raid_error_info pqi_error_info;
  5536. struct ciss_error_info ciss_error_info;
  5537. if (pqi_ctrl_offline(ctrl_info))
  5538. return -ENXIO;
  5539. if (pqi_ofa_in_progress(ctrl_info) && pqi_ctrl_blocked(ctrl_info))
  5540. return -EBUSY;
  5541. if (!arg)
  5542. return -EINVAL;
  5543. if (!capable(CAP_SYS_RAWIO))
  5544. return -EPERM;
  5545. if (copy_from_user(&iocommand, arg, sizeof(iocommand)))
  5546. return -EFAULT;
  5547. if (iocommand.buf_size < 1 &&
  5548. iocommand.Request.Type.Direction != XFER_NONE)
  5549. return -EINVAL;
  5550. if (iocommand.Request.CDBLen > sizeof(request.cdb))
  5551. return -EINVAL;
  5552. if (iocommand.Request.Type.Type != TYPE_CMD)
  5553. return -EINVAL;
  5554. switch (iocommand.Request.Type.Direction) {
  5555. case XFER_NONE:
  5556. case XFER_WRITE:
  5557. case XFER_READ:
  5558. case XFER_READ | XFER_WRITE:
  5559. break;
  5560. default:
  5561. return -EINVAL;
  5562. }
  5563. if (iocommand.buf_size > 0) {
  5564. kernel_buffer = kmalloc(iocommand.buf_size, GFP_KERNEL);
  5565. if (!kernel_buffer)
  5566. return -ENOMEM;
  5567. if (iocommand.Request.Type.Direction & XFER_WRITE) {
  5568. if (copy_from_user(kernel_buffer, iocommand.buf,
  5569. iocommand.buf_size)) {
  5570. rc = -EFAULT;
  5571. goto out;
  5572. }
  5573. } else {
  5574. memset(kernel_buffer, 0, iocommand.buf_size);
  5575. }
  5576. }
  5577. memset(&request, 0, sizeof(request));
  5578. request.header.iu_type = PQI_REQUEST_IU_RAID_PATH_IO;
  5579. iu_length = offsetof(struct pqi_raid_path_request, sg_descriptors) -
  5580. PQI_REQUEST_HEADER_LENGTH;
  5581. memcpy(request.lun_number, iocommand.LUN_info.LunAddrBytes,
  5582. sizeof(request.lun_number));
  5583. memcpy(request.cdb, iocommand.Request.CDB, iocommand.Request.CDBLen);
  5584. request.additional_cdb_bytes_usage = SOP_ADDITIONAL_CDB_BYTES_0;
  5585. switch (iocommand.Request.Type.Direction) {
  5586. case XFER_NONE:
  5587. request.data_direction = SOP_NO_DIRECTION_FLAG;
  5588. break;
  5589. case XFER_WRITE:
  5590. request.data_direction = SOP_WRITE_FLAG;
  5591. break;
  5592. case XFER_READ:
  5593. request.data_direction = SOP_READ_FLAG;
  5594. break;
  5595. case XFER_READ | XFER_WRITE:
  5596. request.data_direction = SOP_BIDIRECTIONAL;
  5597. break;
  5598. }
  5599. request.task_attribute = SOP_TASK_ATTRIBUTE_SIMPLE;
  5600. if (iocommand.buf_size > 0) {
  5601. put_unaligned_le32(iocommand.buf_size, &request.buffer_length);
  5602. rc = pqi_map_single(ctrl_info->pci_dev,
  5603. &request.sg_descriptors[0], kernel_buffer,
  5604. iocommand.buf_size, DMA_BIDIRECTIONAL);
  5605. if (rc)
  5606. goto out;
  5607. iu_length += sizeof(request.sg_descriptors[0]);
  5608. }
  5609. put_unaligned_le16(iu_length, &request.header.iu_length);
  5610. if (ctrl_info->raid_iu_timeout_supported)
  5611. put_unaligned_le32(iocommand.Request.Timeout, &request.timeout);
  5612. rc = pqi_submit_raid_request_synchronous(ctrl_info, &request.header,
  5613. PQI_SYNC_FLAGS_INTERRUPTABLE, &pqi_error_info);
  5614. if (iocommand.buf_size > 0)
  5615. pqi_pci_unmap(ctrl_info->pci_dev, request.sg_descriptors, 1,
  5616. DMA_BIDIRECTIONAL);
  5617. memset(&iocommand.error_info, 0, sizeof(iocommand.error_info));
  5618. if (rc == 0) {
  5619. pqi_error_info_to_ciss(&pqi_error_info, &ciss_error_info);
  5620. iocommand.error_info.ScsiStatus = ciss_error_info.scsi_status;
  5621. iocommand.error_info.CommandStatus =
  5622. ciss_error_info.command_status;
  5623. sense_data_length = ciss_error_info.sense_data_length;
  5624. if (sense_data_length) {
  5625. if (sense_data_length >
  5626. sizeof(iocommand.error_info.SenseInfo))
  5627. sense_data_length =
  5628. sizeof(iocommand.error_info.SenseInfo);
  5629. memcpy(iocommand.error_info.SenseInfo,
  5630. pqi_error_info.data, sense_data_length);
  5631. iocommand.error_info.SenseLen = sense_data_length;
  5632. }
  5633. }
  5634. if (copy_to_user(arg, &iocommand, sizeof(iocommand))) {
  5635. rc = -EFAULT;
  5636. goto out;
  5637. }
  5638. if (rc == 0 && iocommand.buf_size > 0 &&
  5639. (iocommand.Request.Type.Direction & XFER_READ)) {
  5640. if (copy_to_user(iocommand.buf, kernel_buffer,
  5641. iocommand.buf_size)) {
  5642. rc = -EFAULT;
  5643. }
  5644. }
  5645. out:
  5646. kfree(kernel_buffer);
  5647. return rc;
  5648. }
  5649. static int pqi_ioctl(struct scsi_device *sdev, unsigned int cmd,
  5650. void __user *arg)
  5651. {
  5652. int rc;
  5653. struct pqi_ctrl_info *ctrl_info;
  5654. ctrl_info = shost_to_hba(sdev->host);
  5655. switch (cmd) {
  5656. case CCISS_DEREGDISK:
  5657. case CCISS_REGNEWDISK:
  5658. case CCISS_REGNEWD:
  5659. rc = pqi_scan_scsi_devices(ctrl_info);
  5660. break;
  5661. case CCISS_GETPCIINFO:
  5662. rc = pqi_getpciinfo_ioctl(ctrl_info, arg);
  5663. break;
  5664. case CCISS_GETDRIVVER:
  5665. rc = pqi_getdrivver_ioctl(arg);
  5666. break;
  5667. case CCISS_PASSTHRU:
  5668. rc = pqi_passthru_ioctl(ctrl_info, arg);
  5669. break;
  5670. default:
  5671. rc = -EINVAL;
  5672. break;
  5673. }
  5674. return rc;
  5675. }
  5676. static ssize_t pqi_firmware_version_show(struct device *dev,
  5677. struct device_attribute *attr, char *buffer)
  5678. {
  5679. struct Scsi_Host *shost;
  5680. struct pqi_ctrl_info *ctrl_info;
  5681. shost = class_to_shost(dev);
  5682. ctrl_info = shost_to_hba(shost);
  5683. return scnprintf(buffer, PAGE_SIZE, "%s\n", ctrl_info->firmware_version);
  5684. }
  5685. static ssize_t pqi_driver_version_show(struct device *dev,
  5686. struct device_attribute *attr, char *buffer)
  5687. {
  5688. return scnprintf(buffer, PAGE_SIZE, "%s\n", DRIVER_VERSION BUILD_TIMESTAMP);
  5689. }
  5690. static ssize_t pqi_serial_number_show(struct device *dev,
  5691. struct device_attribute *attr, char *buffer)
  5692. {
  5693. struct Scsi_Host *shost;
  5694. struct pqi_ctrl_info *ctrl_info;
  5695. shost = class_to_shost(dev);
  5696. ctrl_info = shost_to_hba(shost);
  5697. return scnprintf(buffer, PAGE_SIZE, "%s\n", ctrl_info->serial_number);
  5698. }
  5699. static ssize_t pqi_model_show(struct device *dev,
  5700. struct device_attribute *attr, char *buffer)
  5701. {
  5702. struct Scsi_Host *shost;
  5703. struct pqi_ctrl_info *ctrl_info;
  5704. shost = class_to_shost(dev);
  5705. ctrl_info = shost_to_hba(shost);
  5706. return scnprintf(buffer, PAGE_SIZE, "%s\n", ctrl_info->model);
  5707. }
  5708. static ssize_t pqi_vendor_show(struct device *dev,
  5709. struct device_attribute *attr, char *buffer)
  5710. {
  5711. struct Scsi_Host *shost;
  5712. struct pqi_ctrl_info *ctrl_info;
  5713. shost = class_to_shost(dev);
  5714. ctrl_info = shost_to_hba(shost);
  5715. return scnprintf(buffer, PAGE_SIZE, "%s\n", ctrl_info->vendor);
  5716. }
  5717. static ssize_t pqi_host_rescan_store(struct device *dev,
  5718. struct device_attribute *attr, const char *buffer, size_t count)
  5719. {
  5720. struct Scsi_Host *shost = class_to_shost(dev);
  5721. pqi_scan_start(shost);
  5722. return count;
  5723. }
  5724. static ssize_t pqi_lockup_action_show(struct device *dev,
  5725. struct device_attribute *attr, char *buffer)
  5726. {
  5727. int count = 0;
  5728. unsigned int i;
  5729. for (i = 0; i < ARRAY_SIZE(pqi_lockup_actions); i++) {
  5730. if (pqi_lockup_actions[i].action == pqi_lockup_action)
  5731. count += scnprintf(buffer + count, PAGE_SIZE - count,
  5732. "[%s] ", pqi_lockup_actions[i].name);
  5733. else
  5734. count += scnprintf(buffer + count, PAGE_SIZE - count,
  5735. "%s ", pqi_lockup_actions[i].name);
  5736. }
  5737. count += scnprintf(buffer + count, PAGE_SIZE - count, "\n");
  5738. return count;
  5739. }
  5740. static ssize_t pqi_lockup_action_store(struct device *dev,
  5741. struct device_attribute *attr, const char *buffer, size_t count)
  5742. {
  5743. unsigned int i;
  5744. char *action_name;
  5745. char action_name_buffer[32];
  5746. strlcpy(action_name_buffer, buffer, sizeof(action_name_buffer));
  5747. action_name = strstrip(action_name_buffer);
  5748. for (i = 0; i < ARRAY_SIZE(pqi_lockup_actions); i++) {
  5749. if (strcmp(action_name, pqi_lockup_actions[i].name) == 0) {
  5750. pqi_lockup_action = pqi_lockup_actions[i].action;
  5751. return count;
  5752. }
  5753. }
  5754. return -EINVAL;
  5755. }
  5756. static ssize_t pqi_host_enable_stream_detection_show(struct device *dev,
  5757. struct device_attribute *attr, char *buffer)
  5758. {
  5759. struct Scsi_Host *shost = class_to_shost(dev);
  5760. struct pqi_ctrl_info *ctrl_info = shost_to_hba(shost);
  5761. return scnprintf(buffer, 10, "%x\n",
  5762. ctrl_info->enable_stream_detection);
  5763. }
  5764. static ssize_t pqi_host_enable_stream_detection_store(struct device *dev,
  5765. struct device_attribute *attr, const char *buffer, size_t count)
  5766. {
  5767. struct Scsi_Host *shost = class_to_shost(dev);
  5768. struct pqi_ctrl_info *ctrl_info = shost_to_hba(shost);
  5769. u8 set_stream_detection = 0;
  5770. if (kstrtou8(buffer, 0, &set_stream_detection))
  5771. return -EINVAL;
  5772. if (set_stream_detection > 0)
  5773. set_stream_detection = 1;
  5774. ctrl_info->enable_stream_detection = set_stream_detection;
  5775. return count;
  5776. }
  5777. static ssize_t pqi_host_enable_r5_writes_show(struct device *dev,
  5778. struct device_attribute *attr, char *buffer)
  5779. {
  5780. struct Scsi_Host *shost = class_to_shost(dev);
  5781. struct pqi_ctrl_info *ctrl_info = shost_to_hba(shost);
  5782. return scnprintf(buffer, 10, "%x\n", ctrl_info->enable_r5_writes);
  5783. }
  5784. static ssize_t pqi_host_enable_r5_writes_store(struct device *dev,
  5785. struct device_attribute *attr, const char *buffer, size_t count)
  5786. {
  5787. struct Scsi_Host *shost = class_to_shost(dev);
  5788. struct pqi_ctrl_info *ctrl_info = shost_to_hba(shost);
  5789. u8 set_r5_writes = 0;
  5790. if (kstrtou8(buffer, 0, &set_r5_writes))
  5791. return -EINVAL;
  5792. if (set_r5_writes > 0)
  5793. set_r5_writes = 1;
  5794. ctrl_info->enable_r5_writes = set_r5_writes;
  5795. return count;
  5796. }
  5797. static ssize_t pqi_host_enable_r6_writes_show(struct device *dev,
  5798. struct device_attribute *attr, char *buffer)
  5799. {
  5800. struct Scsi_Host *shost = class_to_shost(dev);
  5801. struct pqi_ctrl_info *ctrl_info = shost_to_hba(shost);
  5802. return scnprintf(buffer, 10, "%x\n", ctrl_info->enable_r6_writes);
  5803. }
  5804. static ssize_t pqi_host_enable_r6_writes_store(struct device *dev,
  5805. struct device_attribute *attr, const char *buffer, size_t count)
  5806. {
  5807. struct Scsi_Host *shost = class_to_shost(dev);
  5808. struct pqi_ctrl_info *ctrl_info = shost_to_hba(shost);
  5809. u8 set_r6_writes = 0;
  5810. if (kstrtou8(buffer, 0, &set_r6_writes))
  5811. return -EINVAL;
  5812. if (set_r6_writes > 0)
  5813. set_r6_writes = 1;
  5814. ctrl_info->enable_r6_writes = set_r6_writes;
  5815. return count;
  5816. }
  5817. static DEVICE_ATTR(driver_version, 0444, pqi_driver_version_show, NULL);
  5818. static DEVICE_ATTR(firmware_version, 0444, pqi_firmware_version_show, NULL);
  5819. static DEVICE_ATTR(model, 0444, pqi_model_show, NULL);
  5820. static DEVICE_ATTR(serial_number, 0444, pqi_serial_number_show, NULL);
  5821. static DEVICE_ATTR(vendor, 0444, pqi_vendor_show, NULL);
  5822. static DEVICE_ATTR(rescan, 0200, NULL, pqi_host_rescan_store);
  5823. static DEVICE_ATTR(lockup_action, 0644, pqi_lockup_action_show,
  5824. pqi_lockup_action_store);
  5825. static DEVICE_ATTR(enable_stream_detection, 0644,
  5826. pqi_host_enable_stream_detection_show,
  5827. pqi_host_enable_stream_detection_store);
  5828. static DEVICE_ATTR(enable_r5_writes, 0644,
  5829. pqi_host_enable_r5_writes_show, pqi_host_enable_r5_writes_store);
  5830. static DEVICE_ATTR(enable_r6_writes, 0644,
  5831. pqi_host_enable_r6_writes_show, pqi_host_enable_r6_writes_store);
  5832. static struct attribute *pqi_shost_attrs[] = {
  5833. &dev_attr_driver_version.attr,
  5834. &dev_attr_firmware_version.attr,
  5835. &dev_attr_model.attr,
  5836. &dev_attr_serial_number.attr,
  5837. &dev_attr_vendor.attr,
  5838. &dev_attr_rescan.attr,
  5839. &dev_attr_lockup_action.attr,
  5840. &dev_attr_enable_stream_detection.attr,
  5841. &dev_attr_enable_r5_writes.attr,
  5842. &dev_attr_enable_r6_writes.attr,
  5843. NULL
  5844. };
  5845. ATTRIBUTE_GROUPS(pqi_shost);
  5846. static ssize_t pqi_unique_id_show(struct device *dev,
  5847. struct device_attribute *attr, char *buffer)
  5848. {
  5849. struct pqi_ctrl_info *ctrl_info;
  5850. struct scsi_device *sdev;
  5851. struct pqi_scsi_dev *device;
  5852. unsigned long flags;
  5853. u8 unique_id[16];
  5854. sdev = to_scsi_device(dev);
  5855. ctrl_info = shost_to_hba(sdev->host);
  5856. if (pqi_ctrl_offline(ctrl_info))
  5857. return -ENODEV;
  5858. spin_lock_irqsave(&ctrl_info->scsi_device_list_lock, flags);
  5859. device = sdev->hostdata;
  5860. if (!device) {
  5861. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  5862. return -ENODEV;
  5863. }
  5864. if (device->is_physical_device)
  5865. memcpy(unique_id, device->wwid, sizeof(device->wwid));
  5866. else
  5867. memcpy(unique_id, device->volume_id, sizeof(device->volume_id));
  5868. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  5869. return scnprintf(buffer, PAGE_SIZE,
  5870. "%02X%02X%02X%02X%02X%02X%02X%02X"
  5871. "%02X%02X%02X%02X%02X%02X%02X%02X\n",
  5872. unique_id[0], unique_id[1], unique_id[2], unique_id[3],
  5873. unique_id[4], unique_id[5], unique_id[6], unique_id[7],
  5874. unique_id[8], unique_id[9], unique_id[10], unique_id[11],
  5875. unique_id[12], unique_id[13], unique_id[14], unique_id[15]);
  5876. }
  5877. static ssize_t pqi_lunid_show(struct device *dev,
  5878. struct device_attribute *attr, char *buffer)
  5879. {
  5880. struct pqi_ctrl_info *ctrl_info;
  5881. struct scsi_device *sdev;
  5882. struct pqi_scsi_dev *device;
  5883. unsigned long flags;
  5884. u8 lunid[8];
  5885. sdev = to_scsi_device(dev);
  5886. ctrl_info = shost_to_hba(sdev->host);
  5887. if (pqi_ctrl_offline(ctrl_info))
  5888. return -ENODEV;
  5889. spin_lock_irqsave(&ctrl_info->scsi_device_list_lock, flags);
  5890. device = sdev->hostdata;
  5891. if (!device) {
  5892. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  5893. return -ENODEV;
  5894. }
  5895. memcpy(lunid, device->scsi3addr, sizeof(lunid));
  5896. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  5897. return scnprintf(buffer, PAGE_SIZE, "0x%8phN\n", lunid);
  5898. }
  5899. #define MAX_PATHS 8
  5900. static ssize_t pqi_path_info_show(struct device *dev,
  5901. struct device_attribute *attr, char *buf)
  5902. {
  5903. struct pqi_ctrl_info *ctrl_info;
  5904. struct scsi_device *sdev;
  5905. struct pqi_scsi_dev *device;
  5906. unsigned long flags;
  5907. int i;
  5908. int output_len = 0;
  5909. u8 box;
  5910. u8 bay;
  5911. u8 path_map_index;
  5912. char *active;
  5913. u8 phys_connector[2];
  5914. sdev = to_scsi_device(dev);
  5915. ctrl_info = shost_to_hba(sdev->host);
  5916. if (pqi_ctrl_offline(ctrl_info))
  5917. return -ENODEV;
  5918. spin_lock_irqsave(&ctrl_info->scsi_device_list_lock, flags);
  5919. device = sdev->hostdata;
  5920. if (!device) {
  5921. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  5922. return -ENODEV;
  5923. }
  5924. bay = device->bay;
  5925. for (i = 0; i < MAX_PATHS; i++) {
  5926. path_map_index = 1 << i;
  5927. if (i == device->active_path_index)
  5928. active = "Active";
  5929. else if (device->path_map & path_map_index)
  5930. active = "Inactive";
  5931. else
  5932. continue;
  5933. output_len += scnprintf(buf + output_len,
  5934. PAGE_SIZE - output_len,
  5935. "[%d:%d:%d:%d] %20.20s ",
  5936. ctrl_info->scsi_host->host_no,
  5937. device->bus, device->target,
  5938. device->lun,
  5939. scsi_device_type(device->devtype));
  5940. if (device->devtype == TYPE_RAID ||
  5941. pqi_is_logical_device(device))
  5942. goto end_buffer;
  5943. memcpy(&phys_connector, &device->phys_connector[i],
  5944. sizeof(phys_connector));
  5945. if (phys_connector[0] < '0')
  5946. phys_connector[0] = '0';
  5947. if (phys_connector[1] < '0')
  5948. phys_connector[1] = '0';
  5949. output_len += scnprintf(buf + output_len,
  5950. PAGE_SIZE - output_len,
  5951. "PORT: %.2s ", phys_connector);
  5952. box = device->box[i];
  5953. if (box != 0 && box != 0xFF)
  5954. output_len += scnprintf(buf + output_len,
  5955. PAGE_SIZE - output_len,
  5956. "BOX: %hhu ", box);
  5957. if ((device->devtype == TYPE_DISK ||
  5958. device->devtype == TYPE_ZBC) &&
  5959. pqi_expose_device(device))
  5960. output_len += scnprintf(buf + output_len,
  5961. PAGE_SIZE - output_len,
  5962. "BAY: %hhu ", bay);
  5963. end_buffer:
  5964. output_len += scnprintf(buf + output_len,
  5965. PAGE_SIZE - output_len,
  5966. "%s\n", active);
  5967. }
  5968. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  5969. return output_len;
  5970. }
  5971. static ssize_t pqi_sas_address_show(struct device *dev,
  5972. struct device_attribute *attr, char *buffer)
  5973. {
  5974. struct pqi_ctrl_info *ctrl_info;
  5975. struct scsi_device *sdev;
  5976. struct pqi_scsi_dev *device;
  5977. unsigned long flags;
  5978. u64 sas_address;
  5979. sdev = to_scsi_device(dev);
  5980. ctrl_info = shost_to_hba(sdev->host);
  5981. if (pqi_ctrl_offline(ctrl_info))
  5982. return -ENODEV;
  5983. spin_lock_irqsave(&ctrl_info->scsi_device_list_lock, flags);
  5984. device = sdev->hostdata;
  5985. if (!device) {
  5986. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  5987. return -ENODEV;
  5988. }
  5989. sas_address = device->sas_address;
  5990. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  5991. return scnprintf(buffer, PAGE_SIZE, "0x%016llx\n", sas_address);
  5992. }
  5993. static ssize_t pqi_ssd_smart_path_enabled_show(struct device *dev,
  5994. struct device_attribute *attr, char *buffer)
  5995. {
  5996. struct pqi_ctrl_info *ctrl_info;
  5997. struct scsi_device *sdev;
  5998. struct pqi_scsi_dev *device;
  5999. unsigned long flags;
  6000. sdev = to_scsi_device(dev);
  6001. ctrl_info = shost_to_hba(sdev->host);
  6002. if (pqi_ctrl_offline(ctrl_info))
  6003. return -ENODEV;
  6004. spin_lock_irqsave(&ctrl_info->scsi_device_list_lock, flags);
  6005. device = sdev->hostdata;
  6006. if (!device) {
  6007. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  6008. return -ENODEV;
  6009. }
  6010. buffer[0] = device->raid_bypass_enabled ? '1' : '0';
  6011. buffer[1] = '\n';
  6012. buffer[2] = '\0';
  6013. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  6014. return 2;
  6015. }
  6016. static ssize_t pqi_raid_level_show(struct device *dev,
  6017. struct device_attribute *attr, char *buffer)
  6018. {
  6019. struct pqi_ctrl_info *ctrl_info;
  6020. struct scsi_device *sdev;
  6021. struct pqi_scsi_dev *device;
  6022. unsigned long flags;
  6023. char *raid_level;
  6024. sdev = to_scsi_device(dev);
  6025. ctrl_info = shost_to_hba(sdev->host);
  6026. if (pqi_ctrl_offline(ctrl_info))
  6027. return -ENODEV;
  6028. spin_lock_irqsave(&ctrl_info->scsi_device_list_lock, flags);
  6029. device = sdev->hostdata;
  6030. if (!device) {
  6031. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  6032. return -ENODEV;
  6033. }
  6034. if (pqi_is_logical_device(device))
  6035. raid_level = pqi_raid_level_to_string(device->raid_level);
  6036. else
  6037. raid_level = "N/A";
  6038. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  6039. return scnprintf(buffer, PAGE_SIZE, "%s\n", raid_level);
  6040. }
  6041. static ssize_t pqi_raid_bypass_cnt_show(struct device *dev,
  6042. struct device_attribute *attr, char *buffer)
  6043. {
  6044. struct pqi_ctrl_info *ctrl_info;
  6045. struct scsi_device *sdev;
  6046. struct pqi_scsi_dev *device;
  6047. unsigned long flags;
  6048. int raid_bypass_cnt;
  6049. sdev = to_scsi_device(dev);
  6050. ctrl_info = shost_to_hba(sdev->host);
  6051. if (pqi_ctrl_offline(ctrl_info))
  6052. return -ENODEV;
  6053. spin_lock_irqsave(&ctrl_info->scsi_device_list_lock, flags);
  6054. device = sdev->hostdata;
  6055. if (!device) {
  6056. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  6057. return -ENODEV;
  6058. }
  6059. raid_bypass_cnt = atomic_read(&device->raid_bypass_cnt);
  6060. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  6061. return scnprintf(buffer, PAGE_SIZE, "0x%x\n", raid_bypass_cnt);
  6062. }
  6063. static ssize_t pqi_sas_ncq_prio_enable_show(struct device *dev,
  6064. struct device_attribute *attr, char *buf)
  6065. {
  6066. struct pqi_ctrl_info *ctrl_info;
  6067. struct scsi_device *sdev;
  6068. struct pqi_scsi_dev *device;
  6069. unsigned long flags;
  6070. int output_len = 0;
  6071. sdev = to_scsi_device(dev);
  6072. ctrl_info = shost_to_hba(sdev->host);
  6073. if (pqi_ctrl_offline(ctrl_info))
  6074. return -ENODEV;
  6075. spin_lock_irqsave(&ctrl_info->scsi_device_list_lock, flags);
  6076. device = sdev->hostdata;
  6077. if (!device) {
  6078. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  6079. return -ENODEV;
  6080. }
  6081. output_len = snprintf(buf, PAGE_SIZE, "%d\n",
  6082. device->ncq_prio_enable);
  6083. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  6084. return output_len;
  6085. }
  6086. static ssize_t pqi_sas_ncq_prio_enable_store(struct device *dev,
  6087. struct device_attribute *attr,
  6088. const char *buf, size_t count)
  6089. {
  6090. struct pqi_ctrl_info *ctrl_info;
  6091. struct scsi_device *sdev;
  6092. struct pqi_scsi_dev *device;
  6093. unsigned long flags;
  6094. u8 ncq_prio_enable = 0;
  6095. if (kstrtou8(buf, 0, &ncq_prio_enable))
  6096. return -EINVAL;
  6097. sdev = to_scsi_device(dev);
  6098. ctrl_info = shost_to_hba(sdev->host);
  6099. spin_lock_irqsave(&ctrl_info->scsi_device_list_lock, flags);
  6100. device = sdev->hostdata;
  6101. if (!device) {
  6102. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  6103. return -ENODEV;
  6104. }
  6105. if (!device->ncq_prio_support ||
  6106. !device->is_physical_device) {
  6107. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  6108. return -EINVAL;
  6109. }
  6110. device->ncq_prio_enable = ncq_prio_enable;
  6111. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  6112. return strlen(buf);
  6113. }
  6114. static DEVICE_ATTR(lunid, 0444, pqi_lunid_show, NULL);
  6115. static DEVICE_ATTR(unique_id, 0444, pqi_unique_id_show, NULL);
  6116. static DEVICE_ATTR(path_info, 0444, pqi_path_info_show, NULL);
  6117. static DEVICE_ATTR(sas_address, 0444, pqi_sas_address_show, NULL);
  6118. static DEVICE_ATTR(ssd_smart_path_enabled, 0444, pqi_ssd_smart_path_enabled_show, NULL);
  6119. static DEVICE_ATTR(raid_level, 0444, pqi_raid_level_show, NULL);
  6120. static DEVICE_ATTR(raid_bypass_cnt, 0444, pqi_raid_bypass_cnt_show, NULL);
  6121. static DEVICE_ATTR(sas_ncq_prio_enable, 0644,
  6122. pqi_sas_ncq_prio_enable_show, pqi_sas_ncq_prio_enable_store);
  6123. static struct attribute *pqi_sdev_attrs[] = {
  6124. &dev_attr_lunid.attr,
  6125. &dev_attr_unique_id.attr,
  6126. &dev_attr_path_info.attr,
  6127. &dev_attr_sas_address.attr,
  6128. &dev_attr_ssd_smart_path_enabled.attr,
  6129. &dev_attr_raid_level.attr,
  6130. &dev_attr_raid_bypass_cnt.attr,
  6131. &dev_attr_sas_ncq_prio_enable.attr,
  6132. NULL
  6133. };
  6134. ATTRIBUTE_GROUPS(pqi_sdev);
  6135. static struct scsi_host_template pqi_driver_template = {
  6136. .module = THIS_MODULE,
  6137. .name = DRIVER_NAME_SHORT,
  6138. .proc_name = DRIVER_NAME_SHORT,
  6139. .queuecommand = pqi_scsi_queue_command,
  6140. .scan_start = pqi_scan_start,
  6141. .scan_finished = pqi_scan_finished,
  6142. .this_id = -1,
  6143. .eh_device_reset_handler = pqi_eh_device_reset_handler,
  6144. .ioctl = pqi_ioctl,
  6145. .slave_alloc = pqi_slave_alloc,
  6146. .slave_configure = pqi_slave_configure,
  6147. .slave_destroy = pqi_slave_destroy,
  6148. .map_queues = pqi_map_queues,
  6149. .sdev_groups = pqi_sdev_groups,
  6150. .shost_groups = pqi_shost_groups,
  6151. .cmd_size = sizeof(struct pqi_cmd_priv),
  6152. };
  6153. static int pqi_register_scsi(struct pqi_ctrl_info *ctrl_info)
  6154. {
  6155. int rc;
  6156. struct Scsi_Host *shost;
  6157. shost = scsi_host_alloc(&pqi_driver_template, sizeof(ctrl_info));
  6158. if (!shost) {
  6159. dev_err(&ctrl_info->pci_dev->dev, "scsi_host_alloc failed\n");
  6160. return -ENOMEM;
  6161. }
  6162. shost->io_port = 0;
  6163. shost->n_io_port = 0;
  6164. shost->this_id = -1;
  6165. shost->max_channel = PQI_MAX_BUS;
  6166. shost->max_cmd_len = MAX_COMMAND_SIZE;
  6167. shost->max_lun = PQI_MAX_LUNS_PER_DEVICE;
  6168. shost->max_lun = ~0;
  6169. shost->max_id = ~0;
  6170. shost->max_sectors = ctrl_info->max_sectors;
  6171. shost->can_queue = ctrl_info->scsi_ml_can_queue;
  6172. shost->cmd_per_lun = shost->can_queue;
  6173. shost->sg_tablesize = ctrl_info->sg_tablesize;
  6174. shost->transportt = pqi_sas_transport_template;
  6175. shost->irq = pci_irq_vector(ctrl_info->pci_dev, 0);
  6176. shost->unique_id = shost->irq;
  6177. shost->nr_hw_queues = ctrl_info->num_queue_groups;
  6178. shost->host_tagset = 1;
  6179. shost->hostdata[0] = (unsigned long)ctrl_info;
  6180. rc = scsi_add_host(shost, &ctrl_info->pci_dev->dev);
  6181. if (rc) {
  6182. dev_err(&ctrl_info->pci_dev->dev, "scsi_add_host failed\n");
  6183. goto free_host;
  6184. }
  6185. rc = pqi_add_sas_host(shost, ctrl_info);
  6186. if (rc) {
  6187. dev_err(&ctrl_info->pci_dev->dev, "add SAS host failed\n");
  6188. goto remove_host;
  6189. }
  6190. ctrl_info->scsi_host = shost;
  6191. return 0;
  6192. remove_host:
  6193. scsi_remove_host(shost);
  6194. free_host:
  6195. scsi_host_put(shost);
  6196. return rc;
  6197. }
  6198. static void pqi_unregister_scsi(struct pqi_ctrl_info *ctrl_info)
  6199. {
  6200. struct Scsi_Host *shost;
  6201. pqi_delete_sas_host(ctrl_info);
  6202. shost = ctrl_info->scsi_host;
  6203. if (!shost)
  6204. return;
  6205. scsi_remove_host(shost);
  6206. scsi_host_put(shost);
  6207. }
  6208. static int pqi_wait_for_pqi_reset_completion(struct pqi_ctrl_info *ctrl_info)
  6209. {
  6210. int rc = 0;
  6211. struct pqi_device_registers __iomem *pqi_registers;
  6212. unsigned long timeout;
  6213. unsigned int timeout_msecs;
  6214. union pqi_reset_register reset_reg;
  6215. pqi_registers = ctrl_info->pqi_registers;
  6216. timeout_msecs = readw(&pqi_registers->max_reset_timeout) * 100;
  6217. timeout = msecs_to_jiffies(timeout_msecs) + jiffies;
  6218. while (1) {
  6219. msleep(PQI_RESET_POLL_INTERVAL_MSECS);
  6220. reset_reg.all_bits = readl(&pqi_registers->device_reset);
  6221. if (reset_reg.bits.reset_action == PQI_RESET_ACTION_COMPLETED)
  6222. break;
  6223. if (!sis_is_firmware_running(ctrl_info)) {
  6224. rc = -ENXIO;
  6225. break;
  6226. }
  6227. if (time_after(jiffies, timeout)) {
  6228. rc = -ETIMEDOUT;
  6229. break;
  6230. }
  6231. }
  6232. return rc;
  6233. }
  6234. static int pqi_reset(struct pqi_ctrl_info *ctrl_info)
  6235. {
  6236. int rc;
  6237. union pqi_reset_register reset_reg;
  6238. if (ctrl_info->pqi_reset_quiesce_supported) {
  6239. rc = sis_pqi_reset_quiesce(ctrl_info);
  6240. if (rc) {
  6241. dev_err(&ctrl_info->pci_dev->dev,
  6242. "PQI reset failed during quiesce with error %d\n", rc);
  6243. return rc;
  6244. }
  6245. }
  6246. reset_reg.all_bits = 0;
  6247. reset_reg.bits.reset_type = PQI_RESET_TYPE_HARD_RESET;
  6248. reset_reg.bits.reset_action = PQI_RESET_ACTION_RESET;
  6249. writel(reset_reg.all_bits, &ctrl_info->pqi_registers->device_reset);
  6250. rc = pqi_wait_for_pqi_reset_completion(ctrl_info);
  6251. if (rc)
  6252. dev_err(&ctrl_info->pci_dev->dev,
  6253. "PQI reset failed with error %d\n", rc);
  6254. return rc;
  6255. }
  6256. static int pqi_get_ctrl_serial_number(struct pqi_ctrl_info *ctrl_info)
  6257. {
  6258. int rc;
  6259. struct bmic_sense_subsystem_info *sense_info;
  6260. sense_info = kzalloc(sizeof(*sense_info), GFP_KERNEL);
  6261. if (!sense_info)
  6262. return -ENOMEM;
  6263. rc = pqi_sense_subsystem_info(ctrl_info, sense_info);
  6264. if (rc)
  6265. goto out;
  6266. memcpy(ctrl_info->serial_number, sense_info->ctrl_serial_number,
  6267. sizeof(sense_info->ctrl_serial_number));
  6268. ctrl_info->serial_number[sizeof(sense_info->ctrl_serial_number)] = '\0';
  6269. out:
  6270. kfree(sense_info);
  6271. return rc;
  6272. }
  6273. static int pqi_get_ctrl_product_details(struct pqi_ctrl_info *ctrl_info)
  6274. {
  6275. int rc;
  6276. struct bmic_identify_controller *identify;
  6277. identify = kmalloc(sizeof(*identify), GFP_KERNEL);
  6278. if (!identify)
  6279. return -ENOMEM;
  6280. rc = pqi_identify_controller(ctrl_info, identify);
  6281. if (rc)
  6282. goto out;
  6283. if (get_unaligned_le32(&identify->extra_controller_flags) &
  6284. BMIC_IDENTIFY_EXTRA_FLAGS_LONG_FW_VERSION_SUPPORTED) {
  6285. memcpy(ctrl_info->firmware_version,
  6286. identify->firmware_version_long,
  6287. sizeof(identify->firmware_version_long));
  6288. } else {
  6289. memcpy(ctrl_info->firmware_version,
  6290. identify->firmware_version_short,
  6291. sizeof(identify->firmware_version_short));
  6292. ctrl_info->firmware_version
  6293. [sizeof(identify->firmware_version_short)] = '\0';
  6294. snprintf(ctrl_info->firmware_version +
  6295. strlen(ctrl_info->firmware_version),
  6296. sizeof(ctrl_info->firmware_version) -
  6297. sizeof(identify->firmware_version_short),
  6298. "-%u",
  6299. get_unaligned_le16(&identify->firmware_build_number));
  6300. }
  6301. memcpy(ctrl_info->model, identify->product_id,
  6302. sizeof(identify->product_id));
  6303. ctrl_info->model[sizeof(identify->product_id)] = '\0';
  6304. memcpy(ctrl_info->vendor, identify->vendor_id,
  6305. sizeof(identify->vendor_id));
  6306. ctrl_info->vendor[sizeof(identify->vendor_id)] = '\0';
  6307. dev_info(&ctrl_info->pci_dev->dev,
  6308. "Firmware version: %s\n", ctrl_info->firmware_version);
  6309. out:
  6310. kfree(identify);
  6311. return rc;
  6312. }
  6313. struct pqi_config_table_section_info {
  6314. struct pqi_ctrl_info *ctrl_info;
  6315. void *section;
  6316. u32 section_offset;
  6317. void __iomem *section_iomem_addr;
  6318. };
  6319. static inline bool pqi_is_firmware_feature_supported(
  6320. struct pqi_config_table_firmware_features *firmware_features,
  6321. unsigned int bit_position)
  6322. {
  6323. unsigned int byte_index;
  6324. byte_index = bit_position / BITS_PER_BYTE;
  6325. if (byte_index >= le16_to_cpu(firmware_features->num_elements))
  6326. return false;
  6327. return firmware_features->features_supported[byte_index] &
  6328. (1 << (bit_position % BITS_PER_BYTE)) ? true : false;
  6329. }
  6330. static inline bool pqi_is_firmware_feature_enabled(
  6331. struct pqi_config_table_firmware_features *firmware_features,
  6332. void __iomem *firmware_features_iomem_addr,
  6333. unsigned int bit_position)
  6334. {
  6335. unsigned int byte_index;
  6336. u8 __iomem *features_enabled_iomem_addr;
  6337. byte_index = (bit_position / BITS_PER_BYTE) +
  6338. (le16_to_cpu(firmware_features->num_elements) * 2);
  6339. features_enabled_iomem_addr = firmware_features_iomem_addr +
  6340. offsetof(struct pqi_config_table_firmware_features,
  6341. features_supported) + byte_index;
  6342. return *((__force u8 *)features_enabled_iomem_addr) &
  6343. (1 << (bit_position % BITS_PER_BYTE)) ? true : false;
  6344. }
  6345. static inline void pqi_request_firmware_feature(
  6346. struct pqi_config_table_firmware_features *firmware_features,
  6347. unsigned int bit_position)
  6348. {
  6349. unsigned int byte_index;
  6350. byte_index = (bit_position / BITS_PER_BYTE) +
  6351. le16_to_cpu(firmware_features->num_elements);
  6352. firmware_features->features_supported[byte_index] |=
  6353. (1 << (bit_position % BITS_PER_BYTE));
  6354. }
  6355. static int pqi_config_table_update(struct pqi_ctrl_info *ctrl_info,
  6356. u16 first_section, u16 last_section)
  6357. {
  6358. struct pqi_vendor_general_request request;
  6359. memset(&request, 0, sizeof(request));
  6360. request.header.iu_type = PQI_REQUEST_IU_VENDOR_GENERAL;
  6361. put_unaligned_le16(sizeof(request) - PQI_REQUEST_HEADER_LENGTH,
  6362. &request.header.iu_length);
  6363. put_unaligned_le16(PQI_VENDOR_GENERAL_CONFIG_TABLE_UPDATE,
  6364. &request.function_code);
  6365. put_unaligned_le16(first_section,
  6366. &request.data.config_table_update.first_section);
  6367. put_unaligned_le16(last_section,
  6368. &request.data.config_table_update.last_section);
  6369. return pqi_submit_raid_request_synchronous(ctrl_info, &request.header, 0, NULL);
  6370. }
  6371. static int pqi_enable_firmware_features(struct pqi_ctrl_info *ctrl_info,
  6372. struct pqi_config_table_firmware_features *firmware_features,
  6373. void __iomem *firmware_features_iomem_addr)
  6374. {
  6375. void *features_requested;
  6376. void __iomem *features_requested_iomem_addr;
  6377. void __iomem *host_max_known_feature_iomem_addr;
  6378. features_requested = firmware_features->features_supported +
  6379. le16_to_cpu(firmware_features->num_elements);
  6380. features_requested_iomem_addr = firmware_features_iomem_addr +
  6381. (features_requested - (void *)firmware_features);
  6382. memcpy_toio(features_requested_iomem_addr, features_requested,
  6383. le16_to_cpu(firmware_features->num_elements));
  6384. if (pqi_is_firmware_feature_supported(firmware_features,
  6385. PQI_FIRMWARE_FEATURE_MAX_KNOWN_FEATURE)) {
  6386. host_max_known_feature_iomem_addr =
  6387. features_requested_iomem_addr +
  6388. (le16_to_cpu(firmware_features->num_elements) * 2) +
  6389. sizeof(__le16);
  6390. writew(PQI_FIRMWARE_FEATURE_MAXIMUM,
  6391. host_max_known_feature_iomem_addr);
  6392. }
  6393. return pqi_config_table_update(ctrl_info,
  6394. PQI_CONFIG_TABLE_SECTION_FIRMWARE_FEATURES,
  6395. PQI_CONFIG_TABLE_SECTION_FIRMWARE_FEATURES);
  6396. }
  6397. struct pqi_firmware_feature {
  6398. char *feature_name;
  6399. unsigned int feature_bit;
  6400. bool supported;
  6401. bool enabled;
  6402. void (*feature_status)(struct pqi_ctrl_info *ctrl_info,
  6403. struct pqi_firmware_feature *firmware_feature);
  6404. };
  6405. static void pqi_firmware_feature_status(struct pqi_ctrl_info *ctrl_info,
  6406. struct pqi_firmware_feature *firmware_feature)
  6407. {
  6408. if (!firmware_feature->supported) {
  6409. dev_info(&ctrl_info->pci_dev->dev, "%s not supported by controller\n",
  6410. firmware_feature->feature_name);
  6411. return;
  6412. }
  6413. if (firmware_feature->enabled) {
  6414. dev_info(&ctrl_info->pci_dev->dev,
  6415. "%s enabled\n", firmware_feature->feature_name);
  6416. return;
  6417. }
  6418. dev_err(&ctrl_info->pci_dev->dev, "failed to enable %s\n",
  6419. firmware_feature->feature_name);
  6420. }
  6421. static void pqi_ctrl_update_feature_flags(struct pqi_ctrl_info *ctrl_info,
  6422. struct pqi_firmware_feature *firmware_feature)
  6423. {
  6424. switch (firmware_feature->feature_bit) {
  6425. case PQI_FIRMWARE_FEATURE_RAID_1_WRITE_BYPASS:
  6426. ctrl_info->enable_r1_writes = firmware_feature->enabled;
  6427. break;
  6428. case PQI_FIRMWARE_FEATURE_RAID_5_WRITE_BYPASS:
  6429. ctrl_info->enable_r5_writes = firmware_feature->enabled;
  6430. break;
  6431. case PQI_FIRMWARE_FEATURE_RAID_6_WRITE_BYPASS:
  6432. ctrl_info->enable_r6_writes = firmware_feature->enabled;
  6433. break;
  6434. case PQI_FIRMWARE_FEATURE_SOFT_RESET_HANDSHAKE:
  6435. ctrl_info->soft_reset_handshake_supported =
  6436. firmware_feature->enabled &&
  6437. pqi_read_soft_reset_status(ctrl_info);
  6438. break;
  6439. case PQI_FIRMWARE_FEATURE_RAID_IU_TIMEOUT:
  6440. ctrl_info->raid_iu_timeout_supported = firmware_feature->enabled;
  6441. break;
  6442. case PQI_FIRMWARE_FEATURE_TMF_IU_TIMEOUT:
  6443. ctrl_info->tmf_iu_timeout_supported = firmware_feature->enabled;
  6444. break;
  6445. case PQI_FIRMWARE_FEATURE_FW_TRIAGE:
  6446. ctrl_info->firmware_triage_supported = firmware_feature->enabled;
  6447. pqi_save_fw_triage_setting(ctrl_info, firmware_feature->enabled);
  6448. break;
  6449. case PQI_FIRMWARE_FEATURE_RPL_EXTENDED_FORMAT_4_5:
  6450. ctrl_info->rpl_extended_format_4_5_supported = firmware_feature->enabled;
  6451. break;
  6452. case PQI_FIRMWARE_FEATURE_MULTI_LUN_DEVICE_SUPPORT:
  6453. ctrl_info->multi_lun_device_supported = firmware_feature->enabled;
  6454. break;
  6455. }
  6456. pqi_firmware_feature_status(ctrl_info, firmware_feature);
  6457. }
  6458. static inline void pqi_firmware_feature_update(struct pqi_ctrl_info *ctrl_info,
  6459. struct pqi_firmware_feature *firmware_feature)
  6460. {
  6461. if (firmware_feature->feature_status)
  6462. firmware_feature->feature_status(ctrl_info, firmware_feature);
  6463. }
  6464. static DEFINE_MUTEX(pqi_firmware_features_mutex);
  6465. static struct pqi_firmware_feature pqi_firmware_features[] = {
  6466. {
  6467. .feature_name = "Online Firmware Activation",
  6468. .feature_bit = PQI_FIRMWARE_FEATURE_OFA,
  6469. .feature_status = pqi_firmware_feature_status,
  6470. },
  6471. {
  6472. .feature_name = "Serial Management Protocol",
  6473. .feature_bit = PQI_FIRMWARE_FEATURE_SMP,
  6474. .feature_status = pqi_firmware_feature_status,
  6475. },
  6476. {
  6477. .feature_name = "Maximum Known Feature",
  6478. .feature_bit = PQI_FIRMWARE_FEATURE_MAX_KNOWN_FEATURE,
  6479. .feature_status = pqi_firmware_feature_status,
  6480. },
  6481. {
  6482. .feature_name = "RAID 0 Read Bypass",
  6483. .feature_bit = PQI_FIRMWARE_FEATURE_RAID_0_READ_BYPASS,
  6484. .feature_status = pqi_firmware_feature_status,
  6485. },
  6486. {
  6487. .feature_name = "RAID 1 Read Bypass",
  6488. .feature_bit = PQI_FIRMWARE_FEATURE_RAID_1_READ_BYPASS,
  6489. .feature_status = pqi_firmware_feature_status,
  6490. },
  6491. {
  6492. .feature_name = "RAID 5 Read Bypass",
  6493. .feature_bit = PQI_FIRMWARE_FEATURE_RAID_5_READ_BYPASS,
  6494. .feature_status = pqi_firmware_feature_status,
  6495. },
  6496. {
  6497. .feature_name = "RAID 6 Read Bypass",
  6498. .feature_bit = PQI_FIRMWARE_FEATURE_RAID_6_READ_BYPASS,
  6499. .feature_status = pqi_firmware_feature_status,
  6500. },
  6501. {
  6502. .feature_name = "RAID 0 Write Bypass",
  6503. .feature_bit = PQI_FIRMWARE_FEATURE_RAID_0_WRITE_BYPASS,
  6504. .feature_status = pqi_firmware_feature_status,
  6505. },
  6506. {
  6507. .feature_name = "RAID 1 Write Bypass",
  6508. .feature_bit = PQI_FIRMWARE_FEATURE_RAID_1_WRITE_BYPASS,
  6509. .feature_status = pqi_ctrl_update_feature_flags,
  6510. },
  6511. {
  6512. .feature_name = "RAID 5 Write Bypass",
  6513. .feature_bit = PQI_FIRMWARE_FEATURE_RAID_5_WRITE_BYPASS,
  6514. .feature_status = pqi_ctrl_update_feature_flags,
  6515. },
  6516. {
  6517. .feature_name = "RAID 6 Write Bypass",
  6518. .feature_bit = PQI_FIRMWARE_FEATURE_RAID_6_WRITE_BYPASS,
  6519. .feature_status = pqi_ctrl_update_feature_flags,
  6520. },
  6521. {
  6522. .feature_name = "New Soft Reset Handshake",
  6523. .feature_bit = PQI_FIRMWARE_FEATURE_SOFT_RESET_HANDSHAKE,
  6524. .feature_status = pqi_ctrl_update_feature_flags,
  6525. },
  6526. {
  6527. .feature_name = "RAID IU Timeout",
  6528. .feature_bit = PQI_FIRMWARE_FEATURE_RAID_IU_TIMEOUT,
  6529. .feature_status = pqi_ctrl_update_feature_flags,
  6530. },
  6531. {
  6532. .feature_name = "TMF IU Timeout",
  6533. .feature_bit = PQI_FIRMWARE_FEATURE_TMF_IU_TIMEOUT,
  6534. .feature_status = pqi_ctrl_update_feature_flags,
  6535. },
  6536. {
  6537. .feature_name = "RAID Bypass on encrypted logical volumes on NVMe",
  6538. .feature_bit = PQI_FIRMWARE_FEATURE_RAID_BYPASS_ON_ENCRYPTED_NVME,
  6539. .feature_status = pqi_firmware_feature_status,
  6540. },
  6541. {
  6542. .feature_name = "Firmware Triage",
  6543. .feature_bit = PQI_FIRMWARE_FEATURE_FW_TRIAGE,
  6544. .feature_status = pqi_ctrl_update_feature_flags,
  6545. },
  6546. {
  6547. .feature_name = "RPL Extended Formats 4 and 5",
  6548. .feature_bit = PQI_FIRMWARE_FEATURE_RPL_EXTENDED_FORMAT_4_5,
  6549. .feature_status = pqi_ctrl_update_feature_flags,
  6550. },
  6551. {
  6552. .feature_name = "Multi-LUN Target",
  6553. .feature_bit = PQI_FIRMWARE_FEATURE_MULTI_LUN_DEVICE_SUPPORT,
  6554. .feature_status = pqi_ctrl_update_feature_flags,
  6555. },
  6556. };
  6557. static void pqi_process_firmware_features(
  6558. struct pqi_config_table_section_info *section_info)
  6559. {
  6560. int rc;
  6561. struct pqi_ctrl_info *ctrl_info;
  6562. struct pqi_config_table_firmware_features *firmware_features;
  6563. void __iomem *firmware_features_iomem_addr;
  6564. unsigned int i;
  6565. unsigned int num_features_supported;
  6566. ctrl_info = section_info->ctrl_info;
  6567. firmware_features = section_info->section;
  6568. firmware_features_iomem_addr = section_info->section_iomem_addr;
  6569. for (i = 0, num_features_supported = 0;
  6570. i < ARRAY_SIZE(pqi_firmware_features); i++) {
  6571. if (pqi_is_firmware_feature_supported(firmware_features,
  6572. pqi_firmware_features[i].feature_bit)) {
  6573. pqi_firmware_features[i].supported = true;
  6574. num_features_supported++;
  6575. } else {
  6576. pqi_firmware_feature_update(ctrl_info,
  6577. &pqi_firmware_features[i]);
  6578. }
  6579. }
  6580. if (num_features_supported == 0)
  6581. return;
  6582. for (i = 0; i < ARRAY_SIZE(pqi_firmware_features); i++) {
  6583. if (!pqi_firmware_features[i].supported)
  6584. continue;
  6585. pqi_request_firmware_feature(firmware_features,
  6586. pqi_firmware_features[i].feature_bit);
  6587. }
  6588. rc = pqi_enable_firmware_features(ctrl_info, firmware_features,
  6589. firmware_features_iomem_addr);
  6590. if (rc) {
  6591. dev_err(&ctrl_info->pci_dev->dev,
  6592. "failed to enable firmware features in PQI configuration table\n");
  6593. for (i = 0; i < ARRAY_SIZE(pqi_firmware_features); i++) {
  6594. if (!pqi_firmware_features[i].supported)
  6595. continue;
  6596. pqi_firmware_feature_update(ctrl_info,
  6597. &pqi_firmware_features[i]);
  6598. }
  6599. return;
  6600. }
  6601. for (i = 0; i < ARRAY_SIZE(pqi_firmware_features); i++) {
  6602. if (!pqi_firmware_features[i].supported)
  6603. continue;
  6604. if (pqi_is_firmware_feature_enabled(firmware_features,
  6605. firmware_features_iomem_addr,
  6606. pqi_firmware_features[i].feature_bit)) {
  6607. pqi_firmware_features[i].enabled = true;
  6608. }
  6609. pqi_firmware_feature_update(ctrl_info,
  6610. &pqi_firmware_features[i]);
  6611. }
  6612. }
  6613. static void pqi_init_firmware_features(void)
  6614. {
  6615. unsigned int i;
  6616. for (i = 0; i < ARRAY_SIZE(pqi_firmware_features); i++) {
  6617. pqi_firmware_features[i].supported = false;
  6618. pqi_firmware_features[i].enabled = false;
  6619. }
  6620. }
  6621. static void pqi_process_firmware_features_section(
  6622. struct pqi_config_table_section_info *section_info)
  6623. {
  6624. mutex_lock(&pqi_firmware_features_mutex);
  6625. pqi_init_firmware_features();
  6626. pqi_process_firmware_features(section_info);
  6627. mutex_unlock(&pqi_firmware_features_mutex);
  6628. }
  6629. /*
  6630. * Reset all controller settings that can be initialized during the processing
  6631. * of the PQI Configuration Table.
  6632. */
  6633. static void pqi_ctrl_reset_config(struct pqi_ctrl_info *ctrl_info)
  6634. {
  6635. ctrl_info->heartbeat_counter = NULL;
  6636. ctrl_info->soft_reset_status = NULL;
  6637. ctrl_info->soft_reset_handshake_supported = false;
  6638. ctrl_info->enable_r1_writes = false;
  6639. ctrl_info->enable_r5_writes = false;
  6640. ctrl_info->enable_r6_writes = false;
  6641. ctrl_info->raid_iu_timeout_supported = false;
  6642. ctrl_info->tmf_iu_timeout_supported = false;
  6643. ctrl_info->firmware_triage_supported = false;
  6644. ctrl_info->rpl_extended_format_4_5_supported = false;
  6645. ctrl_info->multi_lun_device_supported = false;
  6646. }
  6647. static int pqi_process_config_table(struct pqi_ctrl_info *ctrl_info)
  6648. {
  6649. u32 table_length;
  6650. u32 section_offset;
  6651. bool firmware_feature_section_present;
  6652. void __iomem *table_iomem_addr;
  6653. struct pqi_config_table *config_table;
  6654. struct pqi_config_table_section_header *section;
  6655. struct pqi_config_table_section_info section_info;
  6656. struct pqi_config_table_section_info feature_section_info;
  6657. table_length = ctrl_info->config_table_length;
  6658. if (table_length == 0)
  6659. return 0;
  6660. config_table = kmalloc(table_length, GFP_KERNEL);
  6661. if (!config_table) {
  6662. dev_err(&ctrl_info->pci_dev->dev,
  6663. "failed to allocate memory for PQI configuration table\n");
  6664. return -ENOMEM;
  6665. }
  6666. /*
  6667. * Copy the config table contents from I/O memory space into the
  6668. * temporary buffer.
  6669. */
  6670. table_iomem_addr = ctrl_info->iomem_base + ctrl_info->config_table_offset;
  6671. memcpy_fromio(config_table, table_iomem_addr, table_length);
  6672. firmware_feature_section_present = false;
  6673. section_info.ctrl_info = ctrl_info;
  6674. section_offset = get_unaligned_le32(&config_table->first_section_offset);
  6675. while (section_offset) {
  6676. section = (void *)config_table + section_offset;
  6677. section_info.section = section;
  6678. section_info.section_offset = section_offset;
  6679. section_info.section_iomem_addr = table_iomem_addr + section_offset;
  6680. switch (get_unaligned_le16(&section->section_id)) {
  6681. case PQI_CONFIG_TABLE_SECTION_FIRMWARE_FEATURES:
  6682. firmware_feature_section_present = true;
  6683. feature_section_info = section_info;
  6684. break;
  6685. case PQI_CONFIG_TABLE_SECTION_HEARTBEAT:
  6686. if (pqi_disable_heartbeat)
  6687. dev_warn(&ctrl_info->pci_dev->dev,
  6688. "heartbeat disabled by module parameter\n");
  6689. else
  6690. ctrl_info->heartbeat_counter =
  6691. table_iomem_addr +
  6692. section_offset +
  6693. offsetof(struct pqi_config_table_heartbeat,
  6694. heartbeat_counter);
  6695. break;
  6696. case PQI_CONFIG_TABLE_SECTION_SOFT_RESET:
  6697. ctrl_info->soft_reset_status =
  6698. table_iomem_addr +
  6699. section_offset +
  6700. offsetof(struct pqi_config_table_soft_reset,
  6701. soft_reset_status);
  6702. break;
  6703. }
  6704. section_offset = get_unaligned_le16(&section->next_section_offset);
  6705. }
  6706. /*
  6707. * We process the firmware feature section after all other sections
  6708. * have been processed so that the feature bit callbacks can take
  6709. * into account the settings configured by other sections.
  6710. */
  6711. if (firmware_feature_section_present)
  6712. pqi_process_firmware_features_section(&feature_section_info);
  6713. kfree(config_table);
  6714. return 0;
  6715. }
  6716. /* Switches the controller from PQI mode back into SIS mode. */
  6717. static int pqi_revert_to_sis_mode(struct pqi_ctrl_info *ctrl_info)
  6718. {
  6719. int rc;
  6720. pqi_change_irq_mode(ctrl_info, IRQ_MODE_NONE);
  6721. rc = pqi_reset(ctrl_info);
  6722. if (rc)
  6723. return rc;
  6724. rc = sis_reenable_sis_mode(ctrl_info);
  6725. if (rc) {
  6726. dev_err(&ctrl_info->pci_dev->dev,
  6727. "re-enabling SIS mode failed with error %d\n", rc);
  6728. return rc;
  6729. }
  6730. pqi_save_ctrl_mode(ctrl_info, SIS_MODE);
  6731. return 0;
  6732. }
  6733. /*
  6734. * If the controller isn't already in SIS mode, this function forces it into
  6735. * SIS mode.
  6736. */
  6737. static int pqi_force_sis_mode(struct pqi_ctrl_info *ctrl_info)
  6738. {
  6739. if (!sis_is_firmware_running(ctrl_info))
  6740. return -ENXIO;
  6741. if (pqi_get_ctrl_mode(ctrl_info) == SIS_MODE)
  6742. return 0;
  6743. if (sis_is_kernel_up(ctrl_info)) {
  6744. pqi_save_ctrl_mode(ctrl_info, SIS_MODE);
  6745. return 0;
  6746. }
  6747. return pqi_revert_to_sis_mode(ctrl_info);
  6748. }
  6749. static void pqi_perform_lockup_action(void)
  6750. {
  6751. switch (pqi_lockup_action) {
  6752. case PANIC:
  6753. panic("FATAL: Smart Family Controller lockup detected");
  6754. break;
  6755. case REBOOT:
  6756. emergency_restart();
  6757. break;
  6758. case NONE:
  6759. default:
  6760. break;
  6761. }
  6762. }
  6763. static int pqi_ctrl_init(struct pqi_ctrl_info *ctrl_info)
  6764. {
  6765. int rc;
  6766. u32 product_id;
  6767. if (reset_devices) {
  6768. if (pqi_is_fw_triage_supported(ctrl_info)) {
  6769. rc = sis_wait_for_fw_triage_completion(ctrl_info);
  6770. if (rc)
  6771. return rc;
  6772. }
  6773. sis_soft_reset(ctrl_info);
  6774. ssleep(PQI_POST_RESET_DELAY_SECS);
  6775. } else {
  6776. rc = pqi_force_sis_mode(ctrl_info);
  6777. if (rc)
  6778. return rc;
  6779. }
  6780. /*
  6781. * Wait until the controller is ready to start accepting SIS
  6782. * commands.
  6783. */
  6784. rc = sis_wait_for_ctrl_ready(ctrl_info);
  6785. if (rc) {
  6786. if (reset_devices) {
  6787. dev_err(&ctrl_info->pci_dev->dev,
  6788. "kdump init failed with error %d\n", rc);
  6789. pqi_lockup_action = REBOOT;
  6790. pqi_perform_lockup_action();
  6791. }
  6792. return rc;
  6793. }
  6794. /*
  6795. * Get the controller properties. This allows us to determine
  6796. * whether or not it supports PQI mode.
  6797. */
  6798. rc = sis_get_ctrl_properties(ctrl_info);
  6799. if (rc) {
  6800. dev_err(&ctrl_info->pci_dev->dev,
  6801. "error obtaining controller properties\n");
  6802. return rc;
  6803. }
  6804. rc = sis_get_pqi_capabilities(ctrl_info);
  6805. if (rc) {
  6806. dev_err(&ctrl_info->pci_dev->dev,
  6807. "error obtaining controller capabilities\n");
  6808. return rc;
  6809. }
  6810. product_id = sis_get_product_id(ctrl_info);
  6811. ctrl_info->product_id = (u8)product_id;
  6812. ctrl_info->product_revision = (u8)(product_id >> 8);
  6813. if (reset_devices) {
  6814. if (ctrl_info->max_outstanding_requests >
  6815. PQI_MAX_OUTSTANDING_REQUESTS_KDUMP)
  6816. ctrl_info->max_outstanding_requests =
  6817. PQI_MAX_OUTSTANDING_REQUESTS_KDUMP;
  6818. } else {
  6819. if (ctrl_info->max_outstanding_requests >
  6820. PQI_MAX_OUTSTANDING_REQUESTS)
  6821. ctrl_info->max_outstanding_requests =
  6822. PQI_MAX_OUTSTANDING_REQUESTS;
  6823. }
  6824. pqi_calculate_io_resources(ctrl_info);
  6825. rc = pqi_alloc_error_buffer(ctrl_info);
  6826. if (rc) {
  6827. dev_err(&ctrl_info->pci_dev->dev,
  6828. "failed to allocate PQI error buffer\n");
  6829. return rc;
  6830. }
  6831. /*
  6832. * If the function we are about to call succeeds, the
  6833. * controller will transition from legacy SIS mode
  6834. * into PQI mode.
  6835. */
  6836. rc = sis_init_base_struct_addr(ctrl_info);
  6837. if (rc) {
  6838. dev_err(&ctrl_info->pci_dev->dev,
  6839. "error initializing PQI mode\n");
  6840. return rc;
  6841. }
  6842. /* Wait for the controller to complete the SIS -> PQI transition. */
  6843. rc = pqi_wait_for_pqi_mode_ready(ctrl_info);
  6844. if (rc) {
  6845. dev_err(&ctrl_info->pci_dev->dev,
  6846. "transition to PQI mode failed\n");
  6847. return rc;
  6848. }
  6849. /* From here on, we are running in PQI mode. */
  6850. ctrl_info->pqi_mode_enabled = true;
  6851. pqi_save_ctrl_mode(ctrl_info, PQI_MODE);
  6852. rc = pqi_alloc_admin_queues(ctrl_info);
  6853. if (rc) {
  6854. dev_err(&ctrl_info->pci_dev->dev,
  6855. "failed to allocate admin queues\n");
  6856. return rc;
  6857. }
  6858. rc = pqi_create_admin_queues(ctrl_info);
  6859. if (rc) {
  6860. dev_err(&ctrl_info->pci_dev->dev,
  6861. "error creating admin queues\n");
  6862. return rc;
  6863. }
  6864. rc = pqi_report_device_capability(ctrl_info);
  6865. if (rc) {
  6866. dev_err(&ctrl_info->pci_dev->dev,
  6867. "obtaining device capability failed\n");
  6868. return rc;
  6869. }
  6870. rc = pqi_validate_device_capability(ctrl_info);
  6871. if (rc)
  6872. return rc;
  6873. pqi_calculate_queue_resources(ctrl_info);
  6874. rc = pqi_enable_msix_interrupts(ctrl_info);
  6875. if (rc)
  6876. return rc;
  6877. if (ctrl_info->num_msix_vectors_enabled < ctrl_info->num_queue_groups) {
  6878. ctrl_info->max_msix_vectors =
  6879. ctrl_info->num_msix_vectors_enabled;
  6880. pqi_calculate_queue_resources(ctrl_info);
  6881. }
  6882. rc = pqi_alloc_io_resources(ctrl_info);
  6883. if (rc)
  6884. return rc;
  6885. rc = pqi_alloc_operational_queues(ctrl_info);
  6886. if (rc) {
  6887. dev_err(&ctrl_info->pci_dev->dev,
  6888. "failed to allocate operational queues\n");
  6889. return rc;
  6890. }
  6891. pqi_init_operational_queues(ctrl_info);
  6892. rc = pqi_create_queues(ctrl_info);
  6893. if (rc)
  6894. return rc;
  6895. rc = pqi_request_irqs(ctrl_info);
  6896. if (rc)
  6897. return rc;
  6898. pqi_change_irq_mode(ctrl_info, IRQ_MODE_MSIX);
  6899. ctrl_info->controller_online = true;
  6900. rc = pqi_process_config_table(ctrl_info);
  6901. if (rc)
  6902. return rc;
  6903. pqi_start_heartbeat_timer(ctrl_info);
  6904. if (ctrl_info->enable_r5_writes || ctrl_info->enable_r6_writes) {
  6905. rc = pqi_get_advanced_raid_bypass_config(ctrl_info);
  6906. if (rc) { /* Supported features not returned correctly. */
  6907. dev_err(&ctrl_info->pci_dev->dev,
  6908. "error obtaining advanced RAID bypass configuration\n");
  6909. return rc;
  6910. }
  6911. ctrl_info->ciss_report_log_flags |=
  6912. CISS_REPORT_LOG_FLAG_DRIVE_TYPE_MIX;
  6913. }
  6914. rc = pqi_enable_events(ctrl_info);
  6915. if (rc) {
  6916. dev_err(&ctrl_info->pci_dev->dev,
  6917. "error enabling events\n");
  6918. return rc;
  6919. }
  6920. /* Register with the SCSI subsystem. */
  6921. rc = pqi_register_scsi(ctrl_info);
  6922. if (rc)
  6923. return rc;
  6924. rc = pqi_get_ctrl_product_details(ctrl_info);
  6925. if (rc) {
  6926. dev_err(&ctrl_info->pci_dev->dev,
  6927. "error obtaining product details\n");
  6928. return rc;
  6929. }
  6930. rc = pqi_get_ctrl_serial_number(ctrl_info);
  6931. if (rc) {
  6932. dev_err(&ctrl_info->pci_dev->dev,
  6933. "error obtaining ctrl serial number\n");
  6934. return rc;
  6935. }
  6936. rc = pqi_set_diag_rescan(ctrl_info);
  6937. if (rc) {
  6938. dev_err(&ctrl_info->pci_dev->dev,
  6939. "error enabling multi-lun rescan\n");
  6940. return rc;
  6941. }
  6942. rc = pqi_write_driver_version_to_host_wellness(ctrl_info);
  6943. if (rc) {
  6944. dev_err(&ctrl_info->pci_dev->dev,
  6945. "error updating host wellness\n");
  6946. return rc;
  6947. }
  6948. pqi_schedule_update_time_worker(ctrl_info);
  6949. pqi_scan_scsi_devices(ctrl_info);
  6950. return 0;
  6951. }
  6952. static void pqi_reinit_queues(struct pqi_ctrl_info *ctrl_info)
  6953. {
  6954. unsigned int i;
  6955. struct pqi_admin_queues *admin_queues;
  6956. struct pqi_event_queue *event_queue;
  6957. admin_queues = &ctrl_info->admin_queues;
  6958. admin_queues->iq_pi_copy = 0;
  6959. admin_queues->oq_ci_copy = 0;
  6960. writel(0, admin_queues->oq_pi);
  6961. for (i = 0; i < ctrl_info->num_queue_groups; i++) {
  6962. ctrl_info->queue_groups[i].iq_pi_copy[RAID_PATH] = 0;
  6963. ctrl_info->queue_groups[i].iq_pi_copy[AIO_PATH] = 0;
  6964. ctrl_info->queue_groups[i].oq_ci_copy = 0;
  6965. writel(0, ctrl_info->queue_groups[i].iq_ci[RAID_PATH]);
  6966. writel(0, ctrl_info->queue_groups[i].iq_ci[AIO_PATH]);
  6967. writel(0, ctrl_info->queue_groups[i].oq_pi);
  6968. }
  6969. event_queue = &ctrl_info->event_queue;
  6970. writel(0, event_queue->oq_pi);
  6971. event_queue->oq_ci_copy = 0;
  6972. }
  6973. static int pqi_ctrl_init_resume(struct pqi_ctrl_info *ctrl_info)
  6974. {
  6975. int rc;
  6976. rc = pqi_force_sis_mode(ctrl_info);
  6977. if (rc)
  6978. return rc;
  6979. /*
  6980. * Wait until the controller is ready to start accepting SIS
  6981. * commands.
  6982. */
  6983. rc = sis_wait_for_ctrl_ready_resume(ctrl_info);
  6984. if (rc)
  6985. return rc;
  6986. /*
  6987. * Get the controller properties. This allows us to determine
  6988. * whether or not it supports PQI mode.
  6989. */
  6990. rc = sis_get_ctrl_properties(ctrl_info);
  6991. if (rc) {
  6992. dev_err(&ctrl_info->pci_dev->dev,
  6993. "error obtaining controller properties\n");
  6994. return rc;
  6995. }
  6996. rc = sis_get_pqi_capabilities(ctrl_info);
  6997. if (rc) {
  6998. dev_err(&ctrl_info->pci_dev->dev,
  6999. "error obtaining controller capabilities\n");
  7000. return rc;
  7001. }
  7002. /*
  7003. * If the function we are about to call succeeds, the
  7004. * controller will transition from legacy SIS mode
  7005. * into PQI mode.
  7006. */
  7007. rc = sis_init_base_struct_addr(ctrl_info);
  7008. if (rc) {
  7009. dev_err(&ctrl_info->pci_dev->dev,
  7010. "error initializing PQI mode\n");
  7011. return rc;
  7012. }
  7013. /* Wait for the controller to complete the SIS -> PQI transition. */
  7014. rc = pqi_wait_for_pqi_mode_ready(ctrl_info);
  7015. if (rc) {
  7016. dev_err(&ctrl_info->pci_dev->dev,
  7017. "transition to PQI mode failed\n");
  7018. return rc;
  7019. }
  7020. /* From here on, we are running in PQI mode. */
  7021. ctrl_info->pqi_mode_enabled = true;
  7022. pqi_save_ctrl_mode(ctrl_info, PQI_MODE);
  7023. pqi_reinit_queues(ctrl_info);
  7024. rc = pqi_create_admin_queues(ctrl_info);
  7025. if (rc) {
  7026. dev_err(&ctrl_info->pci_dev->dev,
  7027. "error creating admin queues\n");
  7028. return rc;
  7029. }
  7030. rc = pqi_create_queues(ctrl_info);
  7031. if (rc)
  7032. return rc;
  7033. pqi_change_irq_mode(ctrl_info, IRQ_MODE_MSIX);
  7034. ctrl_info->controller_online = true;
  7035. pqi_ctrl_unblock_requests(ctrl_info);
  7036. pqi_ctrl_reset_config(ctrl_info);
  7037. rc = pqi_process_config_table(ctrl_info);
  7038. if (rc)
  7039. return rc;
  7040. pqi_start_heartbeat_timer(ctrl_info);
  7041. if (ctrl_info->enable_r5_writes || ctrl_info->enable_r6_writes) {
  7042. rc = pqi_get_advanced_raid_bypass_config(ctrl_info);
  7043. if (rc) {
  7044. dev_err(&ctrl_info->pci_dev->dev,
  7045. "error obtaining advanced RAID bypass configuration\n");
  7046. return rc;
  7047. }
  7048. ctrl_info->ciss_report_log_flags |=
  7049. CISS_REPORT_LOG_FLAG_DRIVE_TYPE_MIX;
  7050. }
  7051. rc = pqi_enable_events(ctrl_info);
  7052. if (rc) {
  7053. dev_err(&ctrl_info->pci_dev->dev,
  7054. "error enabling events\n");
  7055. return rc;
  7056. }
  7057. rc = pqi_get_ctrl_product_details(ctrl_info);
  7058. if (rc) {
  7059. dev_err(&ctrl_info->pci_dev->dev,
  7060. "error obtaining product details\n");
  7061. return rc;
  7062. }
  7063. rc = pqi_set_diag_rescan(ctrl_info);
  7064. if (rc) {
  7065. dev_err(&ctrl_info->pci_dev->dev,
  7066. "error enabling multi-lun rescan\n");
  7067. return rc;
  7068. }
  7069. rc = pqi_write_driver_version_to_host_wellness(ctrl_info);
  7070. if (rc) {
  7071. dev_err(&ctrl_info->pci_dev->dev,
  7072. "error updating host wellness\n");
  7073. return rc;
  7074. }
  7075. if (pqi_ofa_in_progress(ctrl_info))
  7076. pqi_ctrl_unblock_scan(ctrl_info);
  7077. pqi_scan_scsi_devices(ctrl_info);
  7078. return 0;
  7079. }
  7080. static inline int pqi_set_pcie_completion_timeout(struct pci_dev *pci_dev, u16 timeout)
  7081. {
  7082. int rc;
  7083. rc = pcie_capability_clear_and_set_word(pci_dev, PCI_EXP_DEVCTL2,
  7084. PCI_EXP_DEVCTL2_COMP_TIMEOUT, timeout);
  7085. return pcibios_err_to_errno(rc);
  7086. }
  7087. static int pqi_pci_init(struct pqi_ctrl_info *ctrl_info)
  7088. {
  7089. int rc;
  7090. u64 mask;
  7091. rc = pci_enable_device(ctrl_info->pci_dev);
  7092. if (rc) {
  7093. dev_err(&ctrl_info->pci_dev->dev,
  7094. "failed to enable PCI device\n");
  7095. return rc;
  7096. }
  7097. if (sizeof(dma_addr_t) > 4)
  7098. mask = DMA_BIT_MASK(64);
  7099. else
  7100. mask = DMA_BIT_MASK(32);
  7101. rc = dma_set_mask_and_coherent(&ctrl_info->pci_dev->dev, mask);
  7102. if (rc) {
  7103. dev_err(&ctrl_info->pci_dev->dev, "failed to set DMA mask\n");
  7104. goto disable_device;
  7105. }
  7106. rc = pci_request_regions(ctrl_info->pci_dev, DRIVER_NAME_SHORT);
  7107. if (rc) {
  7108. dev_err(&ctrl_info->pci_dev->dev,
  7109. "failed to obtain PCI resources\n");
  7110. goto disable_device;
  7111. }
  7112. ctrl_info->iomem_base = ioremap(pci_resource_start(
  7113. ctrl_info->pci_dev, 0),
  7114. sizeof(struct pqi_ctrl_registers));
  7115. if (!ctrl_info->iomem_base) {
  7116. dev_err(&ctrl_info->pci_dev->dev,
  7117. "failed to map memory for controller registers\n");
  7118. rc = -ENOMEM;
  7119. goto release_regions;
  7120. }
  7121. #define PCI_EXP_COMP_TIMEOUT_65_TO_210_MS 0x6
  7122. /* Increase the PCIe completion timeout. */
  7123. rc = pqi_set_pcie_completion_timeout(ctrl_info->pci_dev,
  7124. PCI_EXP_COMP_TIMEOUT_65_TO_210_MS);
  7125. if (rc) {
  7126. dev_err(&ctrl_info->pci_dev->dev,
  7127. "failed to set PCIe completion timeout\n");
  7128. goto release_regions;
  7129. }
  7130. /* Enable bus mastering. */
  7131. pci_set_master(ctrl_info->pci_dev);
  7132. ctrl_info->registers = ctrl_info->iomem_base;
  7133. ctrl_info->pqi_registers = &ctrl_info->registers->pqi_registers;
  7134. pci_set_drvdata(ctrl_info->pci_dev, ctrl_info);
  7135. return 0;
  7136. release_regions:
  7137. pci_release_regions(ctrl_info->pci_dev);
  7138. disable_device:
  7139. pci_disable_device(ctrl_info->pci_dev);
  7140. return rc;
  7141. }
  7142. static void pqi_cleanup_pci_init(struct pqi_ctrl_info *ctrl_info)
  7143. {
  7144. iounmap(ctrl_info->iomem_base);
  7145. pci_release_regions(ctrl_info->pci_dev);
  7146. if (pci_is_enabled(ctrl_info->pci_dev))
  7147. pci_disable_device(ctrl_info->pci_dev);
  7148. pci_set_drvdata(ctrl_info->pci_dev, NULL);
  7149. }
  7150. static struct pqi_ctrl_info *pqi_alloc_ctrl_info(int numa_node)
  7151. {
  7152. struct pqi_ctrl_info *ctrl_info;
  7153. ctrl_info = kzalloc_node(sizeof(struct pqi_ctrl_info),
  7154. GFP_KERNEL, numa_node);
  7155. if (!ctrl_info)
  7156. return NULL;
  7157. mutex_init(&ctrl_info->scan_mutex);
  7158. mutex_init(&ctrl_info->lun_reset_mutex);
  7159. mutex_init(&ctrl_info->ofa_mutex);
  7160. INIT_LIST_HEAD(&ctrl_info->scsi_device_list);
  7161. spin_lock_init(&ctrl_info->scsi_device_list_lock);
  7162. INIT_WORK(&ctrl_info->event_work, pqi_event_worker);
  7163. atomic_set(&ctrl_info->num_interrupts, 0);
  7164. INIT_DELAYED_WORK(&ctrl_info->rescan_work, pqi_rescan_worker);
  7165. INIT_DELAYED_WORK(&ctrl_info->update_time_work, pqi_update_time_worker);
  7166. timer_setup(&ctrl_info->heartbeat_timer, pqi_heartbeat_timer_handler, 0);
  7167. INIT_WORK(&ctrl_info->ctrl_offline_work, pqi_ctrl_offline_worker);
  7168. INIT_WORK(&ctrl_info->ofa_memory_alloc_work, pqi_ofa_memory_alloc_worker);
  7169. INIT_WORK(&ctrl_info->ofa_quiesce_work, pqi_ofa_quiesce_worker);
  7170. sema_init(&ctrl_info->sync_request_sem,
  7171. PQI_RESERVED_IO_SLOTS_SYNCHRONOUS_REQUESTS);
  7172. init_waitqueue_head(&ctrl_info->block_requests_wait);
  7173. ctrl_info->ctrl_id = atomic_inc_return(&pqi_controller_count) - 1;
  7174. ctrl_info->irq_mode = IRQ_MODE_NONE;
  7175. ctrl_info->max_msix_vectors = PQI_MAX_MSIX_VECTORS;
  7176. ctrl_info->ciss_report_log_flags = CISS_REPORT_LOG_FLAG_UNIQUE_LUN_ID;
  7177. ctrl_info->max_transfer_encrypted_sas_sata =
  7178. PQI_DEFAULT_MAX_TRANSFER_ENCRYPTED_SAS_SATA;
  7179. ctrl_info->max_transfer_encrypted_nvme =
  7180. PQI_DEFAULT_MAX_TRANSFER_ENCRYPTED_NVME;
  7181. ctrl_info->max_write_raid_5_6 = PQI_DEFAULT_MAX_WRITE_RAID_5_6;
  7182. ctrl_info->max_write_raid_1_10_2drive = ~0;
  7183. ctrl_info->max_write_raid_1_10_3drive = ~0;
  7184. ctrl_info->disable_managed_interrupts = pqi_disable_managed_interrupts;
  7185. return ctrl_info;
  7186. }
  7187. static inline void pqi_free_ctrl_info(struct pqi_ctrl_info *ctrl_info)
  7188. {
  7189. kfree(ctrl_info);
  7190. }
  7191. static void pqi_free_interrupts(struct pqi_ctrl_info *ctrl_info)
  7192. {
  7193. pqi_free_irqs(ctrl_info);
  7194. pqi_disable_msix_interrupts(ctrl_info);
  7195. }
  7196. static void pqi_free_ctrl_resources(struct pqi_ctrl_info *ctrl_info)
  7197. {
  7198. pqi_free_interrupts(ctrl_info);
  7199. if (ctrl_info->queue_memory_base)
  7200. dma_free_coherent(&ctrl_info->pci_dev->dev,
  7201. ctrl_info->queue_memory_length,
  7202. ctrl_info->queue_memory_base,
  7203. ctrl_info->queue_memory_base_dma_handle);
  7204. if (ctrl_info->admin_queue_memory_base)
  7205. dma_free_coherent(&ctrl_info->pci_dev->dev,
  7206. ctrl_info->admin_queue_memory_length,
  7207. ctrl_info->admin_queue_memory_base,
  7208. ctrl_info->admin_queue_memory_base_dma_handle);
  7209. pqi_free_all_io_requests(ctrl_info);
  7210. if (ctrl_info->error_buffer)
  7211. dma_free_coherent(&ctrl_info->pci_dev->dev,
  7212. ctrl_info->error_buffer_length,
  7213. ctrl_info->error_buffer,
  7214. ctrl_info->error_buffer_dma_handle);
  7215. if (ctrl_info->iomem_base)
  7216. pqi_cleanup_pci_init(ctrl_info);
  7217. pqi_free_ctrl_info(ctrl_info);
  7218. }
  7219. static void pqi_remove_ctrl(struct pqi_ctrl_info *ctrl_info)
  7220. {
  7221. ctrl_info->controller_online = false;
  7222. pqi_stop_heartbeat_timer(ctrl_info);
  7223. pqi_ctrl_block_requests(ctrl_info);
  7224. pqi_cancel_rescan_worker(ctrl_info);
  7225. pqi_cancel_update_time_worker(ctrl_info);
  7226. if (ctrl_info->ctrl_removal_state == PQI_CTRL_SURPRISE_REMOVAL) {
  7227. pqi_fail_all_outstanding_requests(ctrl_info);
  7228. ctrl_info->pqi_mode_enabled = false;
  7229. }
  7230. pqi_unregister_scsi(ctrl_info);
  7231. if (ctrl_info->pqi_mode_enabled)
  7232. pqi_revert_to_sis_mode(ctrl_info);
  7233. pqi_free_ctrl_resources(ctrl_info);
  7234. }
  7235. static void pqi_ofa_ctrl_quiesce(struct pqi_ctrl_info *ctrl_info)
  7236. {
  7237. pqi_ctrl_block_scan(ctrl_info);
  7238. pqi_scsi_block_requests(ctrl_info);
  7239. pqi_ctrl_block_device_reset(ctrl_info);
  7240. pqi_ctrl_block_requests(ctrl_info);
  7241. pqi_ctrl_wait_until_quiesced(ctrl_info);
  7242. pqi_stop_heartbeat_timer(ctrl_info);
  7243. }
  7244. static void pqi_ofa_ctrl_unquiesce(struct pqi_ctrl_info *ctrl_info)
  7245. {
  7246. pqi_start_heartbeat_timer(ctrl_info);
  7247. pqi_ctrl_unblock_requests(ctrl_info);
  7248. pqi_ctrl_unblock_device_reset(ctrl_info);
  7249. pqi_scsi_unblock_requests(ctrl_info);
  7250. pqi_ctrl_unblock_scan(ctrl_info);
  7251. }
  7252. static int pqi_ofa_alloc_mem(struct pqi_ctrl_info *ctrl_info, u32 total_size, u32 chunk_size)
  7253. {
  7254. int i;
  7255. u32 sg_count;
  7256. struct device *dev;
  7257. struct pqi_ofa_memory *ofap;
  7258. struct pqi_sg_descriptor *mem_descriptor;
  7259. dma_addr_t dma_handle;
  7260. ofap = ctrl_info->pqi_ofa_mem_virt_addr;
  7261. sg_count = DIV_ROUND_UP(total_size, chunk_size);
  7262. if (sg_count == 0 || sg_count > PQI_OFA_MAX_SG_DESCRIPTORS)
  7263. goto out;
  7264. ctrl_info->pqi_ofa_chunk_virt_addr = kmalloc_array(sg_count, sizeof(void *), GFP_KERNEL);
  7265. if (!ctrl_info->pqi_ofa_chunk_virt_addr)
  7266. goto out;
  7267. dev = &ctrl_info->pci_dev->dev;
  7268. for (i = 0; i < sg_count; i++) {
  7269. ctrl_info->pqi_ofa_chunk_virt_addr[i] =
  7270. dma_alloc_coherent(dev, chunk_size, &dma_handle, GFP_KERNEL);
  7271. if (!ctrl_info->pqi_ofa_chunk_virt_addr[i])
  7272. goto out_free_chunks;
  7273. mem_descriptor = &ofap->sg_descriptor[i];
  7274. put_unaligned_le64((u64)dma_handle, &mem_descriptor->address);
  7275. put_unaligned_le32(chunk_size, &mem_descriptor->length);
  7276. }
  7277. put_unaligned_le32(CISS_SG_LAST, &mem_descriptor->flags);
  7278. put_unaligned_le16(sg_count, &ofap->num_memory_descriptors);
  7279. put_unaligned_le32(sg_count * chunk_size, &ofap->bytes_allocated);
  7280. return 0;
  7281. out_free_chunks:
  7282. while (--i >= 0) {
  7283. mem_descriptor = &ofap->sg_descriptor[i];
  7284. dma_free_coherent(dev, chunk_size,
  7285. ctrl_info->pqi_ofa_chunk_virt_addr[i],
  7286. get_unaligned_le64(&mem_descriptor->address));
  7287. }
  7288. kfree(ctrl_info->pqi_ofa_chunk_virt_addr);
  7289. out:
  7290. return -ENOMEM;
  7291. }
  7292. static int pqi_ofa_alloc_host_buffer(struct pqi_ctrl_info *ctrl_info)
  7293. {
  7294. u32 total_size;
  7295. u32 chunk_size;
  7296. u32 min_chunk_size;
  7297. if (ctrl_info->ofa_bytes_requested == 0)
  7298. return 0;
  7299. total_size = PAGE_ALIGN(ctrl_info->ofa_bytes_requested);
  7300. min_chunk_size = DIV_ROUND_UP(total_size, PQI_OFA_MAX_SG_DESCRIPTORS);
  7301. min_chunk_size = PAGE_ALIGN(min_chunk_size);
  7302. for (chunk_size = total_size; chunk_size >= min_chunk_size;) {
  7303. if (pqi_ofa_alloc_mem(ctrl_info, total_size, chunk_size) == 0)
  7304. return 0;
  7305. chunk_size /= 2;
  7306. chunk_size = PAGE_ALIGN(chunk_size);
  7307. }
  7308. return -ENOMEM;
  7309. }
  7310. static void pqi_ofa_setup_host_buffer(struct pqi_ctrl_info *ctrl_info)
  7311. {
  7312. struct device *dev;
  7313. struct pqi_ofa_memory *ofap;
  7314. dev = &ctrl_info->pci_dev->dev;
  7315. ofap = dma_alloc_coherent(dev, sizeof(*ofap),
  7316. &ctrl_info->pqi_ofa_mem_dma_handle, GFP_KERNEL);
  7317. if (!ofap)
  7318. return;
  7319. ctrl_info->pqi_ofa_mem_virt_addr = ofap;
  7320. if (pqi_ofa_alloc_host_buffer(ctrl_info) < 0) {
  7321. dev_err(dev,
  7322. "failed to allocate host buffer for Online Firmware Activation\n");
  7323. dma_free_coherent(dev, sizeof(*ofap), ofap, ctrl_info->pqi_ofa_mem_dma_handle);
  7324. ctrl_info->pqi_ofa_mem_virt_addr = NULL;
  7325. return;
  7326. }
  7327. put_unaligned_le16(PQI_OFA_VERSION, &ofap->version);
  7328. memcpy(&ofap->signature, PQI_OFA_SIGNATURE, sizeof(ofap->signature));
  7329. }
  7330. static void pqi_ofa_free_host_buffer(struct pqi_ctrl_info *ctrl_info)
  7331. {
  7332. unsigned int i;
  7333. struct device *dev;
  7334. struct pqi_ofa_memory *ofap;
  7335. struct pqi_sg_descriptor *mem_descriptor;
  7336. unsigned int num_memory_descriptors;
  7337. ofap = ctrl_info->pqi_ofa_mem_virt_addr;
  7338. if (!ofap)
  7339. return;
  7340. dev = &ctrl_info->pci_dev->dev;
  7341. if (get_unaligned_le32(&ofap->bytes_allocated) == 0)
  7342. goto out;
  7343. mem_descriptor = ofap->sg_descriptor;
  7344. num_memory_descriptors =
  7345. get_unaligned_le16(&ofap->num_memory_descriptors);
  7346. for (i = 0; i < num_memory_descriptors; i++) {
  7347. dma_free_coherent(dev,
  7348. get_unaligned_le32(&mem_descriptor[i].length),
  7349. ctrl_info->pqi_ofa_chunk_virt_addr[i],
  7350. get_unaligned_le64(&mem_descriptor[i].address));
  7351. }
  7352. kfree(ctrl_info->pqi_ofa_chunk_virt_addr);
  7353. out:
  7354. dma_free_coherent(dev, sizeof(*ofap), ofap,
  7355. ctrl_info->pqi_ofa_mem_dma_handle);
  7356. ctrl_info->pqi_ofa_mem_virt_addr = NULL;
  7357. }
  7358. static int pqi_ofa_host_memory_update(struct pqi_ctrl_info *ctrl_info)
  7359. {
  7360. u32 buffer_length;
  7361. struct pqi_vendor_general_request request;
  7362. struct pqi_ofa_memory *ofap;
  7363. memset(&request, 0, sizeof(request));
  7364. request.header.iu_type = PQI_REQUEST_IU_VENDOR_GENERAL;
  7365. put_unaligned_le16(sizeof(request) - PQI_REQUEST_HEADER_LENGTH,
  7366. &request.header.iu_length);
  7367. put_unaligned_le16(PQI_VENDOR_GENERAL_HOST_MEMORY_UPDATE,
  7368. &request.function_code);
  7369. ofap = ctrl_info->pqi_ofa_mem_virt_addr;
  7370. if (ofap) {
  7371. buffer_length = offsetof(struct pqi_ofa_memory, sg_descriptor) +
  7372. get_unaligned_le16(&ofap->num_memory_descriptors) *
  7373. sizeof(struct pqi_sg_descriptor);
  7374. put_unaligned_le64((u64)ctrl_info->pqi_ofa_mem_dma_handle,
  7375. &request.data.ofa_memory_allocation.buffer_address);
  7376. put_unaligned_le32(buffer_length,
  7377. &request.data.ofa_memory_allocation.buffer_length);
  7378. }
  7379. return pqi_submit_raid_request_synchronous(ctrl_info, &request.header, 0, NULL);
  7380. }
  7381. static int pqi_ofa_ctrl_restart(struct pqi_ctrl_info *ctrl_info, unsigned int delay_secs)
  7382. {
  7383. ssleep(delay_secs);
  7384. return pqi_ctrl_init_resume(ctrl_info);
  7385. }
  7386. static struct pqi_raid_error_info pqi_ctrl_offline_raid_error_info = {
  7387. .data_out_result = PQI_DATA_IN_OUT_HARDWARE_ERROR,
  7388. .status = SAM_STAT_CHECK_CONDITION,
  7389. };
  7390. static void pqi_fail_all_outstanding_requests(struct pqi_ctrl_info *ctrl_info)
  7391. {
  7392. unsigned int i;
  7393. struct pqi_io_request *io_request;
  7394. struct scsi_cmnd *scmd;
  7395. struct scsi_device *sdev;
  7396. for (i = 0; i < ctrl_info->max_io_slots; i++) {
  7397. io_request = &ctrl_info->io_request_pool[i];
  7398. if (atomic_read(&io_request->refcount) == 0)
  7399. continue;
  7400. scmd = io_request->scmd;
  7401. if (scmd) {
  7402. sdev = scmd->device;
  7403. if (!sdev || !scsi_device_online(sdev)) {
  7404. pqi_free_io_request(io_request);
  7405. continue;
  7406. } else {
  7407. set_host_byte(scmd, DID_NO_CONNECT);
  7408. }
  7409. } else {
  7410. io_request->status = -ENXIO;
  7411. io_request->error_info =
  7412. &pqi_ctrl_offline_raid_error_info;
  7413. }
  7414. io_request->io_complete_callback(io_request,
  7415. io_request->context);
  7416. }
  7417. }
  7418. static void pqi_take_ctrl_offline_deferred(struct pqi_ctrl_info *ctrl_info)
  7419. {
  7420. pqi_perform_lockup_action();
  7421. pqi_stop_heartbeat_timer(ctrl_info);
  7422. pqi_free_interrupts(ctrl_info);
  7423. pqi_cancel_rescan_worker(ctrl_info);
  7424. pqi_cancel_update_time_worker(ctrl_info);
  7425. pqi_ctrl_wait_until_quiesced(ctrl_info);
  7426. pqi_fail_all_outstanding_requests(ctrl_info);
  7427. pqi_ctrl_unblock_requests(ctrl_info);
  7428. }
  7429. static void pqi_ctrl_offline_worker(struct work_struct *work)
  7430. {
  7431. struct pqi_ctrl_info *ctrl_info;
  7432. ctrl_info = container_of(work, struct pqi_ctrl_info, ctrl_offline_work);
  7433. pqi_take_ctrl_offline_deferred(ctrl_info);
  7434. }
  7435. static void pqi_take_ctrl_offline(struct pqi_ctrl_info *ctrl_info,
  7436. enum pqi_ctrl_shutdown_reason ctrl_shutdown_reason)
  7437. {
  7438. if (!ctrl_info->controller_online)
  7439. return;
  7440. ctrl_info->controller_online = false;
  7441. ctrl_info->pqi_mode_enabled = false;
  7442. pqi_ctrl_block_requests(ctrl_info);
  7443. if (!pqi_disable_ctrl_shutdown)
  7444. sis_shutdown_ctrl(ctrl_info, ctrl_shutdown_reason);
  7445. pci_disable_device(ctrl_info->pci_dev);
  7446. dev_err(&ctrl_info->pci_dev->dev, "controller offline\n");
  7447. schedule_work(&ctrl_info->ctrl_offline_work);
  7448. }
  7449. static void pqi_print_ctrl_info(struct pci_dev *pci_dev,
  7450. const struct pci_device_id *id)
  7451. {
  7452. char *ctrl_description;
  7453. if (id->driver_data)
  7454. ctrl_description = (char *)id->driver_data;
  7455. else
  7456. ctrl_description = "Microchip Smart Family Controller";
  7457. dev_info(&pci_dev->dev, "%s found\n", ctrl_description);
  7458. }
  7459. static int pqi_pci_probe(struct pci_dev *pci_dev,
  7460. const struct pci_device_id *id)
  7461. {
  7462. int rc;
  7463. int node;
  7464. struct pqi_ctrl_info *ctrl_info;
  7465. pqi_print_ctrl_info(pci_dev, id);
  7466. if (pqi_disable_device_id_wildcards &&
  7467. id->subvendor == PCI_ANY_ID &&
  7468. id->subdevice == PCI_ANY_ID) {
  7469. dev_warn(&pci_dev->dev,
  7470. "controller not probed because device ID wildcards are disabled\n");
  7471. return -ENODEV;
  7472. }
  7473. if (id->subvendor == PCI_ANY_ID || id->subdevice == PCI_ANY_ID)
  7474. dev_warn(&pci_dev->dev,
  7475. "controller device ID matched using wildcards\n");
  7476. node = dev_to_node(&pci_dev->dev);
  7477. if (node == NUMA_NO_NODE) {
  7478. node = cpu_to_node(0);
  7479. if (node == NUMA_NO_NODE)
  7480. node = 0;
  7481. set_dev_node(&pci_dev->dev, node);
  7482. }
  7483. ctrl_info = pqi_alloc_ctrl_info(node);
  7484. if (!ctrl_info) {
  7485. dev_err(&pci_dev->dev,
  7486. "failed to allocate controller info block\n");
  7487. return -ENOMEM;
  7488. }
  7489. ctrl_info->pci_dev = pci_dev;
  7490. rc = pqi_pci_init(ctrl_info);
  7491. if (rc)
  7492. goto error;
  7493. rc = pqi_ctrl_init(ctrl_info);
  7494. if (rc)
  7495. goto error;
  7496. return 0;
  7497. error:
  7498. pqi_remove_ctrl(ctrl_info);
  7499. return rc;
  7500. }
  7501. static void pqi_pci_remove(struct pci_dev *pci_dev)
  7502. {
  7503. struct pqi_ctrl_info *ctrl_info;
  7504. u16 vendor_id;
  7505. ctrl_info = pci_get_drvdata(pci_dev);
  7506. if (!ctrl_info)
  7507. return;
  7508. pci_read_config_word(ctrl_info->pci_dev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
  7509. if (vendor_id == 0xffff)
  7510. ctrl_info->ctrl_removal_state = PQI_CTRL_SURPRISE_REMOVAL;
  7511. else
  7512. ctrl_info->ctrl_removal_state = PQI_CTRL_GRACEFUL_REMOVAL;
  7513. pqi_remove_ctrl(ctrl_info);
  7514. }
  7515. static void pqi_crash_if_pending_command(struct pqi_ctrl_info *ctrl_info)
  7516. {
  7517. unsigned int i;
  7518. struct pqi_io_request *io_request;
  7519. struct scsi_cmnd *scmd;
  7520. for (i = 0; i < ctrl_info->max_io_slots; i++) {
  7521. io_request = &ctrl_info->io_request_pool[i];
  7522. if (atomic_read(&io_request->refcount) == 0)
  7523. continue;
  7524. scmd = io_request->scmd;
  7525. WARN_ON(scmd != NULL); /* IO command from SML */
  7526. WARN_ON(scmd == NULL); /* Non-IO cmd or driver initiated*/
  7527. }
  7528. }
  7529. static void pqi_shutdown(struct pci_dev *pci_dev)
  7530. {
  7531. int rc;
  7532. struct pqi_ctrl_info *ctrl_info;
  7533. enum bmic_flush_cache_shutdown_event shutdown_event;
  7534. ctrl_info = pci_get_drvdata(pci_dev);
  7535. if (!ctrl_info) {
  7536. dev_err(&pci_dev->dev,
  7537. "cache could not be flushed\n");
  7538. return;
  7539. }
  7540. pqi_wait_until_ofa_finished(ctrl_info);
  7541. pqi_scsi_block_requests(ctrl_info);
  7542. pqi_ctrl_block_device_reset(ctrl_info);
  7543. pqi_ctrl_block_requests(ctrl_info);
  7544. pqi_ctrl_wait_until_quiesced(ctrl_info);
  7545. if (system_state == SYSTEM_RESTART)
  7546. shutdown_event = RESTART;
  7547. else
  7548. shutdown_event = SHUTDOWN;
  7549. /*
  7550. * Write all data in the controller's battery-backed cache to
  7551. * storage.
  7552. */
  7553. rc = pqi_flush_cache(ctrl_info, shutdown_event);
  7554. if (rc)
  7555. dev_err(&pci_dev->dev,
  7556. "unable to flush controller cache\n");
  7557. pqi_crash_if_pending_command(ctrl_info);
  7558. pqi_reset(ctrl_info);
  7559. }
  7560. static void pqi_process_lockup_action_param(void)
  7561. {
  7562. unsigned int i;
  7563. if (!pqi_lockup_action_param)
  7564. return;
  7565. for (i = 0; i < ARRAY_SIZE(pqi_lockup_actions); i++) {
  7566. if (strcmp(pqi_lockup_action_param,
  7567. pqi_lockup_actions[i].name) == 0) {
  7568. pqi_lockup_action = pqi_lockup_actions[i].action;
  7569. return;
  7570. }
  7571. }
  7572. pr_warn("%s: invalid lockup action setting \"%s\" - supported settings: none, reboot, panic\n",
  7573. DRIVER_NAME_SHORT, pqi_lockup_action_param);
  7574. }
  7575. #define PQI_CTRL_READY_TIMEOUT_PARAM_MIN_SECS 30
  7576. #define PQI_CTRL_READY_TIMEOUT_PARAM_MAX_SECS (30 * 60)
  7577. static void pqi_process_ctrl_ready_timeout_param(void)
  7578. {
  7579. if (pqi_ctrl_ready_timeout_secs == 0)
  7580. return;
  7581. if (pqi_ctrl_ready_timeout_secs < PQI_CTRL_READY_TIMEOUT_PARAM_MIN_SECS) {
  7582. pr_warn("%s: ctrl_ready_timeout parm of %u second(s) is less than minimum timeout of %d seconds - setting timeout to %d seconds\n",
  7583. DRIVER_NAME_SHORT, pqi_ctrl_ready_timeout_secs, PQI_CTRL_READY_TIMEOUT_PARAM_MIN_SECS, PQI_CTRL_READY_TIMEOUT_PARAM_MIN_SECS);
  7584. pqi_ctrl_ready_timeout_secs = PQI_CTRL_READY_TIMEOUT_PARAM_MIN_SECS;
  7585. } else if (pqi_ctrl_ready_timeout_secs > PQI_CTRL_READY_TIMEOUT_PARAM_MAX_SECS) {
  7586. pr_warn("%s: ctrl_ready_timeout parm of %u seconds is greater than maximum timeout of %d seconds - setting timeout to %d seconds\n",
  7587. DRIVER_NAME_SHORT, pqi_ctrl_ready_timeout_secs, PQI_CTRL_READY_TIMEOUT_PARAM_MAX_SECS, PQI_CTRL_READY_TIMEOUT_PARAM_MAX_SECS);
  7588. pqi_ctrl_ready_timeout_secs = PQI_CTRL_READY_TIMEOUT_PARAM_MAX_SECS;
  7589. }
  7590. sis_ctrl_ready_timeout_secs = pqi_ctrl_ready_timeout_secs;
  7591. }
  7592. static void pqi_process_module_params(void)
  7593. {
  7594. pqi_process_lockup_action_param();
  7595. pqi_process_ctrl_ready_timeout_param();
  7596. }
  7597. #if defined(CONFIG_PM)
  7598. static inline enum bmic_flush_cache_shutdown_event pqi_get_flush_cache_shutdown_event(struct pci_dev *pci_dev)
  7599. {
  7600. if (pci_dev->subsystem_vendor == PCI_VENDOR_ID_ADAPTEC2 && pci_dev->subsystem_device == 0x1304)
  7601. return RESTART;
  7602. return SUSPEND;
  7603. }
  7604. static int pqi_suspend_or_freeze(struct device *dev, bool suspend)
  7605. {
  7606. struct pci_dev *pci_dev;
  7607. struct pqi_ctrl_info *ctrl_info;
  7608. pci_dev = to_pci_dev(dev);
  7609. ctrl_info = pci_get_drvdata(pci_dev);
  7610. pqi_wait_until_ofa_finished(ctrl_info);
  7611. pqi_ctrl_block_scan(ctrl_info);
  7612. pqi_scsi_block_requests(ctrl_info);
  7613. pqi_ctrl_block_device_reset(ctrl_info);
  7614. pqi_ctrl_block_requests(ctrl_info);
  7615. pqi_ctrl_wait_until_quiesced(ctrl_info);
  7616. if (suspend) {
  7617. enum bmic_flush_cache_shutdown_event shutdown_event;
  7618. shutdown_event = pqi_get_flush_cache_shutdown_event(pci_dev);
  7619. pqi_flush_cache(ctrl_info, shutdown_event);
  7620. }
  7621. pqi_stop_heartbeat_timer(ctrl_info);
  7622. pqi_crash_if_pending_command(ctrl_info);
  7623. pqi_free_irqs(ctrl_info);
  7624. ctrl_info->controller_online = false;
  7625. ctrl_info->pqi_mode_enabled = false;
  7626. return 0;
  7627. }
  7628. static __maybe_unused int pqi_suspend(struct device *dev)
  7629. {
  7630. return pqi_suspend_or_freeze(dev, true);
  7631. }
  7632. static int pqi_resume_or_restore(struct device *dev)
  7633. {
  7634. int rc;
  7635. struct pci_dev *pci_dev;
  7636. struct pqi_ctrl_info *ctrl_info;
  7637. pci_dev = to_pci_dev(dev);
  7638. ctrl_info = pci_get_drvdata(pci_dev);
  7639. rc = pqi_request_irqs(ctrl_info);
  7640. if (rc)
  7641. return rc;
  7642. pqi_ctrl_unblock_device_reset(ctrl_info);
  7643. pqi_ctrl_unblock_requests(ctrl_info);
  7644. pqi_scsi_unblock_requests(ctrl_info);
  7645. pqi_ctrl_unblock_scan(ctrl_info);
  7646. ssleep(PQI_POST_RESET_DELAY_SECS);
  7647. return pqi_ctrl_init_resume(ctrl_info);
  7648. }
  7649. static int pqi_freeze(struct device *dev)
  7650. {
  7651. return pqi_suspend_or_freeze(dev, false);
  7652. }
  7653. static int pqi_thaw(struct device *dev)
  7654. {
  7655. int rc;
  7656. struct pci_dev *pci_dev;
  7657. struct pqi_ctrl_info *ctrl_info;
  7658. pci_dev = to_pci_dev(dev);
  7659. ctrl_info = pci_get_drvdata(pci_dev);
  7660. rc = pqi_request_irqs(ctrl_info);
  7661. if (rc)
  7662. return rc;
  7663. ctrl_info->controller_online = true;
  7664. ctrl_info->pqi_mode_enabled = true;
  7665. pqi_ctrl_unblock_device_reset(ctrl_info);
  7666. pqi_ctrl_unblock_requests(ctrl_info);
  7667. pqi_scsi_unblock_requests(ctrl_info);
  7668. pqi_ctrl_unblock_scan(ctrl_info);
  7669. return 0;
  7670. }
  7671. static int pqi_poweroff(struct device *dev)
  7672. {
  7673. struct pci_dev *pci_dev;
  7674. struct pqi_ctrl_info *ctrl_info;
  7675. enum bmic_flush_cache_shutdown_event shutdown_event;
  7676. pci_dev = to_pci_dev(dev);
  7677. ctrl_info = pci_get_drvdata(pci_dev);
  7678. shutdown_event = pqi_get_flush_cache_shutdown_event(pci_dev);
  7679. pqi_flush_cache(ctrl_info, shutdown_event);
  7680. return 0;
  7681. }
  7682. static const struct dev_pm_ops pqi_pm_ops = {
  7683. .suspend = pqi_suspend,
  7684. .resume = pqi_resume_or_restore,
  7685. .freeze = pqi_freeze,
  7686. .thaw = pqi_thaw,
  7687. .poweroff = pqi_poweroff,
  7688. .restore = pqi_resume_or_restore,
  7689. };
  7690. #endif /* CONFIG_PM */
  7691. /* Define the PCI IDs for the controllers that we support. */
  7692. static const struct pci_device_id pqi_pci_id_table[] = {
  7693. {
  7694. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7695. 0x105b, 0x1211)
  7696. },
  7697. {
  7698. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7699. 0x105b, 0x1321)
  7700. },
  7701. {
  7702. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7703. 0x152d, 0x8a22)
  7704. },
  7705. {
  7706. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7707. 0x152d, 0x8a23)
  7708. },
  7709. {
  7710. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7711. 0x152d, 0x8a24)
  7712. },
  7713. {
  7714. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7715. 0x152d, 0x8a36)
  7716. },
  7717. {
  7718. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7719. 0x152d, 0x8a37)
  7720. },
  7721. {
  7722. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7723. 0x193d, 0x1104)
  7724. },
  7725. {
  7726. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7727. 0x193d, 0x1105)
  7728. },
  7729. {
  7730. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7731. 0x193d, 0x1106)
  7732. },
  7733. {
  7734. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7735. 0x193d, 0x1107)
  7736. },
  7737. {
  7738. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7739. 0x193d, 0x1108)
  7740. },
  7741. {
  7742. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7743. 0x193d, 0x1109)
  7744. },
  7745. {
  7746. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7747. 0x193d, 0x110b)
  7748. },
  7749. {
  7750. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7751. 0x193d, 0x8460)
  7752. },
  7753. {
  7754. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7755. 0x193d, 0x8461)
  7756. },
  7757. {
  7758. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7759. 0x193d, 0xc460)
  7760. },
  7761. {
  7762. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7763. 0x193d, 0xc461)
  7764. },
  7765. {
  7766. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7767. 0x193d, 0xf460)
  7768. },
  7769. {
  7770. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7771. 0x193d, 0xf461)
  7772. },
  7773. {
  7774. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7775. 0x1bd4, 0x0045)
  7776. },
  7777. {
  7778. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7779. 0x1bd4, 0x0046)
  7780. },
  7781. {
  7782. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7783. 0x1bd4, 0x0047)
  7784. },
  7785. {
  7786. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7787. 0x1bd4, 0x0048)
  7788. },
  7789. {
  7790. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7791. 0x1bd4, 0x004a)
  7792. },
  7793. {
  7794. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7795. 0x1bd4, 0x004b)
  7796. },
  7797. {
  7798. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7799. 0x1bd4, 0x004c)
  7800. },
  7801. {
  7802. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7803. 0x1bd4, 0x004f)
  7804. },
  7805. {
  7806. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7807. 0x1bd4, 0x0051)
  7808. },
  7809. {
  7810. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7811. 0x1bd4, 0x0052)
  7812. },
  7813. {
  7814. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7815. 0x1bd4, 0x0053)
  7816. },
  7817. {
  7818. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7819. 0x1bd4, 0x0054)
  7820. },
  7821. {
  7822. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7823. 0x1bd4, 0x006b)
  7824. },
  7825. {
  7826. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7827. 0x1bd4, 0x006c)
  7828. },
  7829. {
  7830. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7831. 0x1bd4, 0x006d)
  7832. },
  7833. {
  7834. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7835. 0x1bd4, 0x006f)
  7836. },
  7837. {
  7838. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7839. 0x1bd4, 0x0070)
  7840. },
  7841. {
  7842. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7843. 0x1bd4, 0x0071)
  7844. },
  7845. {
  7846. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7847. 0x1bd4, 0x0072)
  7848. },
  7849. {
  7850. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7851. 0x1bd4, 0x0086)
  7852. },
  7853. {
  7854. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7855. 0x1bd4, 0x0087)
  7856. },
  7857. {
  7858. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7859. 0x1bd4, 0x0088)
  7860. },
  7861. {
  7862. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7863. 0x1bd4, 0x0089)
  7864. },
  7865. {
  7866. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7867. 0x19e5, 0xd227)
  7868. },
  7869. {
  7870. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7871. 0x19e5, 0xd228)
  7872. },
  7873. {
  7874. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7875. 0x19e5, 0xd229)
  7876. },
  7877. {
  7878. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7879. 0x19e5, 0xd22a)
  7880. },
  7881. {
  7882. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7883. 0x19e5, 0xd22b)
  7884. },
  7885. {
  7886. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7887. 0x19e5, 0xd22c)
  7888. },
  7889. {
  7890. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7891. PCI_VENDOR_ID_ADAPTEC2, 0x0110)
  7892. },
  7893. {
  7894. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7895. PCI_VENDOR_ID_ADAPTEC2, 0x0608)
  7896. },
  7897. {
  7898. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7899. PCI_VENDOR_ID_ADAPTEC2, 0x0659)
  7900. },
  7901. {
  7902. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7903. PCI_VENDOR_ID_ADAPTEC2, 0x0800)
  7904. },
  7905. {
  7906. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7907. PCI_VENDOR_ID_ADAPTEC2, 0x0801)
  7908. },
  7909. {
  7910. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7911. PCI_VENDOR_ID_ADAPTEC2, 0x0802)
  7912. },
  7913. {
  7914. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7915. PCI_VENDOR_ID_ADAPTEC2, 0x0803)
  7916. },
  7917. {
  7918. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7919. PCI_VENDOR_ID_ADAPTEC2, 0x0804)
  7920. },
  7921. {
  7922. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7923. PCI_VENDOR_ID_ADAPTEC2, 0x0805)
  7924. },
  7925. {
  7926. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7927. PCI_VENDOR_ID_ADAPTEC2, 0x0806)
  7928. },
  7929. {
  7930. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7931. PCI_VENDOR_ID_ADAPTEC2, 0x0807)
  7932. },
  7933. {
  7934. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7935. PCI_VENDOR_ID_ADAPTEC2, 0x0808)
  7936. },
  7937. {
  7938. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7939. PCI_VENDOR_ID_ADAPTEC2, 0x0809)
  7940. },
  7941. {
  7942. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7943. PCI_VENDOR_ID_ADAPTEC2, 0x080a)
  7944. },
  7945. {
  7946. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7947. PCI_VENDOR_ID_ADAPTEC2, 0x0900)
  7948. },
  7949. {
  7950. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7951. PCI_VENDOR_ID_ADAPTEC2, 0x0901)
  7952. },
  7953. {
  7954. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7955. PCI_VENDOR_ID_ADAPTEC2, 0x0902)
  7956. },
  7957. {
  7958. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7959. PCI_VENDOR_ID_ADAPTEC2, 0x0903)
  7960. },
  7961. {
  7962. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7963. PCI_VENDOR_ID_ADAPTEC2, 0x0904)
  7964. },
  7965. {
  7966. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7967. PCI_VENDOR_ID_ADAPTEC2, 0x0905)
  7968. },
  7969. {
  7970. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7971. PCI_VENDOR_ID_ADAPTEC2, 0x0906)
  7972. },
  7973. {
  7974. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7975. PCI_VENDOR_ID_ADAPTEC2, 0x0907)
  7976. },
  7977. {
  7978. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7979. PCI_VENDOR_ID_ADAPTEC2, 0x0908)
  7980. },
  7981. {
  7982. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7983. PCI_VENDOR_ID_ADAPTEC2, 0x090a)
  7984. },
  7985. {
  7986. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7987. PCI_VENDOR_ID_ADAPTEC2, 0x1200)
  7988. },
  7989. {
  7990. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7991. PCI_VENDOR_ID_ADAPTEC2, 0x1201)
  7992. },
  7993. {
  7994. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7995. PCI_VENDOR_ID_ADAPTEC2, 0x1202)
  7996. },
  7997. {
  7998. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  7999. PCI_VENDOR_ID_ADAPTEC2, 0x1280)
  8000. },
  8001. {
  8002. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8003. PCI_VENDOR_ID_ADAPTEC2, 0x1281)
  8004. },
  8005. {
  8006. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8007. PCI_VENDOR_ID_ADAPTEC2, 0x1282)
  8008. },
  8009. {
  8010. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8011. PCI_VENDOR_ID_ADAPTEC2, 0x1300)
  8012. },
  8013. {
  8014. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8015. PCI_VENDOR_ID_ADAPTEC2, 0x1301)
  8016. },
  8017. {
  8018. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8019. PCI_VENDOR_ID_ADAPTEC2, 0x1302)
  8020. },
  8021. {
  8022. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8023. PCI_VENDOR_ID_ADAPTEC2, 0x1303)
  8024. },
  8025. {
  8026. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8027. PCI_VENDOR_ID_ADAPTEC2, 0x1304)
  8028. },
  8029. {
  8030. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8031. PCI_VENDOR_ID_ADAPTEC2, 0x1380)
  8032. },
  8033. {
  8034. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8035. PCI_VENDOR_ID_ADAPTEC2, 0x1400)
  8036. },
  8037. {
  8038. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8039. PCI_VENDOR_ID_ADAPTEC2, 0x1402)
  8040. },
  8041. {
  8042. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8043. PCI_VENDOR_ID_ADAPTEC2, 0x1410)
  8044. },
  8045. {
  8046. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8047. PCI_VENDOR_ID_ADAPTEC2, 0x1411)
  8048. },
  8049. {
  8050. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8051. PCI_VENDOR_ID_ADAPTEC2, 0x1412)
  8052. },
  8053. {
  8054. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8055. PCI_VENDOR_ID_ADAPTEC2, 0x1420)
  8056. },
  8057. {
  8058. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8059. PCI_VENDOR_ID_ADAPTEC2, 0x1430)
  8060. },
  8061. {
  8062. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8063. PCI_VENDOR_ID_ADAPTEC2, 0x1440)
  8064. },
  8065. {
  8066. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8067. PCI_VENDOR_ID_ADAPTEC2, 0x1441)
  8068. },
  8069. {
  8070. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8071. PCI_VENDOR_ID_ADAPTEC2, 0x1450)
  8072. },
  8073. {
  8074. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8075. PCI_VENDOR_ID_ADAPTEC2, 0x1452)
  8076. },
  8077. {
  8078. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8079. PCI_VENDOR_ID_ADAPTEC2, 0x1460)
  8080. },
  8081. {
  8082. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8083. PCI_VENDOR_ID_ADAPTEC2, 0x1461)
  8084. },
  8085. {
  8086. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8087. PCI_VENDOR_ID_ADAPTEC2, 0x1462)
  8088. },
  8089. {
  8090. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8091. PCI_VENDOR_ID_ADAPTEC2, 0x1463)
  8092. },
  8093. {
  8094. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8095. PCI_VENDOR_ID_ADAPTEC2, 0x1470)
  8096. },
  8097. {
  8098. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8099. PCI_VENDOR_ID_ADAPTEC2, 0x1471)
  8100. },
  8101. {
  8102. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8103. PCI_VENDOR_ID_ADAPTEC2, 0x1472)
  8104. },
  8105. {
  8106. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8107. PCI_VENDOR_ID_ADAPTEC2, 0x1473)
  8108. },
  8109. {
  8110. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8111. PCI_VENDOR_ID_ADAPTEC2, 0x1474)
  8112. },
  8113. {
  8114. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8115. PCI_VENDOR_ID_ADAPTEC2, 0x1475)
  8116. },
  8117. {
  8118. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8119. PCI_VENDOR_ID_ADAPTEC2, 0x1480)
  8120. },
  8121. {
  8122. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8123. PCI_VENDOR_ID_ADAPTEC2, 0x1490)
  8124. },
  8125. {
  8126. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8127. PCI_VENDOR_ID_ADAPTEC2, 0x1491)
  8128. },
  8129. {
  8130. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8131. PCI_VENDOR_ID_ADAPTEC2, 0x14a0)
  8132. },
  8133. {
  8134. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8135. PCI_VENDOR_ID_ADAPTEC2, 0x14a1)
  8136. },
  8137. {
  8138. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8139. PCI_VENDOR_ID_ADAPTEC2, 0x14a2)
  8140. },
  8141. {
  8142. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8143. PCI_VENDOR_ID_ADAPTEC2, 0x14a4)
  8144. },
  8145. {
  8146. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8147. PCI_VENDOR_ID_ADAPTEC2, 0x14a5)
  8148. },
  8149. {
  8150. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8151. PCI_VENDOR_ID_ADAPTEC2, 0x14a6)
  8152. },
  8153. {
  8154. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8155. PCI_VENDOR_ID_ADAPTEC2, 0x14b0)
  8156. },
  8157. {
  8158. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8159. PCI_VENDOR_ID_ADAPTEC2, 0x14b1)
  8160. },
  8161. {
  8162. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8163. PCI_VENDOR_ID_ADAPTEC2, 0x14c0)
  8164. },
  8165. {
  8166. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8167. PCI_VENDOR_ID_ADAPTEC2, 0x14c1)
  8168. },
  8169. {
  8170. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8171. PCI_VENDOR_ID_ADAPTEC2, 0x14c2)
  8172. },
  8173. {
  8174. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8175. PCI_VENDOR_ID_ADAPTEC2, 0x14c3)
  8176. },
  8177. {
  8178. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8179. PCI_VENDOR_ID_ADAPTEC2, 0x14c4)
  8180. },
  8181. {
  8182. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8183. PCI_VENDOR_ID_ADAPTEC2, 0x14d0)
  8184. },
  8185. {
  8186. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8187. PCI_VENDOR_ID_ADAPTEC2, 0x14e0)
  8188. },
  8189. {
  8190. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8191. PCI_VENDOR_ID_ADAPTEC2, 0x14f0)
  8192. },
  8193. {
  8194. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8195. PCI_VENDOR_ID_ADVANTECH, 0x8312)
  8196. },
  8197. {
  8198. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8199. PCI_VENDOR_ID_DELL, 0x1fe0)
  8200. },
  8201. {
  8202. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8203. PCI_VENDOR_ID_HP, 0x0600)
  8204. },
  8205. {
  8206. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8207. PCI_VENDOR_ID_HP, 0x0601)
  8208. },
  8209. {
  8210. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8211. PCI_VENDOR_ID_HP, 0x0602)
  8212. },
  8213. {
  8214. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8215. PCI_VENDOR_ID_HP, 0x0603)
  8216. },
  8217. {
  8218. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8219. PCI_VENDOR_ID_HP, 0x0609)
  8220. },
  8221. {
  8222. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8223. PCI_VENDOR_ID_HP, 0x0650)
  8224. },
  8225. {
  8226. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8227. PCI_VENDOR_ID_HP, 0x0651)
  8228. },
  8229. {
  8230. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8231. PCI_VENDOR_ID_HP, 0x0652)
  8232. },
  8233. {
  8234. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8235. PCI_VENDOR_ID_HP, 0x0653)
  8236. },
  8237. {
  8238. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8239. PCI_VENDOR_ID_HP, 0x0654)
  8240. },
  8241. {
  8242. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8243. PCI_VENDOR_ID_HP, 0x0655)
  8244. },
  8245. {
  8246. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8247. PCI_VENDOR_ID_HP, 0x0700)
  8248. },
  8249. {
  8250. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8251. PCI_VENDOR_ID_HP, 0x0701)
  8252. },
  8253. {
  8254. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8255. PCI_VENDOR_ID_HP, 0x1001)
  8256. },
  8257. {
  8258. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8259. PCI_VENDOR_ID_HP, 0x1002)
  8260. },
  8261. {
  8262. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8263. PCI_VENDOR_ID_HP, 0x1100)
  8264. },
  8265. {
  8266. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8267. PCI_VENDOR_ID_HP, 0x1101)
  8268. },
  8269. {
  8270. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8271. 0x1590, 0x0294)
  8272. },
  8273. {
  8274. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8275. 0x1590, 0x02db)
  8276. },
  8277. {
  8278. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8279. 0x1590, 0x02dc)
  8280. },
  8281. {
  8282. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8283. 0x1590, 0x032e)
  8284. },
  8285. {
  8286. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8287. 0x1590, 0x036f)
  8288. },
  8289. {
  8290. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8291. 0x1590, 0x0381)
  8292. },
  8293. {
  8294. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8295. 0x1590, 0x0382)
  8296. },
  8297. {
  8298. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8299. 0x1590, 0x0383)
  8300. },
  8301. {
  8302. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8303. 0x1d8d, 0x0800)
  8304. },
  8305. {
  8306. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8307. 0x1d8d, 0x0908)
  8308. },
  8309. {
  8310. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8311. 0x1d8d, 0x0806)
  8312. },
  8313. {
  8314. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8315. 0x1d8d, 0x0916)
  8316. },
  8317. {
  8318. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8319. PCI_VENDOR_ID_GIGABYTE, 0x1000)
  8320. },
  8321. {
  8322. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8323. 0x1dfc, 0x3161)
  8324. },
  8325. {
  8326. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8327. 0x1f0c, 0x3161)
  8328. },
  8329. {
  8330. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8331. 0x1cf2, 0x5445)
  8332. },
  8333. {
  8334. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8335. 0x1cf2, 0x5446)
  8336. },
  8337. {
  8338. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8339. 0x1cf2, 0x5447)
  8340. },
  8341. {
  8342. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8343. 0x1cf2, 0x5449)
  8344. },
  8345. {
  8346. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8347. 0x1cf2, 0x544a)
  8348. },
  8349. {
  8350. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8351. 0x1cf2, 0x544b)
  8352. },
  8353. {
  8354. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8355. 0x1cf2, 0x544d)
  8356. },
  8357. {
  8358. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8359. 0x1cf2, 0x544e)
  8360. },
  8361. {
  8362. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8363. 0x1cf2, 0x544f)
  8364. },
  8365. {
  8366. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8367. 0x1cf2, 0x0b27)
  8368. },
  8369. {
  8370. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8371. 0x1cf2, 0x0b29)
  8372. },
  8373. {
  8374. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8375. 0x1cf2, 0x0b45)
  8376. },
  8377. {
  8378. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8379. 0x1cc4, 0x0101)
  8380. },
  8381. {
  8382. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8383. 0x1cc4, 0x0201)
  8384. },
  8385. {
  8386. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8387. PCI_VENDOR_ID_LENOVO, 0x0220)
  8388. },
  8389. {
  8390. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8391. PCI_VENDOR_ID_LENOVO, 0x0221)
  8392. },
  8393. {
  8394. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8395. PCI_VENDOR_ID_LENOVO, 0x0520)
  8396. },
  8397. {
  8398. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8399. PCI_VENDOR_ID_LENOVO, 0x0522)
  8400. },
  8401. {
  8402. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8403. PCI_VENDOR_ID_LENOVO, 0x0620)
  8404. },
  8405. {
  8406. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8407. PCI_VENDOR_ID_LENOVO, 0x0621)
  8408. },
  8409. {
  8410. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8411. PCI_VENDOR_ID_LENOVO, 0x0622)
  8412. },
  8413. {
  8414. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8415. PCI_VENDOR_ID_LENOVO, 0x0623)
  8416. },
  8417. {
  8418. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8419. 0x1e93, 0x1000)
  8420. },
  8421. {
  8422. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8423. 0x1e93, 0x1001)
  8424. },
  8425. {
  8426. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8427. 0x1e93, 0x1002)
  8428. },
  8429. {
  8430. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  8431. PCI_ANY_ID, PCI_ANY_ID)
  8432. },
  8433. { 0 }
  8434. };
  8435. MODULE_DEVICE_TABLE(pci, pqi_pci_id_table);
  8436. static struct pci_driver pqi_pci_driver = {
  8437. .name = DRIVER_NAME_SHORT,
  8438. .id_table = pqi_pci_id_table,
  8439. .probe = pqi_pci_probe,
  8440. .remove = pqi_pci_remove,
  8441. .shutdown = pqi_shutdown,
  8442. #if defined(CONFIG_PM)
  8443. .driver = {
  8444. .pm = &pqi_pm_ops
  8445. },
  8446. #endif
  8447. };
  8448. static int __init pqi_init(void)
  8449. {
  8450. int rc;
  8451. pr_info(DRIVER_NAME "\n");
  8452. pqi_verify_structures();
  8453. sis_verify_structures();
  8454. pqi_sas_transport_template = sas_attach_transport(&pqi_sas_transport_functions);
  8455. if (!pqi_sas_transport_template)
  8456. return -ENODEV;
  8457. pqi_process_module_params();
  8458. rc = pci_register_driver(&pqi_pci_driver);
  8459. if (rc)
  8460. sas_release_transport(pqi_sas_transport_template);
  8461. return rc;
  8462. }
  8463. static void __exit pqi_cleanup(void)
  8464. {
  8465. pci_unregister_driver(&pqi_pci_driver);
  8466. sas_release_transport(pqi_sas_transport_template);
  8467. }
  8468. module_init(pqi_init);
  8469. module_exit(pqi_cleanup);
  8470. static void pqi_verify_structures(void)
  8471. {
  8472. BUILD_BUG_ON(offsetof(struct pqi_ctrl_registers,
  8473. sis_host_to_ctrl_doorbell) != 0x20);
  8474. BUILD_BUG_ON(offsetof(struct pqi_ctrl_registers,
  8475. sis_interrupt_mask) != 0x34);
  8476. BUILD_BUG_ON(offsetof(struct pqi_ctrl_registers,
  8477. sis_ctrl_to_host_doorbell) != 0x9c);
  8478. BUILD_BUG_ON(offsetof(struct pqi_ctrl_registers,
  8479. sis_ctrl_to_host_doorbell_clear) != 0xa0);
  8480. BUILD_BUG_ON(offsetof(struct pqi_ctrl_registers,
  8481. sis_driver_scratch) != 0xb0);
  8482. BUILD_BUG_ON(offsetof(struct pqi_ctrl_registers,
  8483. sis_product_identifier) != 0xb4);
  8484. BUILD_BUG_ON(offsetof(struct pqi_ctrl_registers,
  8485. sis_firmware_status) != 0xbc);
  8486. BUILD_BUG_ON(offsetof(struct pqi_ctrl_registers,
  8487. sis_ctrl_shutdown_reason_code) != 0xcc);
  8488. BUILD_BUG_ON(offsetof(struct pqi_ctrl_registers,
  8489. sis_mailbox) != 0x1000);
  8490. BUILD_BUG_ON(offsetof(struct pqi_ctrl_registers,
  8491. pqi_registers) != 0x4000);
  8492. BUILD_BUG_ON(offsetof(struct pqi_iu_header,
  8493. iu_type) != 0x0);
  8494. BUILD_BUG_ON(offsetof(struct pqi_iu_header,
  8495. iu_length) != 0x2);
  8496. BUILD_BUG_ON(offsetof(struct pqi_iu_header,
  8497. response_queue_id) != 0x4);
  8498. BUILD_BUG_ON(offsetof(struct pqi_iu_header,
  8499. driver_flags) != 0x6);
  8500. BUILD_BUG_ON(sizeof(struct pqi_iu_header) != 0x8);
  8501. BUILD_BUG_ON(offsetof(struct pqi_aio_error_info,
  8502. status) != 0x0);
  8503. BUILD_BUG_ON(offsetof(struct pqi_aio_error_info,
  8504. service_response) != 0x1);
  8505. BUILD_BUG_ON(offsetof(struct pqi_aio_error_info,
  8506. data_present) != 0x2);
  8507. BUILD_BUG_ON(offsetof(struct pqi_aio_error_info,
  8508. reserved) != 0x3);
  8509. BUILD_BUG_ON(offsetof(struct pqi_aio_error_info,
  8510. residual_count) != 0x4);
  8511. BUILD_BUG_ON(offsetof(struct pqi_aio_error_info,
  8512. data_length) != 0x8);
  8513. BUILD_BUG_ON(offsetof(struct pqi_aio_error_info,
  8514. reserved1) != 0xa);
  8515. BUILD_BUG_ON(offsetof(struct pqi_aio_error_info,
  8516. data) != 0xc);
  8517. BUILD_BUG_ON(sizeof(struct pqi_aio_error_info) != 0x10c);
  8518. BUILD_BUG_ON(offsetof(struct pqi_raid_error_info,
  8519. data_in_result) != 0x0);
  8520. BUILD_BUG_ON(offsetof(struct pqi_raid_error_info,
  8521. data_out_result) != 0x1);
  8522. BUILD_BUG_ON(offsetof(struct pqi_raid_error_info,
  8523. reserved) != 0x2);
  8524. BUILD_BUG_ON(offsetof(struct pqi_raid_error_info,
  8525. status) != 0x5);
  8526. BUILD_BUG_ON(offsetof(struct pqi_raid_error_info,
  8527. status_qualifier) != 0x6);
  8528. BUILD_BUG_ON(offsetof(struct pqi_raid_error_info,
  8529. sense_data_length) != 0x8);
  8530. BUILD_BUG_ON(offsetof(struct pqi_raid_error_info,
  8531. response_data_length) != 0xa);
  8532. BUILD_BUG_ON(offsetof(struct pqi_raid_error_info,
  8533. data_in_transferred) != 0xc);
  8534. BUILD_BUG_ON(offsetof(struct pqi_raid_error_info,
  8535. data_out_transferred) != 0x10);
  8536. BUILD_BUG_ON(offsetof(struct pqi_raid_error_info,
  8537. data) != 0x14);
  8538. BUILD_BUG_ON(sizeof(struct pqi_raid_error_info) != 0x114);
  8539. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  8540. signature) != 0x0);
  8541. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  8542. function_and_status_code) != 0x8);
  8543. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  8544. max_admin_iq_elements) != 0x10);
  8545. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  8546. max_admin_oq_elements) != 0x11);
  8547. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  8548. admin_iq_element_length) != 0x12);
  8549. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  8550. admin_oq_element_length) != 0x13);
  8551. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  8552. max_reset_timeout) != 0x14);
  8553. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  8554. legacy_intx_status) != 0x18);
  8555. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  8556. legacy_intx_mask_set) != 0x1c);
  8557. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  8558. legacy_intx_mask_clear) != 0x20);
  8559. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  8560. device_status) != 0x40);
  8561. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  8562. admin_iq_pi_offset) != 0x48);
  8563. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  8564. admin_oq_ci_offset) != 0x50);
  8565. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  8566. admin_iq_element_array_addr) != 0x58);
  8567. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  8568. admin_oq_element_array_addr) != 0x60);
  8569. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  8570. admin_iq_ci_addr) != 0x68);
  8571. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  8572. admin_oq_pi_addr) != 0x70);
  8573. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  8574. admin_iq_num_elements) != 0x78);
  8575. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  8576. admin_oq_num_elements) != 0x79);
  8577. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  8578. admin_queue_int_msg_num) != 0x7a);
  8579. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  8580. device_error) != 0x80);
  8581. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  8582. error_details) != 0x88);
  8583. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  8584. device_reset) != 0x90);
  8585. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  8586. power_action) != 0x94);
  8587. BUILD_BUG_ON(sizeof(struct pqi_device_registers) != 0x100);
  8588. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  8589. header.iu_type) != 0);
  8590. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  8591. header.iu_length) != 2);
  8592. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  8593. header.driver_flags) != 6);
  8594. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  8595. request_id) != 8);
  8596. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  8597. function_code) != 10);
  8598. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  8599. data.report_device_capability.buffer_length) != 44);
  8600. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  8601. data.report_device_capability.sg_descriptor) != 48);
  8602. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  8603. data.create_operational_iq.queue_id) != 12);
  8604. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  8605. data.create_operational_iq.element_array_addr) != 16);
  8606. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  8607. data.create_operational_iq.ci_addr) != 24);
  8608. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  8609. data.create_operational_iq.num_elements) != 32);
  8610. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  8611. data.create_operational_iq.element_length) != 34);
  8612. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  8613. data.create_operational_iq.queue_protocol) != 36);
  8614. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  8615. data.create_operational_oq.queue_id) != 12);
  8616. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  8617. data.create_operational_oq.element_array_addr) != 16);
  8618. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  8619. data.create_operational_oq.pi_addr) != 24);
  8620. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  8621. data.create_operational_oq.num_elements) != 32);
  8622. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  8623. data.create_operational_oq.element_length) != 34);
  8624. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  8625. data.create_operational_oq.queue_protocol) != 36);
  8626. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  8627. data.create_operational_oq.int_msg_num) != 40);
  8628. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  8629. data.create_operational_oq.coalescing_count) != 42);
  8630. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  8631. data.create_operational_oq.min_coalescing_time) != 44);
  8632. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  8633. data.create_operational_oq.max_coalescing_time) != 48);
  8634. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  8635. data.delete_operational_queue.queue_id) != 12);
  8636. BUILD_BUG_ON(sizeof(struct pqi_general_admin_request) != 64);
  8637. BUILD_BUG_ON(sizeof_field(struct pqi_general_admin_request,
  8638. data.create_operational_iq) != 64 - 11);
  8639. BUILD_BUG_ON(sizeof_field(struct pqi_general_admin_request,
  8640. data.create_operational_oq) != 64 - 11);
  8641. BUILD_BUG_ON(sizeof_field(struct pqi_general_admin_request,
  8642. data.delete_operational_queue) != 64 - 11);
  8643. BUILD_BUG_ON(offsetof(struct pqi_general_admin_response,
  8644. header.iu_type) != 0);
  8645. BUILD_BUG_ON(offsetof(struct pqi_general_admin_response,
  8646. header.iu_length) != 2);
  8647. BUILD_BUG_ON(offsetof(struct pqi_general_admin_response,
  8648. header.driver_flags) != 6);
  8649. BUILD_BUG_ON(offsetof(struct pqi_general_admin_response,
  8650. request_id) != 8);
  8651. BUILD_BUG_ON(offsetof(struct pqi_general_admin_response,
  8652. function_code) != 10);
  8653. BUILD_BUG_ON(offsetof(struct pqi_general_admin_response,
  8654. status) != 11);
  8655. BUILD_BUG_ON(offsetof(struct pqi_general_admin_response,
  8656. data.create_operational_iq.status_descriptor) != 12);
  8657. BUILD_BUG_ON(offsetof(struct pqi_general_admin_response,
  8658. data.create_operational_iq.iq_pi_offset) != 16);
  8659. BUILD_BUG_ON(offsetof(struct pqi_general_admin_response,
  8660. data.create_operational_oq.status_descriptor) != 12);
  8661. BUILD_BUG_ON(offsetof(struct pqi_general_admin_response,
  8662. data.create_operational_oq.oq_ci_offset) != 16);
  8663. BUILD_BUG_ON(sizeof(struct pqi_general_admin_response) != 64);
  8664. BUILD_BUG_ON(offsetof(struct pqi_raid_path_request,
  8665. header.iu_type) != 0);
  8666. BUILD_BUG_ON(offsetof(struct pqi_raid_path_request,
  8667. header.iu_length) != 2);
  8668. BUILD_BUG_ON(offsetof(struct pqi_raid_path_request,
  8669. header.response_queue_id) != 4);
  8670. BUILD_BUG_ON(offsetof(struct pqi_raid_path_request,
  8671. header.driver_flags) != 6);
  8672. BUILD_BUG_ON(offsetof(struct pqi_raid_path_request,
  8673. request_id) != 8);
  8674. BUILD_BUG_ON(offsetof(struct pqi_raid_path_request,
  8675. nexus_id) != 10);
  8676. BUILD_BUG_ON(offsetof(struct pqi_raid_path_request,
  8677. buffer_length) != 12);
  8678. BUILD_BUG_ON(offsetof(struct pqi_raid_path_request,
  8679. lun_number) != 16);
  8680. BUILD_BUG_ON(offsetof(struct pqi_raid_path_request,
  8681. protocol_specific) != 24);
  8682. BUILD_BUG_ON(offsetof(struct pqi_raid_path_request,
  8683. error_index) != 27);
  8684. BUILD_BUG_ON(offsetof(struct pqi_raid_path_request,
  8685. cdb) != 32);
  8686. BUILD_BUG_ON(offsetof(struct pqi_raid_path_request,
  8687. timeout) != 60);
  8688. BUILD_BUG_ON(offsetof(struct pqi_raid_path_request,
  8689. sg_descriptors) != 64);
  8690. BUILD_BUG_ON(sizeof(struct pqi_raid_path_request) !=
  8691. PQI_OPERATIONAL_IQ_ELEMENT_LENGTH);
  8692. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  8693. header.iu_type) != 0);
  8694. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  8695. header.iu_length) != 2);
  8696. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  8697. header.response_queue_id) != 4);
  8698. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  8699. header.driver_flags) != 6);
  8700. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  8701. request_id) != 8);
  8702. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  8703. nexus_id) != 12);
  8704. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  8705. buffer_length) != 16);
  8706. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  8707. data_encryption_key_index) != 22);
  8708. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  8709. encrypt_tweak_lower) != 24);
  8710. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  8711. encrypt_tweak_upper) != 28);
  8712. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  8713. cdb) != 32);
  8714. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  8715. error_index) != 48);
  8716. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  8717. num_sg_descriptors) != 50);
  8718. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  8719. cdb_length) != 51);
  8720. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  8721. lun_number) != 52);
  8722. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  8723. sg_descriptors) != 64);
  8724. BUILD_BUG_ON(sizeof(struct pqi_aio_path_request) !=
  8725. PQI_OPERATIONAL_IQ_ELEMENT_LENGTH);
  8726. BUILD_BUG_ON(offsetof(struct pqi_io_response,
  8727. header.iu_type) != 0);
  8728. BUILD_BUG_ON(offsetof(struct pqi_io_response,
  8729. header.iu_length) != 2);
  8730. BUILD_BUG_ON(offsetof(struct pqi_io_response,
  8731. request_id) != 8);
  8732. BUILD_BUG_ON(offsetof(struct pqi_io_response,
  8733. error_index) != 10);
  8734. BUILD_BUG_ON(offsetof(struct pqi_general_management_request,
  8735. header.iu_type) != 0);
  8736. BUILD_BUG_ON(offsetof(struct pqi_general_management_request,
  8737. header.iu_length) != 2);
  8738. BUILD_BUG_ON(offsetof(struct pqi_general_management_request,
  8739. header.response_queue_id) != 4);
  8740. BUILD_BUG_ON(offsetof(struct pqi_general_management_request,
  8741. request_id) != 8);
  8742. BUILD_BUG_ON(offsetof(struct pqi_general_management_request,
  8743. data.report_event_configuration.buffer_length) != 12);
  8744. BUILD_BUG_ON(offsetof(struct pqi_general_management_request,
  8745. data.report_event_configuration.sg_descriptors) != 16);
  8746. BUILD_BUG_ON(offsetof(struct pqi_general_management_request,
  8747. data.set_event_configuration.global_event_oq_id) != 10);
  8748. BUILD_BUG_ON(offsetof(struct pqi_general_management_request,
  8749. data.set_event_configuration.buffer_length) != 12);
  8750. BUILD_BUG_ON(offsetof(struct pqi_general_management_request,
  8751. data.set_event_configuration.sg_descriptors) != 16);
  8752. BUILD_BUG_ON(offsetof(struct pqi_iu_layer_descriptor,
  8753. max_inbound_iu_length) != 6);
  8754. BUILD_BUG_ON(offsetof(struct pqi_iu_layer_descriptor,
  8755. max_outbound_iu_length) != 14);
  8756. BUILD_BUG_ON(sizeof(struct pqi_iu_layer_descriptor) != 16);
  8757. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  8758. data_length) != 0);
  8759. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  8760. iq_arbitration_priority_support_bitmask) != 8);
  8761. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  8762. maximum_aw_a) != 9);
  8763. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  8764. maximum_aw_b) != 10);
  8765. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  8766. maximum_aw_c) != 11);
  8767. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  8768. max_inbound_queues) != 16);
  8769. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  8770. max_elements_per_iq) != 18);
  8771. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  8772. max_iq_element_length) != 24);
  8773. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  8774. min_iq_element_length) != 26);
  8775. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  8776. max_outbound_queues) != 30);
  8777. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  8778. max_elements_per_oq) != 32);
  8779. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  8780. intr_coalescing_time_granularity) != 34);
  8781. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  8782. max_oq_element_length) != 36);
  8783. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  8784. min_oq_element_length) != 38);
  8785. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  8786. iu_layer_descriptors) != 64);
  8787. BUILD_BUG_ON(sizeof(struct pqi_device_capability) != 576);
  8788. BUILD_BUG_ON(offsetof(struct pqi_event_descriptor,
  8789. event_type) != 0);
  8790. BUILD_BUG_ON(offsetof(struct pqi_event_descriptor,
  8791. oq_id) != 2);
  8792. BUILD_BUG_ON(sizeof(struct pqi_event_descriptor) != 4);
  8793. BUILD_BUG_ON(offsetof(struct pqi_event_config,
  8794. num_event_descriptors) != 2);
  8795. BUILD_BUG_ON(offsetof(struct pqi_event_config,
  8796. descriptors) != 4);
  8797. BUILD_BUG_ON(PQI_NUM_SUPPORTED_EVENTS !=
  8798. ARRAY_SIZE(pqi_supported_event_types));
  8799. BUILD_BUG_ON(offsetof(struct pqi_event_response,
  8800. header.iu_type) != 0);
  8801. BUILD_BUG_ON(offsetof(struct pqi_event_response,
  8802. header.iu_length) != 2);
  8803. BUILD_BUG_ON(offsetof(struct pqi_event_response,
  8804. event_type) != 8);
  8805. BUILD_BUG_ON(offsetof(struct pqi_event_response,
  8806. event_id) != 10);
  8807. BUILD_BUG_ON(offsetof(struct pqi_event_response,
  8808. additional_event_id) != 12);
  8809. BUILD_BUG_ON(offsetof(struct pqi_event_response,
  8810. data) != 16);
  8811. BUILD_BUG_ON(sizeof(struct pqi_event_response) != 32);
  8812. BUILD_BUG_ON(offsetof(struct pqi_event_acknowledge_request,
  8813. header.iu_type) != 0);
  8814. BUILD_BUG_ON(offsetof(struct pqi_event_acknowledge_request,
  8815. header.iu_length) != 2);
  8816. BUILD_BUG_ON(offsetof(struct pqi_event_acknowledge_request,
  8817. event_type) != 8);
  8818. BUILD_BUG_ON(offsetof(struct pqi_event_acknowledge_request,
  8819. event_id) != 10);
  8820. BUILD_BUG_ON(offsetof(struct pqi_event_acknowledge_request,
  8821. additional_event_id) != 12);
  8822. BUILD_BUG_ON(sizeof(struct pqi_event_acknowledge_request) != 16);
  8823. BUILD_BUG_ON(offsetof(struct pqi_task_management_request,
  8824. header.iu_type) != 0);
  8825. BUILD_BUG_ON(offsetof(struct pqi_task_management_request,
  8826. header.iu_length) != 2);
  8827. BUILD_BUG_ON(offsetof(struct pqi_task_management_request,
  8828. request_id) != 8);
  8829. BUILD_BUG_ON(offsetof(struct pqi_task_management_request,
  8830. nexus_id) != 10);
  8831. BUILD_BUG_ON(offsetof(struct pqi_task_management_request,
  8832. timeout) != 14);
  8833. BUILD_BUG_ON(offsetof(struct pqi_task_management_request,
  8834. lun_number) != 16);
  8835. BUILD_BUG_ON(offsetof(struct pqi_task_management_request,
  8836. protocol_specific) != 24);
  8837. BUILD_BUG_ON(offsetof(struct pqi_task_management_request,
  8838. outbound_queue_id_to_manage) != 26);
  8839. BUILD_BUG_ON(offsetof(struct pqi_task_management_request,
  8840. request_id_to_manage) != 28);
  8841. BUILD_BUG_ON(offsetof(struct pqi_task_management_request,
  8842. task_management_function) != 30);
  8843. BUILD_BUG_ON(sizeof(struct pqi_task_management_request) != 32);
  8844. BUILD_BUG_ON(offsetof(struct pqi_task_management_response,
  8845. header.iu_type) != 0);
  8846. BUILD_BUG_ON(offsetof(struct pqi_task_management_response,
  8847. header.iu_length) != 2);
  8848. BUILD_BUG_ON(offsetof(struct pqi_task_management_response,
  8849. request_id) != 8);
  8850. BUILD_BUG_ON(offsetof(struct pqi_task_management_response,
  8851. nexus_id) != 10);
  8852. BUILD_BUG_ON(offsetof(struct pqi_task_management_response,
  8853. additional_response_info) != 12);
  8854. BUILD_BUG_ON(offsetof(struct pqi_task_management_response,
  8855. response_code) != 15);
  8856. BUILD_BUG_ON(sizeof(struct pqi_task_management_response) != 16);
  8857. BUILD_BUG_ON(offsetof(struct bmic_identify_controller,
  8858. configured_logical_drive_count) != 0);
  8859. BUILD_BUG_ON(offsetof(struct bmic_identify_controller,
  8860. configuration_signature) != 1);
  8861. BUILD_BUG_ON(offsetof(struct bmic_identify_controller,
  8862. firmware_version_short) != 5);
  8863. BUILD_BUG_ON(offsetof(struct bmic_identify_controller,
  8864. extended_logical_unit_count) != 154);
  8865. BUILD_BUG_ON(offsetof(struct bmic_identify_controller,
  8866. firmware_build_number) != 190);
  8867. BUILD_BUG_ON(offsetof(struct bmic_identify_controller,
  8868. vendor_id) != 200);
  8869. BUILD_BUG_ON(offsetof(struct bmic_identify_controller,
  8870. product_id) != 208);
  8871. BUILD_BUG_ON(offsetof(struct bmic_identify_controller,
  8872. extra_controller_flags) != 286);
  8873. BUILD_BUG_ON(offsetof(struct bmic_identify_controller,
  8874. controller_mode) != 292);
  8875. BUILD_BUG_ON(offsetof(struct bmic_identify_controller,
  8876. spare_part_number) != 293);
  8877. BUILD_BUG_ON(offsetof(struct bmic_identify_controller,
  8878. firmware_version_long) != 325);
  8879. BUILD_BUG_ON(offsetof(struct bmic_identify_physical_device,
  8880. phys_bay_in_box) != 115);
  8881. BUILD_BUG_ON(offsetof(struct bmic_identify_physical_device,
  8882. device_type) != 120);
  8883. BUILD_BUG_ON(offsetof(struct bmic_identify_physical_device,
  8884. redundant_path_present_map) != 1736);
  8885. BUILD_BUG_ON(offsetof(struct bmic_identify_physical_device,
  8886. active_path_number) != 1738);
  8887. BUILD_BUG_ON(offsetof(struct bmic_identify_physical_device,
  8888. alternate_paths_phys_connector) != 1739);
  8889. BUILD_BUG_ON(offsetof(struct bmic_identify_physical_device,
  8890. alternate_paths_phys_box_on_port) != 1755);
  8891. BUILD_BUG_ON(offsetof(struct bmic_identify_physical_device,
  8892. current_queue_depth_limit) != 1796);
  8893. BUILD_BUG_ON(sizeof(struct bmic_identify_physical_device) != 2560);
  8894. BUILD_BUG_ON(sizeof(struct bmic_sense_feature_buffer_header) != 4);
  8895. BUILD_BUG_ON(offsetof(struct bmic_sense_feature_buffer_header,
  8896. page_code) != 0);
  8897. BUILD_BUG_ON(offsetof(struct bmic_sense_feature_buffer_header,
  8898. subpage_code) != 1);
  8899. BUILD_BUG_ON(offsetof(struct bmic_sense_feature_buffer_header,
  8900. buffer_length) != 2);
  8901. BUILD_BUG_ON(sizeof(struct bmic_sense_feature_page_header) != 4);
  8902. BUILD_BUG_ON(offsetof(struct bmic_sense_feature_page_header,
  8903. page_code) != 0);
  8904. BUILD_BUG_ON(offsetof(struct bmic_sense_feature_page_header,
  8905. subpage_code) != 1);
  8906. BUILD_BUG_ON(offsetof(struct bmic_sense_feature_page_header,
  8907. page_length) != 2);
  8908. BUILD_BUG_ON(sizeof(struct bmic_sense_feature_io_page_aio_subpage)
  8909. != 18);
  8910. BUILD_BUG_ON(offsetof(struct bmic_sense_feature_io_page_aio_subpage,
  8911. header) != 0);
  8912. BUILD_BUG_ON(offsetof(struct bmic_sense_feature_io_page_aio_subpage,
  8913. firmware_read_support) != 4);
  8914. BUILD_BUG_ON(offsetof(struct bmic_sense_feature_io_page_aio_subpage,
  8915. driver_read_support) != 5);
  8916. BUILD_BUG_ON(offsetof(struct bmic_sense_feature_io_page_aio_subpage,
  8917. firmware_write_support) != 6);
  8918. BUILD_BUG_ON(offsetof(struct bmic_sense_feature_io_page_aio_subpage,
  8919. driver_write_support) != 7);
  8920. BUILD_BUG_ON(offsetof(struct bmic_sense_feature_io_page_aio_subpage,
  8921. max_transfer_encrypted_sas_sata) != 8);
  8922. BUILD_BUG_ON(offsetof(struct bmic_sense_feature_io_page_aio_subpage,
  8923. max_transfer_encrypted_nvme) != 10);
  8924. BUILD_BUG_ON(offsetof(struct bmic_sense_feature_io_page_aio_subpage,
  8925. max_write_raid_5_6) != 12);
  8926. BUILD_BUG_ON(offsetof(struct bmic_sense_feature_io_page_aio_subpage,
  8927. max_write_raid_1_10_2drive) != 14);
  8928. BUILD_BUG_ON(offsetof(struct bmic_sense_feature_io_page_aio_subpage,
  8929. max_write_raid_1_10_3drive) != 16);
  8930. BUILD_BUG_ON(PQI_ADMIN_IQ_NUM_ELEMENTS > 255);
  8931. BUILD_BUG_ON(PQI_ADMIN_OQ_NUM_ELEMENTS > 255);
  8932. BUILD_BUG_ON(PQI_ADMIN_IQ_ELEMENT_LENGTH %
  8933. PQI_QUEUE_ELEMENT_LENGTH_ALIGNMENT != 0);
  8934. BUILD_BUG_ON(PQI_ADMIN_OQ_ELEMENT_LENGTH %
  8935. PQI_QUEUE_ELEMENT_LENGTH_ALIGNMENT != 0);
  8936. BUILD_BUG_ON(PQI_OPERATIONAL_IQ_ELEMENT_LENGTH > 1048560);
  8937. BUILD_BUG_ON(PQI_OPERATIONAL_IQ_ELEMENT_LENGTH %
  8938. PQI_QUEUE_ELEMENT_LENGTH_ALIGNMENT != 0);
  8939. BUILD_BUG_ON(PQI_OPERATIONAL_OQ_ELEMENT_LENGTH > 1048560);
  8940. BUILD_BUG_ON(PQI_OPERATIONAL_OQ_ELEMENT_LENGTH %
  8941. PQI_QUEUE_ELEMENT_LENGTH_ALIGNMENT != 0);
  8942. BUILD_BUG_ON(PQI_RESERVED_IO_SLOTS >= PQI_MAX_OUTSTANDING_REQUESTS);
  8943. BUILD_BUG_ON(PQI_RESERVED_IO_SLOTS >=
  8944. PQI_MAX_OUTSTANDING_REQUESTS_KDUMP);
  8945. }