qla_inline.h 14 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * QLogic Fibre Channel HBA Driver
  4. * Copyright (c) 2003-2014 QLogic Corporation
  5. */
  6. #include "qla_target.h"
  7. /**
  8. * qla24xx_calc_iocbs() - Determine number of Command Type 3 and
  9. * Continuation Type 1 IOCBs to allocate.
  10. *
  11. * @vha: HA context
  12. * @dsds: number of data segment descriptors needed
  13. *
  14. * Returns the number of IOCB entries needed to store @dsds.
  15. */
  16. static inline uint16_t
  17. qla24xx_calc_iocbs(scsi_qla_host_t *vha, uint16_t dsds)
  18. {
  19. uint16_t iocbs;
  20. iocbs = 1;
  21. if (dsds > 1) {
  22. iocbs += (dsds - 1) / 5;
  23. if ((dsds - 1) % 5)
  24. iocbs++;
  25. }
  26. return iocbs;
  27. }
  28. /*
  29. * qla2x00_debounce_register
  30. * Debounce register.
  31. *
  32. * Input:
  33. * port = register address.
  34. *
  35. * Returns:
  36. * register value.
  37. */
  38. static __inline__ uint16_t
  39. qla2x00_debounce_register(volatile __le16 __iomem *addr)
  40. {
  41. volatile uint16_t first;
  42. volatile uint16_t second;
  43. do {
  44. first = rd_reg_word(addr);
  45. barrier();
  46. cpu_relax();
  47. second = rd_reg_word(addr);
  48. } while (first != second);
  49. return (first);
  50. }
  51. static inline void
  52. qla2x00_poll(struct rsp_que *rsp)
  53. {
  54. struct qla_hw_data *ha = rsp->hw;
  55. if (IS_P3P_TYPE(ha))
  56. qla82xx_poll(0, rsp);
  57. else
  58. ha->isp_ops->intr_handler(0, rsp);
  59. }
  60. static inline uint8_t *
  61. host_to_fcp_swap(uint8_t *fcp, uint32_t bsize)
  62. {
  63. uint32_t *ifcp = (uint32_t *) fcp;
  64. uint32_t *ofcp = (uint32_t *) fcp;
  65. uint32_t iter = bsize >> 2;
  66. for (; iter ; iter--)
  67. *ofcp++ = swab32(*ifcp++);
  68. return fcp;
  69. }
  70. static inline void
  71. host_to_adap(uint8_t *src, uint8_t *dst, uint32_t bsize)
  72. {
  73. uint32_t *isrc = (uint32_t *) src;
  74. __le32 *odest = (__le32 *) dst;
  75. uint32_t iter = bsize >> 2;
  76. for ( ; iter--; isrc++)
  77. *odest++ = cpu_to_le32(*isrc);
  78. }
  79. static inline void
  80. qla2x00_clean_dsd_pool(struct qla_hw_data *ha, struct crc_context *ctx)
  81. {
  82. struct dsd_dma *dsd, *tdsd;
  83. /* clean up allocated prev pool */
  84. list_for_each_entry_safe(dsd, tdsd, &ctx->dsd_list, list) {
  85. dma_pool_free(ha->dl_dma_pool, dsd->dsd_addr,
  86. dsd->dsd_list_dma);
  87. list_del(&dsd->list);
  88. kfree(dsd);
  89. }
  90. INIT_LIST_HEAD(&ctx->dsd_list);
  91. }
  92. static inline void
  93. qla2x00_set_fcport_disc_state(fc_port_t *fcport, int state)
  94. {
  95. int old_val;
  96. uint8_t shiftbits, mask;
  97. uint8_t port_dstate_str_sz;
  98. /* This will have to change when the max no. of states > 16 */
  99. shiftbits = 4;
  100. mask = (1 << shiftbits) - 1;
  101. port_dstate_str_sz = sizeof(port_dstate_str) / sizeof(char *);
  102. fcport->disc_state = state;
  103. while (1) {
  104. old_val = atomic_read(&fcport->shadow_disc_state);
  105. if (old_val == atomic_cmpxchg(&fcport->shadow_disc_state,
  106. old_val, (old_val << shiftbits) | state)) {
  107. ql_dbg(ql_dbg_disc, fcport->vha, 0x2134,
  108. "FCPort %8phC disc_state transition: %s to %s - portid=%06x.\n",
  109. fcport->port_name, (old_val & mask) < port_dstate_str_sz ?
  110. port_dstate_str[old_val & mask] : "Unknown",
  111. port_dstate_str[state], fcport->d_id.b24);
  112. return;
  113. }
  114. }
  115. }
  116. static inline int
  117. qla2x00_hba_err_chk_enabled(srb_t *sp)
  118. {
  119. /*
  120. * Uncomment when corresponding SCSI changes are done.
  121. *
  122. if (!sp->cmd->prot_chk)
  123. return 0;
  124. *
  125. */
  126. switch (scsi_get_prot_op(GET_CMD_SP(sp))) {
  127. case SCSI_PROT_READ_STRIP:
  128. case SCSI_PROT_WRITE_INSERT:
  129. if (ql2xenablehba_err_chk >= 1)
  130. return 1;
  131. break;
  132. case SCSI_PROT_READ_PASS:
  133. case SCSI_PROT_WRITE_PASS:
  134. if (ql2xenablehba_err_chk >= 2)
  135. return 1;
  136. break;
  137. case SCSI_PROT_READ_INSERT:
  138. case SCSI_PROT_WRITE_STRIP:
  139. return 1;
  140. }
  141. return 0;
  142. }
  143. static inline int
  144. qla2x00_reset_active(scsi_qla_host_t *vha)
  145. {
  146. scsi_qla_host_t *base_vha = pci_get_drvdata(vha->hw->pdev);
  147. /* Test appropriate base-vha and vha flags. */
  148. return test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) ||
  149. test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
  150. test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
  151. test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
  152. test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
  153. }
  154. static inline int
  155. qla2x00_chip_is_down(scsi_qla_host_t *vha)
  156. {
  157. return (qla2x00_reset_active(vha) || !vha->hw->flags.fw_started);
  158. }
  159. static void qla2xxx_init_sp(srb_t *sp, scsi_qla_host_t *vha,
  160. struct qla_qpair *qpair, fc_port_t *fcport)
  161. {
  162. memset(sp, 0, sizeof(*sp));
  163. sp->fcport = fcport;
  164. sp->iocbs = 1;
  165. sp->vha = vha;
  166. sp->qpair = qpair;
  167. sp->cmd_type = TYPE_SRB;
  168. /* ref : INIT - normal flow */
  169. kref_init(&sp->cmd_kref);
  170. INIT_LIST_HEAD(&sp->elem);
  171. }
  172. static inline srb_t *
  173. qla2xxx_get_qpair_sp(scsi_qla_host_t *vha, struct qla_qpair *qpair,
  174. fc_port_t *fcport, gfp_t flag)
  175. {
  176. srb_t *sp = NULL;
  177. uint8_t bail;
  178. QLA_QPAIR_MARK_BUSY(qpair, bail);
  179. if (unlikely(bail))
  180. return NULL;
  181. sp = mempool_alloc(qpair->srb_mempool, flag);
  182. if (sp)
  183. qla2xxx_init_sp(sp, vha, qpair, fcport);
  184. else
  185. QLA_QPAIR_MARK_NOT_BUSY(qpair);
  186. return sp;
  187. }
  188. void qla2xxx_rel_done_warning(srb_t *sp, int res);
  189. void qla2xxx_rel_free_warning(srb_t *sp);
  190. static inline void
  191. qla2xxx_rel_qpair_sp(struct qla_qpair *qpair, srb_t *sp)
  192. {
  193. sp->qpair = NULL;
  194. sp->done = qla2xxx_rel_done_warning;
  195. sp->free = qla2xxx_rel_free_warning;
  196. mempool_free(sp, qpair->srb_mempool);
  197. QLA_QPAIR_MARK_NOT_BUSY(qpair);
  198. }
  199. static inline srb_t *
  200. qla2x00_get_sp(scsi_qla_host_t *vha, fc_port_t *fcport, gfp_t flag)
  201. {
  202. srb_t *sp = NULL;
  203. struct qla_qpair *qpair;
  204. if (unlikely(qla_vha_mark_busy(vha)))
  205. return NULL;
  206. qpair = vha->hw->base_qpair;
  207. sp = qla2xxx_get_qpair_sp(vha, qpair, fcport, flag);
  208. if (!sp)
  209. goto done;
  210. sp->vha = vha;
  211. done:
  212. if (!sp)
  213. QLA_VHA_MARK_NOT_BUSY(vha);
  214. return sp;
  215. }
  216. static inline void
  217. qla2x00_rel_sp(srb_t *sp)
  218. {
  219. QLA_VHA_MARK_NOT_BUSY(sp->vha);
  220. qla2xxx_rel_qpair_sp(sp->qpair, sp);
  221. }
  222. static inline int
  223. qla2x00_gid_list_size(struct qla_hw_data *ha)
  224. {
  225. if (IS_QLAFX00(ha))
  226. return sizeof(uint32_t) * 32;
  227. else
  228. return sizeof(struct gid_list_info) * ha->max_fibre_devices;
  229. }
  230. static inline void
  231. qla2x00_handle_mbx_completion(struct qla_hw_data *ha, int status)
  232. {
  233. if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
  234. (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
  235. set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  236. clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
  237. complete(&ha->mbx_intr_comp);
  238. }
  239. }
  240. static inline void
  241. qla2x00_set_retry_delay_timestamp(fc_port_t *fcport, uint16_t sts_qual)
  242. {
  243. u8 scope;
  244. u16 qual;
  245. #define SQ_SCOPE_MASK 0xc000 /* SAM-6 rev5 5.3.2 */
  246. #define SQ_SCOPE_SHIFT 14
  247. #define SQ_QUAL_MASK 0x3fff
  248. #define SQ_MAX_WAIT_SEC 60 /* Max I/O hold off time in seconds. */
  249. #define SQ_MAX_WAIT_TIME (SQ_MAX_WAIT_SEC * 10) /* in 100ms. */
  250. if (!sts_qual) /* Common case. */
  251. return;
  252. scope = (sts_qual & SQ_SCOPE_MASK) >> SQ_SCOPE_SHIFT;
  253. /* Handle only scope 1 or 2, which is for I-T nexus. */
  254. if (scope != 1 && scope != 2)
  255. return;
  256. /* Skip processing, if retry delay timer is already in effect. */
  257. if (fcport->retry_delay_timestamp &&
  258. time_before(jiffies, fcport->retry_delay_timestamp))
  259. return;
  260. qual = sts_qual & SQ_QUAL_MASK;
  261. if (qual < 1 || qual > 0x3fef)
  262. return;
  263. qual = min(qual, (u16)SQ_MAX_WAIT_TIME);
  264. /* qual is expressed in 100ms increments. */
  265. fcport->retry_delay_timestamp = jiffies + (qual * HZ / 10);
  266. ql_log(ql_log_warn, fcport->vha, 0x5101,
  267. "%8phC: I/O throttling requested (status qualifier = %04xh), holding off I/Os for %ums.\n",
  268. fcport->port_name, sts_qual, qual * 100);
  269. }
  270. static inline bool
  271. qla_is_exch_offld_enabled(struct scsi_qla_host *vha)
  272. {
  273. if (qla_ini_mode_enabled(vha) &&
  274. (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT))
  275. return true;
  276. else if (qla_tgt_mode_enabled(vha) &&
  277. (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT))
  278. return true;
  279. else if (qla_dual_mode_enabled(vha) &&
  280. ((vha->ql2xiniexchg + vha->ql2xexchoffld) > FW_DEF_EXCHANGES_CNT))
  281. return true;
  282. else
  283. return false;
  284. }
  285. static inline void
  286. qla_cpu_update(struct qla_qpair *qpair, uint16_t cpuid)
  287. {
  288. qpair->cpuid = cpuid;
  289. if (!list_empty(&qpair->hints_list)) {
  290. struct qla_qpair_hint *h;
  291. list_for_each_entry(h, &qpair->hints_list, hint_elem)
  292. h->cpuid = qpair->cpuid;
  293. }
  294. }
  295. static inline struct qla_qpair_hint *
  296. qla_qpair_to_hint(struct qla_tgt *tgt, struct qla_qpair *qpair)
  297. {
  298. struct qla_qpair_hint *h;
  299. u16 i;
  300. for (i = 0; i < tgt->ha->max_qpairs + 1; i++) {
  301. h = &tgt->qphints[i];
  302. if (h->qpair == qpair)
  303. return h;
  304. }
  305. return NULL;
  306. }
  307. static inline void
  308. qla_83xx_start_iocbs(struct qla_qpair *qpair)
  309. {
  310. struct req_que *req = qpair->req;
  311. req->ring_index++;
  312. if (req->ring_index == req->length) {
  313. req->ring_index = 0;
  314. req->ring_ptr = req->ring;
  315. } else
  316. req->ring_ptr++;
  317. wrt_reg_dword(req->req_q_in, req->ring_index);
  318. }
  319. static inline int
  320. qla2xxx_get_fc4_priority(struct scsi_qla_host *vha)
  321. {
  322. uint32_t data;
  323. data =
  324. ((uint8_t *)vha->hw->nvram)[NVRAM_DUAL_FCP_NVME_FLAG_OFFSET];
  325. return (data >> 6) & BIT_0 ? FC4_PRIORITY_FCP : FC4_PRIORITY_NVME;
  326. }
  327. enum {
  328. RESOURCE_NONE,
  329. RESOURCE_IOCB = BIT_0,
  330. RESOURCE_EXCH = BIT_1, /* exchange */
  331. RESOURCE_FORCE = BIT_2,
  332. RESOURCE_HA = BIT_3,
  333. };
  334. static inline int
  335. qla_get_fw_resources(struct qla_qpair *qp, struct iocb_resource *iores)
  336. {
  337. u16 iocbs_used, i;
  338. u16 exch_used;
  339. struct qla_hw_data *ha = qp->hw;
  340. if (!ql2xenforce_iocb_limit) {
  341. iores->res_type = RESOURCE_NONE;
  342. return 0;
  343. }
  344. if (iores->res_type & RESOURCE_FORCE)
  345. goto force;
  346. if ((iores->iocb_cnt + qp->fwres.iocbs_used) >= qp->fwres.iocbs_qp_limit) {
  347. /* no need to acquire qpair lock. It's just rough calculation */
  348. iocbs_used = ha->base_qpair->fwres.iocbs_used;
  349. for (i = 0; i < ha->max_qpairs; i++) {
  350. if (ha->queue_pair_map[i])
  351. iocbs_used += ha->queue_pair_map[i]->fwres.iocbs_used;
  352. }
  353. if ((iores->iocb_cnt + iocbs_used) >= qp->fwres.iocbs_limit) {
  354. iores->res_type = RESOURCE_NONE;
  355. return -ENOSPC;
  356. }
  357. }
  358. if (iores->res_type & RESOURCE_EXCH) {
  359. exch_used = ha->base_qpair->fwres.exch_used;
  360. for (i = 0; i < ha->max_qpairs; i++) {
  361. if (ha->queue_pair_map[i])
  362. exch_used += ha->queue_pair_map[i]->fwres.exch_used;
  363. }
  364. if ((exch_used + iores->exch_cnt) >= qp->fwres.exch_limit) {
  365. iores->res_type = RESOURCE_NONE;
  366. return -ENOSPC;
  367. }
  368. }
  369. if (ql2xenforce_iocb_limit == 2) {
  370. if ((iores->iocb_cnt + atomic_read(&ha->fwres.iocb_used)) >=
  371. ha->fwres.iocb_limit) {
  372. iores->res_type = RESOURCE_NONE;
  373. return -ENOSPC;
  374. }
  375. if (iores->res_type & RESOURCE_EXCH) {
  376. if ((iores->exch_cnt + atomic_read(&ha->fwres.exch_used)) >=
  377. ha->fwres.exch_limit) {
  378. iores->res_type = RESOURCE_NONE;
  379. return -ENOSPC;
  380. }
  381. }
  382. }
  383. force:
  384. qp->fwres.iocbs_used += iores->iocb_cnt;
  385. qp->fwres.exch_used += iores->exch_cnt;
  386. if (ql2xenforce_iocb_limit == 2) {
  387. atomic_add(iores->iocb_cnt, &ha->fwres.iocb_used);
  388. atomic_add(iores->exch_cnt, &ha->fwres.exch_used);
  389. iores->res_type |= RESOURCE_HA;
  390. }
  391. return 0;
  392. }
  393. /*
  394. * decrement to zero. This routine will not decrement below zero
  395. * @v: pointer of type atomic_t
  396. * @amount: amount to decrement from v
  397. */
  398. static void qla_atomic_dtz(atomic_t *v, int amount)
  399. {
  400. int c, old, dec;
  401. c = atomic_read(v);
  402. for (;;) {
  403. dec = c - amount;
  404. if (unlikely(dec < 0))
  405. dec = 0;
  406. old = atomic_cmpxchg((v), c, dec);
  407. if (likely(old == c))
  408. break;
  409. c = old;
  410. }
  411. }
  412. static inline void
  413. qla_put_fw_resources(struct qla_qpair *qp, struct iocb_resource *iores)
  414. {
  415. struct qla_hw_data *ha = qp->hw;
  416. if (iores->res_type & RESOURCE_HA) {
  417. if (iores->res_type & RESOURCE_IOCB)
  418. qla_atomic_dtz(&ha->fwres.iocb_used, iores->iocb_cnt);
  419. if (iores->res_type & RESOURCE_EXCH)
  420. qla_atomic_dtz(&ha->fwres.exch_used, iores->exch_cnt);
  421. }
  422. if (iores->res_type & RESOURCE_IOCB) {
  423. if (qp->fwres.iocbs_used >= iores->iocb_cnt) {
  424. qp->fwres.iocbs_used -= iores->iocb_cnt;
  425. } else {
  426. /* should not happen */
  427. qp->fwres.iocbs_used = 0;
  428. }
  429. }
  430. if (iores->res_type & RESOURCE_EXCH) {
  431. if (qp->fwres.exch_used >= iores->exch_cnt) {
  432. qp->fwres.exch_used -= iores->exch_cnt;
  433. } else {
  434. /* should not happen */
  435. qp->fwres.exch_used = 0;
  436. }
  437. }
  438. iores->res_type = RESOURCE_NONE;
  439. }
  440. #define ISP_REG_DISCONNECT 0xffffffffU
  441. /**************************************************************************
  442. * qla2x00_isp_reg_stat
  443. *
  444. * Description:
  445. * Read the host status register of ISP before aborting the command.
  446. *
  447. * Input:
  448. * ha = pointer to host adapter structure.
  449. *
  450. *
  451. * Returns:
  452. * Either true or false.
  453. *
  454. * Note: Return true if there is register disconnect.
  455. **************************************************************************/
  456. static inline
  457. uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
  458. {
  459. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  460. struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
  461. if (IS_P3P_TYPE(ha))
  462. return ((rd_reg_dword(&reg82->host_int)) == ISP_REG_DISCONNECT);
  463. else
  464. return ((rd_reg_dword(&reg->host_status)) ==
  465. ISP_REG_DISCONNECT);
  466. }
  467. static inline
  468. bool qla_pci_disconnected(struct scsi_qla_host *vha,
  469. struct device_reg_24xx __iomem *reg)
  470. {
  471. uint32_t stat;
  472. bool ret = false;
  473. stat = rd_reg_dword(&reg->host_status);
  474. if (stat == 0xffffffff) {
  475. ql_log(ql_log_info, vha, 0x8041,
  476. "detected PCI disconnect.\n");
  477. qla_schedule_eeh_work(vha);
  478. ret = true;
  479. }
  480. return ret;
  481. }
  482. static inline bool
  483. fcport_is_smaller(fc_port_t *fcport)
  484. {
  485. if (wwn_to_u64(fcport->port_name) <
  486. wwn_to_u64(fcport->vha->port_name))
  487. return true;
  488. else
  489. return false;
  490. }
  491. static inline bool
  492. fcport_is_bigger(fc_port_t *fcport)
  493. {
  494. return !fcport_is_smaller(fcport);
  495. }
  496. static inline struct qla_qpair *
  497. qla_mapq_nvme_select_qpair(struct qla_hw_data *ha, struct qla_qpair *qpair)
  498. {
  499. int cpuid = raw_smp_processor_id();
  500. if (qpair->cpuid != cpuid &&
  501. ha->qp_cpu_map[cpuid]) {
  502. qpair = ha->qp_cpu_map[cpuid];
  503. }
  504. return qpair;
  505. }
  506. static inline void
  507. qla_mapq_init_qp_cpu_map(struct qla_hw_data *ha,
  508. struct qla_msix_entry *msix,
  509. struct qla_qpair *qpair)
  510. {
  511. const struct cpumask *mask;
  512. unsigned int cpu;
  513. if (!ha->qp_cpu_map)
  514. return;
  515. mask = pci_irq_get_affinity(ha->pdev, msix->vector_base0);
  516. if (!mask)
  517. return;
  518. qpair->cpuid = cpumask_first(mask);
  519. for_each_cpu(cpu, mask) {
  520. ha->qp_cpu_map[cpu] = qpair;
  521. }
  522. msix->cpuid = qpair->cpuid;
  523. qpair->cpu_mapped = true;
  524. }
  525. static inline void
  526. qla_mapq_free_qp_cpu_map(struct qla_hw_data *ha)
  527. {
  528. if (ha->qp_cpu_map) {
  529. kfree(ha->qp_cpu_map);
  530. ha->qp_cpu_map = NULL;
  531. }
  532. }
  533. static inline int qla_mapq_alloc_qp_cpu_map(struct qla_hw_data *ha)
  534. {
  535. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  536. if (!ha->qp_cpu_map) {
  537. ha->qp_cpu_map = kcalloc(NR_CPUS, sizeof(struct qla_qpair *),
  538. GFP_KERNEL);
  539. if (!ha->qp_cpu_map) {
  540. ql_log(ql_log_fatal, vha, 0x0180,
  541. "Unable to allocate memory for qp_cpu_map ptrs.\n");
  542. return -1;
  543. }
  544. }
  545. return 0;
  546. }