mv_sas.c 50 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Marvell 88SE64xx/88SE94xx main function
  4. *
  5. * Copyright 2007 Red Hat, Inc.
  6. * Copyright 2008 Marvell. <[email protected]>
  7. * Copyright 2009-2011 Marvell. <[email protected]>
  8. */
  9. #include "mv_sas.h"
  10. static int mvs_find_tag(struct mvs_info *mvi, struct sas_task *task, u32 *tag)
  11. {
  12. if (task->lldd_task) {
  13. struct mvs_slot_info *slot;
  14. slot = task->lldd_task;
  15. *tag = slot->slot_tag;
  16. return 1;
  17. }
  18. return 0;
  19. }
  20. void mvs_tag_clear(struct mvs_info *mvi, u32 tag)
  21. {
  22. void *bitmap = mvi->tags;
  23. clear_bit(tag, bitmap);
  24. }
  25. void mvs_tag_free(struct mvs_info *mvi, u32 tag)
  26. {
  27. mvs_tag_clear(mvi, tag);
  28. }
  29. void mvs_tag_set(struct mvs_info *mvi, unsigned int tag)
  30. {
  31. void *bitmap = mvi->tags;
  32. set_bit(tag, bitmap);
  33. }
  34. inline int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out)
  35. {
  36. unsigned int index, tag;
  37. void *bitmap = mvi->tags;
  38. index = find_first_zero_bit(bitmap, mvi->tags_num);
  39. tag = index;
  40. if (tag >= mvi->tags_num)
  41. return -SAS_QUEUE_FULL;
  42. mvs_tag_set(mvi, tag);
  43. *tag_out = tag;
  44. return 0;
  45. }
  46. void mvs_tag_init(struct mvs_info *mvi)
  47. {
  48. int i;
  49. for (i = 0; i < mvi->tags_num; ++i)
  50. mvs_tag_clear(mvi, i);
  51. }
  52. static struct mvs_info *mvs_find_dev_mvi(struct domain_device *dev)
  53. {
  54. unsigned long i = 0, j = 0, hi = 0;
  55. struct sas_ha_struct *sha = dev->port->ha;
  56. struct mvs_info *mvi = NULL;
  57. struct asd_sas_phy *phy;
  58. while (sha->sas_port[i]) {
  59. if (sha->sas_port[i] == dev->port) {
  60. spin_lock(&sha->sas_port[i]->phy_list_lock);
  61. phy = container_of(sha->sas_port[i]->phy_list.next,
  62. struct asd_sas_phy, port_phy_el);
  63. spin_unlock(&sha->sas_port[i]->phy_list_lock);
  64. j = 0;
  65. while (sha->sas_phy[j]) {
  66. if (sha->sas_phy[j] == phy)
  67. break;
  68. j++;
  69. }
  70. break;
  71. }
  72. i++;
  73. }
  74. hi = j/((struct mvs_prv_info *)sha->lldd_ha)->n_phy;
  75. mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[hi];
  76. return mvi;
  77. }
  78. static int mvs_find_dev_phyno(struct domain_device *dev, int *phyno)
  79. {
  80. unsigned long i = 0, j = 0, n = 0, num = 0;
  81. struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
  82. struct mvs_info *mvi = mvi_dev->mvi_info;
  83. struct sas_ha_struct *sha = dev->port->ha;
  84. while (sha->sas_port[i]) {
  85. if (sha->sas_port[i] == dev->port) {
  86. struct asd_sas_phy *phy;
  87. spin_lock(&sha->sas_port[i]->phy_list_lock);
  88. list_for_each_entry(phy,
  89. &sha->sas_port[i]->phy_list, port_phy_el) {
  90. j = 0;
  91. while (sha->sas_phy[j]) {
  92. if (sha->sas_phy[j] == phy)
  93. break;
  94. j++;
  95. }
  96. phyno[n] = (j >= mvi->chip->n_phy) ?
  97. (j - mvi->chip->n_phy) : j;
  98. num++;
  99. n++;
  100. }
  101. spin_unlock(&sha->sas_port[i]->phy_list_lock);
  102. break;
  103. }
  104. i++;
  105. }
  106. return num;
  107. }
  108. struct mvs_device *mvs_find_dev_by_reg_set(struct mvs_info *mvi,
  109. u8 reg_set)
  110. {
  111. u32 dev_no;
  112. for (dev_no = 0; dev_no < MVS_MAX_DEVICES; dev_no++) {
  113. if (mvi->devices[dev_no].taskfileset == MVS_ID_NOT_MAPPED)
  114. continue;
  115. if (mvi->devices[dev_no].taskfileset == reg_set)
  116. return &mvi->devices[dev_no];
  117. }
  118. return NULL;
  119. }
  120. static inline void mvs_free_reg_set(struct mvs_info *mvi,
  121. struct mvs_device *dev)
  122. {
  123. if (!dev) {
  124. mv_printk("device has been free.\n");
  125. return;
  126. }
  127. if (dev->taskfileset == MVS_ID_NOT_MAPPED)
  128. return;
  129. MVS_CHIP_DISP->free_reg_set(mvi, &dev->taskfileset);
  130. }
  131. static inline u8 mvs_assign_reg_set(struct mvs_info *mvi,
  132. struct mvs_device *dev)
  133. {
  134. if (dev->taskfileset != MVS_ID_NOT_MAPPED)
  135. return 0;
  136. return MVS_CHIP_DISP->assign_reg_set(mvi, &dev->taskfileset);
  137. }
  138. void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard)
  139. {
  140. u32 no;
  141. for_each_phy(phy_mask, phy_mask, no) {
  142. if (!(phy_mask & 1))
  143. continue;
  144. MVS_CHIP_DISP->phy_reset(mvi, no, hard);
  145. }
  146. }
  147. int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
  148. void *funcdata)
  149. {
  150. int rc = 0, phy_id = sas_phy->id;
  151. u32 tmp, i = 0, hi;
  152. struct sas_ha_struct *sha = sas_phy->ha;
  153. struct mvs_info *mvi = NULL;
  154. while (sha->sas_phy[i]) {
  155. if (sha->sas_phy[i] == sas_phy)
  156. break;
  157. i++;
  158. }
  159. hi = i/((struct mvs_prv_info *)sha->lldd_ha)->n_phy;
  160. mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[hi];
  161. switch (func) {
  162. case PHY_FUNC_SET_LINK_RATE:
  163. MVS_CHIP_DISP->phy_set_link_rate(mvi, phy_id, funcdata);
  164. break;
  165. case PHY_FUNC_HARD_RESET:
  166. tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_id);
  167. if (tmp & PHY_RST_HARD)
  168. break;
  169. MVS_CHIP_DISP->phy_reset(mvi, phy_id, MVS_HARD_RESET);
  170. break;
  171. case PHY_FUNC_LINK_RESET:
  172. MVS_CHIP_DISP->phy_enable(mvi, phy_id);
  173. MVS_CHIP_DISP->phy_reset(mvi, phy_id, MVS_SOFT_RESET);
  174. break;
  175. case PHY_FUNC_DISABLE:
  176. MVS_CHIP_DISP->phy_disable(mvi, phy_id);
  177. break;
  178. case PHY_FUNC_RELEASE_SPINUP_HOLD:
  179. default:
  180. rc = -ENOSYS;
  181. }
  182. msleep(200);
  183. return rc;
  184. }
  185. void mvs_set_sas_addr(struct mvs_info *mvi, int port_id, u32 off_lo,
  186. u32 off_hi, u64 sas_addr)
  187. {
  188. u32 lo = (u32)sas_addr;
  189. u32 hi = (u32)(sas_addr>>32);
  190. MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_lo);
  191. MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, lo);
  192. MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_hi);
  193. MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, hi);
  194. }
  195. static void mvs_bytes_dmaed(struct mvs_info *mvi, int i, gfp_t gfp_flags)
  196. {
  197. struct mvs_phy *phy = &mvi->phy[i];
  198. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  199. if (!phy->phy_attached)
  200. return;
  201. if (!(phy->att_dev_info & PORT_DEV_TRGT_MASK)
  202. && phy->phy_type & PORT_TYPE_SAS) {
  203. return;
  204. }
  205. sas_notify_phy_event(sas_phy, PHYE_OOB_DONE, gfp_flags);
  206. if (sas_phy->phy) {
  207. struct sas_phy *sphy = sas_phy->phy;
  208. sphy->negotiated_linkrate = sas_phy->linkrate;
  209. sphy->minimum_linkrate = phy->minimum_linkrate;
  210. sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
  211. sphy->maximum_linkrate = phy->maximum_linkrate;
  212. sphy->maximum_linkrate_hw = MVS_CHIP_DISP->phy_max_link_rate();
  213. }
  214. if (phy->phy_type & PORT_TYPE_SAS) {
  215. struct sas_identify_frame *id;
  216. id = (struct sas_identify_frame *)phy->frame_rcvd;
  217. id->dev_type = phy->identify.device_type;
  218. id->initiator_bits = SAS_PROTOCOL_ALL;
  219. id->target_bits = phy->identify.target_port_protocols;
  220. /* direct attached SAS device */
  221. if (phy->att_dev_info & PORT_SSP_TRGT_MASK) {
  222. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_PHY_STAT);
  223. MVS_CHIP_DISP->write_port_cfg_data(mvi, i, 0x00);
  224. }
  225. } else if (phy->phy_type & PORT_TYPE_SATA) {
  226. /*Nothing*/
  227. }
  228. mv_dprintk("phy %d byte dmaded.\n", i + mvi->id * mvi->chip->n_phy);
  229. sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
  230. sas_notify_port_event(sas_phy, PORTE_BYTES_DMAED, gfp_flags);
  231. }
  232. void mvs_scan_start(struct Scsi_Host *shost)
  233. {
  234. int i, j;
  235. unsigned short core_nr;
  236. struct mvs_info *mvi;
  237. struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
  238. struct mvs_prv_info *mvs_prv = sha->lldd_ha;
  239. core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
  240. for (j = 0; j < core_nr; j++) {
  241. mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j];
  242. for (i = 0; i < mvi->chip->n_phy; ++i)
  243. mvs_bytes_dmaed(mvi, i, GFP_KERNEL);
  244. }
  245. mvs_prv->scan_finished = 1;
  246. }
  247. int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time)
  248. {
  249. struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
  250. struct mvs_prv_info *mvs_prv = sha->lldd_ha;
  251. if (mvs_prv->scan_finished == 0)
  252. return 0;
  253. sas_drain_work(sha);
  254. return 1;
  255. }
  256. static int mvs_task_prep_smp(struct mvs_info *mvi,
  257. struct mvs_task_exec_info *tei)
  258. {
  259. int elem, rc, i;
  260. struct sas_ha_struct *sha = mvi->sas;
  261. struct sas_task *task = tei->task;
  262. struct mvs_cmd_hdr *hdr = tei->hdr;
  263. struct domain_device *dev = task->dev;
  264. struct asd_sas_port *sas_port = dev->port;
  265. struct sas_phy *sphy = dev->phy;
  266. struct asd_sas_phy *sas_phy = sha->sas_phy[sphy->number];
  267. struct scatterlist *sg_req, *sg_resp;
  268. u32 req_len, resp_len, tag = tei->tag;
  269. void *buf_tmp;
  270. u8 *buf_oaf;
  271. dma_addr_t buf_tmp_dma;
  272. void *buf_prd;
  273. struct mvs_slot_info *slot = &mvi->slot_info[tag];
  274. u32 flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
  275. /*
  276. * DMA-map SMP request, response buffers
  277. */
  278. sg_req = &task->smp_task.smp_req;
  279. elem = dma_map_sg(mvi->dev, sg_req, 1, DMA_TO_DEVICE);
  280. if (!elem)
  281. return -ENOMEM;
  282. req_len = sg_dma_len(sg_req);
  283. sg_resp = &task->smp_task.smp_resp;
  284. elem = dma_map_sg(mvi->dev, sg_resp, 1, DMA_FROM_DEVICE);
  285. if (!elem) {
  286. rc = -ENOMEM;
  287. goto err_out;
  288. }
  289. resp_len = SB_RFB_MAX;
  290. /* must be in dwords */
  291. if ((req_len & 0x3) || (resp_len & 0x3)) {
  292. rc = -EINVAL;
  293. goto err_out_2;
  294. }
  295. /*
  296. * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
  297. */
  298. /* region 1: command table area (MVS_SSP_CMD_SZ bytes) ***** */
  299. buf_tmp = slot->buf;
  300. buf_tmp_dma = slot->buf_dma;
  301. hdr->cmd_tbl = cpu_to_le64(sg_dma_address(sg_req));
  302. /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
  303. buf_oaf = buf_tmp;
  304. hdr->open_frame = cpu_to_le64(buf_tmp_dma);
  305. buf_tmp += MVS_OAF_SZ;
  306. buf_tmp_dma += MVS_OAF_SZ;
  307. /* region 3: PRD table *********************************** */
  308. buf_prd = buf_tmp;
  309. if (tei->n_elem)
  310. hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
  311. else
  312. hdr->prd_tbl = 0;
  313. i = MVS_CHIP_DISP->prd_size() * tei->n_elem;
  314. buf_tmp += i;
  315. buf_tmp_dma += i;
  316. /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
  317. slot->response = buf_tmp;
  318. hdr->status_buf = cpu_to_le64(buf_tmp_dma);
  319. if (mvi->flags & MVF_FLAG_SOC)
  320. hdr->reserved[0] = 0;
  321. /*
  322. * Fill in TX ring and command slot header
  323. */
  324. slot->tx = mvi->tx_prod;
  325. mvi->tx[mvi->tx_prod] = cpu_to_le32((TXQ_CMD_SMP << TXQ_CMD_SHIFT) |
  326. TXQ_MODE_I | tag |
  327. (MVS_PHY_ID << TXQ_PHY_SHIFT));
  328. hdr->flags |= flags;
  329. hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | ((req_len - 4) / 4));
  330. hdr->tags = cpu_to_le32(tag);
  331. hdr->data_len = 0;
  332. /* generate open address frame hdr (first 12 bytes) */
  333. /* initiator, SMP, ftype 1h */
  334. buf_oaf[0] = (1 << 7) | (PROTOCOL_SMP << 4) | 0x01;
  335. buf_oaf[1] = min(sas_port->linkrate, dev->linkrate) & 0xf;
  336. *(u16 *)(buf_oaf + 2) = 0xFFFF; /* SAS SPEC */
  337. memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
  338. /* fill in PRD (scatter/gather) table, if any */
  339. MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
  340. return 0;
  341. err_out_2:
  342. dma_unmap_sg(mvi->dev, &tei->task->smp_task.smp_resp, 1,
  343. DMA_FROM_DEVICE);
  344. err_out:
  345. dma_unmap_sg(mvi->dev, &tei->task->smp_task.smp_req, 1,
  346. DMA_TO_DEVICE);
  347. return rc;
  348. }
  349. static u32 mvs_get_ncq_tag(struct sas_task *task, u32 *tag)
  350. {
  351. struct ata_queued_cmd *qc = task->uldd_task;
  352. if (qc) {
  353. if (qc->tf.command == ATA_CMD_FPDMA_WRITE ||
  354. qc->tf.command == ATA_CMD_FPDMA_READ ||
  355. qc->tf.command == ATA_CMD_FPDMA_RECV ||
  356. qc->tf.command == ATA_CMD_FPDMA_SEND ||
  357. qc->tf.command == ATA_CMD_NCQ_NON_DATA) {
  358. *tag = qc->tag;
  359. return 1;
  360. }
  361. }
  362. return 0;
  363. }
  364. static int mvs_task_prep_ata(struct mvs_info *mvi,
  365. struct mvs_task_exec_info *tei)
  366. {
  367. struct sas_task *task = tei->task;
  368. struct domain_device *dev = task->dev;
  369. struct mvs_device *mvi_dev = dev->lldd_dev;
  370. struct mvs_cmd_hdr *hdr = tei->hdr;
  371. struct asd_sas_port *sas_port = dev->port;
  372. struct mvs_slot_info *slot;
  373. void *buf_prd;
  374. u32 tag = tei->tag, hdr_tag;
  375. u32 flags, del_q;
  376. void *buf_tmp;
  377. u8 *buf_cmd, *buf_oaf;
  378. dma_addr_t buf_tmp_dma;
  379. u32 i, req_len, resp_len;
  380. const u32 max_resp_len = SB_RFB_MAX;
  381. if (mvs_assign_reg_set(mvi, mvi_dev) == MVS_ID_NOT_MAPPED) {
  382. mv_dprintk("Have not enough regiset for dev %d.\n",
  383. mvi_dev->device_id);
  384. return -EBUSY;
  385. }
  386. slot = &mvi->slot_info[tag];
  387. slot->tx = mvi->tx_prod;
  388. del_q = TXQ_MODE_I | tag |
  389. (TXQ_CMD_STP << TXQ_CMD_SHIFT) |
  390. ((sas_port->phy_mask & TXQ_PHY_MASK) << TXQ_PHY_SHIFT) |
  391. (mvi_dev->taskfileset << TXQ_SRS_SHIFT);
  392. mvi->tx[mvi->tx_prod] = cpu_to_le32(del_q);
  393. if (task->data_dir == DMA_FROM_DEVICE)
  394. flags = (MVS_CHIP_DISP->prd_count() << MCH_PRD_LEN_SHIFT);
  395. else
  396. flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
  397. if (task->ata_task.use_ncq)
  398. flags |= MCH_FPDMA;
  399. if (dev->sata_dev.class == ATA_DEV_ATAPI) {
  400. if (task->ata_task.fis.command != ATA_CMD_ID_ATAPI)
  401. flags |= MCH_ATAPI;
  402. }
  403. hdr->flags = cpu_to_le32(flags);
  404. if (task->ata_task.use_ncq && mvs_get_ncq_tag(task, &hdr_tag))
  405. task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
  406. else
  407. hdr_tag = tag;
  408. hdr->tags = cpu_to_le32(hdr_tag);
  409. hdr->data_len = cpu_to_le32(task->total_xfer_len);
  410. /*
  411. * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
  412. */
  413. /* region 1: command table area (MVS_ATA_CMD_SZ bytes) ************** */
  414. buf_cmd = buf_tmp = slot->buf;
  415. buf_tmp_dma = slot->buf_dma;
  416. hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
  417. buf_tmp += MVS_ATA_CMD_SZ;
  418. buf_tmp_dma += MVS_ATA_CMD_SZ;
  419. /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
  420. /* used for STP. unused for SATA? */
  421. buf_oaf = buf_tmp;
  422. hdr->open_frame = cpu_to_le64(buf_tmp_dma);
  423. buf_tmp += MVS_OAF_SZ;
  424. buf_tmp_dma += MVS_OAF_SZ;
  425. /* region 3: PRD table ********************************************* */
  426. buf_prd = buf_tmp;
  427. if (tei->n_elem)
  428. hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
  429. else
  430. hdr->prd_tbl = 0;
  431. i = MVS_CHIP_DISP->prd_size() * MVS_CHIP_DISP->prd_count();
  432. buf_tmp += i;
  433. buf_tmp_dma += i;
  434. /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
  435. slot->response = buf_tmp;
  436. hdr->status_buf = cpu_to_le64(buf_tmp_dma);
  437. if (mvi->flags & MVF_FLAG_SOC)
  438. hdr->reserved[0] = 0;
  439. req_len = sizeof(struct host_to_dev_fis);
  440. resp_len = MVS_SLOT_BUF_SZ - MVS_ATA_CMD_SZ -
  441. sizeof(struct mvs_err_info) - i;
  442. /* request, response lengths */
  443. resp_len = min(resp_len, max_resp_len);
  444. hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | (req_len / 4));
  445. if (likely(!task->ata_task.device_control_reg_update))
  446. task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
  447. /* fill in command FIS and ATAPI CDB */
  448. memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
  449. if (dev->sata_dev.class == ATA_DEV_ATAPI)
  450. memcpy(buf_cmd + STP_ATAPI_CMD,
  451. task->ata_task.atapi_packet, 16);
  452. /* generate open address frame hdr (first 12 bytes) */
  453. /* initiator, STP, ftype 1h */
  454. buf_oaf[0] = (1 << 7) | (PROTOCOL_STP << 4) | 0x1;
  455. buf_oaf[1] = min(sas_port->linkrate, dev->linkrate) & 0xf;
  456. *(u16 *)(buf_oaf + 2) = cpu_to_be16(mvi_dev->device_id + 1);
  457. memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
  458. /* fill in PRD (scatter/gather) table, if any */
  459. MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
  460. if (task->data_dir == DMA_FROM_DEVICE)
  461. MVS_CHIP_DISP->dma_fix(mvi, sas_port->phy_mask,
  462. TRASH_BUCKET_SIZE, tei->n_elem, buf_prd);
  463. return 0;
  464. }
  465. static int mvs_task_prep_ssp(struct mvs_info *mvi,
  466. struct mvs_task_exec_info *tei, int is_tmf,
  467. struct sas_tmf_task *tmf)
  468. {
  469. struct sas_task *task = tei->task;
  470. struct mvs_cmd_hdr *hdr = tei->hdr;
  471. struct mvs_port *port = tei->port;
  472. struct domain_device *dev = task->dev;
  473. struct mvs_device *mvi_dev = dev->lldd_dev;
  474. struct asd_sas_port *sas_port = dev->port;
  475. struct mvs_slot_info *slot;
  476. void *buf_prd;
  477. struct ssp_frame_hdr *ssp_hdr;
  478. void *buf_tmp;
  479. u8 *buf_cmd, *buf_oaf, fburst = 0;
  480. dma_addr_t buf_tmp_dma;
  481. u32 flags;
  482. u32 resp_len, req_len, i, tag = tei->tag;
  483. const u32 max_resp_len = SB_RFB_MAX;
  484. u32 phy_mask;
  485. slot = &mvi->slot_info[tag];
  486. phy_mask = ((port->wide_port_phymap) ? port->wide_port_phymap :
  487. sas_port->phy_mask) & TXQ_PHY_MASK;
  488. slot->tx = mvi->tx_prod;
  489. mvi->tx[mvi->tx_prod] = cpu_to_le32(TXQ_MODE_I | tag |
  490. (TXQ_CMD_SSP << TXQ_CMD_SHIFT) |
  491. (phy_mask << TXQ_PHY_SHIFT));
  492. flags = MCH_RETRY;
  493. if (task->ssp_task.enable_first_burst) {
  494. flags |= MCH_FBURST;
  495. fburst = (1 << 7);
  496. }
  497. if (is_tmf)
  498. flags |= (MCH_SSP_FR_TASK << MCH_SSP_FR_TYPE_SHIFT);
  499. else
  500. flags |= (MCH_SSP_FR_CMD << MCH_SSP_FR_TYPE_SHIFT);
  501. hdr->flags = cpu_to_le32(flags | (tei->n_elem << MCH_PRD_LEN_SHIFT));
  502. hdr->tags = cpu_to_le32(tag);
  503. hdr->data_len = cpu_to_le32(task->total_xfer_len);
  504. /*
  505. * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
  506. */
  507. /* region 1: command table area (MVS_SSP_CMD_SZ bytes) ************** */
  508. buf_cmd = buf_tmp = slot->buf;
  509. buf_tmp_dma = slot->buf_dma;
  510. hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
  511. buf_tmp += MVS_SSP_CMD_SZ;
  512. buf_tmp_dma += MVS_SSP_CMD_SZ;
  513. /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
  514. buf_oaf = buf_tmp;
  515. hdr->open_frame = cpu_to_le64(buf_tmp_dma);
  516. buf_tmp += MVS_OAF_SZ;
  517. buf_tmp_dma += MVS_OAF_SZ;
  518. /* region 3: PRD table ********************************************* */
  519. buf_prd = buf_tmp;
  520. if (tei->n_elem)
  521. hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
  522. else
  523. hdr->prd_tbl = 0;
  524. i = MVS_CHIP_DISP->prd_size() * tei->n_elem;
  525. buf_tmp += i;
  526. buf_tmp_dma += i;
  527. /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
  528. slot->response = buf_tmp;
  529. hdr->status_buf = cpu_to_le64(buf_tmp_dma);
  530. if (mvi->flags & MVF_FLAG_SOC)
  531. hdr->reserved[0] = 0;
  532. resp_len = MVS_SLOT_BUF_SZ - MVS_SSP_CMD_SZ - MVS_OAF_SZ -
  533. sizeof(struct mvs_err_info) - i;
  534. resp_len = min(resp_len, max_resp_len);
  535. req_len = sizeof(struct ssp_frame_hdr) + 28;
  536. /* request, response lengths */
  537. hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | (req_len / 4));
  538. /* generate open address frame hdr (first 12 bytes) */
  539. /* initiator, SSP, ftype 1h */
  540. buf_oaf[0] = (1 << 7) | (PROTOCOL_SSP << 4) | 0x1;
  541. buf_oaf[1] = min(sas_port->linkrate, dev->linkrate) & 0xf;
  542. *(u16 *)(buf_oaf + 2) = cpu_to_be16(mvi_dev->device_id + 1);
  543. memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
  544. /* fill in SSP frame header (Command Table.SSP frame header) */
  545. ssp_hdr = (struct ssp_frame_hdr *)buf_cmd;
  546. if (is_tmf)
  547. ssp_hdr->frame_type = SSP_TASK;
  548. else
  549. ssp_hdr->frame_type = SSP_COMMAND;
  550. memcpy(ssp_hdr->hashed_dest_addr, dev->hashed_sas_addr,
  551. HASHED_SAS_ADDR_SIZE);
  552. memcpy(ssp_hdr->hashed_src_addr,
  553. dev->hashed_sas_addr, HASHED_SAS_ADDR_SIZE);
  554. ssp_hdr->tag = cpu_to_be16(tag);
  555. /* fill in IU for TASK and Command Frame */
  556. buf_cmd += sizeof(*ssp_hdr);
  557. memcpy(buf_cmd, &task->ssp_task.LUN, 8);
  558. if (ssp_hdr->frame_type != SSP_TASK) {
  559. buf_cmd[9] = fburst | task->ssp_task.task_attr |
  560. (task->ssp_task.task_prio << 3);
  561. memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
  562. task->ssp_task.cmd->cmd_len);
  563. } else{
  564. buf_cmd[10] = tmf->tmf;
  565. switch (tmf->tmf) {
  566. case TMF_ABORT_TASK:
  567. case TMF_QUERY_TASK:
  568. buf_cmd[12] =
  569. (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
  570. buf_cmd[13] =
  571. tmf->tag_of_task_to_be_managed & 0xff;
  572. break;
  573. default:
  574. break;
  575. }
  576. }
  577. /* fill in PRD (scatter/gather) table, if any */
  578. MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
  579. return 0;
  580. }
  581. #define DEV_IS_GONE(mvi_dev) ((!mvi_dev || (mvi_dev->dev_type == SAS_PHY_UNUSED)))
  582. static int mvs_task_prep(struct sas_task *task, struct mvs_info *mvi, int is_tmf,
  583. struct sas_tmf_task *tmf, int *pass)
  584. {
  585. struct domain_device *dev = task->dev;
  586. struct mvs_device *mvi_dev = dev->lldd_dev;
  587. struct mvs_task_exec_info tei;
  588. struct mvs_slot_info *slot;
  589. u32 tag = 0xdeadbeef, n_elem = 0;
  590. int rc = 0;
  591. if (!dev->port) {
  592. struct task_status_struct *tsm = &task->task_status;
  593. tsm->resp = SAS_TASK_UNDELIVERED;
  594. tsm->stat = SAS_PHY_DOWN;
  595. /*
  596. * libsas will use dev->port, should
  597. * not call task_done for sata
  598. */
  599. if (dev->dev_type != SAS_SATA_DEV)
  600. task->task_done(task);
  601. return rc;
  602. }
  603. if (DEV_IS_GONE(mvi_dev)) {
  604. if (mvi_dev)
  605. mv_dprintk("device %d not ready.\n",
  606. mvi_dev->device_id);
  607. else
  608. mv_dprintk("device %016llx not ready.\n",
  609. SAS_ADDR(dev->sas_addr));
  610. rc = SAS_PHY_DOWN;
  611. return rc;
  612. }
  613. tei.port = dev->port->lldd_port;
  614. if (tei.port && !tei.port->port_attached && !tmf) {
  615. if (sas_protocol_ata(task->task_proto)) {
  616. struct task_status_struct *ts = &task->task_status;
  617. mv_dprintk("SATA/STP port %d does not attach"
  618. "device.\n", dev->port->id);
  619. ts->resp = SAS_TASK_COMPLETE;
  620. ts->stat = SAS_PHY_DOWN;
  621. task->task_done(task);
  622. } else {
  623. struct task_status_struct *ts = &task->task_status;
  624. mv_dprintk("SAS port %d does not attach"
  625. "device.\n", dev->port->id);
  626. ts->resp = SAS_TASK_UNDELIVERED;
  627. ts->stat = SAS_PHY_DOWN;
  628. task->task_done(task);
  629. }
  630. return rc;
  631. }
  632. if (!sas_protocol_ata(task->task_proto)) {
  633. if (task->num_scatter) {
  634. n_elem = dma_map_sg(mvi->dev,
  635. task->scatter,
  636. task->num_scatter,
  637. task->data_dir);
  638. if (!n_elem) {
  639. rc = -ENOMEM;
  640. goto prep_out;
  641. }
  642. }
  643. } else {
  644. n_elem = task->num_scatter;
  645. }
  646. rc = mvs_tag_alloc(mvi, &tag);
  647. if (rc)
  648. goto err_out;
  649. slot = &mvi->slot_info[tag];
  650. task->lldd_task = NULL;
  651. slot->n_elem = n_elem;
  652. slot->slot_tag = tag;
  653. slot->buf = dma_pool_zalloc(mvi->dma_pool, GFP_ATOMIC, &slot->buf_dma);
  654. if (!slot->buf) {
  655. rc = -ENOMEM;
  656. goto err_out_tag;
  657. }
  658. tei.task = task;
  659. tei.hdr = &mvi->slot[tag];
  660. tei.tag = tag;
  661. tei.n_elem = n_elem;
  662. switch (task->task_proto) {
  663. case SAS_PROTOCOL_SMP:
  664. rc = mvs_task_prep_smp(mvi, &tei);
  665. break;
  666. case SAS_PROTOCOL_SSP:
  667. rc = mvs_task_prep_ssp(mvi, &tei, is_tmf, tmf);
  668. break;
  669. case SAS_PROTOCOL_SATA:
  670. case SAS_PROTOCOL_STP:
  671. case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
  672. rc = mvs_task_prep_ata(mvi, &tei);
  673. break;
  674. default:
  675. dev_printk(KERN_ERR, mvi->dev,
  676. "unknown sas_task proto: 0x%x\n",
  677. task->task_proto);
  678. rc = -EINVAL;
  679. break;
  680. }
  681. if (rc) {
  682. mv_dprintk("rc is %x\n", rc);
  683. goto err_out_slot_buf;
  684. }
  685. slot->task = task;
  686. slot->port = tei.port;
  687. task->lldd_task = slot;
  688. list_add_tail(&slot->entry, &tei.port->list);
  689. mvi_dev->running_req++;
  690. ++(*pass);
  691. mvi->tx_prod = (mvi->tx_prod + 1) & (MVS_CHIP_SLOT_SZ - 1);
  692. return rc;
  693. err_out_slot_buf:
  694. dma_pool_free(mvi->dma_pool, slot->buf, slot->buf_dma);
  695. err_out_tag:
  696. mvs_tag_free(mvi, tag);
  697. err_out:
  698. dev_printk(KERN_ERR, mvi->dev, "mvsas prep failed[%d]!\n", rc);
  699. if (!sas_protocol_ata(task->task_proto))
  700. if (n_elem)
  701. dma_unmap_sg(mvi->dev, task->scatter, n_elem,
  702. task->data_dir);
  703. prep_out:
  704. return rc;
  705. }
  706. int mvs_queue_command(struct sas_task *task, gfp_t gfp_flags)
  707. {
  708. struct mvs_info *mvi = NULL;
  709. u32 rc = 0;
  710. u32 pass = 0;
  711. unsigned long flags = 0;
  712. struct sas_tmf_task *tmf = task->tmf;
  713. int is_tmf = !!task->tmf;
  714. mvi = ((struct mvs_device *)task->dev->lldd_dev)->mvi_info;
  715. spin_lock_irqsave(&mvi->lock, flags);
  716. rc = mvs_task_prep(task, mvi, is_tmf, tmf, &pass);
  717. if (rc)
  718. dev_printk(KERN_ERR, mvi->dev, "mvsas exec failed[%d]!\n", rc);
  719. if (likely(pass))
  720. MVS_CHIP_DISP->start_delivery(mvi, (mvi->tx_prod - 1) &
  721. (MVS_CHIP_SLOT_SZ - 1));
  722. spin_unlock_irqrestore(&mvi->lock, flags);
  723. return rc;
  724. }
  725. static void mvs_slot_free(struct mvs_info *mvi, u32 rx_desc)
  726. {
  727. u32 slot_idx = rx_desc & RXQ_SLOT_MASK;
  728. mvs_tag_clear(mvi, slot_idx);
  729. }
  730. static void mvs_slot_task_free(struct mvs_info *mvi, struct sas_task *task,
  731. struct mvs_slot_info *slot, u32 slot_idx)
  732. {
  733. if (!slot)
  734. return;
  735. if (!slot->task)
  736. return;
  737. if (!sas_protocol_ata(task->task_proto))
  738. if (slot->n_elem)
  739. dma_unmap_sg(mvi->dev, task->scatter,
  740. slot->n_elem, task->data_dir);
  741. switch (task->task_proto) {
  742. case SAS_PROTOCOL_SMP:
  743. dma_unmap_sg(mvi->dev, &task->smp_task.smp_resp, 1,
  744. DMA_FROM_DEVICE);
  745. dma_unmap_sg(mvi->dev, &task->smp_task.smp_req, 1,
  746. DMA_TO_DEVICE);
  747. break;
  748. case SAS_PROTOCOL_SATA:
  749. case SAS_PROTOCOL_STP:
  750. case SAS_PROTOCOL_SSP:
  751. default:
  752. /* do nothing */
  753. break;
  754. }
  755. if (slot->buf) {
  756. dma_pool_free(mvi->dma_pool, slot->buf, slot->buf_dma);
  757. slot->buf = NULL;
  758. }
  759. list_del_init(&slot->entry);
  760. task->lldd_task = NULL;
  761. slot->task = NULL;
  762. slot->port = NULL;
  763. slot->slot_tag = 0xFFFFFFFF;
  764. mvs_slot_free(mvi, slot_idx);
  765. }
  766. static void mvs_update_wideport(struct mvs_info *mvi, int phy_no)
  767. {
  768. struct mvs_phy *phy = &mvi->phy[phy_no];
  769. struct mvs_port *port = phy->port;
  770. int j, no;
  771. for_each_phy(port->wide_port_phymap, j, no) {
  772. if (j & 1) {
  773. MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,
  774. PHYR_WIDE_PORT);
  775. MVS_CHIP_DISP->write_port_cfg_data(mvi, no,
  776. port->wide_port_phymap);
  777. } else {
  778. MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,
  779. PHYR_WIDE_PORT);
  780. MVS_CHIP_DISP->write_port_cfg_data(mvi, no,
  781. 0);
  782. }
  783. }
  784. }
  785. static u32 mvs_is_phy_ready(struct mvs_info *mvi, int i)
  786. {
  787. u32 tmp;
  788. struct mvs_phy *phy = &mvi->phy[i];
  789. struct mvs_port *port = phy->port;
  790. tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, i);
  791. if ((tmp & PHY_READY_MASK) && !(phy->irq_status & PHYEV_POOF)) {
  792. if (!port)
  793. phy->phy_attached = 1;
  794. return tmp;
  795. }
  796. if (port) {
  797. if (phy->phy_type & PORT_TYPE_SAS) {
  798. port->wide_port_phymap &= ~(1U << i);
  799. if (!port->wide_port_phymap)
  800. port->port_attached = 0;
  801. mvs_update_wideport(mvi, i);
  802. } else if (phy->phy_type & PORT_TYPE_SATA)
  803. port->port_attached = 0;
  804. phy->port = NULL;
  805. phy->phy_attached = 0;
  806. phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
  807. }
  808. return 0;
  809. }
  810. static void *mvs_get_d2h_reg(struct mvs_info *mvi, int i, void *buf)
  811. {
  812. u32 *s = (u32 *) buf;
  813. if (!s)
  814. return NULL;
  815. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG3);
  816. s[3] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
  817. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG2);
  818. s[2] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
  819. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG1);
  820. s[1] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
  821. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG0);
  822. s[0] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
  823. if (((s[1] & 0x00FFFFFF) == 0x00EB1401) && (*(u8 *)&s[3] == 0x01))
  824. s[1] = 0x00EB1401 | (*((u8 *)&s[1] + 3) & 0x10);
  825. return s;
  826. }
  827. static u32 mvs_is_sig_fis_received(u32 irq_status)
  828. {
  829. return irq_status & PHYEV_SIG_FIS;
  830. }
  831. static void mvs_sig_remove_timer(struct mvs_phy *phy)
  832. {
  833. if (phy->timer.function)
  834. del_timer(&phy->timer);
  835. phy->timer.function = NULL;
  836. }
  837. void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st)
  838. {
  839. struct mvs_phy *phy = &mvi->phy[i];
  840. struct sas_identify_frame *id;
  841. id = (struct sas_identify_frame *)phy->frame_rcvd;
  842. if (get_st) {
  843. phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, i);
  844. phy->phy_status = mvs_is_phy_ready(mvi, i);
  845. }
  846. if (phy->phy_status) {
  847. int oob_done = 0;
  848. struct asd_sas_phy *sas_phy = &mvi->phy[i].sas_phy;
  849. oob_done = MVS_CHIP_DISP->oob_done(mvi, i);
  850. MVS_CHIP_DISP->fix_phy_info(mvi, i, id);
  851. if (phy->phy_type & PORT_TYPE_SATA) {
  852. phy->identify.target_port_protocols = SAS_PROTOCOL_STP;
  853. if (mvs_is_sig_fis_received(phy->irq_status)) {
  854. mvs_sig_remove_timer(phy);
  855. phy->phy_attached = 1;
  856. phy->att_dev_sas_addr =
  857. i + mvi->id * mvi->chip->n_phy;
  858. if (oob_done)
  859. sas_phy->oob_mode = SATA_OOB_MODE;
  860. phy->frame_rcvd_size =
  861. sizeof(struct dev_to_host_fis);
  862. mvs_get_d2h_reg(mvi, i, id);
  863. } else {
  864. u32 tmp;
  865. dev_printk(KERN_DEBUG, mvi->dev,
  866. "Phy%d : No sig fis\n", i);
  867. tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, i);
  868. MVS_CHIP_DISP->write_port_irq_mask(mvi, i,
  869. tmp | PHYEV_SIG_FIS);
  870. phy->phy_attached = 0;
  871. phy->phy_type &= ~PORT_TYPE_SATA;
  872. goto out_done;
  873. }
  874. } else if (phy->phy_type & PORT_TYPE_SAS
  875. || phy->att_dev_info & PORT_SSP_INIT_MASK) {
  876. phy->phy_attached = 1;
  877. phy->identify.device_type =
  878. phy->att_dev_info & PORT_DEV_TYPE_MASK;
  879. if (phy->identify.device_type == SAS_END_DEVICE)
  880. phy->identify.target_port_protocols =
  881. SAS_PROTOCOL_SSP;
  882. else if (phy->identify.device_type != SAS_PHY_UNUSED)
  883. phy->identify.target_port_protocols =
  884. SAS_PROTOCOL_SMP;
  885. if (oob_done)
  886. sas_phy->oob_mode = SAS_OOB_MODE;
  887. phy->frame_rcvd_size =
  888. sizeof(struct sas_identify_frame);
  889. }
  890. memcpy(sas_phy->attached_sas_addr,
  891. &phy->att_dev_sas_addr, SAS_ADDR_SIZE);
  892. if (MVS_CHIP_DISP->phy_work_around)
  893. MVS_CHIP_DISP->phy_work_around(mvi, i);
  894. }
  895. mv_dprintk("phy %d attach dev info is %x\n",
  896. i + mvi->id * mvi->chip->n_phy, phy->att_dev_info);
  897. mv_dprintk("phy %d attach sas addr is %llx\n",
  898. i + mvi->id * mvi->chip->n_phy, phy->att_dev_sas_addr);
  899. out_done:
  900. if (get_st)
  901. MVS_CHIP_DISP->write_port_irq_stat(mvi, i, phy->irq_status);
  902. }
  903. static void mvs_port_notify_formed(struct asd_sas_phy *sas_phy, int lock)
  904. {
  905. struct sas_ha_struct *sas_ha = sas_phy->ha;
  906. struct mvs_info *mvi = NULL; int i = 0, hi;
  907. struct mvs_phy *phy = sas_phy->lldd_phy;
  908. struct asd_sas_port *sas_port = sas_phy->port;
  909. struct mvs_port *port;
  910. unsigned long flags = 0;
  911. if (!sas_port)
  912. return;
  913. while (sas_ha->sas_phy[i]) {
  914. if (sas_ha->sas_phy[i] == sas_phy)
  915. break;
  916. i++;
  917. }
  918. hi = i/((struct mvs_prv_info *)sas_ha->lldd_ha)->n_phy;
  919. mvi = ((struct mvs_prv_info *)sas_ha->lldd_ha)->mvi[hi];
  920. if (i >= mvi->chip->n_phy)
  921. port = &mvi->port[i - mvi->chip->n_phy];
  922. else
  923. port = &mvi->port[i];
  924. if (lock)
  925. spin_lock_irqsave(&mvi->lock, flags);
  926. port->port_attached = 1;
  927. phy->port = port;
  928. sas_port->lldd_port = port;
  929. if (phy->phy_type & PORT_TYPE_SAS) {
  930. port->wide_port_phymap = sas_port->phy_mask;
  931. mv_printk("set wide port phy map %x\n", sas_port->phy_mask);
  932. mvs_update_wideport(mvi, sas_phy->id);
  933. /* direct attached SAS device */
  934. if (phy->att_dev_info & PORT_SSP_TRGT_MASK) {
  935. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_PHY_STAT);
  936. MVS_CHIP_DISP->write_port_cfg_data(mvi, i, 0x04);
  937. }
  938. }
  939. if (lock)
  940. spin_unlock_irqrestore(&mvi->lock, flags);
  941. }
  942. static void mvs_port_notify_deformed(struct asd_sas_phy *sas_phy, int lock)
  943. {
  944. struct domain_device *dev;
  945. struct mvs_phy *phy = sas_phy->lldd_phy;
  946. struct mvs_info *mvi = phy->mvi;
  947. struct asd_sas_port *port = sas_phy->port;
  948. int phy_no = 0;
  949. while (phy != &mvi->phy[phy_no]) {
  950. phy_no++;
  951. if (phy_no >= MVS_MAX_PHYS)
  952. return;
  953. }
  954. list_for_each_entry(dev, &port->dev_list, dev_list_node)
  955. mvs_do_release_task(phy->mvi, phy_no, dev);
  956. }
  957. void mvs_port_formed(struct asd_sas_phy *sas_phy)
  958. {
  959. mvs_port_notify_formed(sas_phy, 1);
  960. }
  961. void mvs_port_deformed(struct asd_sas_phy *sas_phy)
  962. {
  963. mvs_port_notify_deformed(sas_phy, 1);
  964. }
  965. static struct mvs_device *mvs_alloc_dev(struct mvs_info *mvi)
  966. {
  967. u32 dev;
  968. for (dev = 0; dev < MVS_MAX_DEVICES; dev++) {
  969. if (mvi->devices[dev].dev_type == SAS_PHY_UNUSED) {
  970. mvi->devices[dev].device_id = dev;
  971. return &mvi->devices[dev];
  972. }
  973. }
  974. if (dev == MVS_MAX_DEVICES)
  975. mv_printk("max support %d devices, ignore ..\n",
  976. MVS_MAX_DEVICES);
  977. return NULL;
  978. }
  979. static void mvs_free_dev(struct mvs_device *mvi_dev)
  980. {
  981. u32 id = mvi_dev->device_id;
  982. memset(mvi_dev, 0, sizeof(*mvi_dev));
  983. mvi_dev->device_id = id;
  984. mvi_dev->dev_type = SAS_PHY_UNUSED;
  985. mvi_dev->dev_status = MVS_DEV_NORMAL;
  986. mvi_dev->taskfileset = MVS_ID_NOT_MAPPED;
  987. }
  988. static int mvs_dev_found_notify(struct domain_device *dev, int lock)
  989. {
  990. unsigned long flags = 0;
  991. int res = 0;
  992. struct mvs_info *mvi = NULL;
  993. struct domain_device *parent_dev = dev->parent;
  994. struct mvs_device *mvi_device;
  995. mvi = mvs_find_dev_mvi(dev);
  996. if (lock)
  997. spin_lock_irqsave(&mvi->lock, flags);
  998. mvi_device = mvs_alloc_dev(mvi);
  999. if (!mvi_device) {
  1000. res = -1;
  1001. goto found_out;
  1002. }
  1003. dev->lldd_dev = mvi_device;
  1004. mvi_device->dev_status = MVS_DEV_NORMAL;
  1005. mvi_device->dev_type = dev->dev_type;
  1006. mvi_device->mvi_info = mvi;
  1007. mvi_device->sas_device = dev;
  1008. if (parent_dev && dev_is_expander(parent_dev->dev_type)) {
  1009. int phy_id;
  1010. u8 phy_num = parent_dev->ex_dev.num_phys;
  1011. struct ex_phy *phy;
  1012. for (phy_id = 0; phy_id < phy_num; phy_id++) {
  1013. phy = &parent_dev->ex_dev.ex_phy[phy_id];
  1014. if (SAS_ADDR(phy->attached_sas_addr) ==
  1015. SAS_ADDR(dev->sas_addr)) {
  1016. mvi_device->attached_phy = phy_id;
  1017. break;
  1018. }
  1019. }
  1020. if (phy_id == phy_num) {
  1021. mv_printk("Error: no attached dev:%016llx"
  1022. "at ex:%016llx.\n",
  1023. SAS_ADDR(dev->sas_addr),
  1024. SAS_ADDR(parent_dev->sas_addr));
  1025. res = -1;
  1026. }
  1027. }
  1028. found_out:
  1029. if (lock)
  1030. spin_unlock_irqrestore(&mvi->lock, flags);
  1031. return res;
  1032. }
  1033. int mvs_dev_found(struct domain_device *dev)
  1034. {
  1035. return mvs_dev_found_notify(dev, 1);
  1036. }
  1037. static void mvs_dev_gone_notify(struct domain_device *dev)
  1038. {
  1039. unsigned long flags = 0;
  1040. struct mvs_device *mvi_dev = dev->lldd_dev;
  1041. struct mvs_info *mvi;
  1042. if (!mvi_dev) {
  1043. mv_dprintk("found dev has gone.\n");
  1044. return;
  1045. }
  1046. mvi = mvi_dev->mvi_info;
  1047. spin_lock_irqsave(&mvi->lock, flags);
  1048. mv_dprintk("found dev[%d:%x] is gone.\n",
  1049. mvi_dev->device_id, mvi_dev->dev_type);
  1050. mvs_release_task(mvi, dev);
  1051. mvs_free_reg_set(mvi, mvi_dev);
  1052. mvs_free_dev(mvi_dev);
  1053. dev->lldd_dev = NULL;
  1054. mvi_dev->sas_device = NULL;
  1055. spin_unlock_irqrestore(&mvi->lock, flags);
  1056. }
  1057. void mvs_dev_gone(struct domain_device *dev)
  1058. {
  1059. mvs_dev_gone_notify(dev);
  1060. }
  1061. /* Standard mandates link reset for ATA (type 0)
  1062. and hard reset for SSP (type 1) , only for RECOVERY */
  1063. static int mvs_debug_I_T_nexus_reset(struct domain_device *dev)
  1064. {
  1065. int rc;
  1066. struct sas_phy *phy = sas_get_local_phy(dev);
  1067. int reset_type = (dev->dev_type == SAS_SATA_DEV ||
  1068. (dev->tproto & SAS_PROTOCOL_STP)) ? 0 : 1;
  1069. rc = sas_phy_reset(phy, reset_type);
  1070. sas_put_local_phy(phy);
  1071. msleep(2000);
  1072. return rc;
  1073. }
  1074. /* mandatory SAM-3 */
  1075. int mvs_lu_reset(struct domain_device *dev, u8 *lun)
  1076. {
  1077. unsigned long flags;
  1078. int rc = TMF_RESP_FUNC_FAILED;
  1079. struct mvs_device * mvi_dev = dev->lldd_dev;
  1080. struct mvs_info *mvi = mvi_dev->mvi_info;
  1081. mvi_dev->dev_status = MVS_DEV_EH;
  1082. rc = sas_lu_reset(dev, lun);
  1083. if (rc == TMF_RESP_FUNC_COMPLETE) {
  1084. spin_lock_irqsave(&mvi->lock, flags);
  1085. mvs_release_task(mvi, dev);
  1086. spin_unlock_irqrestore(&mvi->lock, flags);
  1087. }
  1088. /* If failed, fall-through I_T_Nexus reset */
  1089. mv_printk("%s for device[%x]:rc= %d\n", __func__,
  1090. mvi_dev->device_id, rc);
  1091. return rc;
  1092. }
  1093. int mvs_I_T_nexus_reset(struct domain_device *dev)
  1094. {
  1095. unsigned long flags;
  1096. int rc = TMF_RESP_FUNC_FAILED;
  1097. struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
  1098. struct mvs_info *mvi = mvi_dev->mvi_info;
  1099. if (mvi_dev->dev_status != MVS_DEV_EH)
  1100. return TMF_RESP_FUNC_COMPLETE;
  1101. else
  1102. mvi_dev->dev_status = MVS_DEV_NORMAL;
  1103. rc = mvs_debug_I_T_nexus_reset(dev);
  1104. mv_printk("%s for device[%x]:rc= %d\n",
  1105. __func__, mvi_dev->device_id, rc);
  1106. spin_lock_irqsave(&mvi->lock, flags);
  1107. mvs_release_task(mvi, dev);
  1108. spin_unlock_irqrestore(&mvi->lock, flags);
  1109. return rc;
  1110. }
  1111. /* optional SAM-3 */
  1112. int mvs_query_task(struct sas_task *task)
  1113. {
  1114. u32 tag;
  1115. int rc = TMF_RESP_FUNC_FAILED;
  1116. if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SSP) {
  1117. struct domain_device *dev = task->dev;
  1118. struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
  1119. struct mvs_info *mvi = mvi_dev->mvi_info;
  1120. rc = mvs_find_tag(mvi, task, &tag);
  1121. if (rc == 0) {
  1122. rc = TMF_RESP_FUNC_FAILED;
  1123. return rc;
  1124. }
  1125. rc = sas_query_task(task, tag);
  1126. switch (rc) {
  1127. /* The task is still in Lun, release it then */
  1128. case TMF_RESP_FUNC_SUCC:
  1129. /* The task is not in Lun or failed, reset the phy */
  1130. case TMF_RESP_FUNC_FAILED:
  1131. case TMF_RESP_FUNC_COMPLETE:
  1132. break;
  1133. }
  1134. }
  1135. mv_printk("%s:rc= %d\n", __func__, rc);
  1136. return rc;
  1137. }
  1138. /* mandatory SAM-3, still need free task/slot info */
  1139. int mvs_abort_task(struct sas_task *task)
  1140. {
  1141. struct domain_device *dev = task->dev;
  1142. struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
  1143. struct mvs_info *mvi;
  1144. int rc = TMF_RESP_FUNC_FAILED;
  1145. unsigned long flags;
  1146. u32 tag;
  1147. if (!mvi_dev) {
  1148. mv_printk("Device has removed\n");
  1149. return TMF_RESP_FUNC_FAILED;
  1150. }
  1151. mvi = mvi_dev->mvi_info;
  1152. spin_lock_irqsave(&task->task_state_lock, flags);
  1153. if (task->task_state_flags & SAS_TASK_STATE_DONE) {
  1154. spin_unlock_irqrestore(&task->task_state_lock, flags);
  1155. rc = TMF_RESP_FUNC_COMPLETE;
  1156. goto out;
  1157. }
  1158. spin_unlock_irqrestore(&task->task_state_lock, flags);
  1159. mvi_dev->dev_status = MVS_DEV_EH;
  1160. if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SSP) {
  1161. rc = mvs_find_tag(mvi, task, &tag);
  1162. if (rc == 0) {
  1163. mv_printk("No such tag in %s\n", __func__);
  1164. rc = TMF_RESP_FUNC_FAILED;
  1165. return rc;
  1166. }
  1167. rc = sas_abort_task(task, tag);
  1168. /* if successful, clear the task and callback forwards.*/
  1169. if (rc == TMF_RESP_FUNC_COMPLETE) {
  1170. u32 slot_no;
  1171. struct mvs_slot_info *slot;
  1172. if (task->lldd_task) {
  1173. slot = task->lldd_task;
  1174. slot_no = (u32) (slot - mvi->slot_info);
  1175. spin_lock_irqsave(&mvi->lock, flags);
  1176. mvs_slot_complete(mvi, slot_no, 1);
  1177. spin_unlock_irqrestore(&mvi->lock, flags);
  1178. }
  1179. }
  1180. } else if (task->task_proto & SAS_PROTOCOL_SATA ||
  1181. task->task_proto & SAS_PROTOCOL_STP) {
  1182. if (SAS_SATA_DEV == dev->dev_type) {
  1183. struct mvs_slot_info *slot = task->lldd_task;
  1184. u32 slot_idx = (u32)(slot - mvi->slot_info);
  1185. mv_dprintk("mvs_abort_task() mvi=%p task=%p "
  1186. "slot=%p slot_idx=x%x\n",
  1187. mvi, task, slot, slot_idx);
  1188. task->task_state_flags |= SAS_TASK_STATE_ABORTED;
  1189. mvs_slot_task_free(mvi, task, slot, slot_idx);
  1190. rc = TMF_RESP_FUNC_COMPLETE;
  1191. goto out;
  1192. }
  1193. }
  1194. out:
  1195. if (rc != TMF_RESP_FUNC_COMPLETE)
  1196. mv_printk("%s:rc= %d\n", __func__, rc);
  1197. return rc;
  1198. }
  1199. static int mvs_sata_done(struct mvs_info *mvi, struct sas_task *task,
  1200. u32 slot_idx, int err)
  1201. {
  1202. struct mvs_device *mvi_dev = task->dev->lldd_dev;
  1203. struct task_status_struct *tstat = &task->task_status;
  1204. struct ata_task_resp *resp = (struct ata_task_resp *)tstat->buf;
  1205. int stat = SAM_STAT_GOOD;
  1206. resp->frame_len = sizeof(struct dev_to_host_fis);
  1207. memcpy(&resp->ending_fis[0],
  1208. SATA_RECEIVED_D2H_FIS(mvi_dev->taskfileset),
  1209. sizeof(struct dev_to_host_fis));
  1210. tstat->buf_valid_size = sizeof(*resp);
  1211. if (unlikely(err)) {
  1212. if (unlikely(err & CMD_ISS_STPD))
  1213. stat = SAS_OPEN_REJECT;
  1214. else
  1215. stat = SAS_PROTO_RESPONSE;
  1216. }
  1217. return stat;
  1218. }
  1219. static void mvs_set_sense(u8 *buffer, int len, int d_sense,
  1220. int key, int asc, int ascq)
  1221. {
  1222. memset(buffer, 0, len);
  1223. if (d_sense) {
  1224. /* Descriptor format */
  1225. if (len < 4) {
  1226. mv_printk("Length %d of sense buffer too small to "
  1227. "fit sense %x:%x:%x", len, key, asc, ascq);
  1228. }
  1229. buffer[0] = 0x72; /* Response Code */
  1230. if (len > 1)
  1231. buffer[1] = key; /* Sense Key */
  1232. if (len > 2)
  1233. buffer[2] = asc; /* ASC */
  1234. if (len > 3)
  1235. buffer[3] = ascq; /* ASCQ */
  1236. } else {
  1237. if (len < 14) {
  1238. mv_printk("Length %d of sense buffer too small to "
  1239. "fit sense %x:%x:%x", len, key, asc, ascq);
  1240. }
  1241. buffer[0] = 0x70; /* Response Code */
  1242. if (len > 2)
  1243. buffer[2] = key; /* Sense Key */
  1244. if (len > 7)
  1245. buffer[7] = 0x0a; /* Additional Sense Length */
  1246. if (len > 12)
  1247. buffer[12] = asc; /* ASC */
  1248. if (len > 13)
  1249. buffer[13] = ascq; /* ASCQ */
  1250. }
  1251. return;
  1252. }
  1253. static void mvs_fill_ssp_resp_iu(struct ssp_response_iu *iu,
  1254. u8 key, u8 asc, u8 asc_q)
  1255. {
  1256. iu->datapres = SAS_DATAPRES_SENSE_DATA;
  1257. iu->response_data_len = 0;
  1258. iu->sense_data_len = 17;
  1259. iu->status = 02;
  1260. mvs_set_sense(iu->sense_data, 17, 0,
  1261. key, asc, asc_q);
  1262. }
  1263. static int mvs_slot_err(struct mvs_info *mvi, struct sas_task *task,
  1264. u32 slot_idx)
  1265. {
  1266. struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
  1267. int stat;
  1268. u32 err_dw0 = le32_to_cpu(*(u32 *)slot->response);
  1269. u32 err_dw1 = le32_to_cpu(*((u32 *)slot->response + 1));
  1270. u32 tfs = 0;
  1271. enum mvs_port_type type = PORT_TYPE_SAS;
  1272. if (err_dw0 & CMD_ISS_STPD)
  1273. MVS_CHIP_DISP->issue_stop(mvi, type, tfs);
  1274. MVS_CHIP_DISP->command_active(mvi, slot_idx);
  1275. stat = SAM_STAT_CHECK_CONDITION;
  1276. switch (task->task_proto) {
  1277. case SAS_PROTOCOL_SSP:
  1278. {
  1279. stat = SAS_ABORTED_TASK;
  1280. if ((err_dw0 & NO_DEST) || err_dw1 & bit(31)) {
  1281. struct ssp_response_iu *iu = slot->response +
  1282. sizeof(struct mvs_err_info);
  1283. mvs_fill_ssp_resp_iu(iu, NOT_READY, 0x04, 01);
  1284. sas_ssp_task_response(mvi->dev, task, iu);
  1285. stat = SAM_STAT_CHECK_CONDITION;
  1286. }
  1287. if (err_dw1 & bit(31))
  1288. mv_printk("reuse same slot, retry command.\n");
  1289. break;
  1290. }
  1291. case SAS_PROTOCOL_SMP:
  1292. stat = SAM_STAT_CHECK_CONDITION;
  1293. break;
  1294. case SAS_PROTOCOL_SATA:
  1295. case SAS_PROTOCOL_STP:
  1296. case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
  1297. {
  1298. task->ata_task.use_ncq = 0;
  1299. stat = SAS_PROTO_RESPONSE;
  1300. mvs_sata_done(mvi, task, slot_idx, err_dw0);
  1301. }
  1302. break;
  1303. default:
  1304. break;
  1305. }
  1306. return stat;
  1307. }
  1308. int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags)
  1309. {
  1310. u32 slot_idx = rx_desc & RXQ_SLOT_MASK;
  1311. struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
  1312. struct sas_task *task = slot->task;
  1313. struct mvs_device *mvi_dev = NULL;
  1314. struct task_status_struct *tstat;
  1315. struct domain_device *dev;
  1316. u32 aborted;
  1317. void *to;
  1318. enum exec_status sts;
  1319. if (unlikely(!task || !task->lldd_task || !task->dev))
  1320. return -1;
  1321. tstat = &task->task_status;
  1322. dev = task->dev;
  1323. mvi_dev = dev->lldd_dev;
  1324. spin_lock(&task->task_state_lock);
  1325. task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
  1326. task->task_state_flags |= SAS_TASK_STATE_DONE;
  1327. /* race condition*/
  1328. aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED;
  1329. spin_unlock(&task->task_state_lock);
  1330. memset(tstat, 0, sizeof(*tstat));
  1331. tstat->resp = SAS_TASK_COMPLETE;
  1332. if (unlikely(aborted)) {
  1333. tstat->stat = SAS_ABORTED_TASK;
  1334. if (mvi_dev && mvi_dev->running_req)
  1335. mvi_dev->running_req--;
  1336. if (sas_protocol_ata(task->task_proto))
  1337. mvs_free_reg_set(mvi, mvi_dev);
  1338. mvs_slot_task_free(mvi, task, slot, slot_idx);
  1339. return -1;
  1340. }
  1341. /* when no device attaching, go ahead and complete by error handling*/
  1342. if (unlikely(!mvi_dev || flags)) {
  1343. if (!mvi_dev)
  1344. mv_dprintk("port has not device.\n");
  1345. tstat->stat = SAS_PHY_DOWN;
  1346. goto out;
  1347. }
  1348. /*
  1349. * error info record present; slot->response is 32 bit aligned but may
  1350. * not be 64 bit aligned, so check for zero in two 32 bit reads
  1351. */
  1352. if (unlikely((rx_desc & RXQ_ERR)
  1353. && (*((u32 *)slot->response)
  1354. || *(((u32 *)slot->response) + 1)))) {
  1355. mv_dprintk("port %d slot %d rx_desc %X has error info"
  1356. "%016llX.\n", slot->port->sas_port.id, slot_idx,
  1357. rx_desc, get_unaligned_le64(slot->response));
  1358. tstat->stat = mvs_slot_err(mvi, task, slot_idx);
  1359. tstat->resp = SAS_TASK_COMPLETE;
  1360. goto out;
  1361. }
  1362. switch (task->task_proto) {
  1363. case SAS_PROTOCOL_SSP:
  1364. /* hw says status == 0, datapres == 0 */
  1365. if (rx_desc & RXQ_GOOD) {
  1366. tstat->stat = SAS_SAM_STAT_GOOD;
  1367. tstat->resp = SAS_TASK_COMPLETE;
  1368. }
  1369. /* response frame present */
  1370. else if (rx_desc & RXQ_RSP) {
  1371. struct ssp_response_iu *iu = slot->response +
  1372. sizeof(struct mvs_err_info);
  1373. sas_ssp_task_response(mvi->dev, task, iu);
  1374. } else
  1375. tstat->stat = SAS_SAM_STAT_CHECK_CONDITION;
  1376. break;
  1377. case SAS_PROTOCOL_SMP: {
  1378. struct scatterlist *sg_resp = &task->smp_task.smp_resp;
  1379. tstat->stat = SAS_SAM_STAT_GOOD;
  1380. to = kmap_atomic(sg_page(sg_resp));
  1381. memcpy(to + sg_resp->offset,
  1382. slot->response + sizeof(struct mvs_err_info),
  1383. sg_dma_len(sg_resp));
  1384. kunmap_atomic(to);
  1385. break;
  1386. }
  1387. case SAS_PROTOCOL_SATA:
  1388. case SAS_PROTOCOL_STP:
  1389. case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: {
  1390. tstat->stat = mvs_sata_done(mvi, task, slot_idx, 0);
  1391. break;
  1392. }
  1393. default:
  1394. tstat->stat = SAS_SAM_STAT_CHECK_CONDITION;
  1395. break;
  1396. }
  1397. if (!slot->port->port_attached) {
  1398. mv_dprintk("port %d has removed.\n", slot->port->sas_port.id);
  1399. tstat->stat = SAS_PHY_DOWN;
  1400. }
  1401. out:
  1402. if (mvi_dev && mvi_dev->running_req) {
  1403. mvi_dev->running_req--;
  1404. if (sas_protocol_ata(task->task_proto) && !mvi_dev->running_req)
  1405. mvs_free_reg_set(mvi, mvi_dev);
  1406. }
  1407. mvs_slot_task_free(mvi, task, slot, slot_idx);
  1408. sts = tstat->stat;
  1409. spin_unlock(&mvi->lock);
  1410. if (task->task_done)
  1411. task->task_done(task);
  1412. spin_lock(&mvi->lock);
  1413. return sts;
  1414. }
  1415. void mvs_do_release_task(struct mvs_info *mvi,
  1416. int phy_no, struct domain_device *dev)
  1417. {
  1418. u32 slot_idx;
  1419. struct mvs_phy *phy;
  1420. struct mvs_port *port;
  1421. struct mvs_slot_info *slot, *slot2;
  1422. phy = &mvi->phy[phy_no];
  1423. port = phy->port;
  1424. if (!port)
  1425. return;
  1426. /* clean cmpl queue in case request is already finished */
  1427. mvs_int_rx(mvi, false);
  1428. list_for_each_entry_safe(slot, slot2, &port->list, entry) {
  1429. struct sas_task *task;
  1430. slot_idx = (u32) (slot - mvi->slot_info);
  1431. task = slot->task;
  1432. if (dev && task->dev != dev)
  1433. continue;
  1434. mv_printk("Release slot [%x] tag[%x], task [%p]:\n",
  1435. slot_idx, slot->slot_tag, task);
  1436. MVS_CHIP_DISP->command_active(mvi, slot_idx);
  1437. mvs_slot_complete(mvi, slot_idx, 1);
  1438. }
  1439. }
  1440. void mvs_release_task(struct mvs_info *mvi,
  1441. struct domain_device *dev)
  1442. {
  1443. int i, phyno[WIDE_PORT_MAX_PHY], num;
  1444. num = mvs_find_dev_phyno(dev, phyno);
  1445. for (i = 0; i < num; i++)
  1446. mvs_do_release_task(mvi, phyno[i], dev);
  1447. }
  1448. static void mvs_phy_disconnected(struct mvs_phy *phy)
  1449. {
  1450. phy->phy_attached = 0;
  1451. phy->att_dev_info = 0;
  1452. phy->att_dev_sas_addr = 0;
  1453. }
  1454. static void mvs_work_queue(struct work_struct *work)
  1455. {
  1456. struct delayed_work *dw = container_of(work, struct delayed_work, work);
  1457. struct mvs_wq *mwq = container_of(dw, struct mvs_wq, work_q);
  1458. struct mvs_info *mvi = mwq->mvi;
  1459. unsigned long flags;
  1460. u32 phy_no = (unsigned long) mwq->data;
  1461. struct mvs_phy *phy = &mvi->phy[phy_no];
  1462. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  1463. spin_lock_irqsave(&mvi->lock, flags);
  1464. if (mwq->handler & PHY_PLUG_EVENT) {
  1465. if (phy->phy_event & PHY_PLUG_OUT) {
  1466. u32 tmp;
  1467. tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no);
  1468. phy->phy_event &= ~PHY_PLUG_OUT;
  1469. if (!(tmp & PHY_READY_MASK)) {
  1470. sas_phy_disconnected(sas_phy);
  1471. mvs_phy_disconnected(phy);
  1472. sas_notify_phy_event(sas_phy,
  1473. PHYE_LOSS_OF_SIGNAL, GFP_ATOMIC);
  1474. mv_dprintk("phy%d Removed Device\n", phy_no);
  1475. } else {
  1476. MVS_CHIP_DISP->detect_porttype(mvi, phy_no);
  1477. mvs_update_phyinfo(mvi, phy_no, 1);
  1478. mvs_bytes_dmaed(mvi, phy_no, GFP_ATOMIC);
  1479. mvs_port_notify_formed(sas_phy, 0);
  1480. mv_dprintk("phy%d Attached Device\n", phy_no);
  1481. }
  1482. }
  1483. } else if (mwq->handler & EXP_BRCT_CHG) {
  1484. phy->phy_event &= ~EXP_BRCT_CHG;
  1485. sas_notify_port_event(sas_phy,
  1486. PORTE_BROADCAST_RCVD, GFP_ATOMIC);
  1487. mv_dprintk("phy%d Got Broadcast Change\n", phy_no);
  1488. }
  1489. list_del(&mwq->entry);
  1490. spin_unlock_irqrestore(&mvi->lock, flags);
  1491. kfree(mwq);
  1492. }
  1493. static int mvs_handle_event(struct mvs_info *mvi, void *data, int handler)
  1494. {
  1495. struct mvs_wq *mwq;
  1496. int ret = 0;
  1497. mwq = kmalloc(sizeof(struct mvs_wq), GFP_ATOMIC);
  1498. if (mwq) {
  1499. mwq->mvi = mvi;
  1500. mwq->data = data;
  1501. mwq->handler = handler;
  1502. MV_INIT_DELAYED_WORK(&mwq->work_q, mvs_work_queue, mwq);
  1503. list_add_tail(&mwq->entry, &mvi->wq_list);
  1504. schedule_delayed_work(&mwq->work_q, HZ * 2);
  1505. } else
  1506. ret = -ENOMEM;
  1507. return ret;
  1508. }
  1509. static void mvs_sig_time_out(struct timer_list *t)
  1510. {
  1511. struct mvs_phy *phy = from_timer(phy, t, timer);
  1512. struct mvs_info *mvi = phy->mvi;
  1513. u8 phy_no;
  1514. for (phy_no = 0; phy_no < mvi->chip->n_phy; phy_no++) {
  1515. if (&mvi->phy[phy_no] == phy) {
  1516. mv_dprintk("Get signature time out, reset phy %d\n",
  1517. phy_no+mvi->id*mvi->chip->n_phy);
  1518. MVS_CHIP_DISP->phy_reset(mvi, phy_no, MVS_HARD_RESET);
  1519. }
  1520. }
  1521. }
  1522. void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events)
  1523. {
  1524. u32 tmp;
  1525. struct mvs_phy *phy = &mvi->phy[phy_no];
  1526. phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, phy_no);
  1527. MVS_CHIP_DISP->write_port_irq_stat(mvi, phy_no, phy->irq_status);
  1528. mv_dprintk("phy %d ctrl sts=0x%08X.\n", phy_no+mvi->id*mvi->chip->n_phy,
  1529. MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no));
  1530. mv_dprintk("phy %d irq sts = 0x%08X\n", phy_no+mvi->id*mvi->chip->n_phy,
  1531. phy->irq_status);
  1532. /*
  1533. * events is port event now ,
  1534. * we need check the interrupt status which belongs to per port.
  1535. */
  1536. if (phy->irq_status & PHYEV_DCDR_ERR) {
  1537. mv_dprintk("phy %d STP decoding error.\n",
  1538. phy_no + mvi->id*mvi->chip->n_phy);
  1539. }
  1540. if (phy->irq_status & PHYEV_POOF) {
  1541. mdelay(500);
  1542. if (!(phy->phy_event & PHY_PLUG_OUT)) {
  1543. int dev_sata = phy->phy_type & PORT_TYPE_SATA;
  1544. int ready;
  1545. mvs_do_release_task(mvi, phy_no, NULL);
  1546. phy->phy_event |= PHY_PLUG_OUT;
  1547. MVS_CHIP_DISP->clear_srs_irq(mvi, 0, 1);
  1548. mvs_handle_event(mvi,
  1549. (void *)(unsigned long)phy_no,
  1550. PHY_PLUG_EVENT);
  1551. ready = mvs_is_phy_ready(mvi, phy_no);
  1552. if (ready || dev_sata) {
  1553. if (MVS_CHIP_DISP->stp_reset)
  1554. MVS_CHIP_DISP->stp_reset(mvi,
  1555. phy_no);
  1556. else
  1557. MVS_CHIP_DISP->phy_reset(mvi,
  1558. phy_no, MVS_SOFT_RESET);
  1559. return;
  1560. }
  1561. }
  1562. }
  1563. if (phy->irq_status & PHYEV_COMWAKE) {
  1564. tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, phy_no);
  1565. MVS_CHIP_DISP->write_port_irq_mask(mvi, phy_no,
  1566. tmp | PHYEV_SIG_FIS);
  1567. if (phy->timer.function == NULL) {
  1568. phy->timer.function = mvs_sig_time_out;
  1569. phy->timer.expires = jiffies + 5*HZ;
  1570. add_timer(&phy->timer);
  1571. }
  1572. }
  1573. if (phy->irq_status & (PHYEV_SIG_FIS | PHYEV_ID_DONE)) {
  1574. phy->phy_status = mvs_is_phy_ready(mvi, phy_no);
  1575. mv_dprintk("notify plug in on phy[%d]\n", phy_no);
  1576. if (phy->phy_status) {
  1577. mdelay(10);
  1578. MVS_CHIP_DISP->detect_porttype(mvi, phy_no);
  1579. if (phy->phy_type & PORT_TYPE_SATA) {
  1580. tmp = MVS_CHIP_DISP->read_port_irq_mask(
  1581. mvi, phy_no);
  1582. tmp &= ~PHYEV_SIG_FIS;
  1583. MVS_CHIP_DISP->write_port_irq_mask(mvi,
  1584. phy_no, tmp);
  1585. }
  1586. mvs_update_phyinfo(mvi, phy_no, 0);
  1587. if (phy->phy_type & PORT_TYPE_SAS) {
  1588. MVS_CHIP_DISP->phy_reset(mvi, phy_no, MVS_PHY_TUNE);
  1589. mdelay(10);
  1590. }
  1591. mvs_bytes_dmaed(mvi, phy_no, GFP_ATOMIC);
  1592. /* whether driver is going to handle hot plug */
  1593. if (phy->phy_event & PHY_PLUG_OUT) {
  1594. mvs_port_notify_formed(&phy->sas_phy, 0);
  1595. phy->phy_event &= ~PHY_PLUG_OUT;
  1596. }
  1597. } else {
  1598. mv_dprintk("plugin interrupt but phy%d is gone\n",
  1599. phy_no + mvi->id*mvi->chip->n_phy);
  1600. }
  1601. } else if (phy->irq_status & PHYEV_BROAD_CH) {
  1602. mv_dprintk("phy %d broadcast change.\n",
  1603. phy_no + mvi->id*mvi->chip->n_phy);
  1604. mvs_handle_event(mvi, (void *)(unsigned long)phy_no,
  1605. EXP_BRCT_CHG);
  1606. }
  1607. }
  1608. int mvs_int_rx(struct mvs_info *mvi, bool self_clear)
  1609. {
  1610. u32 rx_prod_idx, rx_desc;
  1611. bool attn = false;
  1612. /* the first dword in the RX ring is special: it contains
  1613. * a mirror of the hardware's RX producer index, so that
  1614. * we don't have to stall the CPU reading that register.
  1615. * The actual RX ring is offset by one dword, due to this.
  1616. */
  1617. rx_prod_idx = mvi->rx_cons;
  1618. mvi->rx_cons = le32_to_cpu(mvi->rx[0]);
  1619. if (mvi->rx_cons == 0xfff) /* h/w hasn't touched RX ring yet */
  1620. return 0;
  1621. /* The CMPL_Q may come late, read from register and try again
  1622. * note: if coalescing is enabled,
  1623. * it will need to read from register every time for sure
  1624. */
  1625. if (unlikely(mvi->rx_cons == rx_prod_idx))
  1626. mvi->rx_cons = MVS_CHIP_DISP->rx_update(mvi) & RX_RING_SZ_MASK;
  1627. if (mvi->rx_cons == rx_prod_idx)
  1628. return 0;
  1629. while (mvi->rx_cons != rx_prod_idx) {
  1630. /* increment our internal RX consumer pointer */
  1631. rx_prod_idx = (rx_prod_idx + 1) & (MVS_RX_RING_SZ - 1);
  1632. rx_desc = le32_to_cpu(mvi->rx[rx_prod_idx + 1]);
  1633. if (likely(rx_desc & RXQ_DONE))
  1634. mvs_slot_complete(mvi, rx_desc, 0);
  1635. if (rx_desc & RXQ_ATTN) {
  1636. attn = true;
  1637. } else if (rx_desc & RXQ_ERR) {
  1638. if (!(rx_desc & RXQ_DONE))
  1639. mvs_slot_complete(mvi, rx_desc, 0);
  1640. } else if (rx_desc & RXQ_SLOT_RESET) {
  1641. mvs_slot_free(mvi, rx_desc);
  1642. }
  1643. }
  1644. if (attn && self_clear)
  1645. MVS_CHIP_DISP->int_full(mvi);
  1646. return 0;
  1647. }
  1648. int mvs_gpio_write(struct sas_ha_struct *sha, u8 reg_type, u8 reg_index,
  1649. u8 reg_count, u8 *write_data)
  1650. {
  1651. struct mvs_prv_info *mvs_prv = sha->lldd_ha;
  1652. struct mvs_info *mvi = mvs_prv->mvi[0];
  1653. if (MVS_CHIP_DISP->gpio_write) {
  1654. return MVS_CHIP_DISP->gpio_write(mvs_prv, reg_type,
  1655. reg_index, reg_count, write_data);
  1656. }
  1657. return -ENOSYS;
  1658. }