host.c 81 KB

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  1. /*
  2. * This file is provided under a dual BSD/GPLv2 license. When using or
  3. * redistributing this file, you may do so under either license.
  4. *
  5. * GPL LICENSE SUMMARY
  6. *
  7. * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of version 2 of the GNU General Public License as
  11. * published by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful, but
  14. * WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  16. * General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  21. * The full GNU General Public License is included in this distribution
  22. * in the file called LICENSE.GPL.
  23. *
  24. * BSD LICENSE
  25. *
  26. * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
  27. * All rights reserved.
  28. *
  29. * Redistribution and use in source and binary forms, with or without
  30. * modification, are permitted provided that the following conditions
  31. * are met:
  32. *
  33. * * Redistributions of source code must retain the above copyright
  34. * notice, this list of conditions and the following disclaimer.
  35. * * Redistributions in binary form must reproduce the above copyright
  36. * notice, this list of conditions and the following disclaimer in
  37. * the documentation and/or other materials provided with the
  38. * distribution.
  39. * * Neither the name of Intel Corporation nor the names of its
  40. * contributors may be used to endorse or promote products derived
  41. * from this software without specific prior written permission.
  42. *
  43. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  44. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  45. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  46. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  47. * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  48. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  49. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  50. * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  51. * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  52. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  53. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  54. */
  55. #include <linux/circ_buf.h>
  56. #include <linux/device.h>
  57. #include <scsi/sas.h>
  58. #include "host.h"
  59. #include "isci.h"
  60. #include "port.h"
  61. #include "probe_roms.h"
  62. #include "remote_device.h"
  63. #include "request.h"
  64. #include "scu_completion_codes.h"
  65. #include "scu_event_codes.h"
  66. #include "registers.h"
  67. #include "scu_remote_node_context.h"
  68. #include "scu_task_context.h"
  69. #define SCU_CONTEXT_RAM_INIT_STALL_TIME 200
  70. #define smu_max_ports(dcc_value) \
  71. (\
  72. (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_MASK) \
  73. >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT) + 1 \
  74. )
  75. #define smu_max_task_contexts(dcc_value) \
  76. (\
  77. (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_MASK) \
  78. >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_SHIFT) + 1 \
  79. )
  80. #define smu_max_rncs(dcc_value) \
  81. (\
  82. (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_MASK) \
  83. >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_SHIFT) + 1 \
  84. )
  85. #define SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT 100
  86. /*
  87. * The number of milliseconds to wait while a given phy is consuming power
  88. * before allowing another set of phys to consume power. Ultimately, this will
  89. * be specified by OEM parameter.
  90. */
  91. #define SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL 500
  92. /*
  93. * NORMALIZE_PUT_POINTER() -
  94. *
  95. * This macro will normalize the completion queue put pointer so its value can
  96. * be used as an array inde
  97. */
  98. #define NORMALIZE_PUT_POINTER(x) \
  99. ((x) & SMU_COMPLETION_QUEUE_PUT_POINTER_MASK)
  100. /*
  101. * NORMALIZE_EVENT_POINTER() -
  102. *
  103. * This macro will normalize the completion queue event entry so its value can
  104. * be used as an index.
  105. */
  106. #define NORMALIZE_EVENT_POINTER(x) \
  107. (\
  108. ((x) & SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_MASK) \
  109. >> SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_SHIFT \
  110. )
  111. /*
  112. * NORMALIZE_GET_POINTER() -
  113. *
  114. * This macro will normalize the completion queue get pointer so its value can
  115. * be used as an index into an array
  116. */
  117. #define NORMALIZE_GET_POINTER(x) \
  118. ((x) & SMU_COMPLETION_QUEUE_GET_POINTER_MASK)
  119. /*
  120. * NORMALIZE_GET_POINTER_CYCLE_BIT() -
  121. *
  122. * This macro will normalize the completion queue cycle pointer so it matches
  123. * the completion queue cycle bit
  124. */
  125. #define NORMALIZE_GET_POINTER_CYCLE_BIT(x) \
  126. ((SMU_CQGR_CYCLE_BIT & (x)) << (31 - SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT))
  127. /*
  128. * COMPLETION_QUEUE_CYCLE_BIT() -
  129. *
  130. * This macro will return the cycle bit of the completion queue entry
  131. */
  132. #define COMPLETION_QUEUE_CYCLE_BIT(x) ((x) & 0x80000000)
  133. /* Init the state machine and call the state entry function (if any) */
  134. void sci_init_sm(struct sci_base_state_machine *sm,
  135. const struct sci_base_state *state_table, u32 initial_state)
  136. {
  137. sci_state_transition_t handler;
  138. sm->initial_state_id = initial_state;
  139. sm->previous_state_id = initial_state;
  140. sm->current_state_id = initial_state;
  141. sm->state_table = state_table;
  142. handler = sm->state_table[initial_state].enter_state;
  143. if (handler)
  144. handler(sm);
  145. }
  146. /* Call the state exit fn, update the current state, call the state entry fn */
  147. void sci_change_state(struct sci_base_state_machine *sm, u32 next_state)
  148. {
  149. sci_state_transition_t handler;
  150. handler = sm->state_table[sm->current_state_id].exit_state;
  151. if (handler)
  152. handler(sm);
  153. sm->previous_state_id = sm->current_state_id;
  154. sm->current_state_id = next_state;
  155. handler = sm->state_table[sm->current_state_id].enter_state;
  156. if (handler)
  157. handler(sm);
  158. }
  159. static bool sci_controller_completion_queue_has_entries(struct isci_host *ihost)
  160. {
  161. u32 get_value = ihost->completion_queue_get;
  162. u32 get_index = get_value & SMU_COMPLETION_QUEUE_GET_POINTER_MASK;
  163. if (NORMALIZE_GET_POINTER_CYCLE_BIT(get_value) ==
  164. COMPLETION_QUEUE_CYCLE_BIT(ihost->completion_queue[get_index]))
  165. return true;
  166. return false;
  167. }
  168. static bool sci_controller_isr(struct isci_host *ihost)
  169. {
  170. if (sci_controller_completion_queue_has_entries(ihost))
  171. return true;
  172. /* we have a spurious interrupt it could be that we have already
  173. * emptied the completion queue from a previous interrupt
  174. * FIXME: really!?
  175. */
  176. writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status);
  177. /* There is a race in the hardware that could cause us not to be
  178. * notified of an interrupt completion if we do not take this
  179. * step. We will mask then unmask the interrupts so if there is
  180. * another interrupt pending the clearing of the interrupt
  181. * source we get the next interrupt message.
  182. */
  183. spin_lock(&ihost->scic_lock);
  184. if (test_bit(IHOST_IRQ_ENABLED, &ihost->flags)) {
  185. writel(0xFF000000, &ihost->smu_registers->interrupt_mask);
  186. writel(0, &ihost->smu_registers->interrupt_mask);
  187. }
  188. spin_unlock(&ihost->scic_lock);
  189. return false;
  190. }
  191. irqreturn_t isci_msix_isr(int vec, void *data)
  192. {
  193. struct isci_host *ihost = data;
  194. if (sci_controller_isr(ihost))
  195. tasklet_schedule(&ihost->completion_tasklet);
  196. return IRQ_HANDLED;
  197. }
  198. static bool sci_controller_error_isr(struct isci_host *ihost)
  199. {
  200. u32 interrupt_status;
  201. interrupt_status =
  202. readl(&ihost->smu_registers->interrupt_status);
  203. interrupt_status &= (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND);
  204. if (interrupt_status != 0) {
  205. /*
  206. * There is an error interrupt pending so let it through and handle
  207. * in the callback */
  208. return true;
  209. }
  210. /*
  211. * There is a race in the hardware that could cause us not to be notified
  212. * of an interrupt completion if we do not take this step. We will mask
  213. * then unmask the error interrupts so if there was another interrupt
  214. * pending we will be notified.
  215. * Could we write the value of (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND)? */
  216. writel(0xff, &ihost->smu_registers->interrupt_mask);
  217. writel(0, &ihost->smu_registers->interrupt_mask);
  218. return false;
  219. }
  220. static void sci_controller_task_completion(struct isci_host *ihost, u32 ent)
  221. {
  222. u32 index = SCU_GET_COMPLETION_INDEX(ent);
  223. struct isci_request *ireq = ihost->reqs[index];
  224. /* Make sure that we really want to process this IO request */
  225. if (test_bit(IREQ_ACTIVE, &ireq->flags) &&
  226. ireq->io_tag != SCI_CONTROLLER_INVALID_IO_TAG &&
  227. ISCI_TAG_SEQ(ireq->io_tag) == ihost->io_request_sequence[index])
  228. /* Yep this is a valid io request pass it along to the
  229. * io request handler
  230. */
  231. sci_io_request_tc_completion(ireq, ent);
  232. }
  233. static void sci_controller_sdma_completion(struct isci_host *ihost, u32 ent)
  234. {
  235. u32 index;
  236. struct isci_request *ireq;
  237. struct isci_remote_device *idev;
  238. index = SCU_GET_COMPLETION_INDEX(ent);
  239. switch (scu_get_command_request_type(ent)) {
  240. case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_TC:
  241. case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_TC:
  242. ireq = ihost->reqs[index];
  243. dev_warn(&ihost->pdev->dev, "%s: %x for io request %p\n",
  244. __func__, ent, ireq);
  245. /* @todo For a post TC operation we need to fail the IO
  246. * request
  247. */
  248. break;
  249. case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_RNC:
  250. case SCU_CONTEXT_COMMAND_REQUEST_TYPE_OTHER_RNC:
  251. case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_RNC:
  252. idev = ihost->device_table[index];
  253. dev_warn(&ihost->pdev->dev, "%s: %x for device %p\n",
  254. __func__, ent, idev);
  255. /* @todo For a port RNC operation we need to fail the
  256. * device
  257. */
  258. break;
  259. default:
  260. dev_warn(&ihost->pdev->dev, "%s: unknown completion type %x\n",
  261. __func__, ent);
  262. break;
  263. }
  264. }
  265. static void sci_controller_unsolicited_frame(struct isci_host *ihost, u32 ent)
  266. {
  267. u32 index;
  268. u32 frame_index;
  269. struct scu_unsolicited_frame_header *frame_header;
  270. struct isci_phy *iphy;
  271. struct isci_remote_device *idev;
  272. enum sci_status result = SCI_FAILURE;
  273. frame_index = SCU_GET_FRAME_INDEX(ent);
  274. frame_header = ihost->uf_control.buffers.array[frame_index].header;
  275. ihost->uf_control.buffers.array[frame_index].state = UNSOLICITED_FRAME_IN_USE;
  276. if (SCU_GET_FRAME_ERROR(ent)) {
  277. /*
  278. * / @todo If the IAF frame or SIGNATURE FIS frame has an error will
  279. * / this cause a problem? We expect the phy initialization will
  280. * / fail if there is an error in the frame. */
  281. sci_controller_release_frame(ihost, frame_index);
  282. return;
  283. }
  284. if (frame_header->is_address_frame) {
  285. index = SCU_GET_PROTOCOL_ENGINE_INDEX(ent);
  286. iphy = &ihost->phys[index];
  287. result = sci_phy_frame_handler(iphy, frame_index);
  288. } else {
  289. index = SCU_GET_COMPLETION_INDEX(ent);
  290. if (index == SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) {
  291. /*
  292. * This is a signature fis or a frame from a direct attached SATA
  293. * device that has not yet been created. In either case forwared
  294. * the frame to the PE and let it take care of the frame data. */
  295. index = SCU_GET_PROTOCOL_ENGINE_INDEX(ent);
  296. iphy = &ihost->phys[index];
  297. result = sci_phy_frame_handler(iphy, frame_index);
  298. } else {
  299. if (index < ihost->remote_node_entries)
  300. idev = ihost->device_table[index];
  301. else
  302. idev = NULL;
  303. if (idev != NULL)
  304. result = sci_remote_device_frame_handler(idev, frame_index);
  305. else
  306. sci_controller_release_frame(ihost, frame_index);
  307. }
  308. }
  309. if (result != SCI_SUCCESS) {
  310. /*
  311. * / @todo Is there any reason to report some additional error message
  312. * / when we get this failure notifiction? */
  313. }
  314. }
  315. static void sci_controller_event_completion(struct isci_host *ihost, u32 ent)
  316. {
  317. struct isci_remote_device *idev;
  318. struct isci_request *ireq;
  319. struct isci_phy *iphy;
  320. u32 index;
  321. index = SCU_GET_COMPLETION_INDEX(ent);
  322. switch (scu_get_event_type(ent)) {
  323. case SCU_EVENT_TYPE_SMU_COMMAND_ERROR:
  324. /* / @todo The driver did something wrong and we need to fix the condtion. */
  325. dev_err(&ihost->pdev->dev,
  326. "%s: SCIC Controller 0x%p received SMU command error "
  327. "0x%x\n",
  328. __func__,
  329. ihost,
  330. ent);
  331. break;
  332. case SCU_EVENT_TYPE_SMU_PCQ_ERROR:
  333. case SCU_EVENT_TYPE_SMU_ERROR:
  334. case SCU_EVENT_TYPE_FATAL_MEMORY_ERROR:
  335. /*
  336. * / @todo This is a hardware failure and its likely that we want to
  337. * / reset the controller. */
  338. dev_err(&ihost->pdev->dev,
  339. "%s: SCIC Controller 0x%p received fatal controller "
  340. "event 0x%x\n",
  341. __func__,
  342. ihost,
  343. ent);
  344. break;
  345. case SCU_EVENT_TYPE_TRANSPORT_ERROR:
  346. ireq = ihost->reqs[index];
  347. sci_io_request_event_handler(ireq, ent);
  348. break;
  349. case SCU_EVENT_TYPE_PTX_SCHEDULE_EVENT:
  350. switch (scu_get_event_specifier(ent)) {
  351. case SCU_EVENT_SPECIFIC_SMP_RESPONSE_NO_PE:
  352. case SCU_EVENT_SPECIFIC_TASK_TIMEOUT:
  353. ireq = ihost->reqs[index];
  354. if (ireq != NULL)
  355. sci_io_request_event_handler(ireq, ent);
  356. else
  357. dev_warn(&ihost->pdev->dev,
  358. "%s: SCIC Controller 0x%p received "
  359. "event 0x%x for io request object "
  360. "that doesn't exist.\n",
  361. __func__,
  362. ihost,
  363. ent);
  364. break;
  365. case SCU_EVENT_SPECIFIC_IT_NEXUS_TIMEOUT:
  366. idev = ihost->device_table[index];
  367. if (idev != NULL)
  368. sci_remote_device_event_handler(idev, ent);
  369. else
  370. dev_warn(&ihost->pdev->dev,
  371. "%s: SCIC Controller 0x%p received "
  372. "event 0x%x for remote device object "
  373. "that doesn't exist.\n",
  374. __func__,
  375. ihost,
  376. ent);
  377. break;
  378. }
  379. break;
  380. case SCU_EVENT_TYPE_BROADCAST_CHANGE:
  381. /*
  382. * direct the broadcast change event to the phy first and then let
  383. * the phy redirect the broadcast change to the port object */
  384. case SCU_EVENT_TYPE_ERR_CNT_EVENT:
  385. /*
  386. * direct error counter event to the phy object since that is where
  387. * we get the event notification. This is a type 4 event. */
  388. case SCU_EVENT_TYPE_OSSP_EVENT:
  389. index = SCU_GET_PROTOCOL_ENGINE_INDEX(ent);
  390. iphy = &ihost->phys[index];
  391. sci_phy_event_handler(iphy, ent);
  392. break;
  393. case SCU_EVENT_TYPE_RNC_SUSPEND_TX:
  394. case SCU_EVENT_TYPE_RNC_SUSPEND_TX_RX:
  395. case SCU_EVENT_TYPE_RNC_OPS_MISC:
  396. if (index < ihost->remote_node_entries) {
  397. idev = ihost->device_table[index];
  398. if (idev != NULL)
  399. sci_remote_device_event_handler(idev, ent);
  400. } else
  401. dev_err(&ihost->pdev->dev,
  402. "%s: SCIC Controller 0x%p received event 0x%x "
  403. "for remote device object 0x%0x that doesn't "
  404. "exist.\n",
  405. __func__,
  406. ihost,
  407. ent,
  408. index);
  409. break;
  410. default:
  411. dev_warn(&ihost->pdev->dev,
  412. "%s: SCIC Controller received unknown event code %x\n",
  413. __func__,
  414. ent);
  415. break;
  416. }
  417. }
  418. static void sci_controller_process_completions(struct isci_host *ihost)
  419. {
  420. u32 completion_count = 0;
  421. u32 ent;
  422. u32 get_index;
  423. u32 get_cycle;
  424. u32 event_get;
  425. u32 event_cycle;
  426. dev_dbg(&ihost->pdev->dev,
  427. "%s: completion queue beginning get:0x%08x\n",
  428. __func__,
  429. ihost->completion_queue_get);
  430. /* Get the component parts of the completion queue */
  431. get_index = NORMALIZE_GET_POINTER(ihost->completion_queue_get);
  432. get_cycle = SMU_CQGR_CYCLE_BIT & ihost->completion_queue_get;
  433. event_get = NORMALIZE_EVENT_POINTER(ihost->completion_queue_get);
  434. event_cycle = SMU_CQGR_EVENT_CYCLE_BIT & ihost->completion_queue_get;
  435. while (
  436. NORMALIZE_GET_POINTER_CYCLE_BIT(get_cycle)
  437. == COMPLETION_QUEUE_CYCLE_BIT(ihost->completion_queue[get_index])
  438. ) {
  439. completion_count++;
  440. ent = ihost->completion_queue[get_index];
  441. /* increment the get pointer and check for rollover to toggle the cycle bit */
  442. get_cycle ^= ((get_index+1) & SCU_MAX_COMPLETION_QUEUE_ENTRIES) <<
  443. (SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT - SCU_MAX_COMPLETION_QUEUE_SHIFT);
  444. get_index = (get_index+1) & (SCU_MAX_COMPLETION_QUEUE_ENTRIES-1);
  445. dev_dbg(&ihost->pdev->dev,
  446. "%s: completion queue entry:0x%08x\n",
  447. __func__,
  448. ent);
  449. switch (SCU_GET_COMPLETION_TYPE(ent)) {
  450. case SCU_COMPLETION_TYPE_TASK:
  451. sci_controller_task_completion(ihost, ent);
  452. break;
  453. case SCU_COMPLETION_TYPE_SDMA:
  454. sci_controller_sdma_completion(ihost, ent);
  455. break;
  456. case SCU_COMPLETION_TYPE_UFI:
  457. sci_controller_unsolicited_frame(ihost, ent);
  458. break;
  459. case SCU_COMPLETION_TYPE_EVENT:
  460. sci_controller_event_completion(ihost, ent);
  461. break;
  462. case SCU_COMPLETION_TYPE_NOTIFY: {
  463. event_cycle ^= ((event_get+1) & SCU_MAX_EVENTS) <<
  464. (SMU_COMPLETION_QUEUE_GET_EVENT_CYCLE_BIT_SHIFT - SCU_MAX_EVENTS_SHIFT);
  465. event_get = (event_get+1) & (SCU_MAX_EVENTS-1);
  466. sci_controller_event_completion(ihost, ent);
  467. break;
  468. }
  469. default:
  470. dev_warn(&ihost->pdev->dev,
  471. "%s: SCIC Controller received unknown "
  472. "completion type %x\n",
  473. __func__,
  474. ent);
  475. break;
  476. }
  477. }
  478. /* Update the get register if we completed one or more entries */
  479. if (completion_count > 0) {
  480. ihost->completion_queue_get =
  481. SMU_CQGR_GEN_BIT(ENABLE) |
  482. SMU_CQGR_GEN_BIT(EVENT_ENABLE) |
  483. event_cycle |
  484. SMU_CQGR_GEN_VAL(EVENT_POINTER, event_get) |
  485. get_cycle |
  486. SMU_CQGR_GEN_VAL(POINTER, get_index);
  487. writel(ihost->completion_queue_get,
  488. &ihost->smu_registers->completion_queue_get);
  489. }
  490. dev_dbg(&ihost->pdev->dev,
  491. "%s: completion queue ending get:0x%08x\n",
  492. __func__,
  493. ihost->completion_queue_get);
  494. }
  495. static void sci_controller_error_handler(struct isci_host *ihost)
  496. {
  497. u32 interrupt_status;
  498. interrupt_status =
  499. readl(&ihost->smu_registers->interrupt_status);
  500. if ((interrupt_status & SMU_ISR_QUEUE_SUSPEND) &&
  501. sci_controller_completion_queue_has_entries(ihost)) {
  502. sci_controller_process_completions(ihost);
  503. writel(SMU_ISR_QUEUE_SUSPEND, &ihost->smu_registers->interrupt_status);
  504. } else {
  505. dev_err(&ihost->pdev->dev, "%s: status: %#x\n", __func__,
  506. interrupt_status);
  507. sci_change_state(&ihost->sm, SCIC_FAILED);
  508. return;
  509. }
  510. /* If we dont process any completions I am not sure that we want to do this.
  511. * We are in the middle of a hardware fault and should probably be reset.
  512. */
  513. writel(0, &ihost->smu_registers->interrupt_mask);
  514. }
  515. irqreturn_t isci_intx_isr(int vec, void *data)
  516. {
  517. irqreturn_t ret = IRQ_NONE;
  518. struct isci_host *ihost = data;
  519. if (sci_controller_isr(ihost)) {
  520. writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status);
  521. tasklet_schedule(&ihost->completion_tasklet);
  522. ret = IRQ_HANDLED;
  523. } else if (sci_controller_error_isr(ihost)) {
  524. spin_lock(&ihost->scic_lock);
  525. sci_controller_error_handler(ihost);
  526. spin_unlock(&ihost->scic_lock);
  527. ret = IRQ_HANDLED;
  528. }
  529. return ret;
  530. }
  531. irqreturn_t isci_error_isr(int vec, void *data)
  532. {
  533. struct isci_host *ihost = data;
  534. if (sci_controller_error_isr(ihost))
  535. sci_controller_error_handler(ihost);
  536. return IRQ_HANDLED;
  537. }
  538. /**
  539. * isci_host_start_complete() - This function is called by the core library,
  540. * through the ISCI Module, to indicate controller start status.
  541. * @ihost: This parameter specifies the ISCI host object
  542. * @completion_status: This parameter specifies the completion status from the
  543. * core library.
  544. *
  545. */
  546. static void isci_host_start_complete(struct isci_host *ihost, enum sci_status completion_status)
  547. {
  548. if (completion_status != SCI_SUCCESS)
  549. dev_info(&ihost->pdev->dev,
  550. "controller start timed out, continuing...\n");
  551. clear_bit(IHOST_START_PENDING, &ihost->flags);
  552. wake_up(&ihost->eventq);
  553. }
  554. int isci_host_scan_finished(struct Scsi_Host *shost, unsigned long time)
  555. {
  556. struct sas_ha_struct *ha = SHOST_TO_SAS_HA(shost);
  557. struct isci_host *ihost = ha->lldd_ha;
  558. if (test_bit(IHOST_START_PENDING, &ihost->flags))
  559. return 0;
  560. sas_drain_work(ha);
  561. return 1;
  562. }
  563. /**
  564. * sci_controller_get_suggested_start_timeout() - This method returns the
  565. * suggested sci_controller_start() timeout amount. The user is free to
  566. * use any timeout value, but this method provides the suggested minimum
  567. * start timeout value. The returned value is based upon empirical
  568. * information determined as a result of interoperability testing.
  569. * @ihost: the handle to the controller object for which to return the
  570. * suggested start timeout.
  571. *
  572. * This method returns the number of milliseconds for the suggested start
  573. * operation timeout.
  574. */
  575. static u32 sci_controller_get_suggested_start_timeout(struct isci_host *ihost)
  576. {
  577. /* Validate the user supplied parameters. */
  578. if (!ihost)
  579. return 0;
  580. /*
  581. * The suggested minimum timeout value for a controller start operation:
  582. *
  583. * Signature FIS Timeout
  584. * + Phy Start Timeout
  585. * + Number of Phy Spin Up Intervals
  586. * ---------------------------------
  587. * Number of milliseconds for the controller start operation.
  588. *
  589. * NOTE: The number of phy spin up intervals will be equivalent
  590. * to the number of phys divided by the number phys allowed
  591. * per interval - 1 (once OEM parameters are supported).
  592. * Currently we assume only 1 phy per interval. */
  593. return SCIC_SDS_SIGNATURE_FIS_TIMEOUT
  594. + SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT
  595. + ((SCI_MAX_PHYS - 1) * SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
  596. }
  597. static void sci_controller_enable_interrupts(struct isci_host *ihost)
  598. {
  599. set_bit(IHOST_IRQ_ENABLED, &ihost->flags);
  600. writel(0, &ihost->smu_registers->interrupt_mask);
  601. }
  602. void sci_controller_disable_interrupts(struct isci_host *ihost)
  603. {
  604. clear_bit(IHOST_IRQ_ENABLED, &ihost->flags);
  605. writel(0xffffffff, &ihost->smu_registers->interrupt_mask);
  606. readl(&ihost->smu_registers->interrupt_mask); /* flush */
  607. }
  608. static void sci_controller_enable_port_task_scheduler(struct isci_host *ihost)
  609. {
  610. u32 port_task_scheduler_value;
  611. port_task_scheduler_value =
  612. readl(&ihost->scu_registers->peg0.ptsg.control);
  613. port_task_scheduler_value |=
  614. (SCU_PTSGCR_GEN_BIT(ETM_ENABLE) |
  615. SCU_PTSGCR_GEN_BIT(PTSG_ENABLE));
  616. writel(port_task_scheduler_value,
  617. &ihost->scu_registers->peg0.ptsg.control);
  618. }
  619. static void sci_controller_assign_task_entries(struct isci_host *ihost)
  620. {
  621. u32 task_assignment;
  622. /*
  623. * Assign all the TCs to function 0
  624. * TODO: Do we actually need to read this register to write it back?
  625. */
  626. task_assignment =
  627. readl(&ihost->smu_registers->task_context_assignment[0]);
  628. task_assignment |= (SMU_TCA_GEN_VAL(STARTING, 0)) |
  629. (SMU_TCA_GEN_VAL(ENDING, ihost->task_context_entries - 1)) |
  630. (SMU_TCA_GEN_BIT(RANGE_CHECK_ENABLE));
  631. writel(task_assignment,
  632. &ihost->smu_registers->task_context_assignment[0]);
  633. }
  634. static void sci_controller_initialize_completion_queue(struct isci_host *ihost)
  635. {
  636. u32 index;
  637. u32 completion_queue_control_value;
  638. u32 completion_queue_get_value;
  639. u32 completion_queue_put_value;
  640. ihost->completion_queue_get = 0;
  641. completion_queue_control_value =
  642. (SMU_CQC_QUEUE_LIMIT_SET(SCU_MAX_COMPLETION_QUEUE_ENTRIES - 1) |
  643. SMU_CQC_EVENT_LIMIT_SET(SCU_MAX_EVENTS - 1));
  644. writel(completion_queue_control_value,
  645. &ihost->smu_registers->completion_queue_control);
  646. /* Set the completion queue get pointer and enable the queue */
  647. completion_queue_get_value = (
  648. (SMU_CQGR_GEN_VAL(POINTER, 0))
  649. | (SMU_CQGR_GEN_VAL(EVENT_POINTER, 0))
  650. | (SMU_CQGR_GEN_BIT(ENABLE))
  651. | (SMU_CQGR_GEN_BIT(EVENT_ENABLE))
  652. );
  653. writel(completion_queue_get_value,
  654. &ihost->smu_registers->completion_queue_get);
  655. /* Set the completion queue put pointer */
  656. completion_queue_put_value = (
  657. (SMU_CQPR_GEN_VAL(POINTER, 0))
  658. | (SMU_CQPR_GEN_VAL(EVENT_POINTER, 0))
  659. );
  660. writel(completion_queue_put_value,
  661. &ihost->smu_registers->completion_queue_put);
  662. /* Initialize the cycle bit of the completion queue entries */
  663. for (index = 0; index < SCU_MAX_COMPLETION_QUEUE_ENTRIES; index++) {
  664. /*
  665. * If get.cycle_bit != completion_queue.cycle_bit
  666. * its not a valid completion queue entry
  667. * so at system start all entries are invalid */
  668. ihost->completion_queue[index] = 0x80000000;
  669. }
  670. }
  671. static void sci_controller_initialize_unsolicited_frame_queue(struct isci_host *ihost)
  672. {
  673. u32 frame_queue_control_value;
  674. u32 frame_queue_get_value;
  675. u32 frame_queue_put_value;
  676. /* Write the queue size */
  677. frame_queue_control_value =
  678. SCU_UFQC_GEN_VAL(QUEUE_SIZE, SCU_MAX_UNSOLICITED_FRAMES);
  679. writel(frame_queue_control_value,
  680. &ihost->scu_registers->sdma.unsolicited_frame_queue_control);
  681. /* Setup the get pointer for the unsolicited frame queue */
  682. frame_queue_get_value = (
  683. SCU_UFQGP_GEN_VAL(POINTER, 0)
  684. | SCU_UFQGP_GEN_BIT(ENABLE_BIT)
  685. );
  686. writel(frame_queue_get_value,
  687. &ihost->scu_registers->sdma.unsolicited_frame_get_pointer);
  688. /* Setup the put pointer for the unsolicited frame queue */
  689. frame_queue_put_value = SCU_UFQPP_GEN_VAL(POINTER, 0);
  690. writel(frame_queue_put_value,
  691. &ihost->scu_registers->sdma.unsolicited_frame_put_pointer);
  692. }
  693. void sci_controller_transition_to_ready(struct isci_host *ihost, enum sci_status status)
  694. {
  695. if (ihost->sm.current_state_id == SCIC_STARTING) {
  696. /*
  697. * We move into the ready state, because some of the phys/ports
  698. * may be up and operational.
  699. */
  700. sci_change_state(&ihost->sm, SCIC_READY);
  701. isci_host_start_complete(ihost, status);
  702. }
  703. }
  704. static bool is_phy_starting(struct isci_phy *iphy)
  705. {
  706. enum sci_phy_states state;
  707. state = iphy->sm.current_state_id;
  708. switch (state) {
  709. case SCI_PHY_STARTING:
  710. case SCI_PHY_SUB_INITIAL:
  711. case SCI_PHY_SUB_AWAIT_SAS_SPEED_EN:
  712. case SCI_PHY_SUB_AWAIT_IAF_UF:
  713. case SCI_PHY_SUB_AWAIT_SAS_POWER:
  714. case SCI_PHY_SUB_AWAIT_SATA_POWER:
  715. case SCI_PHY_SUB_AWAIT_SATA_PHY_EN:
  716. case SCI_PHY_SUB_AWAIT_SATA_SPEED_EN:
  717. case SCI_PHY_SUB_AWAIT_OSSP_EN:
  718. case SCI_PHY_SUB_AWAIT_SIG_FIS_UF:
  719. case SCI_PHY_SUB_FINAL:
  720. return true;
  721. default:
  722. return false;
  723. }
  724. }
  725. bool is_controller_start_complete(struct isci_host *ihost)
  726. {
  727. int i;
  728. for (i = 0; i < SCI_MAX_PHYS; i++) {
  729. struct isci_phy *iphy = &ihost->phys[i];
  730. u32 state = iphy->sm.current_state_id;
  731. /* in apc mode we need to check every phy, in
  732. * mpc mode we only need to check phys that have
  733. * been configured into a port
  734. */
  735. if (is_port_config_apc(ihost))
  736. /* pass */;
  737. else if (!phy_get_non_dummy_port(iphy))
  738. continue;
  739. /* The controller start operation is complete iff:
  740. * - all links have been given an opportunity to start
  741. * - have no indication of a connected device
  742. * - have an indication of a connected device and it has
  743. * finished the link training process.
  744. */
  745. if ((iphy->is_in_link_training == false && state == SCI_PHY_INITIAL) ||
  746. (iphy->is_in_link_training == false && state == SCI_PHY_STOPPED) ||
  747. (iphy->is_in_link_training == true && is_phy_starting(iphy)) ||
  748. (ihost->port_agent.phy_ready_mask != ihost->port_agent.phy_configured_mask))
  749. return false;
  750. }
  751. return true;
  752. }
  753. /**
  754. * sci_controller_start_next_phy - start phy
  755. * @ihost: controller
  756. *
  757. * If all the phys have been started, then attempt to transition the
  758. * controller to the READY state and inform the user
  759. * (sci_cb_controller_start_complete()).
  760. */
  761. static enum sci_status sci_controller_start_next_phy(struct isci_host *ihost)
  762. {
  763. struct sci_oem_params *oem = &ihost->oem_parameters;
  764. struct isci_phy *iphy;
  765. enum sci_status status;
  766. status = SCI_SUCCESS;
  767. if (ihost->phy_startup_timer_pending)
  768. return status;
  769. if (ihost->next_phy_to_start >= SCI_MAX_PHYS) {
  770. if (is_controller_start_complete(ihost)) {
  771. sci_controller_transition_to_ready(ihost, SCI_SUCCESS);
  772. sci_del_timer(&ihost->phy_timer);
  773. ihost->phy_startup_timer_pending = false;
  774. }
  775. } else {
  776. iphy = &ihost->phys[ihost->next_phy_to_start];
  777. if (oem->controller.mode_type == SCIC_PORT_MANUAL_CONFIGURATION_MODE) {
  778. if (phy_get_non_dummy_port(iphy) == NULL) {
  779. ihost->next_phy_to_start++;
  780. /* Caution recursion ahead be forwarned
  781. *
  782. * The PHY was never added to a PORT in MPC mode
  783. * so start the next phy in sequence This phy
  784. * will never go link up and will not draw power
  785. * the OEM parameters either configured the phy
  786. * incorrectly for the PORT or it was never
  787. * assigned to a PORT
  788. */
  789. return sci_controller_start_next_phy(ihost);
  790. }
  791. }
  792. status = sci_phy_start(iphy);
  793. if (status == SCI_SUCCESS) {
  794. sci_mod_timer(&ihost->phy_timer,
  795. SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT);
  796. ihost->phy_startup_timer_pending = true;
  797. } else {
  798. dev_warn(&ihost->pdev->dev,
  799. "%s: Controller stop operation failed "
  800. "to stop phy %d because of status "
  801. "%d.\n",
  802. __func__,
  803. ihost->phys[ihost->next_phy_to_start].phy_index,
  804. status);
  805. }
  806. ihost->next_phy_to_start++;
  807. }
  808. return status;
  809. }
  810. static void phy_startup_timeout(struct timer_list *t)
  811. {
  812. struct sci_timer *tmr = from_timer(tmr, t, timer);
  813. struct isci_host *ihost = container_of(tmr, typeof(*ihost), phy_timer);
  814. unsigned long flags;
  815. enum sci_status status;
  816. spin_lock_irqsave(&ihost->scic_lock, flags);
  817. if (tmr->cancel)
  818. goto done;
  819. ihost->phy_startup_timer_pending = false;
  820. do {
  821. status = sci_controller_start_next_phy(ihost);
  822. } while (status != SCI_SUCCESS);
  823. done:
  824. spin_unlock_irqrestore(&ihost->scic_lock, flags);
  825. }
  826. static u16 isci_tci_active(struct isci_host *ihost)
  827. {
  828. return CIRC_CNT(ihost->tci_head, ihost->tci_tail, SCI_MAX_IO_REQUESTS);
  829. }
  830. static enum sci_status sci_controller_start(struct isci_host *ihost,
  831. u32 timeout)
  832. {
  833. enum sci_status result;
  834. u16 index;
  835. if (ihost->sm.current_state_id != SCIC_INITIALIZED) {
  836. dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
  837. __func__, ihost->sm.current_state_id);
  838. return SCI_FAILURE_INVALID_STATE;
  839. }
  840. /* Build the TCi free pool */
  841. BUILD_BUG_ON(SCI_MAX_IO_REQUESTS > 1 << sizeof(ihost->tci_pool[0]) * 8);
  842. ihost->tci_head = 0;
  843. ihost->tci_tail = 0;
  844. for (index = 0; index < ihost->task_context_entries; index++)
  845. isci_tci_free(ihost, index);
  846. /* Build the RNi free pool */
  847. sci_remote_node_table_initialize(&ihost->available_remote_nodes,
  848. ihost->remote_node_entries);
  849. /*
  850. * Before anything else lets make sure we will not be
  851. * interrupted by the hardware.
  852. */
  853. sci_controller_disable_interrupts(ihost);
  854. /* Enable the port task scheduler */
  855. sci_controller_enable_port_task_scheduler(ihost);
  856. /* Assign all the task entries to ihost physical function */
  857. sci_controller_assign_task_entries(ihost);
  858. /* Now initialize the completion queue */
  859. sci_controller_initialize_completion_queue(ihost);
  860. /* Initialize the unsolicited frame queue for use */
  861. sci_controller_initialize_unsolicited_frame_queue(ihost);
  862. /* Start all of the ports on this controller */
  863. for (index = 0; index < ihost->logical_port_entries; index++) {
  864. struct isci_port *iport = &ihost->ports[index];
  865. result = sci_port_start(iport);
  866. if (result)
  867. return result;
  868. }
  869. sci_controller_start_next_phy(ihost);
  870. sci_mod_timer(&ihost->timer, timeout);
  871. sci_change_state(&ihost->sm, SCIC_STARTING);
  872. return SCI_SUCCESS;
  873. }
  874. void isci_host_start(struct Scsi_Host *shost)
  875. {
  876. struct isci_host *ihost = SHOST_TO_SAS_HA(shost)->lldd_ha;
  877. unsigned long tmo = sci_controller_get_suggested_start_timeout(ihost);
  878. set_bit(IHOST_START_PENDING, &ihost->flags);
  879. spin_lock_irq(&ihost->scic_lock);
  880. sci_controller_start(ihost, tmo);
  881. sci_controller_enable_interrupts(ihost);
  882. spin_unlock_irq(&ihost->scic_lock);
  883. }
  884. static void isci_host_stop_complete(struct isci_host *ihost)
  885. {
  886. sci_controller_disable_interrupts(ihost);
  887. clear_bit(IHOST_STOP_PENDING, &ihost->flags);
  888. wake_up(&ihost->eventq);
  889. }
  890. static void sci_controller_completion_handler(struct isci_host *ihost)
  891. {
  892. /* Empty out the completion queue */
  893. if (sci_controller_completion_queue_has_entries(ihost))
  894. sci_controller_process_completions(ihost);
  895. /* Clear the interrupt and enable all interrupts again */
  896. writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status);
  897. /* Could we write the value of SMU_ISR_COMPLETION? */
  898. writel(0xFF000000, &ihost->smu_registers->interrupt_mask);
  899. writel(0, &ihost->smu_registers->interrupt_mask);
  900. }
  901. void ireq_done(struct isci_host *ihost, struct isci_request *ireq, struct sas_task *task)
  902. {
  903. if (!test_bit(IREQ_ABORT_PATH_ACTIVE, &ireq->flags) &&
  904. !(task->task_state_flags & SAS_TASK_STATE_ABORTED)) {
  905. if (test_bit(IREQ_COMPLETE_IN_TARGET, &ireq->flags)) {
  906. /* Normal notification (task_done) */
  907. dev_dbg(&ihost->pdev->dev,
  908. "%s: Normal - ireq/task = %p/%p\n",
  909. __func__, ireq, task);
  910. task->lldd_task = NULL;
  911. task->task_done(task);
  912. } else {
  913. dev_dbg(&ihost->pdev->dev,
  914. "%s: Error - ireq/task = %p/%p\n",
  915. __func__, ireq, task);
  916. if (sas_protocol_ata(task->task_proto))
  917. task->lldd_task = NULL;
  918. sas_task_abort(task);
  919. }
  920. } else
  921. task->lldd_task = NULL;
  922. if (test_and_clear_bit(IREQ_ABORT_PATH_ACTIVE, &ireq->flags))
  923. wake_up_all(&ihost->eventq);
  924. if (!test_bit(IREQ_NO_AUTO_FREE_TAG, &ireq->flags))
  925. isci_free_tag(ihost, ireq->io_tag);
  926. }
  927. /**
  928. * isci_host_completion_routine() - This function is the delayed service
  929. * routine that calls the sci core library's completion handler. It's
  930. * scheduled as a tasklet from the interrupt service routine when interrupts
  931. * in use, or set as the timeout function in polled mode.
  932. * @data: This parameter specifies the ISCI host object
  933. *
  934. */
  935. void isci_host_completion_routine(unsigned long data)
  936. {
  937. struct isci_host *ihost = (struct isci_host *)data;
  938. u16 active;
  939. spin_lock_irq(&ihost->scic_lock);
  940. sci_controller_completion_handler(ihost);
  941. spin_unlock_irq(&ihost->scic_lock);
  942. /*
  943. * we subtract SCI_MAX_PORTS to account for the number of dummy TCs
  944. * issued for hardware issue workaround
  945. */
  946. active = isci_tci_active(ihost) - SCI_MAX_PORTS;
  947. /*
  948. * the coalesence timeout doubles at each encoding step, so
  949. * update it based on the ilog2 value of the outstanding requests
  950. */
  951. writel(SMU_ICC_GEN_VAL(NUMBER, active) |
  952. SMU_ICC_GEN_VAL(TIMER, ISCI_COALESCE_BASE + ilog2(active)),
  953. &ihost->smu_registers->interrupt_coalesce_control);
  954. }
  955. /**
  956. * sci_controller_stop() - This method will stop an individual controller
  957. * object.This method will invoke the associated user callback upon
  958. * completion. The completion callback is called when the following
  959. * conditions are met: -# the method return status is SCI_SUCCESS. -# the
  960. * controller has been quiesced. This method will ensure that all IO
  961. * requests are quiesced, phys are stopped, and all additional operation by
  962. * the hardware is halted.
  963. * @ihost: the handle to the controller object to stop.
  964. * @timeout: This parameter specifies the number of milliseconds in which the
  965. * stop operation should complete.
  966. *
  967. * The controller must be in the STARTED or STOPPED state. Indicate if the
  968. * controller stop method succeeded or failed in some way. SCI_SUCCESS if the
  969. * stop operation successfully began. SCI_WARNING_ALREADY_IN_STATE if the
  970. * controller is already in the STOPPED state. SCI_FAILURE_INVALID_STATE if the
  971. * controller is not either in the STARTED or STOPPED states.
  972. */
  973. static enum sci_status sci_controller_stop(struct isci_host *ihost, u32 timeout)
  974. {
  975. if (ihost->sm.current_state_id != SCIC_READY) {
  976. dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
  977. __func__, ihost->sm.current_state_id);
  978. return SCI_FAILURE_INVALID_STATE;
  979. }
  980. sci_mod_timer(&ihost->timer, timeout);
  981. sci_change_state(&ihost->sm, SCIC_STOPPING);
  982. return SCI_SUCCESS;
  983. }
  984. /**
  985. * sci_controller_reset() - This method will reset the supplied core
  986. * controller regardless of the state of said controller. This operation is
  987. * considered destructive. In other words, all current operations are wiped
  988. * out. No IO completions for outstanding devices occur. Outstanding IO
  989. * requests are not aborted or completed at the actual remote device.
  990. * @ihost: the handle to the controller object to reset.
  991. *
  992. * Indicate if the controller reset method succeeded or failed in some way.
  993. * SCI_SUCCESS if the reset operation successfully started. SCI_FATAL_ERROR if
  994. * the controller reset operation is unable to complete.
  995. */
  996. static enum sci_status sci_controller_reset(struct isci_host *ihost)
  997. {
  998. switch (ihost->sm.current_state_id) {
  999. case SCIC_RESET:
  1000. case SCIC_READY:
  1001. case SCIC_STOPPING:
  1002. case SCIC_FAILED:
  1003. /*
  1004. * The reset operation is not a graceful cleanup, just
  1005. * perform the state transition.
  1006. */
  1007. sci_change_state(&ihost->sm, SCIC_RESETTING);
  1008. return SCI_SUCCESS;
  1009. default:
  1010. dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
  1011. __func__, ihost->sm.current_state_id);
  1012. return SCI_FAILURE_INVALID_STATE;
  1013. }
  1014. }
  1015. static enum sci_status sci_controller_stop_phys(struct isci_host *ihost)
  1016. {
  1017. u32 index;
  1018. enum sci_status status;
  1019. enum sci_status phy_status;
  1020. status = SCI_SUCCESS;
  1021. for (index = 0; index < SCI_MAX_PHYS; index++) {
  1022. phy_status = sci_phy_stop(&ihost->phys[index]);
  1023. if (phy_status != SCI_SUCCESS &&
  1024. phy_status != SCI_FAILURE_INVALID_STATE) {
  1025. status = SCI_FAILURE;
  1026. dev_warn(&ihost->pdev->dev,
  1027. "%s: Controller stop operation failed to stop "
  1028. "phy %d because of status %d.\n",
  1029. __func__,
  1030. ihost->phys[index].phy_index, phy_status);
  1031. }
  1032. }
  1033. return status;
  1034. }
  1035. /**
  1036. * isci_host_deinit - shutdown frame reception and dma
  1037. * @ihost: host to take down
  1038. *
  1039. * This is called in either the driver shutdown or the suspend path. In
  1040. * the shutdown case libsas went through port teardown and normal device
  1041. * removal (i.e. physical links stayed up to service scsi_device removal
  1042. * commands). In the suspend case we disable the hardware without
  1043. * notifying libsas of the link down events since we want libsas to
  1044. * remember the domain across the suspend/resume cycle
  1045. */
  1046. void isci_host_deinit(struct isci_host *ihost)
  1047. {
  1048. int i;
  1049. /* disable output data selects */
  1050. for (i = 0; i < isci_gpio_count(ihost); i++)
  1051. writel(SGPIO_HW_CONTROL, &ihost->scu_registers->peg0.sgpio.output_data_select[i]);
  1052. set_bit(IHOST_STOP_PENDING, &ihost->flags);
  1053. spin_lock_irq(&ihost->scic_lock);
  1054. sci_controller_stop(ihost, SCIC_CONTROLLER_STOP_TIMEOUT);
  1055. spin_unlock_irq(&ihost->scic_lock);
  1056. wait_for_stop(ihost);
  1057. /* phy stop is after controller stop to allow port and device to
  1058. * go idle before shutting down the phys, but the expectation is
  1059. * that i/o has been shut off well before we reach this
  1060. * function.
  1061. */
  1062. sci_controller_stop_phys(ihost);
  1063. /* disable sgpio: where the above wait should give time for the
  1064. * enclosure to sample the gpios going inactive
  1065. */
  1066. writel(0, &ihost->scu_registers->peg0.sgpio.interface_control);
  1067. spin_lock_irq(&ihost->scic_lock);
  1068. sci_controller_reset(ihost);
  1069. spin_unlock_irq(&ihost->scic_lock);
  1070. /* Cancel any/all outstanding port timers */
  1071. for (i = 0; i < ihost->logical_port_entries; i++) {
  1072. struct isci_port *iport = &ihost->ports[i];
  1073. del_timer_sync(&iport->timer.timer);
  1074. }
  1075. /* Cancel any/all outstanding phy timers */
  1076. for (i = 0; i < SCI_MAX_PHYS; i++) {
  1077. struct isci_phy *iphy = &ihost->phys[i];
  1078. del_timer_sync(&iphy->sata_timer.timer);
  1079. }
  1080. del_timer_sync(&ihost->port_agent.timer.timer);
  1081. del_timer_sync(&ihost->power_control.timer.timer);
  1082. del_timer_sync(&ihost->timer.timer);
  1083. del_timer_sync(&ihost->phy_timer.timer);
  1084. }
  1085. static void __iomem *scu_base(struct isci_host *isci_host)
  1086. {
  1087. struct pci_dev *pdev = isci_host->pdev;
  1088. int id = isci_host->id;
  1089. return pcim_iomap_table(pdev)[SCI_SCU_BAR * 2] + SCI_SCU_BAR_SIZE * id;
  1090. }
  1091. static void __iomem *smu_base(struct isci_host *isci_host)
  1092. {
  1093. struct pci_dev *pdev = isci_host->pdev;
  1094. int id = isci_host->id;
  1095. return pcim_iomap_table(pdev)[SCI_SMU_BAR * 2] + SCI_SMU_BAR_SIZE * id;
  1096. }
  1097. static void sci_controller_initial_state_enter(struct sci_base_state_machine *sm)
  1098. {
  1099. struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
  1100. sci_change_state(&ihost->sm, SCIC_RESET);
  1101. }
  1102. static inline void sci_controller_starting_state_exit(struct sci_base_state_machine *sm)
  1103. {
  1104. struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
  1105. sci_del_timer(&ihost->timer);
  1106. }
  1107. #define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS 853
  1108. #define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS 1280
  1109. #define INTERRUPT_COALESCE_TIMEOUT_MAX_US 2700000
  1110. #define INTERRUPT_COALESCE_NUMBER_MAX 256
  1111. #define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN 7
  1112. #define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX 28
  1113. /**
  1114. * sci_controller_set_interrupt_coalescence() - This method allows the user to
  1115. * configure the interrupt coalescence.
  1116. * @ihost: This parameter represents the handle to the controller object
  1117. * for which its interrupt coalesce register is overridden.
  1118. * @coalesce_number: Used to control the number of entries in the Completion
  1119. * Queue before an interrupt is generated. If the number of entries exceed
  1120. * this number, an interrupt will be generated. The valid range of the input
  1121. * is [0, 256]. A setting of 0 results in coalescing being disabled.
  1122. * @coalesce_timeout: Timeout value in microseconds. The valid range of the
  1123. * input is [0, 2700000] . A setting of 0 is allowed and results in no
  1124. * interrupt coalescing timeout.
  1125. *
  1126. * Indicate if the user successfully set the interrupt coalesce parameters.
  1127. * SCI_SUCCESS The user successfully updated the interrutp coalescence.
  1128. * SCI_FAILURE_INVALID_PARAMETER_VALUE The user input value is out of range.
  1129. */
  1130. static enum sci_status
  1131. sci_controller_set_interrupt_coalescence(struct isci_host *ihost,
  1132. u32 coalesce_number,
  1133. u32 coalesce_timeout)
  1134. {
  1135. u8 timeout_encode = 0;
  1136. u32 min = 0;
  1137. u32 max = 0;
  1138. /* Check if the input parameters fall in the range. */
  1139. if (coalesce_number > INTERRUPT_COALESCE_NUMBER_MAX)
  1140. return SCI_FAILURE_INVALID_PARAMETER_VALUE;
  1141. /*
  1142. * Defined encoding for interrupt coalescing timeout:
  1143. * Value Min Max Units
  1144. * ----- --- --- -----
  1145. * 0 - - Disabled
  1146. * 1 13.3 20.0 ns
  1147. * 2 26.7 40.0
  1148. * 3 53.3 80.0
  1149. * 4 106.7 160.0
  1150. * 5 213.3 320.0
  1151. * 6 426.7 640.0
  1152. * 7 853.3 1280.0
  1153. * 8 1.7 2.6 us
  1154. * 9 3.4 5.1
  1155. * 10 6.8 10.2
  1156. * 11 13.7 20.5
  1157. * 12 27.3 41.0
  1158. * 13 54.6 81.9
  1159. * 14 109.2 163.8
  1160. * 15 218.5 327.7
  1161. * 16 436.9 655.4
  1162. * 17 873.8 1310.7
  1163. * 18 1.7 2.6 ms
  1164. * 19 3.5 5.2
  1165. * 20 7.0 10.5
  1166. * 21 14.0 21.0
  1167. * 22 28.0 41.9
  1168. * 23 55.9 83.9
  1169. * 24 111.8 167.8
  1170. * 25 223.7 335.5
  1171. * 26 447.4 671.1
  1172. * 27 894.8 1342.2
  1173. * 28 1.8 2.7 s
  1174. * Others Undefined */
  1175. /*
  1176. * Use the table above to decide the encode of interrupt coalescing timeout
  1177. * value for register writing. */
  1178. if (coalesce_timeout == 0)
  1179. timeout_encode = 0;
  1180. else{
  1181. /* make the timeout value in unit of (10 ns). */
  1182. coalesce_timeout = coalesce_timeout * 100;
  1183. min = INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS / 10;
  1184. max = INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS / 10;
  1185. /* get the encode of timeout for register writing. */
  1186. for (timeout_encode = INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN;
  1187. timeout_encode <= INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX;
  1188. timeout_encode++) {
  1189. if (min <= coalesce_timeout && max > coalesce_timeout)
  1190. break;
  1191. else if (coalesce_timeout >= max && coalesce_timeout < min * 2
  1192. && coalesce_timeout <= INTERRUPT_COALESCE_TIMEOUT_MAX_US * 100) {
  1193. if ((coalesce_timeout - max) < (2 * min - coalesce_timeout))
  1194. break;
  1195. else{
  1196. timeout_encode++;
  1197. break;
  1198. }
  1199. } else {
  1200. max = max * 2;
  1201. min = min * 2;
  1202. }
  1203. }
  1204. if (timeout_encode == INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX + 1)
  1205. /* the value is out of range. */
  1206. return SCI_FAILURE_INVALID_PARAMETER_VALUE;
  1207. }
  1208. writel(SMU_ICC_GEN_VAL(NUMBER, coalesce_number) |
  1209. SMU_ICC_GEN_VAL(TIMER, timeout_encode),
  1210. &ihost->smu_registers->interrupt_coalesce_control);
  1211. ihost->interrupt_coalesce_number = (u16)coalesce_number;
  1212. ihost->interrupt_coalesce_timeout = coalesce_timeout / 100;
  1213. return SCI_SUCCESS;
  1214. }
  1215. static void sci_controller_ready_state_enter(struct sci_base_state_machine *sm)
  1216. {
  1217. struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
  1218. u32 val;
  1219. /* enable clock gating for power control of the scu unit */
  1220. val = readl(&ihost->smu_registers->clock_gating_control);
  1221. val &= ~(SMU_CGUCR_GEN_BIT(REGCLK_ENABLE) |
  1222. SMU_CGUCR_GEN_BIT(TXCLK_ENABLE) |
  1223. SMU_CGUCR_GEN_BIT(XCLK_ENABLE));
  1224. val |= SMU_CGUCR_GEN_BIT(IDLE_ENABLE);
  1225. writel(val, &ihost->smu_registers->clock_gating_control);
  1226. /* set the default interrupt coalescence number and timeout value. */
  1227. sci_controller_set_interrupt_coalescence(ihost, 0, 0);
  1228. }
  1229. static void sci_controller_ready_state_exit(struct sci_base_state_machine *sm)
  1230. {
  1231. struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
  1232. /* disable interrupt coalescence. */
  1233. sci_controller_set_interrupt_coalescence(ihost, 0, 0);
  1234. }
  1235. static enum sci_status sci_controller_stop_ports(struct isci_host *ihost)
  1236. {
  1237. u32 index;
  1238. enum sci_status port_status;
  1239. enum sci_status status = SCI_SUCCESS;
  1240. for (index = 0; index < ihost->logical_port_entries; index++) {
  1241. struct isci_port *iport = &ihost->ports[index];
  1242. port_status = sci_port_stop(iport);
  1243. if ((port_status != SCI_SUCCESS) &&
  1244. (port_status != SCI_FAILURE_INVALID_STATE)) {
  1245. status = SCI_FAILURE;
  1246. dev_warn(&ihost->pdev->dev,
  1247. "%s: Controller stop operation failed to "
  1248. "stop port %d because of status %d.\n",
  1249. __func__,
  1250. iport->logical_port_index,
  1251. port_status);
  1252. }
  1253. }
  1254. return status;
  1255. }
  1256. static enum sci_status sci_controller_stop_devices(struct isci_host *ihost)
  1257. {
  1258. u32 index;
  1259. enum sci_status status;
  1260. enum sci_status device_status;
  1261. status = SCI_SUCCESS;
  1262. for (index = 0; index < ihost->remote_node_entries; index++) {
  1263. if (ihost->device_table[index] != NULL) {
  1264. /* / @todo What timeout value do we want to provide to this request? */
  1265. device_status = sci_remote_device_stop(ihost->device_table[index], 0);
  1266. if ((device_status != SCI_SUCCESS) &&
  1267. (device_status != SCI_FAILURE_INVALID_STATE)) {
  1268. dev_warn(&ihost->pdev->dev,
  1269. "%s: Controller stop operation failed "
  1270. "to stop device 0x%p because of "
  1271. "status %d.\n",
  1272. __func__,
  1273. ihost->device_table[index], device_status);
  1274. }
  1275. }
  1276. }
  1277. return status;
  1278. }
  1279. static void sci_controller_stopping_state_enter(struct sci_base_state_machine *sm)
  1280. {
  1281. struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
  1282. sci_controller_stop_devices(ihost);
  1283. sci_controller_stop_ports(ihost);
  1284. if (!sci_controller_has_remote_devices_stopping(ihost))
  1285. isci_host_stop_complete(ihost);
  1286. }
  1287. static void sci_controller_stopping_state_exit(struct sci_base_state_machine *sm)
  1288. {
  1289. struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
  1290. sci_del_timer(&ihost->timer);
  1291. }
  1292. static void sci_controller_reset_hardware(struct isci_host *ihost)
  1293. {
  1294. /* Disable interrupts so we dont take any spurious interrupts */
  1295. sci_controller_disable_interrupts(ihost);
  1296. /* Reset the SCU */
  1297. writel(0xFFFFFFFF, &ihost->smu_registers->soft_reset_control);
  1298. /* Delay for 1ms to before clearing the CQP and UFQPR. */
  1299. udelay(1000);
  1300. /* The write to the CQGR clears the CQP */
  1301. writel(0x00000000, &ihost->smu_registers->completion_queue_get);
  1302. /* The write to the UFQGP clears the UFQPR */
  1303. writel(0, &ihost->scu_registers->sdma.unsolicited_frame_get_pointer);
  1304. /* clear all interrupts */
  1305. writel(~SMU_INTERRUPT_STATUS_RESERVED_MASK, &ihost->smu_registers->interrupt_status);
  1306. }
  1307. static void sci_controller_resetting_state_enter(struct sci_base_state_machine *sm)
  1308. {
  1309. struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
  1310. sci_controller_reset_hardware(ihost);
  1311. sci_change_state(&ihost->sm, SCIC_RESET);
  1312. }
  1313. static const struct sci_base_state sci_controller_state_table[] = {
  1314. [SCIC_INITIAL] = {
  1315. .enter_state = sci_controller_initial_state_enter,
  1316. },
  1317. [SCIC_RESET] = {},
  1318. [SCIC_INITIALIZING] = {},
  1319. [SCIC_INITIALIZED] = {},
  1320. [SCIC_STARTING] = {
  1321. .exit_state = sci_controller_starting_state_exit,
  1322. },
  1323. [SCIC_READY] = {
  1324. .enter_state = sci_controller_ready_state_enter,
  1325. .exit_state = sci_controller_ready_state_exit,
  1326. },
  1327. [SCIC_RESETTING] = {
  1328. .enter_state = sci_controller_resetting_state_enter,
  1329. },
  1330. [SCIC_STOPPING] = {
  1331. .enter_state = sci_controller_stopping_state_enter,
  1332. .exit_state = sci_controller_stopping_state_exit,
  1333. },
  1334. [SCIC_FAILED] = {}
  1335. };
  1336. static void controller_timeout(struct timer_list *t)
  1337. {
  1338. struct sci_timer *tmr = from_timer(tmr, t, timer);
  1339. struct isci_host *ihost = container_of(tmr, typeof(*ihost), timer);
  1340. struct sci_base_state_machine *sm = &ihost->sm;
  1341. unsigned long flags;
  1342. spin_lock_irqsave(&ihost->scic_lock, flags);
  1343. if (tmr->cancel)
  1344. goto done;
  1345. if (sm->current_state_id == SCIC_STARTING)
  1346. sci_controller_transition_to_ready(ihost, SCI_FAILURE_TIMEOUT);
  1347. else if (sm->current_state_id == SCIC_STOPPING) {
  1348. sci_change_state(sm, SCIC_FAILED);
  1349. isci_host_stop_complete(ihost);
  1350. } else /* / @todo Now what do we want to do in this case? */
  1351. dev_err(&ihost->pdev->dev,
  1352. "%s: Controller timer fired when controller was not "
  1353. "in a state being timed.\n",
  1354. __func__);
  1355. done:
  1356. spin_unlock_irqrestore(&ihost->scic_lock, flags);
  1357. }
  1358. static enum sci_status sci_controller_construct(struct isci_host *ihost,
  1359. void __iomem *scu_base,
  1360. void __iomem *smu_base)
  1361. {
  1362. u8 i;
  1363. sci_init_sm(&ihost->sm, sci_controller_state_table, SCIC_INITIAL);
  1364. ihost->scu_registers = scu_base;
  1365. ihost->smu_registers = smu_base;
  1366. sci_port_configuration_agent_construct(&ihost->port_agent);
  1367. /* Construct the ports for this controller */
  1368. for (i = 0; i < SCI_MAX_PORTS; i++)
  1369. sci_port_construct(&ihost->ports[i], i, ihost);
  1370. sci_port_construct(&ihost->ports[i], SCIC_SDS_DUMMY_PORT, ihost);
  1371. /* Construct the phys for this controller */
  1372. for (i = 0; i < SCI_MAX_PHYS; i++) {
  1373. /* Add all the PHYs to the dummy port */
  1374. sci_phy_construct(&ihost->phys[i],
  1375. &ihost->ports[SCI_MAX_PORTS], i);
  1376. }
  1377. ihost->invalid_phy_mask = 0;
  1378. sci_init_timer(&ihost->timer, controller_timeout);
  1379. return sci_controller_reset(ihost);
  1380. }
  1381. int sci_oem_parameters_validate(struct sci_oem_params *oem, u8 version)
  1382. {
  1383. int i;
  1384. for (i = 0; i < SCI_MAX_PORTS; i++)
  1385. if (oem->ports[i].phy_mask > SCIC_SDS_PARM_PHY_MASK_MAX)
  1386. return -EINVAL;
  1387. for (i = 0; i < SCI_MAX_PHYS; i++)
  1388. if (oem->phys[i].sas_address.high == 0 &&
  1389. oem->phys[i].sas_address.low == 0)
  1390. return -EINVAL;
  1391. if (oem->controller.mode_type == SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE) {
  1392. for (i = 0; i < SCI_MAX_PHYS; i++)
  1393. if (oem->ports[i].phy_mask != 0)
  1394. return -EINVAL;
  1395. } else if (oem->controller.mode_type == SCIC_PORT_MANUAL_CONFIGURATION_MODE) {
  1396. u8 phy_mask = 0;
  1397. for (i = 0; i < SCI_MAX_PHYS; i++)
  1398. phy_mask |= oem->ports[i].phy_mask;
  1399. if (phy_mask == 0)
  1400. return -EINVAL;
  1401. } else
  1402. return -EINVAL;
  1403. if (oem->controller.max_concurr_spin_up > MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT ||
  1404. oem->controller.max_concurr_spin_up < 1)
  1405. return -EINVAL;
  1406. if (oem->controller.do_enable_ssc) {
  1407. if (version < ISCI_ROM_VER_1_1 && oem->controller.do_enable_ssc != 1)
  1408. return -EINVAL;
  1409. if (version >= ISCI_ROM_VER_1_1) {
  1410. u8 test = oem->controller.ssc_sata_tx_spread_level;
  1411. switch (test) {
  1412. case 0:
  1413. case 2:
  1414. case 3:
  1415. case 6:
  1416. case 7:
  1417. break;
  1418. default:
  1419. return -EINVAL;
  1420. }
  1421. test = oem->controller.ssc_sas_tx_spread_level;
  1422. if (oem->controller.ssc_sas_tx_type == 0) {
  1423. switch (test) {
  1424. case 0:
  1425. case 2:
  1426. case 3:
  1427. break;
  1428. default:
  1429. return -EINVAL;
  1430. }
  1431. } else if (oem->controller.ssc_sas_tx_type == 1) {
  1432. switch (test) {
  1433. case 0:
  1434. case 3:
  1435. case 6:
  1436. break;
  1437. default:
  1438. return -EINVAL;
  1439. }
  1440. }
  1441. }
  1442. }
  1443. return 0;
  1444. }
  1445. static u8 max_spin_up(struct isci_host *ihost)
  1446. {
  1447. if (ihost->user_parameters.max_concurr_spinup)
  1448. return min_t(u8, ihost->user_parameters.max_concurr_spinup,
  1449. MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT);
  1450. else
  1451. return min_t(u8, ihost->oem_parameters.controller.max_concurr_spin_up,
  1452. MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT);
  1453. }
  1454. static void power_control_timeout(struct timer_list *t)
  1455. {
  1456. struct sci_timer *tmr = from_timer(tmr, t, timer);
  1457. struct isci_host *ihost = container_of(tmr, typeof(*ihost), power_control.timer);
  1458. struct isci_phy *iphy;
  1459. unsigned long flags;
  1460. u8 i;
  1461. spin_lock_irqsave(&ihost->scic_lock, flags);
  1462. if (tmr->cancel)
  1463. goto done;
  1464. ihost->power_control.phys_granted_power = 0;
  1465. if (ihost->power_control.phys_waiting == 0) {
  1466. ihost->power_control.timer_started = false;
  1467. goto done;
  1468. }
  1469. for (i = 0; i < SCI_MAX_PHYS; i++) {
  1470. if (ihost->power_control.phys_waiting == 0)
  1471. break;
  1472. iphy = ihost->power_control.requesters[i];
  1473. if (iphy == NULL)
  1474. continue;
  1475. if (ihost->power_control.phys_granted_power >= max_spin_up(ihost))
  1476. break;
  1477. ihost->power_control.requesters[i] = NULL;
  1478. ihost->power_control.phys_waiting--;
  1479. ihost->power_control.phys_granted_power++;
  1480. sci_phy_consume_power_handler(iphy);
  1481. if (iphy->protocol == SAS_PROTOCOL_SSP) {
  1482. u8 j;
  1483. for (j = 0; j < SCI_MAX_PHYS; j++) {
  1484. struct isci_phy *requester = ihost->power_control.requesters[j];
  1485. /*
  1486. * Search the power_control queue to see if there are other phys
  1487. * attached to the same remote device. If found, take all of
  1488. * them out of await_sas_power state.
  1489. */
  1490. if (requester != NULL && requester != iphy) {
  1491. u8 other = memcmp(requester->frame_rcvd.iaf.sas_addr,
  1492. iphy->frame_rcvd.iaf.sas_addr,
  1493. sizeof(requester->frame_rcvd.iaf.sas_addr));
  1494. if (other == 0) {
  1495. ihost->power_control.requesters[j] = NULL;
  1496. ihost->power_control.phys_waiting--;
  1497. sci_phy_consume_power_handler(requester);
  1498. }
  1499. }
  1500. }
  1501. }
  1502. }
  1503. /*
  1504. * It doesn't matter if the power list is empty, we need to start the
  1505. * timer in case another phy becomes ready.
  1506. */
  1507. sci_mod_timer(tmr, SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
  1508. ihost->power_control.timer_started = true;
  1509. done:
  1510. spin_unlock_irqrestore(&ihost->scic_lock, flags);
  1511. }
  1512. void sci_controller_power_control_queue_insert(struct isci_host *ihost,
  1513. struct isci_phy *iphy)
  1514. {
  1515. BUG_ON(iphy == NULL);
  1516. if (ihost->power_control.phys_granted_power < max_spin_up(ihost)) {
  1517. ihost->power_control.phys_granted_power++;
  1518. sci_phy_consume_power_handler(iphy);
  1519. /*
  1520. * stop and start the power_control timer. When the timer fires, the
  1521. * no_of_phys_granted_power will be set to 0
  1522. */
  1523. if (ihost->power_control.timer_started)
  1524. sci_del_timer(&ihost->power_control.timer);
  1525. sci_mod_timer(&ihost->power_control.timer,
  1526. SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
  1527. ihost->power_control.timer_started = true;
  1528. } else {
  1529. /*
  1530. * There are phys, attached to the same sas address as this phy, are
  1531. * already in READY state, this phy don't need wait.
  1532. */
  1533. u8 i;
  1534. struct isci_phy *current_phy;
  1535. for (i = 0; i < SCI_MAX_PHYS; i++) {
  1536. u8 other;
  1537. current_phy = &ihost->phys[i];
  1538. other = memcmp(current_phy->frame_rcvd.iaf.sas_addr,
  1539. iphy->frame_rcvd.iaf.sas_addr,
  1540. sizeof(current_phy->frame_rcvd.iaf.sas_addr));
  1541. if (current_phy->sm.current_state_id == SCI_PHY_READY &&
  1542. current_phy->protocol == SAS_PROTOCOL_SSP &&
  1543. other == 0) {
  1544. sci_phy_consume_power_handler(iphy);
  1545. break;
  1546. }
  1547. }
  1548. if (i == SCI_MAX_PHYS) {
  1549. /* Add the phy in the waiting list */
  1550. ihost->power_control.requesters[iphy->phy_index] = iphy;
  1551. ihost->power_control.phys_waiting++;
  1552. }
  1553. }
  1554. }
  1555. void sci_controller_power_control_queue_remove(struct isci_host *ihost,
  1556. struct isci_phy *iphy)
  1557. {
  1558. BUG_ON(iphy == NULL);
  1559. if (ihost->power_control.requesters[iphy->phy_index])
  1560. ihost->power_control.phys_waiting--;
  1561. ihost->power_control.requesters[iphy->phy_index] = NULL;
  1562. }
  1563. static int is_long_cable(int phy, unsigned char selection_byte)
  1564. {
  1565. return !!(selection_byte & (1 << phy));
  1566. }
  1567. static int is_medium_cable(int phy, unsigned char selection_byte)
  1568. {
  1569. return !!(selection_byte & (1 << (phy + 4)));
  1570. }
  1571. static enum cable_selections decode_selection_byte(
  1572. int phy,
  1573. unsigned char selection_byte)
  1574. {
  1575. return ((selection_byte & (1 << phy)) ? 1 : 0)
  1576. + (selection_byte & (1 << (phy + 4)) ? 2 : 0);
  1577. }
  1578. static unsigned char *to_cable_select(struct isci_host *ihost)
  1579. {
  1580. if (is_cable_select_overridden())
  1581. return ((unsigned char *)&cable_selection_override)
  1582. + ihost->id;
  1583. else
  1584. return &ihost->oem_parameters.controller.cable_selection_mask;
  1585. }
  1586. enum cable_selections decode_cable_selection(struct isci_host *ihost, int phy)
  1587. {
  1588. return decode_selection_byte(phy, *to_cable_select(ihost));
  1589. }
  1590. char *lookup_cable_names(enum cable_selections selection)
  1591. {
  1592. static char *cable_names[] = {
  1593. [short_cable] = "short",
  1594. [long_cable] = "long",
  1595. [medium_cable] = "medium",
  1596. [undefined_cable] = "<undefined, assumed long>" /* bit 0==1 */
  1597. };
  1598. return (selection <= undefined_cable) ? cable_names[selection]
  1599. : cable_names[undefined_cable];
  1600. }
  1601. #define AFE_REGISTER_WRITE_DELAY 10
  1602. static void sci_controller_afe_initialization(struct isci_host *ihost)
  1603. {
  1604. struct scu_afe_registers __iomem *afe = &ihost->scu_registers->afe;
  1605. const struct sci_oem_params *oem = &ihost->oem_parameters;
  1606. struct pci_dev *pdev = ihost->pdev;
  1607. u32 afe_status;
  1608. u32 phy_id;
  1609. unsigned char cable_selection_mask = *to_cable_select(ihost);
  1610. /* Clear DFX Status registers */
  1611. writel(0x0081000f, &afe->afe_dfx_master_control0);
  1612. udelay(AFE_REGISTER_WRITE_DELAY);
  1613. if (is_b0(pdev) || is_c0(pdev) || is_c1(pdev)) {
  1614. /* PM Rx Equalization Save, PM SPhy Rx Acknowledgement
  1615. * Timer, PM Stagger Timer
  1616. */
  1617. writel(0x0007FFFF, &afe->afe_pmsn_master_control2);
  1618. udelay(AFE_REGISTER_WRITE_DELAY);
  1619. }
  1620. /* Configure bias currents to normal */
  1621. if (is_a2(pdev))
  1622. writel(0x00005A00, &afe->afe_bias_control);
  1623. else if (is_b0(pdev) || is_c0(pdev))
  1624. writel(0x00005F00, &afe->afe_bias_control);
  1625. else if (is_c1(pdev))
  1626. writel(0x00005500, &afe->afe_bias_control);
  1627. udelay(AFE_REGISTER_WRITE_DELAY);
  1628. /* Enable PLL */
  1629. if (is_a2(pdev))
  1630. writel(0x80040908, &afe->afe_pll_control0);
  1631. else if (is_b0(pdev) || is_c0(pdev))
  1632. writel(0x80040A08, &afe->afe_pll_control0);
  1633. else if (is_c1(pdev)) {
  1634. writel(0x80000B08, &afe->afe_pll_control0);
  1635. udelay(AFE_REGISTER_WRITE_DELAY);
  1636. writel(0x00000B08, &afe->afe_pll_control0);
  1637. udelay(AFE_REGISTER_WRITE_DELAY);
  1638. writel(0x80000B08, &afe->afe_pll_control0);
  1639. }
  1640. udelay(AFE_REGISTER_WRITE_DELAY);
  1641. /* Wait for the PLL to lock */
  1642. do {
  1643. afe_status = readl(&afe->afe_common_block_status);
  1644. udelay(AFE_REGISTER_WRITE_DELAY);
  1645. } while ((afe_status & 0x00001000) == 0);
  1646. if (is_a2(pdev)) {
  1647. /* Shorten SAS SNW lock time (RxLock timer value from 76
  1648. * us to 50 us)
  1649. */
  1650. writel(0x7bcc96ad, &afe->afe_pmsn_master_control0);
  1651. udelay(AFE_REGISTER_WRITE_DELAY);
  1652. }
  1653. for (phy_id = 0; phy_id < SCI_MAX_PHYS; phy_id++) {
  1654. struct scu_afe_transceiver __iomem *xcvr = &afe->scu_afe_xcvr[phy_id];
  1655. const struct sci_phy_oem_params *oem_phy = &oem->phys[phy_id];
  1656. int cable_length_long =
  1657. is_long_cable(phy_id, cable_selection_mask);
  1658. int cable_length_medium =
  1659. is_medium_cable(phy_id, cable_selection_mask);
  1660. if (is_a2(pdev)) {
  1661. /* All defaults, except the Receive Word
  1662. * Alignament/Comma Detect Enable....(0xe800)
  1663. */
  1664. writel(0x00004512, &xcvr->afe_xcvr_control0);
  1665. udelay(AFE_REGISTER_WRITE_DELAY);
  1666. writel(0x0050100F, &xcvr->afe_xcvr_control1);
  1667. udelay(AFE_REGISTER_WRITE_DELAY);
  1668. } else if (is_b0(pdev)) {
  1669. /* Configure transmitter SSC parameters */
  1670. writel(0x00030000, &xcvr->afe_tx_ssc_control);
  1671. udelay(AFE_REGISTER_WRITE_DELAY);
  1672. } else if (is_c0(pdev)) {
  1673. /* Configure transmitter SSC parameters */
  1674. writel(0x00010202, &xcvr->afe_tx_ssc_control);
  1675. udelay(AFE_REGISTER_WRITE_DELAY);
  1676. /* All defaults, except the Receive Word
  1677. * Alignament/Comma Detect Enable....(0xe800)
  1678. */
  1679. writel(0x00014500, &xcvr->afe_xcvr_control0);
  1680. udelay(AFE_REGISTER_WRITE_DELAY);
  1681. } else if (is_c1(pdev)) {
  1682. /* Configure transmitter SSC parameters */
  1683. writel(0x00010202, &xcvr->afe_tx_ssc_control);
  1684. udelay(AFE_REGISTER_WRITE_DELAY);
  1685. /* All defaults, except the Receive Word
  1686. * Alignament/Comma Detect Enable....(0xe800)
  1687. */
  1688. writel(0x0001C500, &xcvr->afe_xcvr_control0);
  1689. udelay(AFE_REGISTER_WRITE_DELAY);
  1690. }
  1691. /* Power up TX and RX out from power down (PWRDNTX and
  1692. * PWRDNRX) & increase TX int & ext bias 20%....(0xe85c)
  1693. */
  1694. if (is_a2(pdev))
  1695. writel(0x000003F0, &xcvr->afe_channel_control);
  1696. else if (is_b0(pdev)) {
  1697. writel(0x000003D7, &xcvr->afe_channel_control);
  1698. udelay(AFE_REGISTER_WRITE_DELAY);
  1699. writel(0x000003D4, &xcvr->afe_channel_control);
  1700. } else if (is_c0(pdev)) {
  1701. writel(0x000001E7, &xcvr->afe_channel_control);
  1702. udelay(AFE_REGISTER_WRITE_DELAY);
  1703. writel(0x000001E4, &xcvr->afe_channel_control);
  1704. } else if (is_c1(pdev)) {
  1705. writel(cable_length_long ? 0x000002F7 : 0x000001F7,
  1706. &xcvr->afe_channel_control);
  1707. udelay(AFE_REGISTER_WRITE_DELAY);
  1708. writel(cable_length_long ? 0x000002F4 : 0x000001F4,
  1709. &xcvr->afe_channel_control);
  1710. }
  1711. udelay(AFE_REGISTER_WRITE_DELAY);
  1712. if (is_a2(pdev)) {
  1713. /* Enable TX equalization (0xe824) */
  1714. writel(0x00040000, &xcvr->afe_tx_control);
  1715. udelay(AFE_REGISTER_WRITE_DELAY);
  1716. }
  1717. if (is_a2(pdev) || is_b0(pdev))
  1718. /* RDPI=0x0(RX Power On), RXOOBDETPDNC=0x0,
  1719. * TPD=0x0(TX Power On), RDD=0x0(RX Detect
  1720. * Enabled) ....(0xe800)
  1721. */
  1722. writel(0x00004100, &xcvr->afe_xcvr_control0);
  1723. else if (is_c0(pdev))
  1724. writel(0x00014100, &xcvr->afe_xcvr_control0);
  1725. else if (is_c1(pdev))
  1726. writel(0x0001C100, &xcvr->afe_xcvr_control0);
  1727. udelay(AFE_REGISTER_WRITE_DELAY);
  1728. /* Leave DFE/FFE on */
  1729. if (is_a2(pdev))
  1730. writel(0x3F11103F, &xcvr->afe_rx_ssc_control0);
  1731. else if (is_b0(pdev)) {
  1732. writel(0x3F11103F, &xcvr->afe_rx_ssc_control0);
  1733. udelay(AFE_REGISTER_WRITE_DELAY);
  1734. /* Enable TX equalization (0xe824) */
  1735. writel(0x00040000, &xcvr->afe_tx_control);
  1736. } else if (is_c0(pdev)) {
  1737. writel(0x01400C0F, &xcvr->afe_rx_ssc_control1);
  1738. udelay(AFE_REGISTER_WRITE_DELAY);
  1739. writel(0x3F6F103F, &xcvr->afe_rx_ssc_control0);
  1740. udelay(AFE_REGISTER_WRITE_DELAY);
  1741. /* Enable TX equalization (0xe824) */
  1742. writel(0x00040000, &xcvr->afe_tx_control);
  1743. } else if (is_c1(pdev)) {
  1744. writel(cable_length_long ? 0x01500C0C :
  1745. cable_length_medium ? 0x01400C0D : 0x02400C0D,
  1746. &xcvr->afe_xcvr_control1);
  1747. udelay(AFE_REGISTER_WRITE_DELAY);
  1748. writel(0x000003E0, &xcvr->afe_dfx_rx_control1);
  1749. udelay(AFE_REGISTER_WRITE_DELAY);
  1750. writel(cable_length_long ? 0x33091C1F :
  1751. cable_length_medium ? 0x3315181F : 0x2B17161F,
  1752. &xcvr->afe_rx_ssc_control0);
  1753. udelay(AFE_REGISTER_WRITE_DELAY);
  1754. /* Enable TX equalization (0xe824) */
  1755. writel(0x00040000, &xcvr->afe_tx_control);
  1756. }
  1757. udelay(AFE_REGISTER_WRITE_DELAY);
  1758. writel(oem_phy->afe_tx_amp_control0, &xcvr->afe_tx_amp_control0);
  1759. udelay(AFE_REGISTER_WRITE_DELAY);
  1760. writel(oem_phy->afe_tx_amp_control1, &xcvr->afe_tx_amp_control1);
  1761. udelay(AFE_REGISTER_WRITE_DELAY);
  1762. writel(oem_phy->afe_tx_amp_control2, &xcvr->afe_tx_amp_control2);
  1763. udelay(AFE_REGISTER_WRITE_DELAY);
  1764. writel(oem_phy->afe_tx_amp_control3, &xcvr->afe_tx_amp_control3);
  1765. udelay(AFE_REGISTER_WRITE_DELAY);
  1766. }
  1767. /* Transfer control to the PEs */
  1768. writel(0x00010f00, &afe->afe_dfx_master_control0);
  1769. udelay(AFE_REGISTER_WRITE_DELAY);
  1770. }
  1771. static void sci_controller_initialize_power_control(struct isci_host *ihost)
  1772. {
  1773. sci_init_timer(&ihost->power_control.timer, power_control_timeout);
  1774. memset(ihost->power_control.requesters, 0,
  1775. sizeof(ihost->power_control.requesters));
  1776. ihost->power_control.phys_waiting = 0;
  1777. ihost->power_control.phys_granted_power = 0;
  1778. }
  1779. static enum sci_status sci_controller_initialize(struct isci_host *ihost)
  1780. {
  1781. struct sci_base_state_machine *sm = &ihost->sm;
  1782. enum sci_status result = SCI_FAILURE;
  1783. unsigned long i, state, val;
  1784. if (ihost->sm.current_state_id != SCIC_RESET) {
  1785. dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
  1786. __func__, ihost->sm.current_state_id);
  1787. return SCI_FAILURE_INVALID_STATE;
  1788. }
  1789. sci_change_state(sm, SCIC_INITIALIZING);
  1790. sci_init_timer(&ihost->phy_timer, phy_startup_timeout);
  1791. ihost->next_phy_to_start = 0;
  1792. ihost->phy_startup_timer_pending = false;
  1793. sci_controller_initialize_power_control(ihost);
  1794. /*
  1795. * There is nothing to do here for B0 since we do not have to
  1796. * program the AFE registers.
  1797. * / @todo The AFE settings are supposed to be correct for the B0 but
  1798. * / presently they seem to be wrong. */
  1799. sci_controller_afe_initialization(ihost);
  1800. /* Take the hardware out of reset */
  1801. writel(0, &ihost->smu_registers->soft_reset_control);
  1802. /*
  1803. * / @todo Provide meaningfull error code for hardware failure
  1804. * result = SCI_FAILURE_CONTROLLER_HARDWARE; */
  1805. for (i = 100; i >= 1; i--) {
  1806. u32 status;
  1807. /* Loop until the hardware reports success */
  1808. udelay(SCU_CONTEXT_RAM_INIT_STALL_TIME);
  1809. status = readl(&ihost->smu_registers->control_status);
  1810. if ((status & SCU_RAM_INIT_COMPLETED) == SCU_RAM_INIT_COMPLETED)
  1811. break;
  1812. }
  1813. if (i == 0)
  1814. goto out;
  1815. /*
  1816. * Determine what are the actaul device capacities that the
  1817. * hardware will support */
  1818. val = readl(&ihost->smu_registers->device_context_capacity);
  1819. /* Record the smaller of the two capacity values */
  1820. ihost->logical_port_entries = min(smu_max_ports(val), SCI_MAX_PORTS);
  1821. ihost->task_context_entries = min(smu_max_task_contexts(val), SCI_MAX_IO_REQUESTS);
  1822. ihost->remote_node_entries = min(smu_max_rncs(val), SCI_MAX_REMOTE_DEVICES);
  1823. /*
  1824. * Make all PEs that are unassigned match up with the
  1825. * logical ports
  1826. */
  1827. for (i = 0; i < ihost->logical_port_entries; i++) {
  1828. struct scu_port_task_scheduler_group_registers __iomem
  1829. *ptsg = &ihost->scu_registers->peg0.ptsg;
  1830. writel(i, &ptsg->protocol_engine[i]);
  1831. }
  1832. /* Initialize hardware PCI Relaxed ordering in DMA engines */
  1833. val = readl(&ihost->scu_registers->sdma.pdma_configuration);
  1834. val |= SCU_PDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE);
  1835. writel(val, &ihost->scu_registers->sdma.pdma_configuration);
  1836. val = readl(&ihost->scu_registers->sdma.cdma_configuration);
  1837. val |= SCU_CDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE);
  1838. writel(val, &ihost->scu_registers->sdma.cdma_configuration);
  1839. /*
  1840. * Initialize the PHYs before the PORTs because the PHY registers
  1841. * are accessed during the port initialization.
  1842. */
  1843. for (i = 0; i < SCI_MAX_PHYS; i++) {
  1844. result = sci_phy_initialize(&ihost->phys[i],
  1845. &ihost->scu_registers->peg0.pe[i].tl,
  1846. &ihost->scu_registers->peg0.pe[i].ll);
  1847. if (result != SCI_SUCCESS)
  1848. goto out;
  1849. }
  1850. for (i = 0; i < ihost->logical_port_entries; i++) {
  1851. struct isci_port *iport = &ihost->ports[i];
  1852. iport->port_task_scheduler_registers = &ihost->scu_registers->peg0.ptsg.port[i];
  1853. iport->port_pe_configuration_register = &ihost->scu_registers->peg0.ptsg.protocol_engine[0];
  1854. iport->viit_registers = &ihost->scu_registers->peg0.viit[i];
  1855. }
  1856. result = sci_port_configuration_agent_initialize(ihost, &ihost->port_agent);
  1857. out:
  1858. /* Advance the controller state machine */
  1859. if (result == SCI_SUCCESS)
  1860. state = SCIC_INITIALIZED;
  1861. else
  1862. state = SCIC_FAILED;
  1863. sci_change_state(sm, state);
  1864. return result;
  1865. }
  1866. static int sci_controller_dma_alloc(struct isci_host *ihost)
  1867. {
  1868. struct device *dev = &ihost->pdev->dev;
  1869. size_t size;
  1870. int i;
  1871. /* detect re-initialization */
  1872. if (ihost->completion_queue)
  1873. return 0;
  1874. size = SCU_MAX_COMPLETION_QUEUE_ENTRIES * sizeof(u32);
  1875. ihost->completion_queue = dmam_alloc_coherent(dev, size, &ihost->cq_dma,
  1876. GFP_KERNEL);
  1877. if (!ihost->completion_queue)
  1878. return -ENOMEM;
  1879. size = ihost->remote_node_entries * sizeof(union scu_remote_node_context);
  1880. ihost->remote_node_context_table = dmam_alloc_coherent(dev, size, &ihost->rnc_dma,
  1881. GFP_KERNEL);
  1882. if (!ihost->remote_node_context_table)
  1883. return -ENOMEM;
  1884. size = ihost->task_context_entries * sizeof(struct scu_task_context),
  1885. ihost->task_context_table = dmam_alloc_coherent(dev, size, &ihost->tc_dma,
  1886. GFP_KERNEL);
  1887. if (!ihost->task_context_table)
  1888. return -ENOMEM;
  1889. size = SCI_UFI_TOTAL_SIZE;
  1890. ihost->ufi_buf = dmam_alloc_coherent(dev, size, &ihost->ufi_dma, GFP_KERNEL);
  1891. if (!ihost->ufi_buf)
  1892. return -ENOMEM;
  1893. for (i = 0; i < SCI_MAX_IO_REQUESTS; i++) {
  1894. struct isci_request *ireq;
  1895. dma_addr_t dma;
  1896. ireq = dmam_alloc_coherent(dev, sizeof(*ireq), &dma, GFP_KERNEL);
  1897. if (!ireq)
  1898. return -ENOMEM;
  1899. ireq->tc = &ihost->task_context_table[i];
  1900. ireq->owning_controller = ihost;
  1901. ireq->request_daddr = dma;
  1902. ireq->isci_host = ihost;
  1903. ihost->reqs[i] = ireq;
  1904. }
  1905. return 0;
  1906. }
  1907. static int sci_controller_mem_init(struct isci_host *ihost)
  1908. {
  1909. int err = sci_controller_dma_alloc(ihost);
  1910. if (err)
  1911. return err;
  1912. writel(lower_32_bits(ihost->cq_dma), &ihost->smu_registers->completion_queue_lower);
  1913. writel(upper_32_bits(ihost->cq_dma), &ihost->smu_registers->completion_queue_upper);
  1914. writel(lower_32_bits(ihost->rnc_dma), &ihost->smu_registers->remote_node_context_lower);
  1915. writel(upper_32_bits(ihost->rnc_dma), &ihost->smu_registers->remote_node_context_upper);
  1916. writel(lower_32_bits(ihost->tc_dma), &ihost->smu_registers->host_task_table_lower);
  1917. writel(upper_32_bits(ihost->tc_dma), &ihost->smu_registers->host_task_table_upper);
  1918. sci_unsolicited_frame_control_construct(ihost);
  1919. /*
  1920. * Inform the silicon as to the location of the UF headers and
  1921. * address table.
  1922. */
  1923. writel(lower_32_bits(ihost->uf_control.headers.physical_address),
  1924. &ihost->scu_registers->sdma.uf_header_base_address_lower);
  1925. writel(upper_32_bits(ihost->uf_control.headers.physical_address),
  1926. &ihost->scu_registers->sdma.uf_header_base_address_upper);
  1927. writel(lower_32_bits(ihost->uf_control.address_table.physical_address),
  1928. &ihost->scu_registers->sdma.uf_address_table_lower);
  1929. writel(upper_32_bits(ihost->uf_control.address_table.physical_address),
  1930. &ihost->scu_registers->sdma.uf_address_table_upper);
  1931. return 0;
  1932. }
  1933. /**
  1934. * isci_host_init - (re-)initialize hardware and internal (private) state
  1935. * @ihost: host to init
  1936. *
  1937. * Any public facing objects (like asd_sas_port, and asd_sas_phys), or
  1938. * one-time initialization objects like locks and waitqueues, are
  1939. * not touched (they are initialized in isci_host_alloc)
  1940. */
  1941. int isci_host_init(struct isci_host *ihost)
  1942. {
  1943. int i, err;
  1944. enum sci_status status;
  1945. spin_lock_irq(&ihost->scic_lock);
  1946. status = sci_controller_construct(ihost, scu_base(ihost), smu_base(ihost));
  1947. spin_unlock_irq(&ihost->scic_lock);
  1948. if (status != SCI_SUCCESS) {
  1949. dev_err(&ihost->pdev->dev,
  1950. "%s: sci_controller_construct failed - status = %x\n",
  1951. __func__,
  1952. status);
  1953. return -ENODEV;
  1954. }
  1955. spin_lock_irq(&ihost->scic_lock);
  1956. status = sci_controller_initialize(ihost);
  1957. spin_unlock_irq(&ihost->scic_lock);
  1958. if (status != SCI_SUCCESS) {
  1959. dev_warn(&ihost->pdev->dev,
  1960. "%s: sci_controller_initialize failed -"
  1961. " status = 0x%x\n",
  1962. __func__, status);
  1963. return -ENODEV;
  1964. }
  1965. err = sci_controller_mem_init(ihost);
  1966. if (err)
  1967. return err;
  1968. /* enable sgpio */
  1969. writel(1, &ihost->scu_registers->peg0.sgpio.interface_control);
  1970. for (i = 0; i < isci_gpio_count(ihost); i++)
  1971. writel(SGPIO_HW_CONTROL, &ihost->scu_registers->peg0.sgpio.output_data_select[i]);
  1972. writel(0, &ihost->scu_registers->peg0.sgpio.vendor_specific_code);
  1973. return 0;
  1974. }
  1975. void sci_controller_link_up(struct isci_host *ihost, struct isci_port *iport,
  1976. struct isci_phy *iphy)
  1977. {
  1978. switch (ihost->sm.current_state_id) {
  1979. case SCIC_STARTING:
  1980. sci_del_timer(&ihost->phy_timer);
  1981. ihost->phy_startup_timer_pending = false;
  1982. ihost->port_agent.link_up_handler(ihost, &ihost->port_agent,
  1983. iport, iphy);
  1984. sci_controller_start_next_phy(ihost);
  1985. break;
  1986. case SCIC_READY:
  1987. ihost->port_agent.link_up_handler(ihost, &ihost->port_agent,
  1988. iport, iphy);
  1989. break;
  1990. default:
  1991. dev_dbg(&ihost->pdev->dev,
  1992. "%s: SCIC Controller linkup event from phy %d in "
  1993. "unexpected state %d\n", __func__, iphy->phy_index,
  1994. ihost->sm.current_state_id);
  1995. }
  1996. }
  1997. void sci_controller_link_down(struct isci_host *ihost, struct isci_port *iport,
  1998. struct isci_phy *iphy)
  1999. {
  2000. switch (ihost->sm.current_state_id) {
  2001. case SCIC_STARTING:
  2002. case SCIC_READY:
  2003. ihost->port_agent.link_down_handler(ihost, &ihost->port_agent,
  2004. iport, iphy);
  2005. break;
  2006. default:
  2007. dev_dbg(&ihost->pdev->dev,
  2008. "%s: SCIC Controller linkdown event from phy %d in "
  2009. "unexpected state %d\n",
  2010. __func__,
  2011. iphy->phy_index,
  2012. ihost->sm.current_state_id);
  2013. }
  2014. }
  2015. bool sci_controller_has_remote_devices_stopping(struct isci_host *ihost)
  2016. {
  2017. u32 index;
  2018. for (index = 0; index < ihost->remote_node_entries; index++) {
  2019. if ((ihost->device_table[index] != NULL) &&
  2020. (ihost->device_table[index]->sm.current_state_id == SCI_DEV_STOPPING))
  2021. return true;
  2022. }
  2023. return false;
  2024. }
  2025. void sci_controller_remote_device_stopped(struct isci_host *ihost,
  2026. struct isci_remote_device *idev)
  2027. {
  2028. if (ihost->sm.current_state_id != SCIC_STOPPING) {
  2029. dev_dbg(&ihost->pdev->dev,
  2030. "SCIC Controller 0x%p remote device stopped event "
  2031. "from device 0x%p in unexpected state %d\n",
  2032. ihost, idev,
  2033. ihost->sm.current_state_id);
  2034. return;
  2035. }
  2036. if (!sci_controller_has_remote_devices_stopping(ihost))
  2037. isci_host_stop_complete(ihost);
  2038. }
  2039. void sci_controller_post_request(struct isci_host *ihost, u32 request)
  2040. {
  2041. dev_dbg(&ihost->pdev->dev, "%s[%d]: %#x\n",
  2042. __func__, ihost->id, request);
  2043. writel(request, &ihost->smu_registers->post_context_port);
  2044. }
  2045. struct isci_request *sci_request_by_tag(struct isci_host *ihost, u16 io_tag)
  2046. {
  2047. u16 task_index;
  2048. u16 task_sequence;
  2049. task_index = ISCI_TAG_TCI(io_tag);
  2050. if (task_index < ihost->task_context_entries) {
  2051. struct isci_request *ireq = ihost->reqs[task_index];
  2052. if (test_bit(IREQ_ACTIVE, &ireq->flags)) {
  2053. task_sequence = ISCI_TAG_SEQ(io_tag);
  2054. if (task_sequence == ihost->io_request_sequence[task_index])
  2055. return ireq;
  2056. }
  2057. }
  2058. return NULL;
  2059. }
  2060. /**
  2061. * sci_controller_allocate_remote_node_context()
  2062. * This method allocates remote node index and the reserves the remote node
  2063. * context space for use. This method can fail if there are no more remote
  2064. * node index available.
  2065. * @ihost: This is the controller object which contains the set of
  2066. * free remote node ids
  2067. * @idev: This is the device object which is requesting the a remote node
  2068. * id
  2069. * @node_id: This is the remote node id that is assinged to the device if one
  2070. * is available
  2071. *
  2072. * enum sci_status SCI_FAILURE_OUT_OF_RESOURCES if there are no available remote
  2073. * node index available.
  2074. */
  2075. enum sci_status sci_controller_allocate_remote_node_context(struct isci_host *ihost,
  2076. struct isci_remote_device *idev,
  2077. u16 *node_id)
  2078. {
  2079. u16 node_index;
  2080. u32 remote_node_count = sci_remote_device_node_count(idev);
  2081. node_index = sci_remote_node_table_allocate_remote_node(
  2082. &ihost->available_remote_nodes, remote_node_count
  2083. );
  2084. if (node_index != SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) {
  2085. ihost->device_table[node_index] = idev;
  2086. *node_id = node_index;
  2087. return SCI_SUCCESS;
  2088. }
  2089. return SCI_FAILURE_INSUFFICIENT_RESOURCES;
  2090. }
  2091. void sci_controller_free_remote_node_context(struct isci_host *ihost,
  2092. struct isci_remote_device *idev,
  2093. u16 node_id)
  2094. {
  2095. u32 remote_node_count = sci_remote_device_node_count(idev);
  2096. if (ihost->device_table[node_id] == idev) {
  2097. ihost->device_table[node_id] = NULL;
  2098. sci_remote_node_table_release_remote_node_index(
  2099. &ihost->available_remote_nodes, remote_node_count, node_id
  2100. );
  2101. }
  2102. }
  2103. void sci_controller_copy_sata_response(void *response_buffer,
  2104. void *frame_header,
  2105. void *frame_buffer)
  2106. {
  2107. /* XXX type safety? */
  2108. memcpy(response_buffer, frame_header, sizeof(u32));
  2109. memcpy(response_buffer + sizeof(u32),
  2110. frame_buffer,
  2111. sizeof(struct dev_to_host_fis) - sizeof(u32));
  2112. }
  2113. void sci_controller_release_frame(struct isci_host *ihost, u32 frame_index)
  2114. {
  2115. if (sci_unsolicited_frame_control_release_frame(&ihost->uf_control, frame_index))
  2116. writel(ihost->uf_control.get,
  2117. &ihost->scu_registers->sdma.unsolicited_frame_get_pointer);
  2118. }
  2119. void isci_tci_free(struct isci_host *ihost, u16 tci)
  2120. {
  2121. u16 tail = ihost->tci_tail & (SCI_MAX_IO_REQUESTS-1);
  2122. ihost->tci_pool[tail] = tci;
  2123. ihost->tci_tail = tail + 1;
  2124. }
  2125. static u16 isci_tci_alloc(struct isci_host *ihost)
  2126. {
  2127. u16 head = ihost->tci_head & (SCI_MAX_IO_REQUESTS-1);
  2128. u16 tci = ihost->tci_pool[head];
  2129. ihost->tci_head = head + 1;
  2130. return tci;
  2131. }
  2132. static u16 isci_tci_space(struct isci_host *ihost)
  2133. {
  2134. return CIRC_SPACE(ihost->tci_head, ihost->tci_tail, SCI_MAX_IO_REQUESTS);
  2135. }
  2136. u16 isci_alloc_tag(struct isci_host *ihost)
  2137. {
  2138. if (isci_tci_space(ihost)) {
  2139. u16 tci = isci_tci_alloc(ihost);
  2140. u8 seq = ihost->io_request_sequence[tci];
  2141. return ISCI_TAG(seq, tci);
  2142. }
  2143. return SCI_CONTROLLER_INVALID_IO_TAG;
  2144. }
  2145. enum sci_status isci_free_tag(struct isci_host *ihost, u16 io_tag)
  2146. {
  2147. u16 tci = ISCI_TAG_TCI(io_tag);
  2148. u16 seq = ISCI_TAG_SEQ(io_tag);
  2149. /* prevent tail from passing head */
  2150. if (isci_tci_active(ihost) == 0)
  2151. return SCI_FAILURE_INVALID_IO_TAG;
  2152. if (seq == ihost->io_request_sequence[tci]) {
  2153. ihost->io_request_sequence[tci] = (seq+1) & (SCI_MAX_SEQ-1);
  2154. isci_tci_free(ihost, tci);
  2155. return SCI_SUCCESS;
  2156. }
  2157. return SCI_FAILURE_INVALID_IO_TAG;
  2158. }
  2159. enum sci_status sci_controller_start_io(struct isci_host *ihost,
  2160. struct isci_remote_device *idev,
  2161. struct isci_request *ireq)
  2162. {
  2163. enum sci_status status;
  2164. if (ihost->sm.current_state_id != SCIC_READY) {
  2165. dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
  2166. __func__, ihost->sm.current_state_id);
  2167. return SCI_FAILURE_INVALID_STATE;
  2168. }
  2169. status = sci_remote_device_start_io(ihost, idev, ireq);
  2170. if (status != SCI_SUCCESS)
  2171. return status;
  2172. set_bit(IREQ_ACTIVE, &ireq->flags);
  2173. sci_controller_post_request(ihost, ireq->post_context);
  2174. return SCI_SUCCESS;
  2175. }
  2176. enum sci_status sci_controller_terminate_request(struct isci_host *ihost,
  2177. struct isci_remote_device *idev,
  2178. struct isci_request *ireq)
  2179. {
  2180. /* terminate an ongoing (i.e. started) core IO request. This does not
  2181. * abort the IO request at the target, but rather removes the IO
  2182. * request from the host controller.
  2183. */
  2184. enum sci_status status;
  2185. if (ihost->sm.current_state_id != SCIC_READY) {
  2186. dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
  2187. __func__, ihost->sm.current_state_id);
  2188. return SCI_FAILURE_INVALID_STATE;
  2189. }
  2190. status = sci_io_request_terminate(ireq);
  2191. dev_dbg(&ihost->pdev->dev, "%s: status=%d; ireq=%p; flags=%lx\n",
  2192. __func__, status, ireq, ireq->flags);
  2193. if ((status == SCI_SUCCESS) &&
  2194. !test_bit(IREQ_PENDING_ABORT, &ireq->flags) &&
  2195. !test_and_set_bit(IREQ_TC_ABORT_POSTED, &ireq->flags)) {
  2196. /* Utilize the original post context command and or in the
  2197. * POST_TC_ABORT request sub-type.
  2198. */
  2199. sci_controller_post_request(
  2200. ihost, ireq->post_context |
  2201. SCU_CONTEXT_COMMAND_REQUEST_POST_TC_ABORT);
  2202. }
  2203. return status;
  2204. }
  2205. /**
  2206. * sci_controller_complete_io() - This method will perform core specific
  2207. * completion operations for an IO request. After this method is invoked,
  2208. * the user should consider the IO request as invalid until it is properly
  2209. * reused (i.e. re-constructed).
  2210. * @ihost: The handle to the controller object for which to complete the
  2211. * IO request.
  2212. * @idev: The handle to the remote device object for which to complete
  2213. * the IO request.
  2214. * @ireq: the handle to the io request object to complete.
  2215. */
  2216. enum sci_status sci_controller_complete_io(struct isci_host *ihost,
  2217. struct isci_remote_device *idev,
  2218. struct isci_request *ireq)
  2219. {
  2220. enum sci_status status;
  2221. switch (ihost->sm.current_state_id) {
  2222. case SCIC_STOPPING:
  2223. /* XXX: Implement this function */
  2224. return SCI_FAILURE;
  2225. case SCIC_READY:
  2226. status = sci_remote_device_complete_io(ihost, idev, ireq);
  2227. if (status != SCI_SUCCESS)
  2228. return status;
  2229. clear_bit(IREQ_ACTIVE, &ireq->flags);
  2230. return SCI_SUCCESS;
  2231. default:
  2232. dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
  2233. __func__, ihost->sm.current_state_id);
  2234. return SCI_FAILURE_INVALID_STATE;
  2235. }
  2236. }
  2237. enum sci_status sci_controller_continue_io(struct isci_request *ireq)
  2238. {
  2239. struct isci_host *ihost = ireq->owning_controller;
  2240. if (ihost->sm.current_state_id != SCIC_READY) {
  2241. dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
  2242. __func__, ihost->sm.current_state_id);
  2243. return SCI_FAILURE_INVALID_STATE;
  2244. }
  2245. set_bit(IREQ_ACTIVE, &ireq->flags);
  2246. sci_controller_post_request(ihost, ireq->post_context);
  2247. return SCI_SUCCESS;
  2248. }
  2249. /**
  2250. * sci_controller_start_task() - This method is called by the SCIC user to
  2251. * send/start a framework task management request.
  2252. * @ihost: the handle to the controller object for which to start the task
  2253. * management request.
  2254. * @idev: the handle to the remote device object for which to start
  2255. * the task management request.
  2256. * @ireq: the handle to the task request object to start.
  2257. */
  2258. enum sci_status sci_controller_start_task(struct isci_host *ihost,
  2259. struct isci_remote_device *idev,
  2260. struct isci_request *ireq)
  2261. {
  2262. enum sci_status status;
  2263. if (ihost->sm.current_state_id != SCIC_READY) {
  2264. dev_warn(&ihost->pdev->dev,
  2265. "%s: SCIC Controller starting task from invalid "
  2266. "state\n",
  2267. __func__);
  2268. return SCI_FAILURE_INVALID_STATE;
  2269. }
  2270. status = sci_remote_device_start_task(ihost, idev, ireq);
  2271. switch (status) {
  2272. case SCI_FAILURE_RESET_DEVICE_PARTIAL_SUCCESS:
  2273. set_bit(IREQ_ACTIVE, &ireq->flags);
  2274. /*
  2275. * We will let framework know this task request started successfully,
  2276. * although core is still woring on starting the request (to post tc when
  2277. * RNC is resumed.)
  2278. */
  2279. return SCI_SUCCESS;
  2280. case SCI_SUCCESS:
  2281. set_bit(IREQ_ACTIVE, &ireq->flags);
  2282. sci_controller_post_request(ihost, ireq->post_context);
  2283. break;
  2284. default:
  2285. break;
  2286. }
  2287. return status;
  2288. }
  2289. static int sci_write_gpio_tx_gp(struct isci_host *ihost, u8 reg_index, u8 reg_count, u8 *write_data)
  2290. {
  2291. int d;
  2292. /* no support for TX_GP_CFG */
  2293. if (reg_index == 0)
  2294. return -EINVAL;
  2295. for (d = 0; d < isci_gpio_count(ihost); d++) {
  2296. u32 val = 0x444; /* all ODx.n clear */
  2297. int i;
  2298. for (i = 0; i < 3; i++) {
  2299. int bit;
  2300. bit = try_test_sas_gpio_gp_bit(to_sas_gpio_od(d, i),
  2301. write_data, reg_index,
  2302. reg_count);
  2303. if (bit < 0)
  2304. break;
  2305. /* if od is set, clear the 'invert' bit */
  2306. val &= ~(bit << ((i << 2) + 2));
  2307. }
  2308. if (i < 3)
  2309. break;
  2310. writel(val, &ihost->scu_registers->peg0.sgpio.output_data_select[d]);
  2311. }
  2312. /* unless reg_index is > 1, we should always be able to write at
  2313. * least one register
  2314. */
  2315. return d > 0;
  2316. }
  2317. int isci_gpio_write(struct sas_ha_struct *sas_ha, u8 reg_type, u8 reg_index,
  2318. u8 reg_count, u8 *write_data)
  2319. {
  2320. struct isci_host *ihost = sas_ha->lldd_ha;
  2321. int written;
  2322. switch (reg_type) {
  2323. case SAS_GPIO_REG_TX_GP:
  2324. written = sci_write_gpio_tx_gp(ihost, reg_index, reg_count, write_data);
  2325. break;
  2326. default:
  2327. written = -EINVAL;
  2328. }
  2329. return written;
  2330. }