hpsa.c 274 KB

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  1. /*
  2. * Disk Array driver for HP Smart Array SAS controllers
  3. * Copyright (c) 2019-2020 Microchip Technology Inc. and its subsidiaries
  4. * Copyright 2016 Microsemi Corporation
  5. * Copyright 2014-2015 PMC-Sierra, Inc.
  6. * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; version 2 of the License.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  15. * NON INFRINGEMENT. See the GNU General Public License for more details.
  16. *
  17. * Questions/Comments/Bugfixes to [email protected]
  18. *
  19. */
  20. #include <linux/module.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/types.h>
  23. #include <linux/pci.h>
  24. #include <linux/kernel.h>
  25. #include <linux/slab.h>
  26. #include <linux/delay.h>
  27. #include <linux/fs.h>
  28. #include <linux/timer.h>
  29. #include <linux/init.h>
  30. #include <linux/spinlock.h>
  31. #include <linux/compat.h>
  32. #include <linux/blktrace_api.h>
  33. #include <linux/uaccess.h>
  34. #include <linux/io.h>
  35. #include <linux/dma-mapping.h>
  36. #include <linux/completion.h>
  37. #include <linux/moduleparam.h>
  38. #include <scsi/scsi.h>
  39. #include <scsi/scsi_cmnd.h>
  40. #include <scsi/scsi_device.h>
  41. #include <scsi/scsi_host.h>
  42. #include <scsi/scsi_tcq.h>
  43. #include <scsi/scsi_eh.h>
  44. #include <scsi/scsi_transport_sas.h>
  45. #include <scsi/scsi_dbg.h>
  46. #include <linux/cciss_ioctl.h>
  47. #include <linux/string.h>
  48. #include <linux/bitmap.h>
  49. #include <linux/atomic.h>
  50. #include <linux/jiffies.h>
  51. #include <linux/percpu-defs.h>
  52. #include <linux/percpu.h>
  53. #include <asm/unaligned.h>
  54. #include <asm/div64.h>
  55. #include "hpsa_cmd.h"
  56. #include "hpsa.h"
  57. /*
  58. * HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.'
  59. * with an optional trailing '-' followed by a byte value (0-255).
  60. */
  61. #define HPSA_DRIVER_VERSION "3.4.20-200"
  62. #define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
  63. #define HPSA "hpsa"
  64. /* How long to wait for CISS doorbell communication */
  65. #define CLEAR_EVENT_WAIT_INTERVAL 20 /* ms for each msleep() call */
  66. #define MODE_CHANGE_WAIT_INTERVAL 10 /* ms for each msleep() call */
  67. #define MAX_CLEAR_EVENT_WAIT 30000 /* times 20 ms = 600 s */
  68. #define MAX_MODE_CHANGE_WAIT 2000 /* times 10 ms = 20 s */
  69. #define MAX_IOCTL_CONFIG_WAIT 1000
  70. /*define how many times we will try a command because of bus resets */
  71. #define MAX_CMD_RETRIES 3
  72. /* How long to wait before giving up on a command */
  73. #define HPSA_EH_PTRAID_TIMEOUT (240 * HZ)
  74. /* Embedded module documentation macros - see modules.h */
  75. MODULE_AUTHOR("Hewlett-Packard Company");
  76. MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
  77. HPSA_DRIVER_VERSION);
  78. MODULE_VERSION(HPSA_DRIVER_VERSION);
  79. MODULE_LICENSE("GPL");
  80. MODULE_ALIAS("cciss");
  81. static int hpsa_simple_mode;
  82. module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
  83. MODULE_PARM_DESC(hpsa_simple_mode,
  84. "Use 'simple mode' rather than 'performant mode'");
  85. /* define the PCI info for the cards we can control */
  86. static const struct pci_device_id hpsa_pci_device_id[] = {
  87. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
  88. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
  89. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
  90. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
  91. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
  92. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
  93. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
  94. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
  95. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
  96. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
  97. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
  98. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
  99. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
  100. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
  101. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
  102. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103c, 0x1920},
  103. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
  104. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
  105. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
  106. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
  107. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103c, 0x1925},
  108. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
  109. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
  110. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
  111. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
  112. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
  113. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
  114. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
  115. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
  116. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
  117. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
  118. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
  119. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
  120. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C6},
  121. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
  122. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
  123. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
  124. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CA},
  125. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CB},
  126. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CC},
  127. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CD},
  128. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CE},
  129. {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0580},
  130. {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0581},
  131. {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0582},
  132. {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0583},
  133. {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0584},
  134. {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0585},
  135. {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076},
  136. {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087},
  137. {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D},
  138. {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088},
  139. {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f},
  140. {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  141. PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
  142. {PCI_VENDOR_ID_COMPAQ, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  143. PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
  144. {0,}
  145. };
  146. MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
  147. /* board_id = Subsystem Device ID & Vendor ID
  148. * product = Marketing Name for the board
  149. * access = Address of the struct of function pointers
  150. */
  151. static struct board_type products[] = {
  152. {0x40700E11, "Smart Array 5300", &SA5A_access},
  153. {0x40800E11, "Smart Array 5i", &SA5B_access},
  154. {0x40820E11, "Smart Array 532", &SA5B_access},
  155. {0x40830E11, "Smart Array 5312", &SA5B_access},
  156. {0x409A0E11, "Smart Array 641", &SA5A_access},
  157. {0x409B0E11, "Smart Array 642", &SA5A_access},
  158. {0x409C0E11, "Smart Array 6400", &SA5A_access},
  159. {0x409D0E11, "Smart Array 6400 EM", &SA5A_access},
  160. {0x40910E11, "Smart Array 6i", &SA5A_access},
  161. {0x3225103C, "Smart Array P600", &SA5A_access},
  162. {0x3223103C, "Smart Array P800", &SA5A_access},
  163. {0x3234103C, "Smart Array P400", &SA5A_access},
  164. {0x3235103C, "Smart Array P400i", &SA5A_access},
  165. {0x3211103C, "Smart Array E200i", &SA5A_access},
  166. {0x3212103C, "Smart Array E200", &SA5A_access},
  167. {0x3213103C, "Smart Array E200i", &SA5A_access},
  168. {0x3214103C, "Smart Array E200i", &SA5A_access},
  169. {0x3215103C, "Smart Array E200i", &SA5A_access},
  170. {0x3237103C, "Smart Array E500", &SA5A_access},
  171. {0x323D103C, "Smart Array P700m", &SA5A_access},
  172. {0x3241103C, "Smart Array P212", &SA5_access},
  173. {0x3243103C, "Smart Array P410", &SA5_access},
  174. {0x3245103C, "Smart Array P410i", &SA5_access},
  175. {0x3247103C, "Smart Array P411", &SA5_access},
  176. {0x3249103C, "Smart Array P812", &SA5_access},
  177. {0x324A103C, "Smart Array P712m", &SA5_access},
  178. {0x324B103C, "Smart Array P711m", &SA5_access},
  179. {0x3233103C, "HP StorageWorks 1210m", &SA5_access}, /* alias of 333f */
  180. {0x3350103C, "Smart Array P222", &SA5_access},
  181. {0x3351103C, "Smart Array P420", &SA5_access},
  182. {0x3352103C, "Smart Array P421", &SA5_access},
  183. {0x3353103C, "Smart Array P822", &SA5_access},
  184. {0x3354103C, "Smart Array P420i", &SA5_access},
  185. {0x3355103C, "Smart Array P220i", &SA5_access},
  186. {0x3356103C, "Smart Array P721m", &SA5_access},
  187. {0x1920103C, "Smart Array P430i", &SA5_access},
  188. {0x1921103C, "Smart Array P830i", &SA5_access},
  189. {0x1922103C, "Smart Array P430", &SA5_access},
  190. {0x1923103C, "Smart Array P431", &SA5_access},
  191. {0x1924103C, "Smart Array P830", &SA5_access},
  192. {0x1925103C, "Smart Array P831", &SA5_access},
  193. {0x1926103C, "Smart Array P731m", &SA5_access},
  194. {0x1928103C, "Smart Array P230i", &SA5_access},
  195. {0x1929103C, "Smart Array P530", &SA5_access},
  196. {0x21BD103C, "Smart Array P244br", &SA5_access},
  197. {0x21BE103C, "Smart Array P741m", &SA5_access},
  198. {0x21BF103C, "Smart HBA H240ar", &SA5_access},
  199. {0x21C0103C, "Smart Array P440ar", &SA5_access},
  200. {0x21C1103C, "Smart Array P840ar", &SA5_access},
  201. {0x21C2103C, "Smart Array P440", &SA5_access},
  202. {0x21C3103C, "Smart Array P441", &SA5_access},
  203. {0x21C4103C, "Smart Array", &SA5_access},
  204. {0x21C5103C, "Smart Array P841", &SA5_access},
  205. {0x21C6103C, "Smart HBA H244br", &SA5_access},
  206. {0x21C7103C, "Smart HBA H240", &SA5_access},
  207. {0x21C8103C, "Smart HBA H241", &SA5_access},
  208. {0x21C9103C, "Smart Array", &SA5_access},
  209. {0x21CA103C, "Smart Array P246br", &SA5_access},
  210. {0x21CB103C, "Smart Array P840", &SA5_access},
  211. {0x21CC103C, "Smart Array", &SA5_access},
  212. {0x21CD103C, "Smart Array", &SA5_access},
  213. {0x21CE103C, "Smart HBA", &SA5_access},
  214. {0x05809005, "SmartHBA-SA", &SA5_access},
  215. {0x05819005, "SmartHBA-SA 8i", &SA5_access},
  216. {0x05829005, "SmartHBA-SA 8i8e", &SA5_access},
  217. {0x05839005, "SmartHBA-SA 8e", &SA5_access},
  218. {0x05849005, "SmartHBA-SA 16i", &SA5_access},
  219. {0x05859005, "SmartHBA-SA 4i4e", &SA5_access},
  220. {0x00761590, "HP Storage P1224 Array Controller", &SA5_access},
  221. {0x00871590, "HP Storage P1224e Array Controller", &SA5_access},
  222. {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access},
  223. {0x00881590, "HP Storage P1228e Array Controller", &SA5_access},
  224. {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access},
  225. {0xFFFF103C, "Unknown Smart Array", &SA5_access},
  226. };
  227. static struct scsi_transport_template *hpsa_sas_transport_template;
  228. static int hpsa_add_sas_host(struct ctlr_info *h);
  229. static void hpsa_delete_sas_host(struct ctlr_info *h);
  230. static int hpsa_add_sas_device(struct hpsa_sas_node *hpsa_sas_node,
  231. struct hpsa_scsi_dev_t *device);
  232. static void hpsa_remove_sas_device(struct hpsa_scsi_dev_t *device);
  233. static struct hpsa_scsi_dev_t
  234. *hpsa_find_device_by_sas_rphy(struct ctlr_info *h,
  235. struct sas_rphy *rphy);
  236. #define SCSI_CMD_BUSY ((struct scsi_cmnd *)&hpsa_cmd_busy)
  237. static const struct scsi_cmnd hpsa_cmd_busy;
  238. #define SCSI_CMD_IDLE ((struct scsi_cmnd *)&hpsa_cmd_idle)
  239. static const struct scsi_cmnd hpsa_cmd_idle;
  240. static int number_of_controllers;
  241. static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
  242. static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
  243. static int hpsa_ioctl(struct scsi_device *dev, unsigned int cmd,
  244. void __user *arg);
  245. static int hpsa_passthru_ioctl(struct ctlr_info *h,
  246. IOCTL_Command_struct *iocommand);
  247. static int hpsa_big_passthru_ioctl(struct ctlr_info *h,
  248. BIG_IOCTL_Command_struct *ioc);
  249. #ifdef CONFIG_COMPAT
  250. static int hpsa_compat_ioctl(struct scsi_device *dev, unsigned int cmd,
  251. void __user *arg);
  252. #endif
  253. static void cmd_free(struct ctlr_info *h, struct CommandList *c);
  254. static struct CommandList *cmd_alloc(struct ctlr_info *h);
  255. static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c);
  256. static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
  257. struct scsi_cmnd *scmd);
  258. static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
  259. void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
  260. int cmd_type);
  261. static void hpsa_free_cmd_pool(struct ctlr_info *h);
  262. #define VPD_PAGE (1 << 8)
  263. #define HPSA_SIMPLE_ERROR_BITS 0x03
  264. static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
  265. static void hpsa_scan_start(struct Scsi_Host *);
  266. static int hpsa_scan_finished(struct Scsi_Host *sh,
  267. unsigned long elapsed_time);
  268. static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth);
  269. static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
  270. static int hpsa_slave_alloc(struct scsi_device *sdev);
  271. static int hpsa_slave_configure(struct scsi_device *sdev);
  272. static void hpsa_slave_destroy(struct scsi_device *sdev);
  273. static void hpsa_update_scsi_devices(struct ctlr_info *h);
  274. static int check_for_unit_attention(struct ctlr_info *h,
  275. struct CommandList *c);
  276. static void check_ioctl_unit_attention(struct ctlr_info *h,
  277. struct CommandList *c);
  278. /* performant mode helper functions */
  279. static void calc_bucket_map(int *bucket, int num_buckets,
  280. int nsgs, int min_blocks, u32 *bucket_map);
  281. static void hpsa_free_performant_mode(struct ctlr_info *h);
  282. static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
  283. static inline u32 next_command(struct ctlr_info *h, u8 q);
  284. static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
  285. u32 *cfg_base_addr, u64 *cfg_base_addr_index,
  286. u64 *cfg_offset);
  287. static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
  288. unsigned long *memory_bar);
  289. static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id,
  290. bool *legacy_board);
  291. static int wait_for_device_to_become_ready(struct ctlr_info *h,
  292. unsigned char lunaddr[],
  293. int reply_queue);
  294. static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
  295. int wait_for_ready);
  296. static inline void finish_cmd(struct CommandList *c);
  297. static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
  298. #define BOARD_NOT_READY 0
  299. #define BOARD_READY 1
  300. static void hpsa_drain_accel_commands(struct ctlr_info *h);
  301. static void hpsa_flush_cache(struct ctlr_info *h);
  302. static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
  303. struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
  304. u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk);
  305. static void hpsa_command_resubmit_worker(struct work_struct *work);
  306. static u32 lockup_detected(struct ctlr_info *h);
  307. static int detect_controller_lockup(struct ctlr_info *h);
  308. static void hpsa_disable_rld_caching(struct ctlr_info *h);
  309. static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
  310. struct ReportExtendedLUNdata *buf, int bufsize);
  311. static bool hpsa_vpd_page_supported(struct ctlr_info *h,
  312. unsigned char scsi3addr[], u8 page);
  313. static int hpsa_luns_changed(struct ctlr_info *h);
  314. static bool hpsa_cmd_dev_match(struct ctlr_info *h, struct CommandList *c,
  315. struct hpsa_scsi_dev_t *dev,
  316. unsigned char *scsi3addr);
  317. static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
  318. {
  319. unsigned long *priv = shost_priv(sdev->host);
  320. return (struct ctlr_info *) *priv;
  321. }
  322. static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
  323. {
  324. unsigned long *priv = shost_priv(sh);
  325. return (struct ctlr_info *) *priv;
  326. }
  327. static inline bool hpsa_is_cmd_idle(struct CommandList *c)
  328. {
  329. return c->scsi_cmd == SCSI_CMD_IDLE;
  330. }
  331. /* extract sense key, asc, and ascq from sense data. -1 means invalid. */
  332. static void decode_sense_data(const u8 *sense_data, int sense_data_len,
  333. u8 *sense_key, u8 *asc, u8 *ascq)
  334. {
  335. struct scsi_sense_hdr sshdr;
  336. bool rc;
  337. *sense_key = -1;
  338. *asc = -1;
  339. *ascq = -1;
  340. if (sense_data_len < 1)
  341. return;
  342. rc = scsi_normalize_sense(sense_data, sense_data_len, &sshdr);
  343. if (rc) {
  344. *sense_key = sshdr.sense_key;
  345. *asc = sshdr.asc;
  346. *ascq = sshdr.ascq;
  347. }
  348. }
  349. static int check_for_unit_attention(struct ctlr_info *h,
  350. struct CommandList *c)
  351. {
  352. u8 sense_key, asc, ascq;
  353. int sense_len;
  354. if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
  355. sense_len = sizeof(c->err_info->SenseInfo);
  356. else
  357. sense_len = c->err_info->SenseLen;
  358. decode_sense_data(c->err_info->SenseInfo, sense_len,
  359. &sense_key, &asc, &ascq);
  360. if (sense_key != UNIT_ATTENTION || asc == 0xff)
  361. return 0;
  362. switch (asc) {
  363. case STATE_CHANGED:
  364. dev_warn(&h->pdev->dev,
  365. "%s: a state change detected, command retried\n",
  366. h->devname);
  367. break;
  368. case LUN_FAILED:
  369. dev_warn(&h->pdev->dev,
  370. "%s: LUN failure detected\n", h->devname);
  371. break;
  372. case REPORT_LUNS_CHANGED:
  373. dev_warn(&h->pdev->dev,
  374. "%s: report LUN data changed\n", h->devname);
  375. /*
  376. * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
  377. * target (array) devices.
  378. */
  379. break;
  380. case POWER_OR_RESET:
  381. dev_warn(&h->pdev->dev,
  382. "%s: a power on or device reset detected\n",
  383. h->devname);
  384. break;
  385. case UNIT_ATTENTION_CLEARED:
  386. dev_warn(&h->pdev->dev,
  387. "%s: unit attention cleared by another initiator\n",
  388. h->devname);
  389. break;
  390. default:
  391. dev_warn(&h->pdev->dev,
  392. "%s: unknown unit attention detected\n",
  393. h->devname);
  394. break;
  395. }
  396. return 1;
  397. }
  398. static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
  399. {
  400. if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
  401. (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
  402. c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
  403. return 0;
  404. dev_warn(&h->pdev->dev, HPSA "device busy");
  405. return 1;
  406. }
  407. static u32 lockup_detected(struct ctlr_info *h);
  408. static ssize_t host_show_lockup_detected(struct device *dev,
  409. struct device_attribute *attr, char *buf)
  410. {
  411. int ld;
  412. struct ctlr_info *h;
  413. struct Scsi_Host *shost = class_to_shost(dev);
  414. h = shost_to_hba(shost);
  415. ld = lockup_detected(h);
  416. return sprintf(buf, "ld=%d\n", ld);
  417. }
  418. static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev,
  419. struct device_attribute *attr,
  420. const char *buf, size_t count)
  421. {
  422. int status, len;
  423. struct ctlr_info *h;
  424. struct Scsi_Host *shost = class_to_shost(dev);
  425. char tmpbuf[10];
  426. if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
  427. return -EACCES;
  428. len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
  429. strncpy(tmpbuf, buf, len);
  430. tmpbuf[len] = '\0';
  431. if (sscanf(tmpbuf, "%d", &status) != 1)
  432. return -EINVAL;
  433. h = shost_to_hba(shost);
  434. h->acciopath_status = !!status;
  435. dev_warn(&h->pdev->dev,
  436. "hpsa: HP SSD Smart Path %s via sysfs update.\n",
  437. h->acciopath_status ? "enabled" : "disabled");
  438. return count;
  439. }
  440. static ssize_t host_store_raid_offload_debug(struct device *dev,
  441. struct device_attribute *attr,
  442. const char *buf, size_t count)
  443. {
  444. int debug_level, len;
  445. struct ctlr_info *h;
  446. struct Scsi_Host *shost = class_to_shost(dev);
  447. char tmpbuf[10];
  448. if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
  449. return -EACCES;
  450. len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
  451. strncpy(tmpbuf, buf, len);
  452. tmpbuf[len] = '\0';
  453. if (sscanf(tmpbuf, "%d", &debug_level) != 1)
  454. return -EINVAL;
  455. if (debug_level < 0)
  456. debug_level = 0;
  457. h = shost_to_hba(shost);
  458. h->raid_offload_debug = debug_level;
  459. dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n",
  460. h->raid_offload_debug);
  461. return count;
  462. }
  463. static ssize_t host_store_rescan(struct device *dev,
  464. struct device_attribute *attr,
  465. const char *buf, size_t count)
  466. {
  467. struct ctlr_info *h;
  468. struct Scsi_Host *shost = class_to_shost(dev);
  469. h = shost_to_hba(shost);
  470. hpsa_scan_start(h->scsi_host);
  471. return count;
  472. }
  473. static void hpsa_turn_off_ioaccel_for_device(struct hpsa_scsi_dev_t *device)
  474. {
  475. device->offload_enabled = 0;
  476. device->offload_to_be_enabled = 0;
  477. }
  478. static ssize_t host_show_firmware_revision(struct device *dev,
  479. struct device_attribute *attr, char *buf)
  480. {
  481. struct ctlr_info *h;
  482. struct Scsi_Host *shost = class_to_shost(dev);
  483. unsigned char *fwrev;
  484. h = shost_to_hba(shost);
  485. if (!h->hba_inquiry_data)
  486. return 0;
  487. fwrev = &h->hba_inquiry_data[32];
  488. return snprintf(buf, 20, "%c%c%c%c\n",
  489. fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
  490. }
  491. static ssize_t host_show_commands_outstanding(struct device *dev,
  492. struct device_attribute *attr, char *buf)
  493. {
  494. struct Scsi_Host *shost = class_to_shost(dev);
  495. struct ctlr_info *h = shost_to_hba(shost);
  496. return snprintf(buf, 20, "%d\n",
  497. atomic_read(&h->commands_outstanding));
  498. }
  499. static ssize_t host_show_transport_mode(struct device *dev,
  500. struct device_attribute *attr, char *buf)
  501. {
  502. struct ctlr_info *h;
  503. struct Scsi_Host *shost = class_to_shost(dev);
  504. h = shost_to_hba(shost);
  505. return snprintf(buf, 20, "%s\n",
  506. h->transMethod & CFGTBL_Trans_Performant ?
  507. "performant" : "simple");
  508. }
  509. static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev,
  510. struct device_attribute *attr, char *buf)
  511. {
  512. struct ctlr_info *h;
  513. struct Scsi_Host *shost = class_to_shost(dev);
  514. h = shost_to_hba(shost);
  515. return snprintf(buf, 30, "HP SSD Smart Path %s\n",
  516. (h->acciopath_status == 1) ? "enabled" : "disabled");
  517. }
  518. /* List of controllers which cannot be hard reset on kexec with reset_devices */
  519. static u32 unresettable_controller[] = {
  520. 0x324a103C, /* Smart Array P712m */
  521. 0x324b103C, /* Smart Array P711m */
  522. 0x3223103C, /* Smart Array P800 */
  523. 0x3234103C, /* Smart Array P400 */
  524. 0x3235103C, /* Smart Array P400i */
  525. 0x3211103C, /* Smart Array E200i */
  526. 0x3212103C, /* Smart Array E200 */
  527. 0x3213103C, /* Smart Array E200i */
  528. 0x3214103C, /* Smart Array E200i */
  529. 0x3215103C, /* Smart Array E200i */
  530. 0x3237103C, /* Smart Array E500 */
  531. 0x323D103C, /* Smart Array P700m */
  532. 0x40800E11, /* Smart Array 5i */
  533. 0x409C0E11, /* Smart Array 6400 */
  534. 0x409D0E11, /* Smart Array 6400 EM */
  535. 0x40700E11, /* Smart Array 5300 */
  536. 0x40820E11, /* Smart Array 532 */
  537. 0x40830E11, /* Smart Array 5312 */
  538. 0x409A0E11, /* Smart Array 641 */
  539. 0x409B0E11, /* Smart Array 642 */
  540. 0x40910E11, /* Smart Array 6i */
  541. };
  542. /* List of controllers which cannot even be soft reset */
  543. static u32 soft_unresettable_controller[] = {
  544. 0x40800E11, /* Smart Array 5i */
  545. 0x40700E11, /* Smart Array 5300 */
  546. 0x40820E11, /* Smart Array 532 */
  547. 0x40830E11, /* Smart Array 5312 */
  548. 0x409A0E11, /* Smart Array 641 */
  549. 0x409B0E11, /* Smart Array 642 */
  550. 0x40910E11, /* Smart Array 6i */
  551. /* Exclude 640x boards. These are two pci devices in one slot
  552. * which share a battery backed cache module. One controls the
  553. * cache, the other accesses the cache through the one that controls
  554. * it. If we reset the one controlling the cache, the other will
  555. * likely not be happy. Just forbid resetting this conjoined mess.
  556. * The 640x isn't really supported by hpsa anyway.
  557. */
  558. 0x409C0E11, /* Smart Array 6400 */
  559. 0x409D0E11, /* Smart Array 6400 EM */
  560. };
  561. static int board_id_in_array(u32 a[], int nelems, u32 board_id)
  562. {
  563. int i;
  564. for (i = 0; i < nelems; i++)
  565. if (a[i] == board_id)
  566. return 1;
  567. return 0;
  568. }
  569. static int ctlr_is_hard_resettable(u32 board_id)
  570. {
  571. return !board_id_in_array(unresettable_controller,
  572. ARRAY_SIZE(unresettable_controller), board_id);
  573. }
  574. static int ctlr_is_soft_resettable(u32 board_id)
  575. {
  576. return !board_id_in_array(soft_unresettable_controller,
  577. ARRAY_SIZE(soft_unresettable_controller), board_id);
  578. }
  579. static int ctlr_is_resettable(u32 board_id)
  580. {
  581. return ctlr_is_hard_resettable(board_id) ||
  582. ctlr_is_soft_resettable(board_id);
  583. }
  584. static ssize_t host_show_resettable(struct device *dev,
  585. struct device_attribute *attr, char *buf)
  586. {
  587. struct ctlr_info *h;
  588. struct Scsi_Host *shost = class_to_shost(dev);
  589. h = shost_to_hba(shost);
  590. return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
  591. }
  592. static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
  593. {
  594. return (scsi3addr[3] & 0xC0) == 0x40;
  595. }
  596. static const char * const raid_label[] = { "0", "4", "1(+0)", "5", "5+1", "6",
  597. "1(+0)ADM", "UNKNOWN", "PHYS DRV"
  598. };
  599. #define HPSA_RAID_0 0
  600. #define HPSA_RAID_4 1
  601. #define HPSA_RAID_1 2 /* also used for RAID 10 */
  602. #define HPSA_RAID_5 3 /* also used for RAID 50 */
  603. #define HPSA_RAID_51 4
  604. #define HPSA_RAID_6 5 /* also used for RAID 60 */
  605. #define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
  606. #define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 2)
  607. #define PHYSICAL_DRIVE (ARRAY_SIZE(raid_label) - 1)
  608. static inline bool is_logical_device(struct hpsa_scsi_dev_t *device)
  609. {
  610. return !device->physical_device;
  611. }
  612. static ssize_t raid_level_show(struct device *dev,
  613. struct device_attribute *attr, char *buf)
  614. {
  615. ssize_t l = 0;
  616. unsigned char rlevel;
  617. struct ctlr_info *h;
  618. struct scsi_device *sdev;
  619. struct hpsa_scsi_dev_t *hdev;
  620. unsigned long flags;
  621. sdev = to_scsi_device(dev);
  622. h = sdev_to_hba(sdev);
  623. spin_lock_irqsave(&h->lock, flags);
  624. hdev = sdev->hostdata;
  625. if (!hdev) {
  626. spin_unlock_irqrestore(&h->lock, flags);
  627. return -ENODEV;
  628. }
  629. /* Is this even a logical drive? */
  630. if (!is_logical_device(hdev)) {
  631. spin_unlock_irqrestore(&h->lock, flags);
  632. l = snprintf(buf, PAGE_SIZE, "N/A\n");
  633. return l;
  634. }
  635. rlevel = hdev->raid_level;
  636. spin_unlock_irqrestore(&h->lock, flags);
  637. if (rlevel > RAID_UNKNOWN)
  638. rlevel = RAID_UNKNOWN;
  639. l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
  640. return l;
  641. }
  642. static ssize_t lunid_show(struct device *dev,
  643. struct device_attribute *attr, char *buf)
  644. {
  645. struct ctlr_info *h;
  646. struct scsi_device *sdev;
  647. struct hpsa_scsi_dev_t *hdev;
  648. unsigned long flags;
  649. unsigned char lunid[8];
  650. sdev = to_scsi_device(dev);
  651. h = sdev_to_hba(sdev);
  652. spin_lock_irqsave(&h->lock, flags);
  653. hdev = sdev->hostdata;
  654. if (!hdev) {
  655. spin_unlock_irqrestore(&h->lock, flags);
  656. return -ENODEV;
  657. }
  658. memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
  659. spin_unlock_irqrestore(&h->lock, flags);
  660. return snprintf(buf, 20, "0x%8phN\n", lunid);
  661. }
  662. static ssize_t unique_id_show(struct device *dev,
  663. struct device_attribute *attr, char *buf)
  664. {
  665. struct ctlr_info *h;
  666. struct scsi_device *sdev;
  667. struct hpsa_scsi_dev_t *hdev;
  668. unsigned long flags;
  669. unsigned char sn[16];
  670. sdev = to_scsi_device(dev);
  671. h = sdev_to_hba(sdev);
  672. spin_lock_irqsave(&h->lock, flags);
  673. hdev = sdev->hostdata;
  674. if (!hdev) {
  675. spin_unlock_irqrestore(&h->lock, flags);
  676. return -ENODEV;
  677. }
  678. memcpy(sn, hdev->device_id, sizeof(sn));
  679. spin_unlock_irqrestore(&h->lock, flags);
  680. return snprintf(buf, 16 * 2 + 2,
  681. "%02X%02X%02X%02X%02X%02X%02X%02X"
  682. "%02X%02X%02X%02X%02X%02X%02X%02X\n",
  683. sn[0], sn[1], sn[2], sn[3],
  684. sn[4], sn[5], sn[6], sn[7],
  685. sn[8], sn[9], sn[10], sn[11],
  686. sn[12], sn[13], sn[14], sn[15]);
  687. }
  688. static ssize_t sas_address_show(struct device *dev,
  689. struct device_attribute *attr, char *buf)
  690. {
  691. struct ctlr_info *h;
  692. struct scsi_device *sdev;
  693. struct hpsa_scsi_dev_t *hdev;
  694. unsigned long flags;
  695. u64 sas_address;
  696. sdev = to_scsi_device(dev);
  697. h = sdev_to_hba(sdev);
  698. spin_lock_irqsave(&h->lock, flags);
  699. hdev = sdev->hostdata;
  700. if (!hdev || is_logical_device(hdev) || !hdev->expose_device) {
  701. spin_unlock_irqrestore(&h->lock, flags);
  702. return -ENODEV;
  703. }
  704. sas_address = hdev->sas_address;
  705. spin_unlock_irqrestore(&h->lock, flags);
  706. return snprintf(buf, PAGE_SIZE, "0x%016llx\n", sas_address);
  707. }
  708. static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
  709. struct device_attribute *attr, char *buf)
  710. {
  711. struct ctlr_info *h;
  712. struct scsi_device *sdev;
  713. struct hpsa_scsi_dev_t *hdev;
  714. unsigned long flags;
  715. int offload_enabled;
  716. sdev = to_scsi_device(dev);
  717. h = sdev_to_hba(sdev);
  718. spin_lock_irqsave(&h->lock, flags);
  719. hdev = sdev->hostdata;
  720. if (!hdev) {
  721. spin_unlock_irqrestore(&h->lock, flags);
  722. return -ENODEV;
  723. }
  724. offload_enabled = hdev->offload_enabled;
  725. spin_unlock_irqrestore(&h->lock, flags);
  726. if (hdev->devtype == TYPE_DISK || hdev->devtype == TYPE_ZBC)
  727. return snprintf(buf, 20, "%d\n", offload_enabled);
  728. else
  729. return snprintf(buf, 40, "%s\n",
  730. "Not applicable for a controller");
  731. }
  732. #define MAX_PATHS 8
  733. static ssize_t path_info_show(struct device *dev,
  734. struct device_attribute *attr, char *buf)
  735. {
  736. struct ctlr_info *h;
  737. struct scsi_device *sdev;
  738. struct hpsa_scsi_dev_t *hdev;
  739. unsigned long flags;
  740. int i;
  741. int output_len = 0;
  742. u8 box;
  743. u8 bay;
  744. u8 path_map_index = 0;
  745. char *active;
  746. unsigned char phys_connector[2];
  747. sdev = to_scsi_device(dev);
  748. h = sdev_to_hba(sdev);
  749. spin_lock_irqsave(&h->devlock, flags);
  750. hdev = sdev->hostdata;
  751. if (!hdev) {
  752. spin_unlock_irqrestore(&h->devlock, flags);
  753. return -ENODEV;
  754. }
  755. bay = hdev->bay;
  756. for (i = 0; i < MAX_PATHS; i++) {
  757. path_map_index = 1<<i;
  758. if (i == hdev->active_path_index)
  759. active = "Active";
  760. else if (hdev->path_map & path_map_index)
  761. active = "Inactive";
  762. else
  763. continue;
  764. output_len += scnprintf(buf + output_len,
  765. PAGE_SIZE - output_len,
  766. "[%d:%d:%d:%d] %20.20s ",
  767. h->scsi_host->host_no,
  768. hdev->bus, hdev->target, hdev->lun,
  769. scsi_device_type(hdev->devtype));
  770. if (hdev->devtype == TYPE_RAID || is_logical_device(hdev)) {
  771. output_len += scnprintf(buf + output_len,
  772. PAGE_SIZE - output_len,
  773. "%s\n", active);
  774. continue;
  775. }
  776. box = hdev->box[i];
  777. memcpy(&phys_connector, &hdev->phys_connector[i],
  778. sizeof(phys_connector));
  779. if (phys_connector[0] < '0')
  780. phys_connector[0] = '0';
  781. if (phys_connector[1] < '0')
  782. phys_connector[1] = '0';
  783. output_len += scnprintf(buf + output_len,
  784. PAGE_SIZE - output_len,
  785. "PORT: %.2s ",
  786. phys_connector);
  787. if ((hdev->devtype == TYPE_DISK || hdev->devtype == TYPE_ZBC) &&
  788. hdev->expose_device) {
  789. if (box == 0 || box == 0xFF) {
  790. output_len += scnprintf(buf + output_len,
  791. PAGE_SIZE - output_len,
  792. "BAY: %hhu %s\n",
  793. bay, active);
  794. } else {
  795. output_len += scnprintf(buf + output_len,
  796. PAGE_SIZE - output_len,
  797. "BOX: %hhu BAY: %hhu %s\n",
  798. box, bay, active);
  799. }
  800. } else if (box != 0 && box != 0xFF) {
  801. output_len += scnprintf(buf + output_len,
  802. PAGE_SIZE - output_len, "BOX: %hhu %s\n",
  803. box, active);
  804. } else
  805. output_len += scnprintf(buf + output_len,
  806. PAGE_SIZE - output_len, "%s\n", active);
  807. }
  808. spin_unlock_irqrestore(&h->devlock, flags);
  809. return output_len;
  810. }
  811. static ssize_t host_show_ctlr_num(struct device *dev,
  812. struct device_attribute *attr, char *buf)
  813. {
  814. struct ctlr_info *h;
  815. struct Scsi_Host *shost = class_to_shost(dev);
  816. h = shost_to_hba(shost);
  817. return snprintf(buf, 20, "%d\n", h->ctlr);
  818. }
  819. static ssize_t host_show_legacy_board(struct device *dev,
  820. struct device_attribute *attr, char *buf)
  821. {
  822. struct ctlr_info *h;
  823. struct Scsi_Host *shost = class_to_shost(dev);
  824. h = shost_to_hba(shost);
  825. return snprintf(buf, 20, "%d\n", h->legacy_board ? 1 : 0);
  826. }
  827. static DEVICE_ATTR_RO(raid_level);
  828. static DEVICE_ATTR_RO(lunid);
  829. static DEVICE_ATTR_RO(unique_id);
  830. static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
  831. static DEVICE_ATTR_RO(sas_address);
  832. static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
  833. host_show_hp_ssd_smart_path_enabled, NULL);
  834. static DEVICE_ATTR_RO(path_info);
  835. static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH,
  836. host_show_hp_ssd_smart_path_status,
  837. host_store_hp_ssd_smart_path_status);
  838. static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL,
  839. host_store_raid_offload_debug);
  840. static DEVICE_ATTR(firmware_revision, S_IRUGO,
  841. host_show_firmware_revision, NULL);
  842. static DEVICE_ATTR(commands_outstanding, S_IRUGO,
  843. host_show_commands_outstanding, NULL);
  844. static DEVICE_ATTR(transport_mode, S_IRUGO,
  845. host_show_transport_mode, NULL);
  846. static DEVICE_ATTR(resettable, S_IRUGO,
  847. host_show_resettable, NULL);
  848. static DEVICE_ATTR(lockup_detected, S_IRUGO,
  849. host_show_lockup_detected, NULL);
  850. static DEVICE_ATTR(ctlr_num, S_IRUGO,
  851. host_show_ctlr_num, NULL);
  852. static DEVICE_ATTR(legacy_board, S_IRUGO,
  853. host_show_legacy_board, NULL);
  854. static struct attribute *hpsa_sdev_attrs[] = {
  855. &dev_attr_raid_level.attr,
  856. &dev_attr_lunid.attr,
  857. &dev_attr_unique_id.attr,
  858. &dev_attr_hp_ssd_smart_path_enabled.attr,
  859. &dev_attr_path_info.attr,
  860. &dev_attr_sas_address.attr,
  861. NULL,
  862. };
  863. ATTRIBUTE_GROUPS(hpsa_sdev);
  864. static struct attribute *hpsa_shost_attrs[] = {
  865. &dev_attr_rescan.attr,
  866. &dev_attr_firmware_revision.attr,
  867. &dev_attr_commands_outstanding.attr,
  868. &dev_attr_transport_mode.attr,
  869. &dev_attr_resettable.attr,
  870. &dev_attr_hp_ssd_smart_path_status.attr,
  871. &dev_attr_raid_offload_debug.attr,
  872. &dev_attr_lockup_detected.attr,
  873. &dev_attr_ctlr_num.attr,
  874. &dev_attr_legacy_board.attr,
  875. NULL,
  876. };
  877. ATTRIBUTE_GROUPS(hpsa_shost);
  878. #define HPSA_NRESERVED_CMDS (HPSA_CMDS_RESERVED_FOR_DRIVER +\
  879. HPSA_MAX_CONCURRENT_PASSTHRUS)
  880. static struct scsi_host_template hpsa_driver_template = {
  881. .module = THIS_MODULE,
  882. .name = HPSA,
  883. .proc_name = HPSA,
  884. .queuecommand = hpsa_scsi_queue_command,
  885. .scan_start = hpsa_scan_start,
  886. .scan_finished = hpsa_scan_finished,
  887. .change_queue_depth = hpsa_change_queue_depth,
  888. .this_id = -1,
  889. .eh_device_reset_handler = hpsa_eh_device_reset_handler,
  890. .ioctl = hpsa_ioctl,
  891. .slave_alloc = hpsa_slave_alloc,
  892. .slave_configure = hpsa_slave_configure,
  893. .slave_destroy = hpsa_slave_destroy,
  894. #ifdef CONFIG_COMPAT
  895. .compat_ioctl = hpsa_compat_ioctl,
  896. #endif
  897. .sdev_groups = hpsa_sdev_groups,
  898. .shost_groups = hpsa_shost_groups,
  899. .max_sectors = 2048,
  900. .no_write_same = 1,
  901. };
  902. static inline u32 next_command(struct ctlr_info *h, u8 q)
  903. {
  904. u32 a;
  905. struct reply_queue_buffer *rq = &h->reply_queue[q];
  906. if (h->transMethod & CFGTBL_Trans_io_accel1)
  907. return h->access.command_completed(h, q);
  908. if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
  909. return h->access.command_completed(h, q);
  910. if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
  911. a = rq->head[rq->current_entry];
  912. rq->current_entry++;
  913. atomic_dec(&h->commands_outstanding);
  914. } else {
  915. a = FIFO_EMPTY;
  916. }
  917. /* Check for wraparound */
  918. if (rq->current_entry == h->max_commands) {
  919. rq->current_entry = 0;
  920. rq->wraparound ^= 1;
  921. }
  922. return a;
  923. }
  924. /*
  925. * There are some special bits in the bus address of the
  926. * command that we have to set for the controller to know
  927. * how to process the command:
  928. *
  929. * Normal performant mode:
  930. * bit 0: 1 means performant mode, 0 means simple mode.
  931. * bits 1-3 = block fetch table entry
  932. * bits 4-6 = command type (== 0)
  933. *
  934. * ioaccel1 mode:
  935. * bit 0 = "performant mode" bit.
  936. * bits 1-3 = block fetch table entry
  937. * bits 4-6 = command type (== 110)
  938. * (command type is needed because ioaccel1 mode
  939. * commands are submitted through the same register as normal
  940. * mode commands, so this is how the controller knows whether
  941. * the command is normal mode or ioaccel1 mode.)
  942. *
  943. * ioaccel2 mode:
  944. * bit 0 = "performant mode" bit.
  945. * bits 1-4 = block fetch table entry (note extra bit)
  946. * bits 4-6 = not needed, because ioaccel2 mode has
  947. * a separate special register for submitting commands.
  948. */
  949. /*
  950. * set_performant_mode: Modify the tag for cciss performant
  951. * set bit 0 for pull model, bits 3-1 for block fetch
  952. * register number
  953. */
  954. #define DEFAULT_REPLY_QUEUE (-1)
  955. static void set_performant_mode(struct ctlr_info *h, struct CommandList *c,
  956. int reply_queue)
  957. {
  958. if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
  959. c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
  960. if (unlikely(!h->msix_vectors))
  961. return;
  962. c->Header.ReplyQueue = reply_queue;
  963. }
  964. }
  965. static void set_ioaccel1_performant_mode(struct ctlr_info *h,
  966. struct CommandList *c,
  967. int reply_queue)
  968. {
  969. struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
  970. /*
  971. * Tell the controller to post the reply to the queue for this
  972. * processor. This seems to give the best I/O throughput.
  973. */
  974. cp->ReplyQueue = reply_queue;
  975. /*
  976. * Set the bits in the address sent down to include:
  977. * - performant mode bit (bit 0)
  978. * - pull count (bits 1-3)
  979. * - command type (bits 4-6)
  980. */
  981. c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
  982. IOACCEL1_BUSADDR_CMDTYPE;
  983. }
  984. static void set_ioaccel2_tmf_performant_mode(struct ctlr_info *h,
  985. struct CommandList *c,
  986. int reply_queue)
  987. {
  988. struct hpsa_tmf_struct *cp = (struct hpsa_tmf_struct *)
  989. &h->ioaccel2_cmd_pool[c->cmdindex];
  990. /* Tell the controller to post the reply to the queue for this
  991. * processor. This seems to give the best I/O throughput.
  992. */
  993. cp->reply_queue = reply_queue;
  994. /* Set the bits in the address sent down to include:
  995. * - performant mode bit not used in ioaccel mode 2
  996. * - pull count (bits 0-3)
  997. * - command type isn't needed for ioaccel2
  998. */
  999. c->busaddr |= h->ioaccel2_blockFetchTable[0];
  1000. }
  1001. static void set_ioaccel2_performant_mode(struct ctlr_info *h,
  1002. struct CommandList *c,
  1003. int reply_queue)
  1004. {
  1005. struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
  1006. /*
  1007. * Tell the controller to post the reply to the queue for this
  1008. * processor. This seems to give the best I/O throughput.
  1009. */
  1010. cp->reply_queue = reply_queue;
  1011. /*
  1012. * Set the bits in the address sent down to include:
  1013. * - performant mode bit not used in ioaccel mode 2
  1014. * - pull count (bits 0-3)
  1015. * - command type isn't needed for ioaccel2
  1016. */
  1017. c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
  1018. }
  1019. static int is_firmware_flash_cmd(u8 *cdb)
  1020. {
  1021. return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
  1022. }
  1023. /*
  1024. * During firmware flash, the heartbeat register may not update as frequently
  1025. * as it should. So we dial down lockup detection during firmware flash. and
  1026. * dial it back up when firmware flash completes.
  1027. */
  1028. #define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
  1029. #define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
  1030. #define HPSA_EVENT_MONITOR_INTERVAL (15 * HZ)
  1031. static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
  1032. struct CommandList *c)
  1033. {
  1034. if (!is_firmware_flash_cmd(c->Request.CDB))
  1035. return;
  1036. atomic_inc(&h->firmware_flash_in_progress);
  1037. h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
  1038. }
  1039. static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
  1040. struct CommandList *c)
  1041. {
  1042. if (is_firmware_flash_cmd(c->Request.CDB) &&
  1043. atomic_dec_and_test(&h->firmware_flash_in_progress))
  1044. h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
  1045. }
  1046. static void __enqueue_cmd_and_start_io(struct ctlr_info *h,
  1047. struct CommandList *c, int reply_queue)
  1048. {
  1049. dial_down_lockup_detection_during_fw_flash(h, c);
  1050. atomic_inc(&h->commands_outstanding);
  1051. /*
  1052. * Check to see if the command is being retried.
  1053. */
  1054. if (c->device && !c->retry_pending)
  1055. atomic_inc(&c->device->commands_outstanding);
  1056. reply_queue = h->reply_map[raw_smp_processor_id()];
  1057. switch (c->cmd_type) {
  1058. case CMD_IOACCEL1:
  1059. set_ioaccel1_performant_mode(h, c, reply_queue);
  1060. writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
  1061. break;
  1062. case CMD_IOACCEL2:
  1063. set_ioaccel2_performant_mode(h, c, reply_queue);
  1064. writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
  1065. break;
  1066. case IOACCEL2_TMF:
  1067. set_ioaccel2_tmf_performant_mode(h, c, reply_queue);
  1068. writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
  1069. break;
  1070. default:
  1071. set_performant_mode(h, c, reply_queue);
  1072. h->access.submit_command(h, c);
  1073. }
  1074. }
  1075. static void enqueue_cmd_and_start_io(struct ctlr_info *h, struct CommandList *c)
  1076. {
  1077. __enqueue_cmd_and_start_io(h, c, DEFAULT_REPLY_QUEUE);
  1078. }
  1079. static inline int is_hba_lunid(unsigned char scsi3addr[])
  1080. {
  1081. return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
  1082. }
  1083. static inline int is_scsi_rev_5(struct ctlr_info *h)
  1084. {
  1085. if (!h->hba_inquiry_data)
  1086. return 0;
  1087. if ((h->hba_inquiry_data[2] & 0x07) == 5)
  1088. return 1;
  1089. return 0;
  1090. }
  1091. static int hpsa_find_target_lun(struct ctlr_info *h,
  1092. unsigned char scsi3addr[], int bus, int *target, int *lun)
  1093. {
  1094. /* finds an unused bus, target, lun for a new physical device
  1095. * assumes h->devlock is held
  1096. */
  1097. int i, found = 0;
  1098. DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
  1099. bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
  1100. for (i = 0; i < h->ndevices; i++) {
  1101. if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
  1102. __set_bit(h->dev[i]->target, lun_taken);
  1103. }
  1104. i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
  1105. if (i < HPSA_MAX_DEVICES) {
  1106. /* *bus = 1; */
  1107. *target = i;
  1108. *lun = 0;
  1109. found = 1;
  1110. }
  1111. return !found;
  1112. }
  1113. static void hpsa_show_dev_msg(const char *level, struct ctlr_info *h,
  1114. struct hpsa_scsi_dev_t *dev, char *description)
  1115. {
  1116. #define LABEL_SIZE 25
  1117. char label[LABEL_SIZE];
  1118. if (h == NULL || h->pdev == NULL || h->scsi_host == NULL)
  1119. return;
  1120. switch (dev->devtype) {
  1121. case TYPE_RAID:
  1122. snprintf(label, LABEL_SIZE, "controller");
  1123. break;
  1124. case TYPE_ENCLOSURE:
  1125. snprintf(label, LABEL_SIZE, "enclosure");
  1126. break;
  1127. case TYPE_DISK:
  1128. case TYPE_ZBC:
  1129. if (dev->external)
  1130. snprintf(label, LABEL_SIZE, "external");
  1131. else if (!is_logical_dev_addr_mode(dev->scsi3addr))
  1132. snprintf(label, LABEL_SIZE, "%s",
  1133. raid_label[PHYSICAL_DRIVE]);
  1134. else
  1135. snprintf(label, LABEL_SIZE, "RAID-%s",
  1136. dev->raid_level > RAID_UNKNOWN ? "?" :
  1137. raid_label[dev->raid_level]);
  1138. break;
  1139. case TYPE_ROM:
  1140. snprintf(label, LABEL_SIZE, "rom");
  1141. break;
  1142. case TYPE_TAPE:
  1143. snprintf(label, LABEL_SIZE, "tape");
  1144. break;
  1145. case TYPE_MEDIUM_CHANGER:
  1146. snprintf(label, LABEL_SIZE, "changer");
  1147. break;
  1148. default:
  1149. snprintf(label, LABEL_SIZE, "UNKNOWN");
  1150. break;
  1151. }
  1152. dev_printk(level, &h->pdev->dev,
  1153. "scsi %d:%d:%d:%d: %s %s %.8s %.16s %s SSDSmartPathCap%c En%c Exp=%d\n",
  1154. h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
  1155. description,
  1156. scsi_device_type(dev->devtype),
  1157. dev->vendor,
  1158. dev->model,
  1159. label,
  1160. dev->offload_config ? '+' : '-',
  1161. dev->offload_to_be_enabled ? '+' : '-',
  1162. dev->expose_device);
  1163. }
  1164. /* Add an entry into h->dev[] array. */
  1165. static int hpsa_scsi_add_entry(struct ctlr_info *h,
  1166. struct hpsa_scsi_dev_t *device,
  1167. struct hpsa_scsi_dev_t *added[], int *nadded)
  1168. {
  1169. /* assumes h->devlock is held */
  1170. int n = h->ndevices;
  1171. int i;
  1172. unsigned char addr1[8], addr2[8];
  1173. struct hpsa_scsi_dev_t *sd;
  1174. if (n >= HPSA_MAX_DEVICES) {
  1175. dev_err(&h->pdev->dev, "too many devices, some will be "
  1176. "inaccessible.\n");
  1177. return -1;
  1178. }
  1179. /* physical devices do not have lun or target assigned until now. */
  1180. if (device->lun != -1)
  1181. /* Logical device, lun is already assigned. */
  1182. goto lun_assigned;
  1183. /* If this device a non-zero lun of a multi-lun device
  1184. * byte 4 of the 8-byte LUN addr will contain the logical
  1185. * unit no, zero otherwise.
  1186. */
  1187. if (device->scsi3addr[4] == 0) {
  1188. /* This is not a non-zero lun of a multi-lun device */
  1189. if (hpsa_find_target_lun(h, device->scsi3addr,
  1190. device->bus, &device->target, &device->lun) != 0)
  1191. return -1;
  1192. goto lun_assigned;
  1193. }
  1194. /* This is a non-zero lun of a multi-lun device.
  1195. * Search through our list and find the device which
  1196. * has the same 8 byte LUN address, excepting byte 4 and 5.
  1197. * Assign the same bus and target for this new LUN.
  1198. * Use the logical unit number from the firmware.
  1199. */
  1200. memcpy(addr1, device->scsi3addr, 8);
  1201. addr1[4] = 0;
  1202. addr1[5] = 0;
  1203. for (i = 0; i < n; i++) {
  1204. sd = h->dev[i];
  1205. memcpy(addr2, sd->scsi3addr, 8);
  1206. addr2[4] = 0;
  1207. addr2[5] = 0;
  1208. /* differ only in byte 4 and 5? */
  1209. if (memcmp(addr1, addr2, 8) == 0) {
  1210. device->bus = sd->bus;
  1211. device->target = sd->target;
  1212. device->lun = device->scsi3addr[4];
  1213. break;
  1214. }
  1215. }
  1216. if (device->lun == -1) {
  1217. dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
  1218. " suspect firmware bug or unsupported hardware "
  1219. "configuration.\n");
  1220. return -1;
  1221. }
  1222. lun_assigned:
  1223. h->dev[n] = device;
  1224. h->ndevices++;
  1225. added[*nadded] = device;
  1226. (*nadded)++;
  1227. hpsa_show_dev_msg(KERN_INFO, h, device,
  1228. device->expose_device ? "added" : "masked");
  1229. return 0;
  1230. }
  1231. /*
  1232. * Called during a scan operation.
  1233. *
  1234. * Update an entry in h->dev[] array.
  1235. */
  1236. static void hpsa_scsi_update_entry(struct ctlr_info *h,
  1237. int entry, struct hpsa_scsi_dev_t *new_entry)
  1238. {
  1239. /* assumes h->devlock is held */
  1240. BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
  1241. /* Raid level changed. */
  1242. h->dev[entry]->raid_level = new_entry->raid_level;
  1243. /*
  1244. * ioacccel_handle may have changed for a dual domain disk
  1245. */
  1246. h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
  1247. /* Raid offload parameters changed. Careful about the ordering. */
  1248. if (new_entry->offload_config && new_entry->offload_to_be_enabled) {
  1249. /*
  1250. * if drive is newly offload_enabled, we want to copy the
  1251. * raid map data first. If previously offload_enabled and
  1252. * offload_config were set, raid map data had better be
  1253. * the same as it was before. If raid map data has changed
  1254. * then it had better be the case that
  1255. * h->dev[entry]->offload_enabled is currently 0.
  1256. */
  1257. h->dev[entry]->raid_map = new_entry->raid_map;
  1258. h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
  1259. }
  1260. if (new_entry->offload_to_be_enabled) {
  1261. h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
  1262. wmb(); /* set ioaccel_handle *before* hba_ioaccel_enabled */
  1263. }
  1264. h->dev[entry]->hba_ioaccel_enabled = new_entry->hba_ioaccel_enabled;
  1265. h->dev[entry]->offload_config = new_entry->offload_config;
  1266. h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror;
  1267. h->dev[entry]->queue_depth = new_entry->queue_depth;
  1268. /*
  1269. * We can turn off ioaccel offload now, but need to delay turning
  1270. * ioaccel on until we can update h->dev[entry]->phys_disk[], but we
  1271. * can't do that until all the devices are updated.
  1272. */
  1273. h->dev[entry]->offload_to_be_enabled = new_entry->offload_to_be_enabled;
  1274. /*
  1275. * turn ioaccel off immediately if told to do so.
  1276. */
  1277. if (!new_entry->offload_to_be_enabled)
  1278. h->dev[entry]->offload_enabled = 0;
  1279. hpsa_show_dev_msg(KERN_INFO, h, h->dev[entry], "updated");
  1280. }
  1281. /* Replace an entry from h->dev[] array. */
  1282. static void hpsa_scsi_replace_entry(struct ctlr_info *h,
  1283. int entry, struct hpsa_scsi_dev_t *new_entry,
  1284. struct hpsa_scsi_dev_t *added[], int *nadded,
  1285. struct hpsa_scsi_dev_t *removed[], int *nremoved)
  1286. {
  1287. /* assumes h->devlock is held */
  1288. BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
  1289. removed[*nremoved] = h->dev[entry];
  1290. (*nremoved)++;
  1291. /*
  1292. * New physical devices won't have target/lun assigned yet
  1293. * so we need to preserve the values in the slot we are replacing.
  1294. */
  1295. if (new_entry->target == -1) {
  1296. new_entry->target = h->dev[entry]->target;
  1297. new_entry->lun = h->dev[entry]->lun;
  1298. }
  1299. h->dev[entry] = new_entry;
  1300. added[*nadded] = new_entry;
  1301. (*nadded)++;
  1302. hpsa_show_dev_msg(KERN_INFO, h, new_entry, "replaced");
  1303. }
  1304. /* Remove an entry from h->dev[] array. */
  1305. static void hpsa_scsi_remove_entry(struct ctlr_info *h, int entry,
  1306. struct hpsa_scsi_dev_t *removed[], int *nremoved)
  1307. {
  1308. /* assumes h->devlock is held */
  1309. int i;
  1310. struct hpsa_scsi_dev_t *sd;
  1311. BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
  1312. sd = h->dev[entry];
  1313. removed[*nremoved] = h->dev[entry];
  1314. (*nremoved)++;
  1315. for (i = entry; i < h->ndevices-1; i++)
  1316. h->dev[i] = h->dev[i+1];
  1317. h->ndevices--;
  1318. hpsa_show_dev_msg(KERN_INFO, h, sd, "removed");
  1319. }
  1320. #define SCSI3ADDR_EQ(a, b) ( \
  1321. (a)[7] == (b)[7] && \
  1322. (a)[6] == (b)[6] && \
  1323. (a)[5] == (b)[5] && \
  1324. (a)[4] == (b)[4] && \
  1325. (a)[3] == (b)[3] && \
  1326. (a)[2] == (b)[2] && \
  1327. (a)[1] == (b)[1] && \
  1328. (a)[0] == (b)[0])
  1329. static void fixup_botched_add(struct ctlr_info *h,
  1330. struct hpsa_scsi_dev_t *added)
  1331. {
  1332. /* called when scsi_add_device fails in order to re-adjust
  1333. * h->dev[] to match the mid layer's view.
  1334. */
  1335. unsigned long flags;
  1336. int i, j;
  1337. spin_lock_irqsave(&h->lock, flags);
  1338. for (i = 0; i < h->ndevices; i++) {
  1339. if (h->dev[i] == added) {
  1340. for (j = i; j < h->ndevices-1; j++)
  1341. h->dev[j] = h->dev[j+1];
  1342. h->ndevices--;
  1343. break;
  1344. }
  1345. }
  1346. spin_unlock_irqrestore(&h->lock, flags);
  1347. kfree(added);
  1348. }
  1349. static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
  1350. struct hpsa_scsi_dev_t *dev2)
  1351. {
  1352. /* we compare everything except lun and target as these
  1353. * are not yet assigned. Compare parts likely
  1354. * to differ first
  1355. */
  1356. if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
  1357. sizeof(dev1->scsi3addr)) != 0)
  1358. return 0;
  1359. if (memcmp(dev1->device_id, dev2->device_id,
  1360. sizeof(dev1->device_id)) != 0)
  1361. return 0;
  1362. if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
  1363. return 0;
  1364. if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
  1365. return 0;
  1366. if (dev1->devtype != dev2->devtype)
  1367. return 0;
  1368. if (dev1->bus != dev2->bus)
  1369. return 0;
  1370. return 1;
  1371. }
  1372. static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
  1373. struct hpsa_scsi_dev_t *dev2)
  1374. {
  1375. /* Device attributes that can change, but don't mean
  1376. * that the device is a different device, nor that the OS
  1377. * needs to be told anything about the change.
  1378. */
  1379. if (dev1->raid_level != dev2->raid_level)
  1380. return 1;
  1381. if (dev1->offload_config != dev2->offload_config)
  1382. return 1;
  1383. if (dev1->offload_to_be_enabled != dev2->offload_to_be_enabled)
  1384. return 1;
  1385. if (!is_logical_dev_addr_mode(dev1->scsi3addr))
  1386. if (dev1->queue_depth != dev2->queue_depth)
  1387. return 1;
  1388. /*
  1389. * This can happen for dual domain devices. An active
  1390. * path change causes the ioaccel handle to change
  1391. *
  1392. * for example note the handle differences between p0 and p1
  1393. * Device WWN ,WWN hash,Handle
  1394. * D016 p0|0x3 [02]P2E:01:01,0x5000C5005FC4DACA,0x9B5616,0x01030003
  1395. * p1 0x5000C5005FC4DAC9,0x6798C0,0x00040004
  1396. */
  1397. if (dev1->ioaccel_handle != dev2->ioaccel_handle)
  1398. return 1;
  1399. return 0;
  1400. }
  1401. /* Find needle in haystack. If exact match found, return DEVICE_SAME,
  1402. * and return needle location in *index. If scsi3addr matches, but not
  1403. * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
  1404. * location in *index.
  1405. * In the case of a minor device attribute change, such as RAID level, just
  1406. * return DEVICE_UPDATED, along with the updated device's location in index.
  1407. * If needle not found, return DEVICE_NOT_FOUND.
  1408. */
  1409. static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
  1410. struct hpsa_scsi_dev_t *haystack[], int haystack_size,
  1411. int *index)
  1412. {
  1413. int i;
  1414. #define DEVICE_NOT_FOUND 0
  1415. #define DEVICE_CHANGED 1
  1416. #define DEVICE_SAME 2
  1417. #define DEVICE_UPDATED 3
  1418. if (needle == NULL)
  1419. return DEVICE_NOT_FOUND;
  1420. for (i = 0; i < haystack_size; i++) {
  1421. if (haystack[i] == NULL) /* previously removed. */
  1422. continue;
  1423. if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
  1424. *index = i;
  1425. if (device_is_the_same(needle, haystack[i])) {
  1426. if (device_updated(needle, haystack[i]))
  1427. return DEVICE_UPDATED;
  1428. return DEVICE_SAME;
  1429. } else {
  1430. /* Keep offline devices offline */
  1431. if (needle->volume_offline)
  1432. return DEVICE_NOT_FOUND;
  1433. return DEVICE_CHANGED;
  1434. }
  1435. }
  1436. }
  1437. *index = -1;
  1438. return DEVICE_NOT_FOUND;
  1439. }
  1440. static void hpsa_monitor_offline_device(struct ctlr_info *h,
  1441. unsigned char scsi3addr[])
  1442. {
  1443. struct offline_device_entry *device;
  1444. unsigned long flags;
  1445. /* Check to see if device is already on the list */
  1446. spin_lock_irqsave(&h->offline_device_lock, flags);
  1447. list_for_each_entry(device, &h->offline_device_list, offline_list) {
  1448. if (memcmp(device->scsi3addr, scsi3addr,
  1449. sizeof(device->scsi3addr)) == 0) {
  1450. spin_unlock_irqrestore(&h->offline_device_lock, flags);
  1451. return;
  1452. }
  1453. }
  1454. spin_unlock_irqrestore(&h->offline_device_lock, flags);
  1455. /* Device is not on the list, add it. */
  1456. device = kmalloc(sizeof(*device), GFP_KERNEL);
  1457. if (!device)
  1458. return;
  1459. memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr));
  1460. spin_lock_irqsave(&h->offline_device_lock, flags);
  1461. list_add_tail(&device->offline_list, &h->offline_device_list);
  1462. spin_unlock_irqrestore(&h->offline_device_lock, flags);
  1463. }
  1464. /* Print a message explaining various offline volume states */
  1465. static void hpsa_show_volume_status(struct ctlr_info *h,
  1466. struct hpsa_scsi_dev_t *sd)
  1467. {
  1468. if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED)
  1469. dev_info(&h->pdev->dev,
  1470. "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n",
  1471. h->scsi_host->host_no,
  1472. sd->bus, sd->target, sd->lun);
  1473. switch (sd->volume_offline) {
  1474. case HPSA_LV_OK:
  1475. break;
  1476. case HPSA_LV_UNDERGOING_ERASE:
  1477. dev_info(&h->pdev->dev,
  1478. "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n",
  1479. h->scsi_host->host_no,
  1480. sd->bus, sd->target, sd->lun);
  1481. break;
  1482. case HPSA_LV_NOT_AVAILABLE:
  1483. dev_info(&h->pdev->dev,
  1484. "C%d:B%d:T%d:L%d Volume is waiting for transforming volume.\n",
  1485. h->scsi_host->host_no,
  1486. sd->bus, sd->target, sd->lun);
  1487. break;
  1488. case HPSA_LV_UNDERGOING_RPI:
  1489. dev_info(&h->pdev->dev,
  1490. "C%d:B%d:T%d:L%d Volume is undergoing rapid parity init.\n",
  1491. h->scsi_host->host_no,
  1492. sd->bus, sd->target, sd->lun);
  1493. break;
  1494. case HPSA_LV_PENDING_RPI:
  1495. dev_info(&h->pdev->dev,
  1496. "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n",
  1497. h->scsi_host->host_no,
  1498. sd->bus, sd->target, sd->lun);
  1499. break;
  1500. case HPSA_LV_ENCRYPTED_NO_KEY:
  1501. dev_info(&h->pdev->dev,
  1502. "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n",
  1503. h->scsi_host->host_no,
  1504. sd->bus, sd->target, sd->lun);
  1505. break;
  1506. case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
  1507. dev_info(&h->pdev->dev,
  1508. "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n",
  1509. h->scsi_host->host_no,
  1510. sd->bus, sd->target, sd->lun);
  1511. break;
  1512. case HPSA_LV_UNDERGOING_ENCRYPTION:
  1513. dev_info(&h->pdev->dev,
  1514. "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n",
  1515. h->scsi_host->host_no,
  1516. sd->bus, sd->target, sd->lun);
  1517. break;
  1518. case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
  1519. dev_info(&h->pdev->dev,
  1520. "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n",
  1521. h->scsi_host->host_no,
  1522. sd->bus, sd->target, sd->lun);
  1523. break;
  1524. case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
  1525. dev_info(&h->pdev->dev,
  1526. "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n",
  1527. h->scsi_host->host_no,
  1528. sd->bus, sd->target, sd->lun);
  1529. break;
  1530. case HPSA_LV_PENDING_ENCRYPTION:
  1531. dev_info(&h->pdev->dev,
  1532. "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n",
  1533. h->scsi_host->host_no,
  1534. sd->bus, sd->target, sd->lun);
  1535. break;
  1536. case HPSA_LV_PENDING_ENCRYPTION_REKEYING:
  1537. dev_info(&h->pdev->dev,
  1538. "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n",
  1539. h->scsi_host->host_no,
  1540. sd->bus, sd->target, sd->lun);
  1541. break;
  1542. }
  1543. }
  1544. /*
  1545. * Figure the list of physical drive pointers for a logical drive with
  1546. * raid offload configured.
  1547. */
  1548. static void hpsa_figure_phys_disk_ptrs(struct ctlr_info *h,
  1549. struct hpsa_scsi_dev_t *dev[], int ndevices,
  1550. struct hpsa_scsi_dev_t *logical_drive)
  1551. {
  1552. struct raid_map_data *map = &logical_drive->raid_map;
  1553. struct raid_map_disk_data *dd = &map->data[0];
  1554. int i, j;
  1555. int total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
  1556. le16_to_cpu(map->metadata_disks_per_row);
  1557. int nraid_map_entries = le16_to_cpu(map->row_cnt) *
  1558. le16_to_cpu(map->layout_map_count) *
  1559. total_disks_per_row;
  1560. int nphys_disk = le16_to_cpu(map->layout_map_count) *
  1561. total_disks_per_row;
  1562. int qdepth;
  1563. if (nraid_map_entries > RAID_MAP_MAX_ENTRIES)
  1564. nraid_map_entries = RAID_MAP_MAX_ENTRIES;
  1565. logical_drive->nphysical_disks = nraid_map_entries;
  1566. qdepth = 0;
  1567. for (i = 0; i < nraid_map_entries; i++) {
  1568. logical_drive->phys_disk[i] = NULL;
  1569. if (!logical_drive->offload_config)
  1570. continue;
  1571. for (j = 0; j < ndevices; j++) {
  1572. if (dev[j] == NULL)
  1573. continue;
  1574. if (dev[j]->devtype != TYPE_DISK &&
  1575. dev[j]->devtype != TYPE_ZBC)
  1576. continue;
  1577. if (is_logical_device(dev[j]))
  1578. continue;
  1579. if (dev[j]->ioaccel_handle != dd[i].ioaccel_handle)
  1580. continue;
  1581. logical_drive->phys_disk[i] = dev[j];
  1582. if (i < nphys_disk)
  1583. qdepth = min(h->nr_cmds, qdepth +
  1584. logical_drive->phys_disk[i]->queue_depth);
  1585. break;
  1586. }
  1587. /*
  1588. * This can happen if a physical drive is removed and
  1589. * the logical drive is degraded. In that case, the RAID
  1590. * map data will refer to a physical disk which isn't actually
  1591. * present. And in that case offload_enabled should already
  1592. * be 0, but we'll turn it off here just in case
  1593. */
  1594. if (!logical_drive->phys_disk[i]) {
  1595. dev_warn(&h->pdev->dev,
  1596. "%s: [%d:%d:%d:%d] A phys disk component of LV is missing, turning off offload_enabled for LV.\n",
  1597. __func__,
  1598. h->scsi_host->host_no, logical_drive->bus,
  1599. logical_drive->target, logical_drive->lun);
  1600. hpsa_turn_off_ioaccel_for_device(logical_drive);
  1601. logical_drive->queue_depth = 8;
  1602. }
  1603. }
  1604. if (nraid_map_entries)
  1605. /*
  1606. * This is correct for reads, too high for full stripe writes,
  1607. * way too high for partial stripe writes
  1608. */
  1609. logical_drive->queue_depth = qdepth;
  1610. else {
  1611. if (logical_drive->external)
  1612. logical_drive->queue_depth = EXTERNAL_QD;
  1613. else
  1614. logical_drive->queue_depth = h->nr_cmds;
  1615. }
  1616. }
  1617. static void hpsa_update_log_drive_phys_drive_ptrs(struct ctlr_info *h,
  1618. struct hpsa_scsi_dev_t *dev[], int ndevices)
  1619. {
  1620. int i;
  1621. for (i = 0; i < ndevices; i++) {
  1622. if (dev[i] == NULL)
  1623. continue;
  1624. if (dev[i]->devtype != TYPE_DISK &&
  1625. dev[i]->devtype != TYPE_ZBC)
  1626. continue;
  1627. if (!is_logical_device(dev[i]))
  1628. continue;
  1629. /*
  1630. * If offload is currently enabled, the RAID map and
  1631. * phys_disk[] assignment *better* not be changing
  1632. * because we would be changing ioaccel phsy_disk[] pointers
  1633. * on a ioaccel volume processing I/O requests.
  1634. *
  1635. * If an ioaccel volume status changed, initially because it was
  1636. * re-configured and thus underwent a transformation, or
  1637. * a drive failed, we would have received a state change
  1638. * request and ioaccel should have been turned off. When the
  1639. * transformation completes, we get another state change
  1640. * request to turn ioaccel back on. In this case, we need
  1641. * to update the ioaccel information.
  1642. *
  1643. * Thus: If it is not currently enabled, but will be after
  1644. * the scan completes, make sure the ioaccel pointers
  1645. * are up to date.
  1646. */
  1647. if (!dev[i]->offload_enabled && dev[i]->offload_to_be_enabled)
  1648. hpsa_figure_phys_disk_ptrs(h, dev, ndevices, dev[i]);
  1649. }
  1650. }
  1651. static int hpsa_add_device(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
  1652. {
  1653. int rc = 0;
  1654. if (!h->scsi_host)
  1655. return 1;
  1656. if (is_logical_device(device)) /* RAID */
  1657. rc = scsi_add_device(h->scsi_host, device->bus,
  1658. device->target, device->lun);
  1659. else /* HBA */
  1660. rc = hpsa_add_sas_device(h->sas_host, device);
  1661. return rc;
  1662. }
  1663. static int hpsa_find_outstanding_commands_for_dev(struct ctlr_info *h,
  1664. struct hpsa_scsi_dev_t *dev)
  1665. {
  1666. int i;
  1667. int count = 0;
  1668. for (i = 0; i < h->nr_cmds; i++) {
  1669. struct CommandList *c = h->cmd_pool + i;
  1670. int refcount = atomic_inc_return(&c->refcount);
  1671. if (refcount > 1 && hpsa_cmd_dev_match(h, c, dev,
  1672. dev->scsi3addr)) {
  1673. unsigned long flags;
  1674. spin_lock_irqsave(&h->lock, flags); /* Implied MB */
  1675. if (!hpsa_is_cmd_idle(c))
  1676. ++count;
  1677. spin_unlock_irqrestore(&h->lock, flags);
  1678. }
  1679. cmd_free(h, c);
  1680. }
  1681. return count;
  1682. }
  1683. #define NUM_WAIT 20
  1684. static void hpsa_wait_for_outstanding_commands_for_dev(struct ctlr_info *h,
  1685. struct hpsa_scsi_dev_t *device)
  1686. {
  1687. int cmds = 0;
  1688. int waits = 0;
  1689. int num_wait = NUM_WAIT;
  1690. if (device->external)
  1691. num_wait = HPSA_EH_PTRAID_TIMEOUT;
  1692. while (1) {
  1693. cmds = hpsa_find_outstanding_commands_for_dev(h, device);
  1694. if (cmds == 0)
  1695. break;
  1696. if (++waits > num_wait)
  1697. break;
  1698. msleep(1000);
  1699. }
  1700. if (waits > num_wait) {
  1701. dev_warn(&h->pdev->dev,
  1702. "%s: removing device [%d:%d:%d:%d] with %d outstanding commands!\n",
  1703. __func__,
  1704. h->scsi_host->host_no,
  1705. device->bus, device->target, device->lun, cmds);
  1706. }
  1707. }
  1708. static void hpsa_remove_device(struct ctlr_info *h,
  1709. struct hpsa_scsi_dev_t *device)
  1710. {
  1711. struct scsi_device *sdev = NULL;
  1712. if (!h->scsi_host)
  1713. return;
  1714. /*
  1715. * Allow for commands to drain
  1716. */
  1717. device->removed = 1;
  1718. hpsa_wait_for_outstanding_commands_for_dev(h, device);
  1719. if (is_logical_device(device)) { /* RAID */
  1720. sdev = scsi_device_lookup(h->scsi_host, device->bus,
  1721. device->target, device->lun);
  1722. if (sdev) {
  1723. scsi_remove_device(sdev);
  1724. scsi_device_put(sdev);
  1725. } else {
  1726. /*
  1727. * We don't expect to get here. Future commands
  1728. * to this device will get a selection timeout as
  1729. * if the device were gone.
  1730. */
  1731. hpsa_show_dev_msg(KERN_WARNING, h, device,
  1732. "didn't find device for removal.");
  1733. }
  1734. } else { /* HBA */
  1735. hpsa_remove_sas_device(device);
  1736. }
  1737. }
  1738. static void adjust_hpsa_scsi_table(struct ctlr_info *h,
  1739. struct hpsa_scsi_dev_t *sd[], int nsds)
  1740. {
  1741. /* sd contains scsi3 addresses and devtypes, and inquiry
  1742. * data. This function takes what's in sd to be the current
  1743. * reality and updates h->dev[] to reflect that reality.
  1744. */
  1745. int i, entry, device_change, changes = 0;
  1746. struct hpsa_scsi_dev_t *csd;
  1747. unsigned long flags;
  1748. struct hpsa_scsi_dev_t **added, **removed;
  1749. int nadded, nremoved;
  1750. /*
  1751. * A reset can cause a device status to change
  1752. * re-schedule the scan to see what happened.
  1753. */
  1754. spin_lock_irqsave(&h->reset_lock, flags);
  1755. if (h->reset_in_progress) {
  1756. h->drv_req_rescan = 1;
  1757. spin_unlock_irqrestore(&h->reset_lock, flags);
  1758. return;
  1759. }
  1760. spin_unlock_irqrestore(&h->reset_lock, flags);
  1761. added = kcalloc(HPSA_MAX_DEVICES, sizeof(*added), GFP_KERNEL);
  1762. removed = kcalloc(HPSA_MAX_DEVICES, sizeof(*removed), GFP_KERNEL);
  1763. if (!added || !removed) {
  1764. dev_warn(&h->pdev->dev, "out of memory in "
  1765. "adjust_hpsa_scsi_table\n");
  1766. goto free_and_out;
  1767. }
  1768. spin_lock_irqsave(&h->devlock, flags);
  1769. /* find any devices in h->dev[] that are not in
  1770. * sd[] and remove them from h->dev[], and for any
  1771. * devices which have changed, remove the old device
  1772. * info and add the new device info.
  1773. * If minor device attributes change, just update
  1774. * the existing device structure.
  1775. */
  1776. i = 0;
  1777. nremoved = 0;
  1778. nadded = 0;
  1779. while (i < h->ndevices) {
  1780. csd = h->dev[i];
  1781. device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
  1782. if (device_change == DEVICE_NOT_FOUND) {
  1783. changes++;
  1784. hpsa_scsi_remove_entry(h, i, removed, &nremoved);
  1785. continue; /* remove ^^^, hence i not incremented */
  1786. } else if (device_change == DEVICE_CHANGED) {
  1787. changes++;
  1788. hpsa_scsi_replace_entry(h, i, sd[entry],
  1789. added, &nadded, removed, &nremoved);
  1790. /* Set it to NULL to prevent it from being freed
  1791. * at the bottom of hpsa_update_scsi_devices()
  1792. */
  1793. sd[entry] = NULL;
  1794. } else if (device_change == DEVICE_UPDATED) {
  1795. hpsa_scsi_update_entry(h, i, sd[entry]);
  1796. }
  1797. i++;
  1798. }
  1799. /* Now, make sure every device listed in sd[] is also
  1800. * listed in h->dev[], adding them if they aren't found
  1801. */
  1802. for (i = 0; i < nsds; i++) {
  1803. if (!sd[i]) /* if already added above. */
  1804. continue;
  1805. /* Don't add devices which are NOT READY, FORMAT IN PROGRESS
  1806. * as the SCSI mid-layer does not handle such devices well.
  1807. * It relentlessly loops sending TUR at 3Hz, then READ(10)
  1808. * at 160Hz, and prevents the system from coming up.
  1809. */
  1810. if (sd[i]->volume_offline) {
  1811. hpsa_show_volume_status(h, sd[i]);
  1812. hpsa_show_dev_msg(KERN_INFO, h, sd[i], "offline");
  1813. continue;
  1814. }
  1815. device_change = hpsa_scsi_find_entry(sd[i], h->dev,
  1816. h->ndevices, &entry);
  1817. if (device_change == DEVICE_NOT_FOUND) {
  1818. changes++;
  1819. if (hpsa_scsi_add_entry(h, sd[i], added, &nadded) != 0)
  1820. break;
  1821. sd[i] = NULL; /* prevent from being freed later. */
  1822. } else if (device_change == DEVICE_CHANGED) {
  1823. /* should never happen... */
  1824. changes++;
  1825. dev_warn(&h->pdev->dev,
  1826. "device unexpectedly changed.\n");
  1827. /* but if it does happen, we just ignore that device */
  1828. }
  1829. }
  1830. hpsa_update_log_drive_phys_drive_ptrs(h, h->dev, h->ndevices);
  1831. /*
  1832. * Now that h->dev[]->phys_disk[] is coherent, we can enable
  1833. * any logical drives that need it enabled.
  1834. *
  1835. * The raid map should be current by now.
  1836. *
  1837. * We are updating the device list used for I/O requests.
  1838. */
  1839. for (i = 0; i < h->ndevices; i++) {
  1840. if (h->dev[i] == NULL)
  1841. continue;
  1842. h->dev[i]->offload_enabled = h->dev[i]->offload_to_be_enabled;
  1843. }
  1844. spin_unlock_irqrestore(&h->devlock, flags);
  1845. /* Monitor devices which are in one of several NOT READY states to be
  1846. * brought online later. This must be done without holding h->devlock,
  1847. * so don't touch h->dev[]
  1848. */
  1849. for (i = 0; i < nsds; i++) {
  1850. if (!sd[i]) /* if already added above. */
  1851. continue;
  1852. if (sd[i]->volume_offline)
  1853. hpsa_monitor_offline_device(h, sd[i]->scsi3addr);
  1854. }
  1855. /* Don't notify scsi mid layer of any changes the first time through
  1856. * (or if there are no changes) scsi_scan_host will do it later the
  1857. * first time through.
  1858. */
  1859. if (!changes)
  1860. goto free_and_out;
  1861. /* Notify scsi mid layer of any removed devices */
  1862. for (i = 0; i < nremoved; i++) {
  1863. if (removed[i] == NULL)
  1864. continue;
  1865. if (removed[i]->expose_device)
  1866. hpsa_remove_device(h, removed[i]);
  1867. kfree(removed[i]);
  1868. removed[i] = NULL;
  1869. }
  1870. /* Notify scsi mid layer of any added devices */
  1871. for (i = 0; i < nadded; i++) {
  1872. int rc = 0;
  1873. if (added[i] == NULL)
  1874. continue;
  1875. if (!(added[i]->expose_device))
  1876. continue;
  1877. rc = hpsa_add_device(h, added[i]);
  1878. if (!rc)
  1879. continue;
  1880. dev_warn(&h->pdev->dev,
  1881. "addition failed %d, device not added.", rc);
  1882. /* now we have to remove it from h->dev,
  1883. * since it didn't get added to scsi mid layer
  1884. */
  1885. fixup_botched_add(h, added[i]);
  1886. h->drv_req_rescan = 1;
  1887. }
  1888. free_and_out:
  1889. kfree(added);
  1890. kfree(removed);
  1891. }
  1892. /*
  1893. * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
  1894. * Assume's h->devlock is held.
  1895. */
  1896. static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
  1897. int bus, int target, int lun)
  1898. {
  1899. int i;
  1900. struct hpsa_scsi_dev_t *sd;
  1901. for (i = 0; i < h->ndevices; i++) {
  1902. sd = h->dev[i];
  1903. if (sd->bus == bus && sd->target == target && sd->lun == lun)
  1904. return sd;
  1905. }
  1906. return NULL;
  1907. }
  1908. static int hpsa_slave_alloc(struct scsi_device *sdev)
  1909. {
  1910. struct hpsa_scsi_dev_t *sd = NULL;
  1911. unsigned long flags;
  1912. struct ctlr_info *h;
  1913. h = sdev_to_hba(sdev);
  1914. spin_lock_irqsave(&h->devlock, flags);
  1915. if (sdev_channel(sdev) == HPSA_PHYSICAL_DEVICE_BUS) {
  1916. struct scsi_target *starget;
  1917. struct sas_rphy *rphy;
  1918. starget = scsi_target(sdev);
  1919. rphy = target_to_rphy(starget);
  1920. sd = hpsa_find_device_by_sas_rphy(h, rphy);
  1921. if (sd) {
  1922. sd->target = sdev_id(sdev);
  1923. sd->lun = sdev->lun;
  1924. }
  1925. }
  1926. if (!sd)
  1927. sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
  1928. sdev_id(sdev), sdev->lun);
  1929. if (sd && sd->expose_device) {
  1930. atomic_set(&sd->ioaccel_cmds_out, 0);
  1931. sdev->hostdata = sd;
  1932. } else
  1933. sdev->hostdata = NULL;
  1934. spin_unlock_irqrestore(&h->devlock, flags);
  1935. return 0;
  1936. }
  1937. /* configure scsi device based on internal per-device structure */
  1938. #define CTLR_TIMEOUT (120 * HZ)
  1939. static int hpsa_slave_configure(struct scsi_device *sdev)
  1940. {
  1941. struct hpsa_scsi_dev_t *sd;
  1942. int queue_depth;
  1943. sd = sdev->hostdata;
  1944. sdev->no_uld_attach = !sd || !sd->expose_device;
  1945. if (sd) {
  1946. sd->was_removed = 0;
  1947. queue_depth = sd->queue_depth != 0 ?
  1948. sd->queue_depth : sdev->host->can_queue;
  1949. if (sd->external) {
  1950. queue_depth = EXTERNAL_QD;
  1951. sdev->eh_timeout = HPSA_EH_PTRAID_TIMEOUT;
  1952. blk_queue_rq_timeout(sdev->request_queue,
  1953. HPSA_EH_PTRAID_TIMEOUT);
  1954. }
  1955. if (is_hba_lunid(sd->scsi3addr)) {
  1956. sdev->eh_timeout = CTLR_TIMEOUT;
  1957. blk_queue_rq_timeout(sdev->request_queue, CTLR_TIMEOUT);
  1958. }
  1959. } else {
  1960. queue_depth = sdev->host->can_queue;
  1961. }
  1962. scsi_change_queue_depth(sdev, queue_depth);
  1963. return 0;
  1964. }
  1965. static void hpsa_slave_destroy(struct scsi_device *sdev)
  1966. {
  1967. struct hpsa_scsi_dev_t *hdev = NULL;
  1968. hdev = sdev->hostdata;
  1969. if (hdev)
  1970. hdev->was_removed = 1;
  1971. }
  1972. static void hpsa_free_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
  1973. {
  1974. int i;
  1975. if (!h->ioaccel2_cmd_sg_list)
  1976. return;
  1977. for (i = 0; i < h->nr_cmds; i++) {
  1978. kfree(h->ioaccel2_cmd_sg_list[i]);
  1979. h->ioaccel2_cmd_sg_list[i] = NULL;
  1980. }
  1981. kfree(h->ioaccel2_cmd_sg_list);
  1982. h->ioaccel2_cmd_sg_list = NULL;
  1983. }
  1984. static int hpsa_allocate_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
  1985. {
  1986. int i;
  1987. if (h->chainsize <= 0)
  1988. return 0;
  1989. h->ioaccel2_cmd_sg_list =
  1990. kcalloc(h->nr_cmds, sizeof(*h->ioaccel2_cmd_sg_list),
  1991. GFP_KERNEL);
  1992. if (!h->ioaccel2_cmd_sg_list)
  1993. return -ENOMEM;
  1994. for (i = 0; i < h->nr_cmds; i++) {
  1995. h->ioaccel2_cmd_sg_list[i] =
  1996. kmalloc_array(h->maxsgentries,
  1997. sizeof(*h->ioaccel2_cmd_sg_list[i]),
  1998. GFP_KERNEL);
  1999. if (!h->ioaccel2_cmd_sg_list[i])
  2000. goto clean;
  2001. }
  2002. return 0;
  2003. clean:
  2004. hpsa_free_ioaccel2_sg_chain_blocks(h);
  2005. return -ENOMEM;
  2006. }
  2007. static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
  2008. {
  2009. int i;
  2010. if (!h->cmd_sg_list)
  2011. return;
  2012. for (i = 0; i < h->nr_cmds; i++) {
  2013. kfree(h->cmd_sg_list[i]);
  2014. h->cmd_sg_list[i] = NULL;
  2015. }
  2016. kfree(h->cmd_sg_list);
  2017. h->cmd_sg_list = NULL;
  2018. }
  2019. static int hpsa_alloc_sg_chain_blocks(struct ctlr_info *h)
  2020. {
  2021. int i;
  2022. if (h->chainsize <= 0)
  2023. return 0;
  2024. h->cmd_sg_list = kcalloc(h->nr_cmds, sizeof(*h->cmd_sg_list),
  2025. GFP_KERNEL);
  2026. if (!h->cmd_sg_list)
  2027. return -ENOMEM;
  2028. for (i = 0; i < h->nr_cmds; i++) {
  2029. h->cmd_sg_list[i] = kmalloc_array(h->chainsize,
  2030. sizeof(*h->cmd_sg_list[i]),
  2031. GFP_KERNEL);
  2032. if (!h->cmd_sg_list[i])
  2033. goto clean;
  2034. }
  2035. return 0;
  2036. clean:
  2037. hpsa_free_sg_chain_blocks(h);
  2038. return -ENOMEM;
  2039. }
  2040. static int hpsa_map_ioaccel2_sg_chain_block(struct ctlr_info *h,
  2041. struct io_accel2_cmd *cp, struct CommandList *c)
  2042. {
  2043. struct ioaccel2_sg_element *chain_block;
  2044. u64 temp64;
  2045. u32 chain_size;
  2046. chain_block = h->ioaccel2_cmd_sg_list[c->cmdindex];
  2047. chain_size = le32_to_cpu(cp->sg[0].length);
  2048. temp64 = dma_map_single(&h->pdev->dev, chain_block, chain_size,
  2049. DMA_TO_DEVICE);
  2050. if (dma_mapping_error(&h->pdev->dev, temp64)) {
  2051. /* prevent subsequent unmapping */
  2052. cp->sg->address = 0;
  2053. return -1;
  2054. }
  2055. cp->sg->address = cpu_to_le64(temp64);
  2056. return 0;
  2057. }
  2058. static void hpsa_unmap_ioaccel2_sg_chain_block(struct ctlr_info *h,
  2059. struct io_accel2_cmd *cp)
  2060. {
  2061. struct ioaccel2_sg_element *chain_sg;
  2062. u64 temp64;
  2063. u32 chain_size;
  2064. chain_sg = cp->sg;
  2065. temp64 = le64_to_cpu(chain_sg->address);
  2066. chain_size = le32_to_cpu(cp->sg[0].length);
  2067. dma_unmap_single(&h->pdev->dev, temp64, chain_size, DMA_TO_DEVICE);
  2068. }
  2069. static int hpsa_map_sg_chain_block(struct ctlr_info *h,
  2070. struct CommandList *c)
  2071. {
  2072. struct SGDescriptor *chain_sg, *chain_block;
  2073. u64 temp64;
  2074. u32 chain_len;
  2075. chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
  2076. chain_block = h->cmd_sg_list[c->cmdindex];
  2077. chain_sg->Ext = cpu_to_le32(HPSA_SG_CHAIN);
  2078. chain_len = sizeof(*chain_sg) *
  2079. (le16_to_cpu(c->Header.SGTotal) - h->max_cmd_sg_entries);
  2080. chain_sg->Len = cpu_to_le32(chain_len);
  2081. temp64 = dma_map_single(&h->pdev->dev, chain_block, chain_len,
  2082. DMA_TO_DEVICE);
  2083. if (dma_mapping_error(&h->pdev->dev, temp64)) {
  2084. /* prevent subsequent unmapping */
  2085. chain_sg->Addr = cpu_to_le64(0);
  2086. return -1;
  2087. }
  2088. chain_sg->Addr = cpu_to_le64(temp64);
  2089. return 0;
  2090. }
  2091. static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
  2092. struct CommandList *c)
  2093. {
  2094. struct SGDescriptor *chain_sg;
  2095. if (le16_to_cpu(c->Header.SGTotal) <= h->max_cmd_sg_entries)
  2096. return;
  2097. chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
  2098. dma_unmap_single(&h->pdev->dev, le64_to_cpu(chain_sg->Addr),
  2099. le32_to_cpu(chain_sg->Len), DMA_TO_DEVICE);
  2100. }
  2101. /* Decode the various types of errors on ioaccel2 path.
  2102. * Return 1 for any error that should generate a RAID path retry.
  2103. * Return 0 for errors that don't require a RAID path retry.
  2104. */
  2105. static int handle_ioaccel_mode2_error(struct ctlr_info *h,
  2106. struct CommandList *c,
  2107. struct scsi_cmnd *cmd,
  2108. struct io_accel2_cmd *c2,
  2109. struct hpsa_scsi_dev_t *dev)
  2110. {
  2111. int data_len;
  2112. int retry = 0;
  2113. u32 ioaccel2_resid = 0;
  2114. switch (c2->error_data.serv_response) {
  2115. case IOACCEL2_SERV_RESPONSE_COMPLETE:
  2116. switch (c2->error_data.status) {
  2117. case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
  2118. if (cmd)
  2119. cmd->result = 0;
  2120. break;
  2121. case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
  2122. cmd->result |= SAM_STAT_CHECK_CONDITION;
  2123. if (c2->error_data.data_present !=
  2124. IOACCEL2_SENSE_DATA_PRESENT) {
  2125. memset(cmd->sense_buffer, 0,
  2126. SCSI_SENSE_BUFFERSIZE);
  2127. break;
  2128. }
  2129. /* copy the sense data */
  2130. data_len = c2->error_data.sense_data_len;
  2131. if (data_len > SCSI_SENSE_BUFFERSIZE)
  2132. data_len = SCSI_SENSE_BUFFERSIZE;
  2133. if (data_len > sizeof(c2->error_data.sense_data_buff))
  2134. data_len =
  2135. sizeof(c2->error_data.sense_data_buff);
  2136. memcpy(cmd->sense_buffer,
  2137. c2->error_data.sense_data_buff, data_len);
  2138. retry = 1;
  2139. break;
  2140. case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
  2141. retry = 1;
  2142. break;
  2143. case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
  2144. retry = 1;
  2145. break;
  2146. case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
  2147. retry = 1;
  2148. break;
  2149. case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
  2150. retry = 1;
  2151. break;
  2152. default:
  2153. retry = 1;
  2154. break;
  2155. }
  2156. break;
  2157. case IOACCEL2_SERV_RESPONSE_FAILURE:
  2158. switch (c2->error_data.status) {
  2159. case IOACCEL2_STATUS_SR_IO_ERROR:
  2160. case IOACCEL2_STATUS_SR_IO_ABORTED:
  2161. case IOACCEL2_STATUS_SR_OVERRUN:
  2162. retry = 1;
  2163. break;
  2164. case IOACCEL2_STATUS_SR_UNDERRUN:
  2165. cmd->result = (DID_OK << 16); /* host byte */
  2166. ioaccel2_resid = get_unaligned_le32(
  2167. &c2->error_data.resid_cnt[0]);
  2168. scsi_set_resid(cmd, ioaccel2_resid);
  2169. break;
  2170. case IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE:
  2171. case IOACCEL2_STATUS_SR_INVALID_DEVICE:
  2172. case IOACCEL2_STATUS_SR_IOACCEL_DISABLED:
  2173. /*
  2174. * Did an HBA disk disappear? We will eventually
  2175. * get a state change event from the controller but
  2176. * in the meantime, we need to tell the OS that the
  2177. * HBA disk is no longer there and stop I/O
  2178. * from going down. This allows the potential re-insert
  2179. * of the disk to get the same device node.
  2180. */
  2181. if (dev->physical_device && dev->expose_device) {
  2182. cmd->result = DID_NO_CONNECT << 16;
  2183. dev->removed = 1;
  2184. h->drv_req_rescan = 1;
  2185. dev_warn(&h->pdev->dev,
  2186. "%s: device is gone!\n", __func__);
  2187. } else
  2188. /*
  2189. * Retry by sending down the RAID path.
  2190. * We will get an event from ctlr to
  2191. * trigger rescan regardless.
  2192. */
  2193. retry = 1;
  2194. break;
  2195. default:
  2196. retry = 1;
  2197. }
  2198. break;
  2199. case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
  2200. break;
  2201. case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
  2202. break;
  2203. case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
  2204. retry = 1;
  2205. break;
  2206. case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
  2207. break;
  2208. default:
  2209. retry = 1;
  2210. break;
  2211. }
  2212. if (dev->in_reset)
  2213. retry = 0;
  2214. return retry; /* retry on raid path? */
  2215. }
  2216. static void hpsa_cmd_resolve_events(struct ctlr_info *h,
  2217. struct CommandList *c)
  2218. {
  2219. struct hpsa_scsi_dev_t *dev = c->device;
  2220. /*
  2221. * Reset c->scsi_cmd here so that the reset handler will know
  2222. * this command has completed. Then, check to see if the handler is
  2223. * waiting for this command, and, if so, wake it.
  2224. */
  2225. c->scsi_cmd = SCSI_CMD_IDLE;
  2226. mb(); /* Declare command idle before checking for pending events. */
  2227. if (dev) {
  2228. atomic_dec(&dev->commands_outstanding);
  2229. if (dev->in_reset &&
  2230. atomic_read(&dev->commands_outstanding) <= 0)
  2231. wake_up_all(&h->event_sync_wait_queue);
  2232. }
  2233. }
  2234. static void hpsa_cmd_resolve_and_free(struct ctlr_info *h,
  2235. struct CommandList *c)
  2236. {
  2237. hpsa_cmd_resolve_events(h, c);
  2238. cmd_tagged_free(h, c);
  2239. }
  2240. static void hpsa_cmd_free_and_done(struct ctlr_info *h,
  2241. struct CommandList *c, struct scsi_cmnd *cmd)
  2242. {
  2243. hpsa_cmd_resolve_and_free(h, c);
  2244. if (cmd)
  2245. scsi_done(cmd);
  2246. }
  2247. static void hpsa_retry_cmd(struct ctlr_info *h, struct CommandList *c)
  2248. {
  2249. INIT_WORK(&c->work, hpsa_command_resubmit_worker);
  2250. queue_work_on(raw_smp_processor_id(), h->resubmit_wq, &c->work);
  2251. }
  2252. static void process_ioaccel2_completion(struct ctlr_info *h,
  2253. struct CommandList *c, struct scsi_cmnd *cmd,
  2254. struct hpsa_scsi_dev_t *dev)
  2255. {
  2256. struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
  2257. /* check for good status */
  2258. if (likely(c2->error_data.serv_response == 0 &&
  2259. c2->error_data.status == 0)) {
  2260. cmd->result = 0;
  2261. return hpsa_cmd_free_and_done(h, c, cmd);
  2262. }
  2263. /*
  2264. * Any RAID offload error results in retry which will use
  2265. * the normal I/O path so the controller can handle whatever is
  2266. * wrong.
  2267. */
  2268. if (is_logical_device(dev) &&
  2269. c2->error_data.serv_response ==
  2270. IOACCEL2_SERV_RESPONSE_FAILURE) {
  2271. if (c2->error_data.status ==
  2272. IOACCEL2_STATUS_SR_IOACCEL_DISABLED) {
  2273. hpsa_turn_off_ioaccel_for_device(dev);
  2274. }
  2275. if (dev->in_reset) {
  2276. cmd->result = DID_RESET << 16;
  2277. return hpsa_cmd_free_and_done(h, c, cmd);
  2278. }
  2279. return hpsa_retry_cmd(h, c);
  2280. }
  2281. if (handle_ioaccel_mode2_error(h, c, cmd, c2, dev))
  2282. return hpsa_retry_cmd(h, c);
  2283. return hpsa_cmd_free_and_done(h, c, cmd);
  2284. }
  2285. /* Returns 0 on success, < 0 otherwise. */
  2286. static int hpsa_evaluate_tmf_status(struct ctlr_info *h,
  2287. struct CommandList *cp)
  2288. {
  2289. u8 tmf_status = cp->err_info->ScsiStatus;
  2290. switch (tmf_status) {
  2291. case CISS_TMF_COMPLETE:
  2292. /*
  2293. * CISS_TMF_COMPLETE never happens, instead,
  2294. * ei->CommandStatus == 0 for this case.
  2295. */
  2296. case CISS_TMF_SUCCESS:
  2297. return 0;
  2298. case CISS_TMF_INVALID_FRAME:
  2299. case CISS_TMF_NOT_SUPPORTED:
  2300. case CISS_TMF_FAILED:
  2301. case CISS_TMF_WRONG_LUN:
  2302. case CISS_TMF_OVERLAPPED_TAG:
  2303. break;
  2304. default:
  2305. dev_warn(&h->pdev->dev, "Unknown TMF status: 0x%02x\n",
  2306. tmf_status);
  2307. break;
  2308. }
  2309. return -tmf_status;
  2310. }
  2311. static void complete_scsi_command(struct CommandList *cp)
  2312. {
  2313. struct scsi_cmnd *cmd;
  2314. struct ctlr_info *h;
  2315. struct ErrorInfo *ei;
  2316. struct hpsa_scsi_dev_t *dev;
  2317. struct io_accel2_cmd *c2;
  2318. u8 sense_key;
  2319. u8 asc; /* additional sense code */
  2320. u8 ascq; /* additional sense code qualifier */
  2321. unsigned long sense_data_size;
  2322. ei = cp->err_info;
  2323. cmd = cp->scsi_cmd;
  2324. h = cp->h;
  2325. if (!cmd->device) {
  2326. cmd->result = DID_NO_CONNECT << 16;
  2327. return hpsa_cmd_free_and_done(h, cp, cmd);
  2328. }
  2329. dev = cmd->device->hostdata;
  2330. if (!dev) {
  2331. cmd->result = DID_NO_CONNECT << 16;
  2332. return hpsa_cmd_free_and_done(h, cp, cmd);
  2333. }
  2334. c2 = &h->ioaccel2_cmd_pool[cp->cmdindex];
  2335. scsi_dma_unmap(cmd); /* undo the DMA mappings */
  2336. if ((cp->cmd_type == CMD_SCSI) &&
  2337. (le16_to_cpu(cp->Header.SGTotal) > h->max_cmd_sg_entries))
  2338. hpsa_unmap_sg_chain_block(h, cp);
  2339. if ((cp->cmd_type == CMD_IOACCEL2) &&
  2340. (c2->sg[0].chain_indicator == IOACCEL2_CHAIN))
  2341. hpsa_unmap_ioaccel2_sg_chain_block(h, c2);
  2342. cmd->result = (DID_OK << 16); /* host byte */
  2343. /* SCSI command has already been cleaned up in SML */
  2344. if (dev->was_removed) {
  2345. hpsa_cmd_resolve_and_free(h, cp);
  2346. return;
  2347. }
  2348. if (cp->cmd_type == CMD_IOACCEL2 || cp->cmd_type == CMD_IOACCEL1) {
  2349. if (dev->physical_device && dev->expose_device &&
  2350. dev->removed) {
  2351. cmd->result = DID_NO_CONNECT << 16;
  2352. return hpsa_cmd_free_and_done(h, cp, cmd);
  2353. }
  2354. if (likely(cp->phys_disk != NULL))
  2355. atomic_dec(&cp->phys_disk->ioaccel_cmds_out);
  2356. }
  2357. /*
  2358. * We check for lockup status here as it may be set for
  2359. * CMD_SCSI, CMD_IOACCEL1 and CMD_IOACCEL2 commands by
  2360. * fail_all_oustanding_cmds()
  2361. */
  2362. if (unlikely(ei->CommandStatus == CMD_CTLR_LOCKUP)) {
  2363. /* DID_NO_CONNECT will prevent a retry */
  2364. cmd->result = DID_NO_CONNECT << 16;
  2365. return hpsa_cmd_free_and_done(h, cp, cmd);
  2366. }
  2367. if (cp->cmd_type == CMD_IOACCEL2)
  2368. return process_ioaccel2_completion(h, cp, cmd, dev);
  2369. scsi_set_resid(cmd, ei->ResidualCnt);
  2370. if (ei->CommandStatus == 0)
  2371. return hpsa_cmd_free_and_done(h, cp, cmd);
  2372. /* For I/O accelerator commands, copy over some fields to the normal
  2373. * CISS header used below for error handling.
  2374. */
  2375. if (cp->cmd_type == CMD_IOACCEL1) {
  2376. struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
  2377. cp->Header.SGList = scsi_sg_count(cmd);
  2378. cp->Header.SGTotal = cpu_to_le16(cp->Header.SGList);
  2379. cp->Request.CDBLen = le16_to_cpu(c->io_flags) &
  2380. IOACCEL1_IOFLAGS_CDBLEN_MASK;
  2381. cp->Header.tag = c->tag;
  2382. memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
  2383. memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
  2384. /* Any RAID offload error results in retry which will use
  2385. * the normal I/O path so the controller can handle whatever's
  2386. * wrong.
  2387. */
  2388. if (is_logical_device(dev)) {
  2389. if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
  2390. dev->offload_enabled = 0;
  2391. return hpsa_retry_cmd(h, cp);
  2392. }
  2393. }
  2394. /* an error has occurred */
  2395. switch (ei->CommandStatus) {
  2396. case CMD_TARGET_STATUS:
  2397. cmd->result |= ei->ScsiStatus;
  2398. /* copy the sense data */
  2399. if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
  2400. sense_data_size = SCSI_SENSE_BUFFERSIZE;
  2401. else
  2402. sense_data_size = sizeof(ei->SenseInfo);
  2403. if (ei->SenseLen < sense_data_size)
  2404. sense_data_size = ei->SenseLen;
  2405. memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
  2406. if (ei->ScsiStatus)
  2407. decode_sense_data(ei->SenseInfo, sense_data_size,
  2408. &sense_key, &asc, &ascq);
  2409. if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
  2410. switch (sense_key) {
  2411. case ABORTED_COMMAND:
  2412. cmd->result |= DID_SOFT_ERROR << 16;
  2413. break;
  2414. case UNIT_ATTENTION:
  2415. if (asc == 0x3F && ascq == 0x0E)
  2416. h->drv_req_rescan = 1;
  2417. break;
  2418. case ILLEGAL_REQUEST:
  2419. if (asc == 0x25 && ascq == 0x00) {
  2420. dev->removed = 1;
  2421. cmd->result = DID_NO_CONNECT << 16;
  2422. }
  2423. break;
  2424. }
  2425. break;
  2426. }
  2427. /* Problem was not a check condition
  2428. * Pass it up to the upper layers...
  2429. */
  2430. if (ei->ScsiStatus) {
  2431. dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
  2432. "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
  2433. "Returning result: 0x%x\n",
  2434. cp, ei->ScsiStatus,
  2435. sense_key, asc, ascq,
  2436. cmd->result);
  2437. } else { /* scsi status is zero??? How??? */
  2438. dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
  2439. "Returning no connection.\n", cp),
  2440. /* Ordinarily, this case should never happen,
  2441. * but there is a bug in some released firmware
  2442. * revisions that allows it to happen if, for
  2443. * example, a 4100 backplane loses power and
  2444. * the tape drive is in it. We assume that
  2445. * it's a fatal error of some kind because we
  2446. * can't show that it wasn't. We will make it
  2447. * look like selection timeout since that is
  2448. * the most common reason for this to occur,
  2449. * and it's severe enough.
  2450. */
  2451. cmd->result = DID_NO_CONNECT << 16;
  2452. }
  2453. break;
  2454. case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
  2455. break;
  2456. case CMD_DATA_OVERRUN:
  2457. dev_warn(&h->pdev->dev,
  2458. "CDB %16phN data overrun\n", cp->Request.CDB);
  2459. break;
  2460. case CMD_INVALID: {
  2461. /* print_bytes(cp, sizeof(*cp), 1, 0);
  2462. print_cmd(cp); */
  2463. /* We get CMD_INVALID if you address a non-existent device
  2464. * instead of a selection timeout (no response). You will
  2465. * see this if you yank out a drive, then try to access it.
  2466. * This is kind of a shame because it means that any other
  2467. * CMD_INVALID (e.g. driver bug) will get interpreted as a
  2468. * missing target. */
  2469. cmd->result = DID_NO_CONNECT << 16;
  2470. }
  2471. break;
  2472. case CMD_PROTOCOL_ERR:
  2473. cmd->result = DID_ERROR << 16;
  2474. dev_warn(&h->pdev->dev, "CDB %16phN : protocol error\n",
  2475. cp->Request.CDB);
  2476. break;
  2477. case CMD_HARDWARE_ERR:
  2478. cmd->result = DID_ERROR << 16;
  2479. dev_warn(&h->pdev->dev, "CDB %16phN : hardware error\n",
  2480. cp->Request.CDB);
  2481. break;
  2482. case CMD_CONNECTION_LOST:
  2483. cmd->result = DID_ERROR << 16;
  2484. dev_warn(&h->pdev->dev, "CDB %16phN : connection lost\n",
  2485. cp->Request.CDB);
  2486. break;
  2487. case CMD_ABORTED:
  2488. cmd->result = DID_ABORT << 16;
  2489. break;
  2490. case CMD_ABORT_FAILED:
  2491. cmd->result = DID_ERROR << 16;
  2492. dev_warn(&h->pdev->dev, "CDB %16phN : abort failed\n",
  2493. cp->Request.CDB);
  2494. break;
  2495. case CMD_UNSOLICITED_ABORT:
  2496. cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
  2497. dev_warn(&h->pdev->dev, "CDB %16phN : unsolicited abort\n",
  2498. cp->Request.CDB);
  2499. break;
  2500. case CMD_TIMEOUT:
  2501. cmd->result = DID_TIME_OUT << 16;
  2502. dev_warn(&h->pdev->dev, "CDB %16phN timed out\n",
  2503. cp->Request.CDB);
  2504. break;
  2505. case CMD_UNABORTABLE:
  2506. cmd->result = DID_ERROR << 16;
  2507. dev_warn(&h->pdev->dev, "Command unabortable\n");
  2508. break;
  2509. case CMD_TMF_STATUS:
  2510. if (hpsa_evaluate_tmf_status(h, cp)) /* TMF failed? */
  2511. cmd->result = DID_ERROR << 16;
  2512. break;
  2513. case CMD_IOACCEL_DISABLED:
  2514. /* This only handles the direct pass-through case since RAID
  2515. * offload is handled above. Just attempt a retry.
  2516. */
  2517. cmd->result = DID_SOFT_ERROR << 16;
  2518. dev_warn(&h->pdev->dev,
  2519. "cp %p had HP SSD Smart Path error\n", cp);
  2520. break;
  2521. default:
  2522. cmd->result = DID_ERROR << 16;
  2523. dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
  2524. cp, ei->CommandStatus);
  2525. }
  2526. return hpsa_cmd_free_and_done(h, cp, cmd);
  2527. }
  2528. static void hpsa_pci_unmap(struct pci_dev *pdev, struct CommandList *c,
  2529. int sg_used, enum dma_data_direction data_direction)
  2530. {
  2531. int i;
  2532. for (i = 0; i < sg_used; i++)
  2533. dma_unmap_single(&pdev->dev, le64_to_cpu(c->SG[i].Addr),
  2534. le32_to_cpu(c->SG[i].Len),
  2535. data_direction);
  2536. }
  2537. static int hpsa_map_one(struct pci_dev *pdev,
  2538. struct CommandList *cp,
  2539. unsigned char *buf,
  2540. size_t buflen,
  2541. enum dma_data_direction data_direction)
  2542. {
  2543. u64 addr64;
  2544. if (buflen == 0 || data_direction == DMA_NONE) {
  2545. cp->Header.SGList = 0;
  2546. cp->Header.SGTotal = cpu_to_le16(0);
  2547. return 0;
  2548. }
  2549. addr64 = dma_map_single(&pdev->dev, buf, buflen, data_direction);
  2550. if (dma_mapping_error(&pdev->dev, addr64)) {
  2551. /* Prevent subsequent unmap of something never mapped */
  2552. cp->Header.SGList = 0;
  2553. cp->Header.SGTotal = cpu_to_le16(0);
  2554. return -1;
  2555. }
  2556. cp->SG[0].Addr = cpu_to_le64(addr64);
  2557. cp->SG[0].Len = cpu_to_le32(buflen);
  2558. cp->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* we are not chaining */
  2559. cp->Header.SGList = 1; /* no. SGs contig in this cmd */
  2560. cp->Header.SGTotal = cpu_to_le16(1); /* total sgs in cmd list */
  2561. return 0;
  2562. }
  2563. #define NO_TIMEOUT ((unsigned long) -1)
  2564. #define DEFAULT_TIMEOUT 30000 /* milliseconds */
  2565. static int hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
  2566. struct CommandList *c, int reply_queue, unsigned long timeout_msecs)
  2567. {
  2568. DECLARE_COMPLETION_ONSTACK(wait);
  2569. c->waiting = &wait;
  2570. __enqueue_cmd_and_start_io(h, c, reply_queue);
  2571. if (timeout_msecs == NO_TIMEOUT) {
  2572. /* TODO: get rid of this no-timeout thing */
  2573. wait_for_completion_io(&wait);
  2574. return IO_OK;
  2575. }
  2576. if (!wait_for_completion_io_timeout(&wait,
  2577. msecs_to_jiffies(timeout_msecs))) {
  2578. dev_warn(&h->pdev->dev, "Command timed out.\n");
  2579. return -ETIMEDOUT;
  2580. }
  2581. return IO_OK;
  2582. }
  2583. static int hpsa_scsi_do_simple_cmd(struct ctlr_info *h, struct CommandList *c,
  2584. int reply_queue, unsigned long timeout_msecs)
  2585. {
  2586. if (unlikely(lockup_detected(h))) {
  2587. c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
  2588. return IO_OK;
  2589. }
  2590. return hpsa_scsi_do_simple_cmd_core(h, c, reply_queue, timeout_msecs);
  2591. }
  2592. static u32 lockup_detected(struct ctlr_info *h)
  2593. {
  2594. int cpu;
  2595. u32 rc, *lockup_detected;
  2596. cpu = get_cpu();
  2597. lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
  2598. rc = *lockup_detected;
  2599. put_cpu();
  2600. return rc;
  2601. }
  2602. #define MAX_DRIVER_CMD_RETRIES 25
  2603. static int hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
  2604. struct CommandList *c, enum dma_data_direction data_direction,
  2605. unsigned long timeout_msecs)
  2606. {
  2607. int backoff_time = 10, retry_count = 0;
  2608. int rc;
  2609. do {
  2610. memset(c->err_info, 0, sizeof(*c->err_info));
  2611. rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
  2612. timeout_msecs);
  2613. if (rc)
  2614. break;
  2615. retry_count++;
  2616. if (retry_count > 3) {
  2617. msleep(backoff_time);
  2618. if (backoff_time < 1000)
  2619. backoff_time *= 2;
  2620. }
  2621. } while ((check_for_unit_attention(h, c) ||
  2622. check_for_busy(h, c)) &&
  2623. retry_count <= MAX_DRIVER_CMD_RETRIES);
  2624. hpsa_pci_unmap(h->pdev, c, 1, data_direction);
  2625. if (retry_count > MAX_DRIVER_CMD_RETRIES)
  2626. rc = -EIO;
  2627. return rc;
  2628. }
  2629. static void hpsa_print_cmd(struct ctlr_info *h, char *txt,
  2630. struct CommandList *c)
  2631. {
  2632. const u8 *cdb = c->Request.CDB;
  2633. const u8 *lun = c->Header.LUN.LunAddrBytes;
  2634. dev_warn(&h->pdev->dev, "%s: LUN:%8phN CDB:%16phN\n",
  2635. txt, lun, cdb);
  2636. }
  2637. static void hpsa_scsi_interpret_error(struct ctlr_info *h,
  2638. struct CommandList *cp)
  2639. {
  2640. const struct ErrorInfo *ei = cp->err_info;
  2641. struct device *d = &cp->h->pdev->dev;
  2642. u8 sense_key, asc, ascq;
  2643. int sense_len;
  2644. switch (ei->CommandStatus) {
  2645. case CMD_TARGET_STATUS:
  2646. if (ei->SenseLen > sizeof(ei->SenseInfo))
  2647. sense_len = sizeof(ei->SenseInfo);
  2648. else
  2649. sense_len = ei->SenseLen;
  2650. decode_sense_data(ei->SenseInfo, sense_len,
  2651. &sense_key, &asc, &ascq);
  2652. hpsa_print_cmd(h, "SCSI status", cp);
  2653. if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION)
  2654. dev_warn(d, "SCSI Status = 02, Sense key = 0x%02x, ASC = 0x%02x, ASCQ = 0x%02x\n",
  2655. sense_key, asc, ascq);
  2656. else
  2657. dev_warn(d, "SCSI Status = 0x%02x\n", ei->ScsiStatus);
  2658. if (ei->ScsiStatus == 0)
  2659. dev_warn(d, "SCSI status is abnormally zero. "
  2660. "(probably indicates selection timeout "
  2661. "reported incorrectly due to a known "
  2662. "firmware bug, circa July, 2001.)\n");
  2663. break;
  2664. case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
  2665. break;
  2666. case CMD_DATA_OVERRUN:
  2667. hpsa_print_cmd(h, "overrun condition", cp);
  2668. break;
  2669. case CMD_INVALID: {
  2670. /* controller unfortunately reports SCSI passthru's
  2671. * to non-existent targets as invalid commands.
  2672. */
  2673. hpsa_print_cmd(h, "invalid command", cp);
  2674. dev_warn(d, "probably means device no longer present\n");
  2675. }
  2676. break;
  2677. case CMD_PROTOCOL_ERR:
  2678. hpsa_print_cmd(h, "protocol error", cp);
  2679. break;
  2680. case CMD_HARDWARE_ERR:
  2681. hpsa_print_cmd(h, "hardware error", cp);
  2682. break;
  2683. case CMD_CONNECTION_LOST:
  2684. hpsa_print_cmd(h, "connection lost", cp);
  2685. break;
  2686. case CMD_ABORTED:
  2687. hpsa_print_cmd(h, "aborted", cp);
  2688. break;
  2689. case CMD_ABORT_FAILED:
  2690. hpsa_print_cmd(h, "abort failed", cp);
  2691. break;
  2692. case CMD_UNSOLICITED_ABORT:
  2693. hpsa_print_cmd(h, "unsolicited abort", cp);
  2694. break;
  2695. case CMD_TIMEOUT:
  2696. hpsa_print_cmd(h, "timed out", cp);
  2697. break;
  2698. case CMD_UNABORTABLE:
  2699. hpsa_print_cmd(h, "unabortable", cp);
  2700. break;
  2701. case CMD_CTLR_LOCKUP:
  2702. hpsa_print_cmd(h, "controller lockup detected", cp);
  2703. break;
  2704. default:
  2705. hpsa_print_cmd(h, "unknown status", cp);
  2706. dev_warn(d, "Unknown command status %x\n",
  2707. ei->CommandStatus);
  2708. }
  2709. }
  2710. static int hpsa_do_receive_diagnostic(struct ctlr_info *h, u8 *scsi3addr,
  2711. u8 page, u8 *buf, size_t bufsize)
  2712. {
  2713. int rc = IO_OK;
  2714. struct CommandList *c;
  2715. struct ErrorInfo *ei;
  2716. c = cmd_alloc(h);
  2717. if (fill_cmd(c, RECEIVE_DIAGNOSTIC, h, buf, bufsize,
  2718. page, scsi3addr, TYPE_CMD)) {
  2719. rc = -1;
  2720. goto out;
  2721. }
  2722. rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE,
  2723. NO_TIMEOUT);
  2724. if (rc)
  2725. goto out;
  2726. ei = c->err_info;
  2727. if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
  2728. hpsa_scsi_interpret_error(h, c);
  2729. rc = -1;
  2730. }
  2731. out:
  2732. cmd_free(h, c);
  2733. return rc;
  2734. }
  2735. static u64 hpsa_get_enclosure_logical_identifier(struct ctlr_info *h,
  2736. u8 *scsi3addr)
  2737. {
  2738. u8 *buf;
  2739. u64 sa = 0;
  2740. int rc = 0;
  2741. buf = kzalloc(1024, GFP_KERNEL);
  2742. if (!buf)
  2743. return 0;
  2744. rc = hpsa_do_receive_diagnostic(h, scsi3addr, RECEIVE_DIAGNOSTIC,
  2745. buf, 1024);
  2746. if (rc)
  2747. goto out;
  2748. sa = get_unaligned_be64(buf+12);
  2749. out:
  2750. kfree(buf);
  2751. return sa;
  2752. }
  2753. static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
  2754. u16 page, unsigned char *buf,
  2755. unsigned char bufsize)
  2756. {
  2757. int rc = IO_OK;
  2758. struct CommandList *c;
  2759. struct ErrorInfo *ei;
  2760. c = cmd_alloc(h);
  2761. if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
  2762. page, scsi3addr, TYPE_CMD)) {
  2763. rc = -1;
  2764. goto out;
  2765. }
  2766. rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE,
  2767. NO_TIMEOUT);
  2768. if (rc)
  2769. goto out;
  2770. ei = c->err_info;
  2771. if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
  2772. hpsa_scsi_interpret_error(h, c);
  2773. rc = -1;
  2774. }
  2775. out:
  2776. cmd_free(h, c);
  2777. return rc;
  2778. }
  2779. static int hpsa_send_reset(struct ctlr_info *h, struct hpsa_scsi_dev_t *dev,
  2780. u8 reset_type, int reply_queue)
  2781. {
  2782. int rc = IO_OK;
  2783. struct CommandList *c;
  2784. struct ErrorInfo *ei;
  2785. c = cmd_alloc(h);
  2786. c->device = dev;
  2787. /* fill_cmd can't fail here, no data buffer to map. */
  2788. (void) fill_cmd(c, reset_type, h, NULL, 0, 0, dev->scsi3addr, TYPE_MSG);
  2789. rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
  2790. if (rc) {
  2791. dev_warn(&h->pdev->dev, "Failed to send reset command\n");
  2792. goto out;
  2793. }
  2794. /* no unmap needed here because no data xfer. */
  2795. ei = c->err_info;
  2796. if (ei->CommandStatus != 0) {
  2797. hpsa_scsi_interpret_error(h, c);
  2798. rc = -1;
  2799. }
  2800. out:
  2801. cmd_free(h, c);
  2802. return rc;
  2803. }
  2804. static bool hpsa_cmd_dev_match(struct ctlr_info *h, struct CommandList *c,
  2805. struct hpsa_scsi_dev_t *dev,
  2806. unsigned char *scsi3addr)
  2807. {
  2808. int i;
  2809. bool match = false;
  2810. struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
  2811. struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2;
  2812. if (hpsa_is_cmd_idle(c))
  2813. return false;
  2814. switch (c->cmd_type) {
  2815. case CMD_SCSI:
  2816. case CMD_IOCTL_PEND:
  2817. match = !memcmp(scsi3addr, &c->Header.LUN.LunAddrBytes,
  2818. sizeof(c->Header.LUN.LunAddrBytes));
  2819. break;
  2820. case CMD_IOACCEL1:
  2821. case CMD_IOACCEL2:
  2822. if (c->phys_disk == dev) {
  2823. /* HBA mode match */
  2824. match = true;
  2825. } else {
  2826. /* Possible RAID mode -- check each phys dev. */
  2827. /* FIXME: Do we need to take out a lock here? If
  2828. * so, we could just call hpsa_get_pdisk_of_ioaccel2()
  2829. * instead. */
  2830. for (i = 0; i < dev->nphysical_disks && !match; i++) {
  2831. /* FIXME: an alternate test might be
  2832. *
  2833. * match = dev->phys_disk[i]->ioaccel_handle
  2834. * == c2->scsi_nexus; */
  2835. match = dev->phys_disk[i] == c->phys_disk;
  2836. }
  2837. }
  2838. break;
  2839. case IOACCEL2_TMF:
  2840. for (i = 0; i < dev->nphysical_disks && !match; i++) {
  2841. match = dev->phys_disk[i]->ioaccel_handle ==
  2842. le32_to_cpu(ac->it_nexus);
  2843. }
  2844. break;
  2845. case 0: /* The command is in the middle of being initialized. */
  2846. match = false;
  2847. break;
  2848. default:
  2849. dev_err(&h->pdev->dev, "unexpected cmd_type: %d\n",
  2850. c->cmd_type);
  2851. BUG();
  2852. }
  2853. return match;
  2854. }
  2855. static int hpsa_do_reset(struct ctlr_info *h, struct hpsa_scsi_dev_t *dev,
  2856. u8 reset_type, int reply_queue)
  2857. {
  2858. int rc = 0;
  2859. /* We can really only handle one reset at a time */
  2860. if (mutex_lock_interruptible(&h->reset_mutex) == -EINTR) {
  2861. dev_warn(&h->pdev->dev, "concurrent reset wait interrupted.\n");
  2862. return -EINTR;
  2863. }
  2864. rc = hpsa_send_reset(h, dev, reset_type, reply_queue);
  2865. if (!rc) {
  2866. /* incremented by sending the reset request */
  2867. atomic_dec(&dev->commands_outstanding);
  2868. wait_event(h->event_sync_wait_queue,
  2869. atomic_read(&dev->commands_outstanding) <= 0 ||
  2870. lockup_detected(h));
  2871. }
  2872. if (unlikely(lockup_detected(h))) {
  2873. dev_warn(&h->pdev->dev,
  2874. "Controller lockup detected during reset wait\n");
  2875. rc = -ENODEV;
  2876. }
  2877. if (!rc)
  2878. rc = wait_for_device_to_become_ready(h, dev->scsi3addr, 0);
  2879. mutex_unlock(&h->reset_mutex);
  2880. return rc;
  2881. }
  2882. static void hpsa_get_raid_level(struct ctlr_info *h,
  2883. unsigned char *scsi3addr, unsigned char *raid_level)
  2884. {
  2885. int rc;
  2886. unsigned char *buf;
  2887. *raid_level = RAID_UNKNOWN;
  2888. buf = kzalloc(64, GFP_KERNEL);
  2889. if (!buf)
  2890. return;
  2891. if (!hpsa_vpd_page_supported(h, scsi3addr,
  2892. HPSA_VPD_LV_DEVICE_GEOMETRY))
  2893. goto exit;
  2894. rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE |
  2895. HPSA_VPD_LV_DEVICE_GEOMETRY, buf, 64);
  2896. if (rc == 0)
  2897. *raid_level = buf[8];
  2898. if (*raid_level > RAID_UNKNOWN)
  2899. *raid_level = RAID_UNKNOWN;
  2900. exit:
  2901. kfree(buf);
  2902. return;
  2903. }
  2904. #define HPSA_MAP_DEBUG
  2905. #ifdef HPSA_MAP_DEBUG
  2906. static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
  2907. struct raid_map_data *map_buff)
  2908. {
  2909. struct raid_map_disk_data *dd = &map_buff->data[0];
  2910. int map, row, col;
  2911. u16 map_cnt, row_cnt, disks_per_row;
  2912. if (rc != 0)
  2913. return;
  2914. /* Show details only if debugging has been activated. */
  2915. if (h->raid_offload_debug < 2)
  2916. return;
  2917. dev_info(&h->pdev->dev, "structure_size = %u\n",
  2918. le32_to_cpu(map_buff->structure_size));
  2919. dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
  2920. le32_to_cpu(map_buff->volume_blk_size));
  2921. dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
  2922. le64_to_cpu(map_buff->volume_blk_cnt));
  2923. dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
  2924. map_buff->phys_blk_shift);
  2925. dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
  2926. map_buff->parity_rotation_shift);
  2927. dev_info(&h->pdev->dev, "strip_size = %u\n",
  2928. le16_to_cpu(map_buff->strip_size));
  2929. dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
  2930. le64_to_cpu(map_buff->disk_starting_blk));
  2931. dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
  2932. le64_to_cpu(map_buff->disk_blk_cnt));
  2933. dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
  2934. le16_to_cpu(map_buff->data_disks_per_row));
  2935. dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
  2936. le16_to_cpu(map_buff->metadata_disks_per_row));
  2937. dev_info(&h->pdev->dev, "row_cnt = %u\n",
  2938. le16_to_cpu(map_buff->row_cnt));
  2939. dev_info(&h->pdev->dev, "layout_map_count = %u\n",
  2940. le16_to_cpu(map_buff->layout_map_count));
  2941. dev_info(&h->pdev->dev, "flags = 0x%x\n",
  2942. le16_to_cpu(map_buff->flags));
  2943. dev_info(&h->pdev->dev, "encryption = %s\n",
  2944. le16_to_cpu(map_buff->flags) &
  2945. RAID_MAP_FLAG_ENCRYPT_ON ? "ON" : "OFF");
  2946. dev_info(&h->pdev->dev, "dekindex = %u\n",
  2947. le16_to_cpu(map_buff->dekindex));
  2948. map_cnt = le16_to_cpu(map_buff->layout_map_count);
  2949. for (map = 0; map < map_cnt; map++) {
  2950. dev_info(&h->pdev->dev, "Map%u:\n", map);
  2951. row_cnt = le16_to_cpu(map_buff->row_cnt);
  2952. for (row = 0; row < row_cnt; row++) {
  2953. dev_info(&h->pdev->dev, " Row%u:\n", row);
  2954. disks_per_row =
  2955. le16_to_cpu(map_buff->data_disks_per_row);
  2956. for (col = 0; col < disks_per_row; col++, dd++)
  2957. dev_info(&h->pdev->dev,
  2958. " D%02u: h=0x%04x xor=%u,%u\n",
  2959. col, dd->ioaccel_handle,
  2960. dd->xor_mult[0], dd->xor_mult[1]);
  2961. disks_per_row =
  2962. le16_to_cpu(map_buff->metadata_disks_per_row);
  2963. for (col = 0; col < disks_per_row; col++, dd++)
  2964. dev_info(&h->pdev->dev,
  2965. " M%02u: h=0x%04x xor=%u,%u\n",
  2966. col, dd->ioaccel_handle,
  2967. dd->xor_mult[0], dd->xor_mult[1]);
  2968. }
  2969. }
  2970. }
  2971. #else
  2972. static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
  2973. __attribute__((unused)) int rc,
  2974. __attribute__((unused)) struct raid_map_data *map_buff)
  2975. {
  2976. }
  2977. #endif
  2978. static int hpsa_get_raid_map(struct ctlr_info *h,
  2979. unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
  2980. {
  2981. int rc = 0;
  2982. struct CommandList *c;
  2983. struct ErrorInfo *ei;
  2984. c = cmd_alloc(h);
  2985. if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
  2986. sizeof(this_device->raid_map), 0,
  2987. scsi3addr, TYPE_CMD)) {
  2988. dev_warn(&h->pdev->dev, "hpsa_get_raid_map fill_cmd failed\n");
  2989. cmd_free(h, c);
  2990. return -1;
  2991. }
  2992. rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE,
  2993. NO_TIMEOUT);
  2994. if (rc)
  2995. goto out;
  2996. ei = c->err_info;
  2997. if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
  2998. hpsa_scsi_interpret_error(h, c);
  2999. rc = -1;
  3000. goto out;
  3001. }
  3002. cmd_free(h, c);
  3003. /* @todo in the future, dynamically allocate RAID map memory */
  3004. if (le32_to_cpu(this_device->raid_map.structure_size) >
  3005. sizeof(this_device->raid_map)) {
  3006. dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
  3007. rc = -1;
  3008. }
  3009. hpsa_debug_map_buff(h, rc, &this_device->raid_map);
  3010. return rc;
  3011. out:
  3012. cmd_free(h, c);
  3013. return rc;
  3014. }
  3015. static int hpsa_bmic_sense_subsystem_information(struct ctlr_info *h,
  3016. unsigned char scsi3addr[], u16 bmic_device_index,
  3017. struct bmic_sense_subsystem_info *buf, size_t bufsize)
  3018. {
  3019. int rc = IO_OK;
  3020. struct CommandList *c;
  3021. struct ErrorInfo *ei;
  3022. c = cmd_alloc(h);
  3023. rc = fill_cmd(c, BMIC_SENSE_SUBSYSTEM_INFORMATION, h, buf, bufsize,
  3024. 0, RAID_CTLR_LUNID, TYPE_CMD);
  3025. if (rc)
  3026. goto out;
  3027. c->Request.CDB[2] = bmic_device_index & 0xff;
  3028. c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff;
  3029. rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE,
  3030. NO_TIMEOUT);
  3031. if (rc)
  3032. goto out;
  3033. ei = c->err_info;
  3034. if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
  3035. hpsa_scsi_interpret_error(h, c);
  3036. rc = -1;
  3037. }
  3038. out:
  3039. cmd_free(h, c);
  3040. return rc;
  3041. }
  3042. static int hpsa_bmic_id_controller(struct ctlr_info *h,
  3043. struct bmic_identify_controller *buf, size_t bufsize)
  3044. {
  3045. int rc = IO_OK;
  3046. struct CommandList *c;
  3047. struct ErrorInfo *ei;
  3048. c = cmd_alloc(h);
  3049. rc = fill_cmd(c, BMIC_IDENTIFY_CONTROLLER, h, buf, bufsize,
  3050. 0, RAID_CTLR_LUNID, TYPE_CMD);
  3051. if (rc)
  3052. goto out;
  3053. rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE,
  3054. NO_TIMEOUT);
  3055. if (rc)
  3056. goto out;
  3057. ei = c->err_info;
  3058. if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
  3059. hpsa_scsi_interpret_error(h, c);
  3060. rc = -1;
  3061. }
  3062. out:
  3063. cmd_free(h, c);
  3064. return rc;
  3065. }
  3066. static int hpsa_bmic_id_physical_device(struct ctlr_info *h,
  3067. unsigned char scsi3addr[], u16 bmic_device_index,
  3068. struct bmic_identify_physical_device *buf, size_t bufsize)
  3069. {
  3070. int rc = IO_OK;
  3071. struct CommandList *c;
  3072. struct ErrorInfo *ei;
  3073. c = cmd_alloc(h);
  3074. rc = fill_cmd(c, BMIC_IDENTIFY_PHYSICAL_DEVICE, h, buf, bufsize,
  3075. 0, RAID_CTLR_LUNID, TYPE_CMD);
  3076. if (rc)
  3077. goto out;
  3078. c->Request.CDB[2] = bmic_device_index & 0xff;
  3079. c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff;
  3080. hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE,
  3081. NO_TIMEOUT);
  3082. ei = c->err_info;
  3083. if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
  3084. hpsa_scsi_interpret_error(h, c);
  3085. rc = -1;
  3086. }
  3087. out:
  3088. cmd_free(h, c);
  3089. return rc;
  3090. }
  3091. /*
  3092. * get enclosure information
  3093. * struct ReportExtendedLUNdata *rlep - Used for BMIC drive number
  3094. * struct hpsa_scsi_dev_t *encl_dev - device entry for enclosure
  3095. * Uses id_physical_device to determine the box_index.
  3096. */
  3097. static void hpsa_get_enclosure_info(struct ctlr_info *h,
  3098. unsigned char *scsi3addr,
  3099. struct ReportExtendedLUNdata *rlep, int rle_index,
  3100. struct hpsa_scsi_dev_t *encl_dev)
  3101. {
  3102. int rc = -1;
  3103. struct CommandList *c = NULL;
  3104. struct ErrorInfo *ei = NULL;
  3105. struct bmic_sense_storage_box_params *bssbp = NULL;
  3106. struct bmic_identify_physical_device *id_phys = NULL;
  3107. struct ext_report_lun_entry *rle;
  3108. u16 bmic_device_index = 0;
  3109. if (rle_index < 0 || rle_index >= HPSA_MAX_PHYS_LUN)
  3110. return;
  3111. rle = &rlep->LUN[rle_index];
  3112. encl_dev->eli =
  3113. hpsa_get_enclosure_logical_identifier(h, scsi3addr);
  3114. bmic_device_index = GET_BMIC_DRIVE_NUMBER(&rle->lunid[0]);
  3115. if (encl_dev->target == -1 || encl_dev->lun == -1) {
  3116. rc = IO_OK;
  3117. goto out;
  3118. }
  3119. if (bmic_device_index == 0xFF00 || MASKED_DEVICE(&rle->lunid[0])) {
  3120. rc = IO_OK;
  3121. goto out;
  3122. }
  3123. bssbp = kzalloc(sizeof(*bssbp), GFP_KERNEL);
  3124. if (!bssbp)
  3125. goto out;
  3126. id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL);
  3127. if (!id_phys)
  3128. goto out;
  3129. rc = hpsa_bmic_id_physical_device(h, scsi3addr, bmic_device_index,
  3130. id_phys, sizeof(*id_phys));
  3131. if (rc) {
  3132. dev_warn(&h->pdev->dev, "%s: id_phys failed %d bdi[0x%x]\n",
  3133. __func__, encl_dev->external, bmic_device_index);
  3134. goto out;
  3135. }
  3136. c = cmd_alloc(h);
  3137. rc = fill_cmd(c, BMIC_SENSE_STORAGE_BOX_PARAMS, h, bssbp,
  3138. sizeof(*bssbp), 0, RAID_CTLR_LUNID, TYPE_CMD);
  3139. if (rc)
  3140. goto out;
  3141. if (id_phys->phys_connector[1] == 'E')
  3142. c->Request.CDB[5] = id_phys->box_index;
  3143. else
  3144. c->Request.CDB[5] = 0;
  3145. rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE,
  3146. NO_TIMEOUT);
  3147. if (rc)
  3148. goto out;
  3149. ei = c->err_info;
  3150. if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
  3151. rc = -1;
  3152. goto out;
  3153. }
  3154. encl_dev->box[id_phys->active_path_number] = bssbp->phys_box_on_port;
  3155. memcpy(&encl_dev->phys_connector[id_phys->active_path_number],
  3156. bssbp->phys_connector, sizeof(bssbp->phys_connector));
  3157. rc = IO_OK;
  3158. out:
  3159. kfree(bssbp);
  3160. kfree(id_phys);
  3161. if (c)
  3162. cmd_free(h, c);
  3163. if (rc != IO_OK)
  3164. hpsa_show_dev_msg(KERN_INFO, h, encl_dev,
  3165. "Error, could not get enclosure information");
  3166. }
  3167. static u64 hpsa_get_sas_address_from_report_physical(struct ctlr_info *h,
  3168. unsigned char *scsi3addr)
  3169. {
  3170. struct ReportExtendedLUNdata *physdev;
  3171. u32 nphysicals;
  3172. u64 sa = 0;
  3173. int i;
  3174. physdev = kzalloc(sizeof(*physdev), GFP_KERNEL);
  3175. if (!physdev)
  3176. return 0;
  3177. if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) {
  3178. dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
  3179. kfree(physdev);
  3180. return 0;
  3181. }
  3182. nphysicals = get_unaligned_be32(physdev->LUNListLength) / 24;
  3183. for (i = 0; i < nphysicals; i++)
  3184. if (!memcmp(&physdev->LUN[i].lunid[0], scsi3addr, 8)) {
  3185. sa = get_unaligned_be64(&physdev->LUN[i].wwid[0]);
  3186. break;
  3187. }
  3188. kfree(physdev);
  3189. return sa;
  3190. }
  3191. static void hpsa_get_sas_address(struct ctlr_info *h, unsigned char *scsi3addr,
  3192. struct hpsa_scsi_dev_t *dev)
  3193. {
  3194. int rc;
  3195. u64 sa = 0;
  3196. if (is_hba_lunid(scsi3addr)) {
  3197. struct bmic_sense_subsystem_info *ssi;
  3198. ssi = kzalloc(sizeof(*ssi), GFP_KERNEL);
  3199. if (!ssi)
  3200. return;
  3201. rc = hpsa_bmic_sense_subsystem_information(h,
  3202. scsi3addr, 0, ssi, sizeof(*ssi));
  3203. if (rc == 0) {
  3204. sa = get_unaligned_be64(ssi->primary_world_wide_id);
  3205. h->sas_address = sa;
  3206. }
  3207. kfree(ssi);
  3208. } else
  3209. sa = hpsa_get_sas_address_from_report_physical(h, scsi3addr);
  3210. dev->sas_address = sa;
  3211. }
  3212. static void hpsa_ext_ctrl_present(struct ctlr_info *h,
  3213. struct ReportExtendedLUNdata *physdev)
  3214. {
  3215. u32 nphysicals;
  3216. int i;
  3217. if (h->discovery_polling)
  3218. return;
  3219. nphysicals = (get_unaligned_be32(physdev->LUNListLength) / 24) + 1;
  3220. for (i = 0; i < nphysicals; i++) {
  3221. if (physdev->LUN[i].device_type ==
  3222. BMIC_DEVICE_TYPE_CONTROLLER
  3223. && !is_hba_lunid(physdev->LUN[i].lunid)) {
  3224. dev_info(&h->pdev->dev,
  3225. "External controller present, activate discovery polling and disable rld caching\n");
  3226. hpsa_disable_rld_caching(h);
  3227. h->discovery_polling = 1;
  3228. break;
  3229. }
  3230. }
  3231. }
  3232. /* Get a device id from inquiry page 0x83 */
  3233. static bool hpsa_vpd_page_supported(struct ctlr_info *h,
  3234. unsigned char scsi3addr[], u8 page)
  3235. {
  3236. int rc;
  3237. int i;
  3238. int pages;
  3239. unsigned char *buf, bufsize;
  3240. buf = kzalloc(256, GFP_KERNEL);
  3241. if (!buf)
  3242. return false;
  3243. /* Get the size of the page list first */
  3244. rc = hpsa_scsi_do_inquiry(h, scsi3addr,
  3245. VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
  3246. buf, HPSA_VPD_HEADER_SZ);
  3247. if (rc != 0)
  3248. goto exit_unsupported;
  3249. pages = buf[3];
  3250. if ((pages + HPSA_VPD_HEADER_SZ) <= 255)
  3251. bufsize = pages + HPSA_VPD_HEADER_SZ;
  3252. else
  3253. bufsize = 255;
  3254. /* Get the whole VPD page list */
  3255. rc = hpsa_scsi_do_inquiry(h, scsi3addr,
  3256. VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
  3257. buf, bufsize);
  3258. if (rc != 0)
  3259. goto exit_unsupported;
  3260. pages = buf[3];
  3261. for (i = 1; i <= pages; i++)
  3262. if (buf[3 + i] == page)
  3263. goto exit_supported;
  3264. exit_unsupported:
  3265. kfree(buf);
  3266. return false;
  3267. exit_supported:
  3268. kfree(buf);
  3269. return true;
  3270. }
  3271. /*
  3272. * Called during a scan operation.
  3273. * Sets ioaccel status on the new device list, not the existing device list
  3274. *
  3275. * The device list used during I/O will be updated later in
  3276. * adjust_hpsa_scsi_table.
  3277. */
  3278. static void hpsa_get_ioaccel_status(struct ctlr_info *h,
  3279. unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
  3280. {
  3281. int rc;
  3282. unsigned char *buf;
  3283. u8 ioaccel_status;
  3284. this_device->offload_config = 0;
  3285. this_device->offload_enabled = 0;
  3286. this_device->offload_to_be_enabled = 0;
  3287. buf = kzalloc(64, GFP_KERNEL);
  3288. if (!buf)
  3289. return;
  3290. if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS))
  3291. goto out;
  3292. rc = hpsa_scsi_do_inquiry(h, scsi3addr,
  3293. VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
  3294. if (rc != 0)
  3295. goto out;
  3296. #define IOACCEL_STATUS_BYTE 4
  3297. #define OFFLOAD_CONFIGURED_BIT 0x01
  3298. #define OFFLOAD_ENABLED_BIT 0x02
  3299. ioaccel_status = buf[IOACCEL_STATUS_BYTE];
  3300. this_device->offload_config =
  3301. !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
  3302. if (this_device->offload_config) {
  3303. bool offload_enabled =
  3304. !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
  3305. /*
  3306. * Check to see if offload can be enabled.
  3307. */
  3308. if (offload_enabled) {
  3309. rc = hpsa_get_raid_map(h, scsi3addr, this_device);
  3310. if (rc) /* could not load raid_map */
  3311. goto out;
  3312. this_device->offload_to_be_enabled = 1;
  3313. }
  3314. }
  3315. out:
  3316. kfree(buf);
  3317. return;
  3318. }
  3319. /* Get the device id from inquiry page 0x83 */
  3320. static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
  3321. unsigned char *device_id, int index, int buflen)
  3322. {
  3323. int rc;
  3324. unsigned char *buf;
  3325. /* Does controller have VPD for device id? */
  3326. if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_DEVICE_ID))
  3327. return 1; /* not supported */
  3328. buf = kzalloc(64, GFP_KERNEL);
  3329. if (!buf)
  3330. return -ENOMEM;
  3331. rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE |
  3332. HPSA_VPD_LV_DEVICE_ID, buf, 64);
  3333. if (rc == 0) {
  3334. if (buflen > 16)
  3335. buflen = 16;
  3336. memcpy(device_id, &buf[8], buflen);
  3337. }
  3338. kfree(buf);
  3339. return rc; /*0 - got id, otherwise, didn't */
  3340. }
  3341. static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
  3342. void *buf, int bufsize,
  3343. int extended_response)
  3344. {
  3345. int rc = IO_OK;
  3346. struct CommandList *c;
  3347. unsigned char scsi3addr[8];
  3348. struct ErrorInfo *ei;
  3349. c = cmd_alloc(h);
  3350. /* address the controller */
  3351. memset(scsi3addr, 0, sizeof(scsi3addr));
  3352. if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
  3353. buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
  3354. rc = -EAGAIN;
  3355. goto out;
  3356. }
  3357. if (extended_response)
  3358. c->Request.CDB[1] = extended_response;
  3359. rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE,
  3360. NO_TIMEOUT);
  3361. if (rc)
  3362. goto out;
  3363. ei = c->err_info;
  3364. if (ei->CommandStatus != 0 &&
  3365. ei->CommandStatus != CMD_DATA_UNDERRUN) {
  3366. hpsa_scsi_interpret_error(h, c);
  3367. rc = -EIO;
  3368. } else {
  3369. struct ReportLUNdata *rld = buf;
  3370. if (rld->extended_response_flag != extended_response) {
  3371. if (!h->legacy_board) {
  3372. dev_err(&h->pdev->dev,
  3373. "report luns requested format %u, got %u\n",
  3374. extended_response,
  3375. rld->extended_response_flag);
  3376. rc = -EINVAL;
  3377. } else
  3378. rc = -EOPNOTSUPP;
  3379. }
  3380. }
  3381. out:
  3382. cmd_free(h, c);
  3383. return rc;
  3384. }
  3385. static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
  3386. struct ReportExtendedLUNdata *buf, int bufsize)
  3387. {
  3388. int rc;
  3389. struct ReportLUNdata *lbuf;
  3390. rc = hpsa_scsi_do_report_luns(h, 0, buf, bufsize,
  3391. HPSA_REPORT_PHYS_EXTENDED);
  3392. if (!rc || rc != -EOPNOTSUPP)
  3393. return rc;
  3394. /* REPORT PHYS EXTENDED is not supported */
  3395. lbuf = kzalloc(sizeof(*lbuf), GFP_KERNEL);
  3396. if (!lbuf)
  3397. return -ENOMEM;
  3398. rc = hpsa_scsi_do_report_luns(h, 0, lbuf, sizeof(*lbuf), 0);
  3399. if (!rc) {
  3400. int i;
  3401. u32 nphys;
  3402. /* Copy ReportLUNdata header */
  3403. memcpy(buf, lbuf, 8);
  3404. nphys = be32_to_cpu(*((__be32 *)lbuf->LUNListLength)) / 8;
  3405. for (i = 0; i < nphys; i++)
  3406. memcpy(buf->LUN[i].lunid, lbuf->LUN[i], 8);
  3407. }
  3408. kfree(lbuf);
  3409. return rc;
  3410. }
  3411. static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
  3412. struct ReportLUNdata *buf, int bufsize)
  3413. {
  3414. return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
  3415. }
  3416. static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
  3417. int bus, int target, int lun)
  3418. {
  3419. device->bus = bus;
  3420. device->target = target;
  3421. device->lun = lun;
  3422. }
  3423. /* Use VPD inquiry to get details of volume status */
  3424. static int hpsa_get_volume_status(struct ctlr_info *h,
  3425. unsigned char scsi3addr[])
  3426. {
  3427. int rc;
  3428. int status;
  3429. int size;
  3430. unsigned char *buf;
  3431. buf = kzalloc(64, GFP_KERNEL);
  3432. if (!buf)
  3433. return HPSA_VPD_LV_STATUS_UNSUPPORTED;
  3434. /* Does controller have VPD for logical volume status? */
  3435. if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS))
  3436. goto exit_failed;
  3437. /* Get the size of the VPD return buffer */
  3438. rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
  3439. buf, HPSA_VPD_HEADER_SZ);
  3440. if (rc != 0)
  3441. goto exit_failed;
  3442. size = buf[3];
  3443. /* Now get the whole VPD buffer */
  3444. rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
  3445. buf, size + HPSA_VPD_HEADER_SZ);
  3446. if (rc != 0)
  3447. goto exit_failed;
  3448. status = buf[4]; /* status byte */
  3449. kfree(buf);
  3450. return status;
  3451. exit_failed:
  3452. kfree(buf);
  3453. return HPSA_VPD_LV_STATUS_UNSUPPORTED;
  3454. }
  3455. /* Determine offline status of a volume.
  3456. * Return either:
  3457. * 0 (not offline)
  3458. * 0xff (offline for unknown reasons)
  3459. * # (integer code indicating one of several NOT READY states
  3460. * describing why a volume is to be kept offline)
  3461. */
  3462. static unsigned char hpsa_volume_offline(struct ctlr_info *h,
  3463. unsigned char scsi3addr[])
  3464. {
  3465. struct CommandList *c;
  3466. unsigned char *sense;
  3467. u8 sense_key, asc, ascq;
  3468. int sense_len;
  3469. int rc, ldstat = 0;
  3470. #define ASC_LUN_NOT_READY 0x04
  3471. #define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04
  3472. #define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02
  3473. c = cmd_alloc(h);
  3474. (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD);
  3475. rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
  3476. NO_TIMEOUT);
  3477. if (rc) {
  3478. cmd_free(h, c);
  3479. return HPSA_VPD_LV_STATUS_UNSUPPORTED;
  3480. }
  3481. sense = c->err_info->SenseInfo;
  3482. if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
  3483. sense_len = sizeof(c->err_info->SenseInfo);
  3484. else
  3485. sense_len = c->err_info->SenseLen;
  3486. decode_sense_data(sense, sense_len, &sense_key, &asc, &ascq);
  3487. cmd_free(h, c);
  3488. /* Determine the reason for not ready state */
  3489. ldstat = hpsa_get_volume_status(h, scsi3addr);
  3490. /* Keep volume offline in certain cases: */
  3491. switch (ldstat) {
  3492. case HPSA_LV_FAILED:
  3493. case HPSA_LV_UNDERGOING_ERASE:
  3494. case HPSA_LV_NOT_AVAILABLE:
  3495. case HPSA_LV_UNDERGOING_RPI:
  3496. case HPSA_LV_PENDING_RPI:
  3497. case HPSA_LV_ENCRYPTED_NO_KEY:
  3498. case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
  3499. case HPSA_LV_UNDERGOING_ENCRYPTION:
  3500. case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
  3501. case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
  3502. return ldstat;
  3503. case HPSA_VPD_LV_STATUS_UNSUPPORTED:
  3504. /* If VPD status page isn't available,
  3505. * use ASC/ASCQ to determine state
  3506. */
  3507. if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) ||
  3508. (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ))
  3509. return ldstat;
  3510. break;
  3511. default:
  3512. break;
  3513. }
  3514. return HPSA_LV_OK;
  3515. }
  3516. static int hpsa_update_device_info(struct ctlr_info *h,
  3517. unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
  3518. unsigned char *is_OBDR_device)
  3519. {
  3520. #define OBDR_SIG_OFFSET 43
  3521. #define OBDR_TAPE_SIG "$DR-10"
  3522. #define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
  3523. #define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
  3524. unsigned char *inq_buff;
  3525. unsigned char *obdr_sig;
  3526. int rc = 0;
  3527. inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
  3528. if (!inq_buff) {
  3529. rc = -ENOMEM;
  3530. goto bail_out;
  3531. }
  3532. /* Do an inquiry to the device to see what it is. */
  3533. if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
  3534. (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
  3535. dev_err(&h->pdev->dev,
  3536. "%s: inquiry failed, device will be skipped.\n",
  3537. __func__);
  3538. rc = HPSA_INQUIRY_FAILED;
  3539. goto bail_out;
  3540. }
  3541. scsi_sanitize_inquiry_string(&inq_buff[8], 8);
  3542. scsi_sanitize_inquiry_string(&inq_buff[16], 16);
  3543. this_device->devtype = (inq_buff[0] & 0x1f);
  3544. memcpy(this_device->scsi3addr, scsi3addr, 8);
  3545. memcpy(this_device->vendor, &inq_buff[8],
  3546. sizeof(this_device->vendor));
  3547. memcpy(this_device->model, &inq_buff[16],
  3548. sizeof(this_device->model));
  3549. this_device->rev = inq_buff[2];
  3550. memset(this_device->device_id, 0,
  3551. sizeof(this_device->device_id));
  3552. if (hpsa_get_device_id(h, scsi3addr, this_device->device_id, 8,
  3553. sizeof(this_device->device_id)) < 0) {
  3554. dev_err(&h->pdev->dev,
  3555. "hpsa%d: %s: can't get device id for [%d:%d:%d:%d]\t%s\t%.16s\n",
  3556. h->ctlr, __func__,
  3557. h->scsi_host->host_no,
  3558. this_device->bus, this_device->target,
  3559. this_device->lun,
  3560. scsi_device_type(this_device->devtype),
  3561. this_device->model);
  3562. rc = HPSA_LV_FAILED;
  3563. goto bail_out;
  3564. }
  3565. if ((this_device->devtype == TYPE_DISK ||
  3566. this_device->devtype == TYPE_ZBC) &&
  3567. is_logical_dev_addr_mode(scsi3addr)) {
  3568. unsigned char volume_offline;
  3569. hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
  3570. if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
  3571. hpsa_get_ioaccel_status(h, scsi3addr, this_device);
  3572. volume_offline = hpsa_volume_offline(h, scsi3addr);
  3573. if (volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED &&
  3574. h->legacy_board) {
  3575. /*
  3576. * Legacy boards might not support volume status
  3577. */
  3578. dev_info(&h->pdev->dev,
  3579. "C0:T%d:L%d Volume status not available, assuming online.\n",
  3580. this_device->target, this_device->lun);
  3581. volume_offline = 0;
  3582. }
  3583. this_device->volume_offline = volume_offline;
  3584. if (volume_offline == HPSA_LV_FAILED) {
  3585. rc = HPSA_LV_FAILED;
  3586. dev_err(&h->pdev->dev,
  3587. "%s: LV failed, device will be skipped.\n",
  3588. __func__);
  3589. goto bail_out;
  3590. }
  3591. } else {
  3592. this_device->raid_level = RAID_UNKNOWN;
  3593. this_device->offload_config = 0;
  3594. hpsa_turn_off_ioaccel_for_device(this_device);
  3595. this_device->hba_ioaccel_enabled = 0;
  3596. this_device->volume_offline = 0;
  3597. this_device->queue_depth = h->nr_cmds;
  3598. }
  3599. if (this_device->external)
  3600. this_device->queue_depth = EXTERNAL_QD;
  3601. if (is_OBDR_device) {
  3602. /* See if this is a One-Button-Disaster-Recovery device
  3603. * by looking for "$DR-10" at offset 43 in inquiry data.
  3604. */
  3605. obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
  3606. *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
  3607. strncmp(obdr_sig, OBDR_TAPE_SIG,
  3608. OBDR_SIG_LEN) == 0);
  3609. }
  3610. kfree(inq_buff);
  3611. return 0;
  3612. bail_out:
  3613. kfree(inq_buff);
  3614. return rc;
  3615. }
  3616. /*
  3617. * Helper function to assign bus, target, lun mapping of devices.
  3618. * Logical drive target and lun are assigned at this time, but
  3619. * physical device lun and target assignment are deferred (assigned
  3620. * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
  3621. */
  3622. static void figure_bus_target_lun(struct ctlr_info *h,
  3623. u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
  3624. {
  3625. u32 lunid = get_unaligned_le32(lunaddrbytes);
  3626. if (!is_logical_dev_addr_mode(lunaddrbytes)) {
  3627. /* physical device, target and lun filled in later */
  3628. if (is_hba_lunid(lunaddrbytes)) {
  3629. int bus = HPSA_HBA_BUS;
  3630. if (!device->rev)
  3631. bus = HPSA_LEGACY_HBA_BUS;
  3632. hpsa_set_bus_target_lun(device,
  3633. bus, 0, lunid & 0x3fff);
  3634. } else
  3635. /* defer target, lun assignment for physical devices */
  3636. hpsa_set_bus_target_lun(device,
  3637. HPSA_PHYSICAL_DEVICE_BUS, -1, -1);
  3638. return;
  3639. }
  3640. /* It's a logical device */
  3641. if (device->external) {
  3642. hpsa_set_bus_target_lun(device,
  3643. HPSA_EXTERNAL_RAID_VOLUME_BUS, (lunid >> 16) & 0x3fff,
  3644. lunid & 0x00ff);
  3645. return;
  3646. }
  3647. hpsa_set_bus_target_lun(device, HPSA_RAID_VOLUME_BUS,
  3648. 0, lunid & 0x3fff);
  3649. }
  3650. static int figure_external_status(struct ctlr_info *h, int raid_ctlr_position,
  3651. int i, int nphysicals, int nlocal_logicals)
  3652. {
  3653. /* In report logicals, local logicals are listed first,
  3654. * then any externals.
  3655. */
  3656. int logicals_start = nphysicals + (raid_ctlr_position == 0);
  3657. if (i == raid_ctlr_position)
  3658. return 0;
  3659. if (i < logicals_start)
  3660. return 0;
  3661. /* i is in logicals range, but still within local logicals */
  3662. if ((i - nphysicals - (raid_ctlr_position == 0)) < nlocal_logicals)
  3663. return 0;
  3664. return 1; /* it's an external lun */
  3665. }
  3666. /*
  3667. * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
  3668. * logdev. The number of luns in physdev and logdev are returned in
  3669. * *nphysicals and *nlogicals, respectively.
  3670. * Returns 0 on success, -1 otherwise.
  3671. */
  3672. static int hpsa_gather_lun_info(struct ctlr_info *h,
  3673. struct ReportExtendedLUNdata *physdev, u32 *nphysicals,
  3674. struct ReportLUNdata *logdev, u32 *nlogicals)
  3675. {
  3676. if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) {
  3677. dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
  3678. return -1;
  3679. }
  3680. *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) / 24;
  3681. if (*nphysicals > HPSA_MAX_PHYS_LUN) {
  3682. dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded. %d LUNs ignored.\n",
  3683. HPSA_MAX_PHYS_LUN, *nphysicals - HPSA_MAX_PHYS_LUN);
  3684. *nphysicals = HPSA_MAX_PHYS_LUN;
  3685. }
  3686. if (hpsa_scsi_do_report_log_luns(h, logdev, sizeof(*logdev))) {
  3687. dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
  3688. return -1;
  3689. }
  3690. *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
  3691. /* Reject Logicals in excess of our max capability. */
  3692. if (*nlogicals > HPSA_MAX_LUN) {
  3693. dev_warn(&h->pdev->dev,
  3694. "maximum logical LUNs (%d) exceeded. "
  3695. "%d LUNs ignored.\n", HPSA_MAX_LUN,
  3696. *nlogicals - HPSA_MAX_LUN);
  3697. *nlogicals = HPSA_MAX_LUN;
  3698. }
  3699. if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
  3700. dev_warn(&h->pdev->dev,
  3701. "maximum logical + physical LUNs (%d) exceeded. "
  3702. "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
  3703. *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
  3704. *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
  3705. }
  3706. return 0;
  3707. }
  3708. static u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position,
  3709. int i, int nphysicals, int nlogicals,
  3710. struct ReportExtendedLUNdata *physdev_list,
  3711. struct ReportLUNdata *logdev_list)
  3712. {
  3713. /* Helper function, figure out where the LUN ID info is coming from
  3714. * given index i, lists of physical and logical devices, where in
  3715. * the list the raid controller is supposed to appear (first or last)
  3716. */
  3717. int logicals_start = nphysicals + (raid_ctlr_position == 0);
  3718. int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
  3719. if (i == raid_ctlr_position)
  3720. return RAID_CTLR_LUNID;
  3721. if (i < logicals_start)
  3722. return &physdev_list->LUN[i -
  3723. (raid_ctlr_position == 0)].lunid[0];
  3724. if (i < last_device)
  3725. return &logdev_list->LUN[i - nphysicals -
  3726. (raid_ctlr_position == 0)][0];
  3727. BUG();
  3728. return NULL;
  3729. }
  3730. /* get physical drive ioaccel handle and queue depth */
  3731. static void hpsa_get_ioaccel_drive_info(struct ctlr_info *h,
  3732. struct hpsa_scsi_dev_t *dev,
  3733. struct ReportExtendedLUNdata *rlep, int rle_index,
  3734. struct bmic_identify_physical_device *id_phys)
  3735. {
  3736. int rc;
  3737. struct ext_report_lun_entry *rle;
  3738. if (rle_index < 0 || rle_index >= HPSA_MAX_PHYS_LUN)
  3739. return;
  3740. rle = &rlep->LUN[rle_index];
  3741. dev->ioaccel_handle = rle->ioaccel_handle;
  3742. if ((rle->device_flags & 0x08) && dev->ioaccel_handle)
  3743. dev->hba_ioaccel_enabled = 1;
  3744. memset(id_phys, 0, sizeof(*id_phys));
  3745. rc = hpsa_bmic_id_physical_device(h, &rle->lunid[0],
  3746. GET_BMIC_DRIVE_NUMBER(&rle->lunid[0]), id_phys,
  3747. sizeof(*id_phys));
  3748. if (!rc)
  3749. /* Reserve space for FW operations */
  3750. #define DRIVE_CMDS_RESERVED_FOR_FW 2
  3751. #define DRIVE_QUEUE_DEPTH 7
  3752. dev->queue_depth =
  3753. le16_to_cpu(id_phys->current_queue_depth_limit) -
  3754. DRIVE_CMDS_RESERVED_FOR_FW;
  3755. else
  3756. dev->queue_depth = DRIVE_QUEUE_DEPTH; /* conservative */
  3757. }
  3758. static void hpsa_get_path_info(struct hpsa_scsi_dev_t *this_device,
  3759. struct ReportExtendedLUNdata *rlep, int rle_index,
  3760. struct bmic_identify_physical_device *id_phys)
  3761. {
  3762. struct ext_report_lun_entry *rle;
  3763. if (rle_index < 0 || rle_index >= HPSA_MAX_PHYS_LUN)
  3764. return;
  3765. rle = &rlep->LUN[rle_index];
  3766. if ((rle->device_flags & 0x08) && this_device->ioaccel_handle)
  3767. this_device->hba_ioaccel_enabled = 1;
  3768. memcpy(&this_device->active_path_index,
  3769. &id_phys->active_path_number,
  3770. sizeof(this_device->active_path_index));
  3771. memcpy(&this_device->path_map,
  3772. &id_phys->redundant_path_present_map,
  3773. sizeof(this_device->path_map));
  3774. memcpy(&this_device->box,
  3775. &id_phys->alternate_paths_phys_box_on_port,
  3776. sizeof(this_device->box));
  3777. memcpy(&this_device->phys_connector,
  3778. &id_phys->alternate_paths_phys_connector,
  3779. sizeof(this_device->phys_connector));
  3780. memcpy(&this_device->bay,
  3781. &id_phys->phys_bay_in_box,
  3782. sizeof(this_device->bay));
  3783. }
  3784. /* get number of local logical disks. */
  3785. static int hpsa_set_local_logical_count(struct ctlr_info *h,
  3786. struct bmic_identify_controller *id_ctlr,
  3787. u32 *nlocals)
  3788. {
  3789. int rc;
  3790. if (!id_ctlr) {
  3791. dev_warn(&h->pdev->dev, "%s: id_ctlr buffer is NULL.\n",
  3792. __func__);
  3793. return -ENOMEM;
  3794. }
  3795. memset(id_ctlr, 0, sizeof(*id_ctlr));
  3796. rc = hpsa_bmic_id_controller(h, id_ctlr, sizeof(*id_ctlr));
  3797. if (!rc)
  3798. if (id_ctlr->configured_logical_drive_count < 255)
  3799. *nlocals = id_ctlr->configured_logical_drive_count;
  3800. else
  3801. *nlocals = le16_to_cpu(
  3802. id_ctlr->extended_logical_unit_count);
  3803. else
  3804. *nlocals = -1;
  3805. return rc;
  3806. }
  3807. static bool hpsa_is_disk_spare(struct ctlr_info *h, u8 *lunaddrbytes)
  3808. {
  3809. struct bmic_identify_physical_device *id_phys;
  3810. bool is_spare = false;
  3811. int rc;
  3812. id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL);
  3813. if (!id_phys)
  3814. return false;
  3815. rc = hpsa_bmic_id_physical_device(h,
  3816. lunaddrbytes,
  3817. GET_BMIC_DRIVE_NUMBER(lunaddrbytes),
  3818. id_phys, sizeof(*id_phys));
  3819. if (rc == 0)
  3820. is_spare = (id_phys->more_flags >> 6) & 0x01;
  3821. kfree(id_phys);
  3822. return is_spare;
  3823. }
  3824. #define RPL_DEV_FLAG_NON_DISK 0x1
  3825. #define RPL_DEV_FLAG_UNCONFIG_DISK_REPORTING_SUPPORTED 0x2
  3826. #define RPL_DEV_FLAG_UNCONFIG_DISK 0x4
  3827. #define BMIC_DEVICE_TYPE_ENCLOSURE 6
  3828. static bool hpsa_skip_device(struct ctlr_info *h, u8 *lunaddrbytes,
  3829. struct ext_report_lun_entry *rle)
  3830. {
  3831. u8 device_flags;
  3832. u8 device_type;
  3833. if (!MASKED_DEVICE(lunaddrbytes))
  3834. return false;
  3835. device_flags = rle->device_flags;
  3836. device_type = rle->device_type;
  3837. if (device_flags & RPL_DEV_FLAG_NON_DISK) {
  3838. if (device_type == BMIC_DEVICE_TYPE_ENCLOSURE)
  3839. return false;
  3840. return true;
  3841. }
  3842. if (!(device_flags & RPL_DEV_FLAG_UNCONFIG_DISK_REPORTING_SUPPORTED))
  3843. return false;
  3844. if (device_flags & RPL_DEV_FLAG_UNCONFIG_DISK)
  3845. return false;
  3846. /*
  3847. * Spares may be spun down, we do not want to
  3848. * do an Inquiry to a RAID set spare drive as
  3849. * that would have them spun up, that is a
  3850. * performance hit because I/O to the RAID device
  3851. * stops while the spin up occurs which can take
  3852. * over 50 seconds.
  3853. */
  3854. if (hpsa_is_disk_spare(h, lunaddrbytes))
  3855. return true;
  3856. return false;
  3857. }
  3858. static void hpsa_update_scsi_devices(struct ctlr_info *h)
  3859. {
  3860. /* the idea here is we could get notified
  3861. * that some devices have changed, so we do a report
  3862. * physical luns and report logical luns cmd, and adjust
  3863. * our list of devices accordingly.
  3864. *
  3865. * The scsi3addr's of devices won't change so long as the
  3866. * adapter is not reset. That means we can rescan and
  3867. * tell which devices we already know about, vs. new
  3868. * devices, vs. disappearing devices.
  3869. */
  3870. struct ReportExtendedLUNdata *physdev_list = NULL;
  3871. struct ReportLUNdata *logdev_list = NULL;
  3872. struct bmic_identify_physical_device *id_phys = NULL;
  3873. struct bmic_identify_controller *id_ctlr = NULL;
  3874. u32 nphysicals = 0;
  3875. u32 nlogicals = 0;
  3876. u32 nlocal_logicals = 0;
  3877. u32 ndev_allocated = 0;
  3878. struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
  3879. int ncurrent = 0;
  3880. int i, ndevs_to_allocate;
  3881. int raid_ctlr_position;
  3882. bool physical_device;
  3883. currentsd = kcalloc(HPSA_MAX_DEVICES, sizeof(*currentsd), GFP_KERNEL);
  3884. physdev_list = kzalloc(sizeof(*physdev_list), GFP_KERNEL);
  3885. logdev_list = kzalloc(sizeof(*logdev_list), GFP_KERNEL);
  3886. tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
  3887. id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL);
  3888. id_ctlr = kzalloc(sizeof(*id_ctlr), GFP_KERNEL);
  3889. if (!currentsd || !physdev_list || !logdev_list ||
  3890. !tmpdevice || !id_phys || !id_ctlr) {
  3891. dev_err(&h->pdev->dev, "out of memory\n");
  3892. goto out;
  3893. }
  3894. h->drv_req_rescan = 0; /* cancel scheduled rescan - we're doing it. */
  3895. if (hpsa_gather_lun_info(h, physdev_list, &nphysicals,
  3896. logdev_list, &nlogicals)) {
  3897. h->drv_req_rescan = 1;
  3898. goto out;
  3899. }
  3900. /* Set number of local logicals (non PTRAID) */
  3901. if (hpsa_set_local_logical_count(h, id_ctlr, &nlocal_logicals)) {
  3902. dev_warn(&h->pdev->dev,
  3903. "%s: Can't determine number of local logical devices.\n",
  3904. __func__);
  3905. }
  3906. /* We might see up to the maximum number of logical and physical disks
  3907. * plus external target devices, and a device for the local RAID
  3908. * controller.
  3909. */
  3910. ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
  3911. hpsa_ext_ctrl_present(h, physdev_list);
  3912. /* Allocate the per device structures */
  3913. for (i = 0; i < ndevs_to_allocate; i++) {
  3914. if (i >= HPSA_MAX_DEVICES) {
  3915. dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
  3916. " %d devices ignored.\n", HPSA_MAX_DEVICES,
  3917. ndevs_to_allocate - HPSA_MAX_DEVICES);
  3918. break;
  3919. }
  3920. currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
  3921. if (!currentsd[i]) {
  3922. h->drv_req_rescan = 1;
  3923. goto out;
  3924. }
  3925. ndev_allocated++;
  3926. }
  3927. if (is_scsi_rev_5(h))
  3928. raid_ctlr_position = 0;
  3929. else
  3930. raid_ctlr_position = nphysicals + nlogicals;
  3931. /* adjust our table of devices */
  3932. for (i = 0; i < nphysicals + nlogicals + 1; i++) {
  3933. u8 *lunaddrbytes, is_OBDR = 0;
  3934. int rc = 0;
  3935. int phys_dev_index = i - (raid_ctlr_position == 0);
  3936. bool skip_device = false;
  3937. memset(tmpdevice, 0, sizeof(*tmpdevice));
  3938. physical_device = i < nphysicals + (raid_ctlr_position == 0);
  3939. /* Figure out where the LUN ID info is coming from */
  3940. lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
  3941. i, nphysicals, nlogicals, physdev_list, logdev_list);
  3942. /* Determine if this is a lun from an external target array */
  3943. tmpdevice->external =
  3944. figure_external_status(h, raid_ctlr_position, i,
  3945. nphysicals, nlocal_logicals);
  3946. /*
  3947. * Skip over some devices such as a spare.
  3948. */
  3949. if (phys_dev_index >= 0 && !tmpdevice->external &&
  3950. physical_device) {
  3951. skip_device = hpsa_skip_device(h, lunaddrbytes,
  3952. &physdev_list->LUN[phys_dev_index]);
  3953. if (skip_device)
  3954. continue;
  3955. }
  3956. /* Get device type, vendor, model, device id, raid_map */
  3957. rc = hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
  3958. &is_OBDR);
  3959. if (rc == -ENOMEM) {
  3960. dev_warn(&h->pdev->dev,
  3961. "Out of memory, rescan deferred.\n");
  3962. h->drv_req_rescan = 1;
  3963. goto out;
  3964. }
  3965. if (rc) {
  3966. h->drv_req_rescan = 1;
  3967. continue;
  3968. }
  3969. figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
  3970. this_device = currentsd[ncurrent];
  3971. *this_device = *tmpdevice;
  3972. this_device->physical_device = physical_device;
  3973. /*
  3974. * Expose all devices except for physical devices that
  3975. * are masked.
  3976. */
  3977. if (MASKED_DEVICE(lunaddrbytes) && this_device->physical_device)
  3978. this_device->expose_device = 0;
  3979. else
  3980. this_device->expose_device = 1;
  3981. /*
  3982. * Get the SAS address for physical devices that are exposed.
  3983. */
  3984. if (this_device->physical_device && this_device->expose_device)
  3985. hpsa_get_sas_address(h, lunaddrbytes, this_device);
  3986. switch (this_device->devtype) {
  3987. case TYPE_ROM:
  3988. /* We don't *really* support actual CD-ROM devices,
  3989. * just "One Button Disaster Recovery" tape drive
  3990. * which temporarily pretends to be a CD-ROM drive.
  3991. * So we check that the device is really an OBDR tape
  3992. * device by checking for "$DR-10" in bytes 43-48 of
  3993. * the inquiry data.
  3994. */
  3995. if (is_OBDR)
  3996. ncurrent++;
  3997. break;
  3998. case TYPE_DISK:
  3999. case TYPE_ZBC:
  4000. if (this_device->physical_device) {
  4001. /* The disk is in HBA mode. */
  4002. /* Never use RAID mapper in HBA mode. */
  4003. this_device->offload_enabled = 0;
  4004. hpsa_get_ioaccel_drive_info(h, this_device,
  4005. physdev_list, phys_dev_index, id_phys);
  4006. hpsa_get_path_info(this_device,
  4007. physdev_list, phys_dev_index, id_phys);
  4008. }
  4009. ncurrent++;
  4010. break;
  4011. case TYPE_TAPE:
  4012. case TYPE_MEDIUM_CHANGER:
  4013. ncurrent++;
  4014. break;
  4015. case TYPE_ENCLOSURE:
  4016. if (!this_device->external)
  4017. hpsa_get_enclosure_info(h, lunaddrbytes,
  4018. physdev_list, phys_dev_index,
  4019. this_device);
  4020. ncurrent++;
  4021. break;
  4022. case TYPE_RAID:
  4023. /* Only present the Smartarray HBA as a RAID controller.
  4024. * If it's a RAID controller other than the HBA itself
  4025. * (an external RAID controller, MSA500 or similar)
  4026. * don't present it.
  4027. */
  4028. if (!is_hba_lunid(lunaddrbytes))
  4029. break;
  4030. ncurrent++;
  4031. break;
  4032. default:
  4033. break;
  4034. }
  4035. if (ncurrent >= HPSA_MAX_DEVICES)
  4036. break;
  4037. }
  4038. if (h->sas_host == NULL) {
  4039. int rc = 0;
  4040. rc = hpsa_add_sas_host(h);
  4041. if (rc) {
  4042. dev_warn(&h->pdev->dev,
  4043. "Could not add sas host %d\n", rc);
  4044. goto out;
  4045. }
  4046. }
  4047. adjust_hpsa_scsi_table(h, currentsd, ncurrent);
  4048. out:
  4049. kfree(tmpdevice);
  4050. for (i = 0; i < ndev_allocated; i++)
  4051. kfree(currentsd[i]);
  4052. kfree(currentsd);
  4053. kfree(physdev_list);
  4054. kfree(logdev_list);
  4055. kfree(id_ctlr);
  4056. kfree(id_phys);
  4057. }
  4058. static void hpsa_set_sg_descriptor(struct SGDescriptor *desc,
  4059. struct scatterlist *sg)
  4060. {
  4061. u64 addr64 = (u64) sg_dma_address(sg);
  4062. unsigned int len = sg_dma_len(sg);
  4063. desc->Addr = cpu_to_le64(addr64);
  4064. desc->Len = cpu_to_le32(len);
  4065. desc->Ext = 0;
  4066. }
  4067. /*
  4068. * hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
  4069. * dma mapping and fills in the scatter gather entries of the
  4070. * hpsa command, cp.
  4071. */
  4072. static int hpsa_scatter_gather(struct ctlr_info *h,
  4073. struct CommandList *cp,
  4074. struct scsi_cmnd *cmd)
  4075. {
  4076. struct scatterlist *sg;
  4077. int use_sg, i, sg_limit, chained;
  4078. struct SGDescriptor *curr_sg;
  4079. BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
  4080. use_sg = scsi_dma_map(cmd);
  4081. if (use_sg < 0)
  4082. return use_sg;
  4083. if (!use_sg)
  4084. goto sglist_finished;
  4085. /*
  4086. * If the number of entries is greater than the max for a single list,
  4087. * then we have a chained list; we will set up all but one entry in the
  4088. * first list (the last entry is saved for link information);
  4089. * otherwise, we don't have a chained list and we'll set up at each of
  4090. * the entries in the one list.
  4091. */
  4092. curr_sg = cp->SG;
  4093. chained = use_sg > h->max_cmd_sg_entries;
  4094. sg_limit = chained ? h->max_cmd_sg_entries - 1 : use_sg;
  4095. scsi_for_each_sg(cmd, sg, sg_limit, i) {
  4096. hpsa_set_sg_descriptor(curr_sg, sg);
  4097. curr_sg++;
  4098. }
  4099. if (chained) {
  4100. /*
  4101. * Continue with the chained list. Set curr_sg to the chained
  4102. * list. Modify the limit to the total count less the entries
  4103. * we've already set up. Resume the scan at the list entry
  4104. * where the previous loop left off.
  4105. */
  4106. curr_sg = h->cmd_sg_list[cp->cmdindex];
  4107. sg_limit = use_sg - sg_limit;
  4108. for_each_sg(sg, sg, sg_limit, i) {
  4109. hpsa_set_sg_descriptor(curr_sg, sg);
  4110. curr_sg++;
  4111. }
  4112. }
  4113. /* Back the pointer up to the last entry and mark it as "last". */
  4114. (curr_sg - 1)->Ext = cpu_to_le32(HPSA_SG_LAST);
  4115. if (use_sg + chained > h->maxSG)
  4116. h->maxSG = use_sg + chained;
  4117. if (chained) {
  4118. cp->Header.SGList = h->max_cmd_sg_entries;
  4119. cp->Header.SGTotal = cpu_to_le16(use_sg + 1);
  4120. if (hpsa_map_sg_chain_block(h, cp)) {
  4121. scsi_dma_unmap(cmd);
  4122. return -1;
  4123. }
  4124. return 0;
  4125. }
  4126. sglist_finished:
  4127. cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
  4128. cp->Header.SGTotal = cpu_to_le16(use_sg); /* total sgs in cmd list */
  4129. return 0;
  4130. }
  4131. static inline void warn_zero_length_transfer(struct ctlr_info *h,
  4132. u8 *cdb, int cdb_len,
  4133. const char *func)
  4134. {
  4135. dev_warn(&h->pdev->dev,
  4136. "%s: Blocking zero-length request: CDB:%*phN\n",
  4137. func, cdb_len, cdb);
  4138. }
  4139. #define IO_ACCEL_INELIGIBLE 1
  4140. /* zero-length transfers trigger hardware errors. */
  4141. static bool is_zero_length_transfer(u8 *cdb)
  4142. {
  4143. u32 block_cnt;
  4144. /* Block zero-length transfer sizes on certain commands. */
  4145. switch (cdb[0]) {
  4146. case READ_10:
  4147. case WRITE_10:
  4148. case VERIFY: /* 0x2F */
  4149. case WRITE_VERIFY: /* 0x2E */
  4150. block_cnt = get_unaligned_be16(&cdb[7]);
  4151. break;
  4152. case READ_12:
  4153. case WRITE_12:
  4154. case VERIFY_12: /* 0xAF */
  4155. case WRITE_VERIFY_12: /* 0xAE */
  4156. block_cnt = get_unaligned_be32(&cdb[6]);
  4157. break;
  4158. case READ_16:
  4159. case WRITE_16:
  4160. case VERIFY_16: /* 0x8F */
  4161. block_cnt = get_unaligned_be32(&cdb[10]);
  4162. break;
  4163. default:
  4164. return false;
  4165. }
  4166. return block_cnt == 0;
  4167. }
  4168. static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
  4169. {
  4170. int is_write = 0;
  4171. u32 block;
  4172. u32 block_cnt;
  4173. /* Perform some CDB fixups if needed using 10 byte reads/writes only */
  4174. switch (cdb[0]) {
  4175. case WRITE_6:
  4176. case WRITE_12:
  4177. is_write = 1;
  4178. fallthrough;
  4179. case READ_6:
  4180. case READ_12:
  4181. if (*cdb_len == 6) {
  4182. block = (((cdb[1] & 0x1F) << 16) |
  4183. (cdb[2] << 8) |
  4184. cdb[3]);
  4185. block_cnt = cdb[4];
  4186. if (block_cnt == 0)
  4187. block_cnt = 256;
  4188. } else {
  4189. BUG_ON(*cdb_len != 12);
  4190. block = get_unaligned_be32(&cdb[2]);
  4191. block_cnt = get_unaligned_be32(&cdb[6]);
  4192. }
  4193. if (block_cnt > 0xffff)
  4194. return IO_ACCEL_INELIGIBLE;
  4195. cdb[0] = is_write ? WRITE_10 : READ_10;
  4196. cdb[1] = 0;
  4197. cdb[2] = (u8) (block >> 24);
  4198. cdb[3] = (u8) (block >> 16);
  4199. cdb[4] = (u8) (block >> 8);
  4200. cdb[5] = (u8) (block);
  4201. cdb[6] = 0;
  4202. cdb[7] = (u8) (block_cnt >> 8);
  4203. cdb[8] = (u8) (block_cnt);
  4204. cdb[9] = 0;
  4205. *cdb_len = 10;
  4206. break;
  4207. }
  4208. return 0;
  4209. }
  4210. static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
  4211. struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
  4212. u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
  4213. {
  4214. struct scsi_cmnd *cmd = c->scsi_cmd;
  4215. struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
  4216. unsigned int len;
  4217. unsigned int total_len = 0;
  4218. struct scatterlist *sg;
  4219. u64 addr64;
  4220. int use_sg, i;
  4221. struct SGDescriptor *curr_sg;
  4222. u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
  4223. /* TODO: implement chaining support */
  4224. if (scsi_sg_count(cmd) > h->ioaccel_maxsg) {
  4225. atomic_dec(&phys_disk->ioaccel_cmds_out);
  4226. return IO_ACCEL_INELIGIBLE;
  4227. }
  4228. BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
  4229. if (is_zero_length_transfer(cdb)) {
  4230. warn_zero_length_transfer(h, cdb, cdb_len, __func__);
  4231. atomic_dec(&phys_disk->ioaccel_cmds_out);
  4232. return IO_ACCEL_INELIGIBLE;
  4233. }
  4234. if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
  4235. atomic_dec(&phys_disk->ioaccel_cmds_out);
  4236. return IO_ACCEL_INELIGIBLE;
  4237. }
  4238. c->cmd_type = CMD_IOACCEL1;
  4239. /* Adjust the DMA address to point to the accelerated command buffer */
  4240. c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
  4241. (c->cmdindex * sizeof(*cp));
  4242. BUG_ON(c->busaddr & 0x0000007F);
  4243. use_sg = scsi_dma_map(cmd);
  4244. if (use_sg < 0) {
  4245. atomic_dec(&phys_disk->ioaccel_cmds_out);
  4246. return use_sg;
  4247. }
  4248. if (use_sg) {
  4249. curr_sg = cp->SG;
  4250. scsi_for_each_sg(cmd, sg, use_sg, i) {
  4251. addr64 = (u64) sg_dma_address(sg);
  4252. len = sg_dma_len(sg);
  4253. total_len += len;
  4254. curr_sg->Addr = cpu_to_le64(addr64);
  4255. curr_sg->Len = cpu_to_le32(len);
  4256. curr_sg->Ext = cpu_to_le32(0);
  4257. curr_sg++;
  4258. }
  4259. (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST);
  4260. switch (cmd->sc_data_direction) {
  4261. case DMA_TO_DEVICE:
  4262. control |= IOACCEL1_CONTROL_DATA_OUT;
  4263. break;
  4264. case DMA_FROM_DEVICE:
  4265. control |= IOACCEL1_CONTROL_DATA_IN;
  4266. break;
  4267. case DMA_NONE:
  4268. control |= IOACCEL1_CONTROL_NODATAXFER;
  4269. break;
  4270. default:
  4271. dev_err(&h->pdev->dev, "unknown data direction: %d\n",
  4272. cmd->sc_data_direction);
  4273. BUG();
  4274. break;
  4275. }
  4276. } else {
  4277. control |= IOACCEL1_CONTROL_NODATAXFER;
  4278. }
  4279. c->Header.SGList = use_sg;
  4280. /* Fill out the command structure to submit */
  4281. cp->dev_handle = cpu_to_le16(ioaccel_handle & 0xFFFF);
  4282. cp->transfer_len = cpu_to_le32(total_len);
  4283. cp->io_flags = cpu_to_le16(IOACCEL1_IOFLAGS_IO_REQ |
  4284. (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK));
  4285. cp->control = cpu_to_le32(control);
  4286. memcpy(cp->CDB, cdb, cdb_len);
  4287. memcpy(cp->CISS_LUN, scsi3addr, 8);
  4288. /* Tag was already set at init time. */
  4289. enqueue_cmd_and_start_io(h, c);
  4290. return 0;
  4291. }
  4292. /*
  4293. * Queue a command directly to a device behind the controller using the
  4294. * I/O accelerator path.
  4295. */
  4296. static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
  4297. struct CommandList *c)
  4298. {
  4299. struct scsi_cmnd *cmd = c->scsi_cmd;
  4300. struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
  4301. if (!dev)
  4302. return -1;
  4303. c->phys_disk = dev;
  4304. if (dev->in_reset)
  4305. return -1;
  4306. return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
  4307. cmd->cmnd, cmd->cmd_len, dev->scsi3addr, dev);
  4308. }
  4309. /*
  4310. * Set encryption parameters for the ioaccel2 request
  4311. */
  4312. static void set_encrypt_ioaccel2(struct ctlr_info *h,
  4313. struct CommandList *c, struct io_accel2_cmd *cp)
  4314. {
  4315. struct scsi_cmnd *cmd = c->scsi_cmd;
  4316. struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
  4317. struct raid_map_data *map = &dev->raid_map;
  4318. u64 first_block;
  4319. /* Are we doing encryption on this device */
  4320. if (!(le16_to_cpu(map->flags) & RAID_MAP_FLAG_ENCRYPT_ON))
  4321. return;
  4322. /* Set the data encryption key index. */
  4323. cp->dekindex = map->dekindex;
  4324. /* Set the encryption enable flag, encoded into direction field. */
  4325. cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK;
  4326. /* Set encryption tweak values based on logical block address
  4327. * If block size is 512, tweak value is LBA.
  4328. * For other block sizes, tweak is (LBA * block size)/ 512)
  4329. */
  4330. switch (cmd->cmnd[0]) {
  4331. /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */
  4332. case READ_6:
  4333. case WRITE_6:
  4334. first_block = (((cmd->cmnd[1] & 0x1F) << 16) |
  4335. (cmd->cmnd[2] << 8) |
  4336. cmd->cmnd[3]);
  4337. break;
  4338. case WRITE_10:
  4339. case READ_10:
  4340. /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */
  4341. case WRITE_12:
  4342. case READ_12:
  4343. first_block = get_unaligned_be32(&cmd->cmnd[2]);
  4344. break;
  4345. case WRITE_16:
  4346. case READ_16:
  4347. first_block = get_unaligned_be64(&cmd->cmnd[2]);
  4348. break;
  4349. default:
  4350. dev_err(&h->pdev->dev,
  4351. "ERROR: %s: size (0x%x) not supported for encryption\n",
  4352. __func__, cmd->cmnd[0]);
  4353. BUG();
  4354. break;
  4355. }
  4356. if (le32_to_cpu(map->volume_blk_size) != 512)
  4357. first_block = first_block *
  4358. le32_to_cpu(map->volume_blk_size)/512;
  4359. cp->tweak_lower = cpu_to_le32(first_block);
  4360. cp->tweak_upper = cpu_to_le32(first_block >> 32);
  4361. }
  4362. static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
  4363. struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
  4364. u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
  4365. {
  4366. struct scsi_cmnd *cmd = c->scsi_cmd;
  4367. struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
  4368. struct ioaccel2_sg_element *curr_sg;
  4369. int use_sg, i;
  4370. struct scatterlist *sg;
  4371. u64 addr64;
  4372. u32 len;
  4373. u32 total_len = 0;
  4374. if (!cmd->device)
  4375. return -1;
  4376. if (!cmd->device->hostdata)
  4377. return -1;
  4378. BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
  4379. if (is_zero_length_transfer(cdb)) {
  4380. warn_zero_length_transfer(h, cdb, cdb_len, __func__);
  4381. atomic_dec(&phys_disk->ioaccel_cmds_out);
  4382. return IO_ACCEL_INELIGIBLE;
  4383. }
  4384. if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
  4385. atomic_dec(&phys_disk->ioaccel_cmds_out);
  4386. return IO_ACCEL_INELIGIBLE;
  4387. }
  4388. c->cmd_type = CMD_IOACCEL2;
  4389. /* Adjust the DMA address to point to the accelerated command buffer */
  4390. c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
  4391. (c->cmdindex * sizeof(*cp));
  4392. BUG_ON(c->busaddr & 0x0000007F);
  4393. memset(cp, 0, sizeof(*cp));
  4394. cp->IU_type = IOACCEL2_IU_TYPE;
  4395. use_sg = scsi_dma_map(cmd);
  4396. if (use_sg < 0) {
  4397. atomic_dec(&phys_disk->ioaccel_cmds_out);
  4398. return use_sg;
  4399. }
  4400. if (use_sg) {
  4401. curr_sg = cp->sg;
  4402. if (use_sg > h->ioaccel_maxsg) {
  4403. addr64 = le64_to_cpu(
  4404. h->ioaccel2_cmd_sg_list[c->cmdindex]->address);
  4405. curr_sg->address = cpu_to_le64(addr64);
  4406. curr_sg->length = 0;
  4407. curr_sg->reserved[0] = 0;
  4408. curr_sg->reserved[1] = 0;
  4409. curr_sg->reserved[2] = 0;
  4410. curr_sg->chain_indicator = IOACCEL2_CHAIN;
  4411. curr_sg = h->ioaccel2_cmd_sg_list[c->cmdindex];
  4412. }
  4413. scsi_for_each_sg(cmd, sg, use_sg, i) {
  4414. addr64 = (u64) sg_dma_address(sg);
  4415. len = sg_dma_len(sg);
  4416. total_len += len;
  4417. curr_sg->address = cpu_to_le64(addr64);
  4418. curr_sg->length = cpu_to_le32(len);
  4419. curr_sg->reserved[0] = 0;
  4420. curr_sg->reserved[1] = 0;
  4421. curr_sg->reserved[2] = 0;
  4422. curr_sg->chain_indicator = 0;
  4423. curr_sg++;
  4424. }
  4425. /*
  4426. * Set the last s/g element bit
  4427. */
  4428. (curr_sg - 1)->chain_indicator = IOACCEL2_LAST_SG;
  4429. switch (cmd->sc_data_direction) {
  4430. case DMA_TO_DEVICE:
  4431. cp->direction &= ~IOACCEL2_DIRECTION_MASK;
  4432. cp->direction |= IOACCEL2_DIR_DATA_OUT;
  4433. break;
  4434. case DMA_FROM_DEVICE:
  4435. cp->direction &= ~IOACCEL2_DIRECTION_MASK;
  4436. cp->direction |= IOACCEL2_DIR_DATA_IN;
  4437. break;
  4438. case DMA_NONE:
  4439. cp->direction &= ~IOACCEL2_DIRECTION_MASK;
  4440. cp->direction |= IOACCEL2_DIR_NO_DATA;
  4441. break;
  4442. default:
  4443. dev_err(&h->pdev->dev, "unknown data direction: %d\n",
  4444. cmd->sc_data_direction);
  4445. BUG();
  4446. break;
  4447. }
  4448. } else {
  4449. cp->direction &= ~IOACCEL2_DIRECTION_MASK;
  4450. cp->direction |= IOACCEL2_DIR_NO_DATA;
  4451. }
  4452. /* Set encryption parameters, if necessary */
  4453. set_encrypt_ioaccel2(h, c, cp);
  4454. cp->scsi_nexus = cpu_to_le32(ioaccel_handle);
  4455. cp->Tag = cpu_to_le32(c->cmdindex << DIRECT_LOOKUP_SHIFT);
  4456. memcpy(cp->cdb, cdb, sizeof(cp->cdb));
  4457. cp->data_len = cpu_to_le32(total_len);
  4458. cp->err_ptr = cpu_to_le64(c->busaddr +
  4459. offsetof(struct io_accel2_cmd, error_data));
  4460. cp->err_len = cpu_to_le32(sizeof(cp->error_data));
  4461. /* fill in sg elements */
  4462. if (use_sg > h->ioaccel_maxsg) {
  4463. cp->sg_count = 1;
  4464. cp->sg[0].length = cpu_to_le32(use_sg * sizeof(cp->sg[0]));
  4465. if (hpsa_map_ioaccel2_sg_chain_block(h, cp, c)) {
  4466. atomic_dec(&phys_disk->ioaccel_cmds_out);
  4467. scsi_dma_unmap(cmd);
  4468. return -1;
  4469. }
  4470. } else
  4471. cp->sg_count = (u8) use_sg;
  4472. if (phys_disk->in_reset) {
  4473. cmd->result = DID_RESET << 16;
  4474. return -1;
  4475. }
  4476. enqueue_cmd_and_start_io(h, c);
  4477. return 0;
  4478. }
  4479. /*
  4480. * Queue a command to the correct I/O accelerator path.
  4481. */
  4482. static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
  4483. struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
  4484. u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
  4485. {
  4486. if (!c->scsi_cmd->device)
  4487. return -1;
  4488. if (!c->scsi_cmd->device->hostdata)
  4489. return -1;
  4490. if (phys_disk->in_reset)
  4491. return -1;
  4492. /* Try to honor the device's queue depth */
  4493. if (atomic_inc_return(&phys_disk->ioaccel_cmds_out) >
  4494. phys_disk->queue_depth) {
  4495. atomic_dec(&phys_disk->ioaccel_cmds_out);
  4496. return IO_ACCEL_INELIGIBLE;
  4497. }
  4498. if (h->transMethod & CFGTBL_Trans_io_accel1)
  4499. return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
  4500. cdb, cdb_len, scsi3addr,
  4501. phys_disk);
  4502. else
  4503. return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
  4504. cdb, cdb_len, scsi3addr,
  4505. phys_disk);
  4506. }
  4507. static void raid_map_helper(struct raid_map_data *map,
  4508. int offload_to_mirror, u32 *map_index, u32 *current_group)
  4509. {
  4510. if (offload_to_mirror == 0) {
  4511. /* use physical disk in the first mirrored group. */
  4512. *map_index %= le16_to_cpu(map->data_disks_per_row);
  4513. return;
  4514. }
  4515. do {
  4516. /* determine mirror group that *map_index indicates */
  4517. *current_group = *map_index /
  4518. le16_to_cpu(map->data_disks_per_row);
  4519. if (offload_to_mirror == *current_group)
  4520. continue;
  4521. if (*current_group < le16_to_cpu(map->layout_map_count) - 1) {
  4522. /* select map index from next group */
  4523. *map_index += le16_to_cpu(map->data_disks_per_row);
  4524. (*current_group)++;
  4525. } else {
  4526. /* select map index from first group */
  4527. *map_index %= le16_to_cpu(map->data_disks_per_row);
  4528. *current_group = 0;
  4529. }
  4530. } while (offload_to_mirror != *current_group);
  4531. }
  4532. /*
  4533. * Attempt to perform offload RAID mapping for a logical volume I/O.
  4534. */
  4535. static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
  4536. struct CommandList *c)
  4537. {
  4538. struct scsi_cmnd *cmd = c->scsi_cmd;
  4539. struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
  4540. struct raid_map_data *map = &dev->raid_map;
  4541. struct raid_map_disk_data *dd = &map->data[0];
  4542. int is_write = 0;
  4543. u32 map_index;
  4544. u64 first_block, last_block;
  4545. u32 block_cnt;
  4546. u32 blocks_per_row;
  4547. u64 first_row, last_row;
  4548. u32 first_row_offset, last_row_offset;
  4549. u32 first_column, last_column;
  4550. u64 r0_first_row, r0_last_row;
  4551. u32 r5or6_blocks_per_row;
  4552. u64 r5or6_first_row, r5or6_last_row;
  4553. u32 r5or6_first_row_offset, r5or6_last_row_offset;
  4554. u32 r5or6_first_column, r5or6_last_column;
  4555. u32 total_disks_per_row;
  4556. u32 stripesize;
  4557. u32 first_group, last_group, current_group;
  4558. u32 map_row;
  4559. u32 disk_handle;
  4560. u64 disk_block;
  4561. u32 disk_block_cnt;
  4562. u8 cdb[16];
  4563. u8 cdb_len;
  4564. u16 strip_size;
  4565. #if BITS_PER_LONG == 32
  4566. u64 tmpdiv;
  4567. #endif
  4568. int offload_to_mirror;
  4569. if (!dev)
  4570. return -1;
  4571. if (dev->in_reset)
  4572. return -1;
  4573. /* check for valid opcode, get LBA and block count */
  4574. switch (cmd->cmnd[0]) {
  4575. case WRITE_6:
  4576. is_write = 1;
  4577. fallthrough;
  4578. case READ_6:
  4579. first_block = (((cmd->cmnd[1] & 0x1F) << 16) |
  4580. (cmd->cmnd[2] << 8) |
  4581. cmd->cmnd[3]);
  4582. block_cnt = cmd->cmnd[4];
  4583. if (block_cnt == 0)
  4584. block_cnt = 256;
  4585. break;
  4586. case WRITE_10:
  4587. is_write = 1;
  4588. fallthrough;
  4589. case READ_10:
  4590. first_block =
  4591. (((u64) cmd->cmnd[2]) << 24) |
  4592. (((u64) cmd->cmnd[3]) << 16) |
  4593. (((u64) cmd->cmnd[4]) << 8) |
  4594. cmd->cmnd[5];
  4595. block_cnt =
  4596. (((u32) cmd->cmnd[7]) << 8) |
  4597. cmd->cmnd[8];
  4598. break;
  4599. case WRITE_12:
  4600. is_write = 1;
  4601. fallthrough;
  4602. case READ_12:
  4603. first_block =
  4604. (((u64) cmd->cmnd[2]) << 24) |
  4605. (((u64) cmd->cmnd[3]) << 16) |
  4606. (((u64) cmd->cmnd[4]) << 8) |
  4607. cmd->cmnd[5];
  4608. block_cnt =
  4609. (((u32) cmd->cmnd[6]) << 24) |
  4610. (((u32) cmd->cmnd[7]) << 16) |
  4611. (((u32) cmd->cmnd[8]) << 8) |
  4612. cmd->cmnd[9];
  4613. break;
  4614. case WRITE_16:
  4615. is_write = 1;
  4616. fallthrough;
  4617. case READ_16:
  4618. first_block =
  4619. (((u64) cmd->cmnd[2]) << 56) |
  4620. (((u64) cmd->cmnd[3]) << 48) |
  4621. (((u64) cmd->cmnd[4]) << 40) |
  4622. (((u64) cmd->cmnd[5]) << 32) |
  4623. (((u64) cmd->cmnd[6]) << 24) |
  4624. (((u64) cmd->cmnd[7]) << 16) |
  4625. (((u64) cmd->cmnd[8]) << 8) |
  4626. cmd->cmnd[9];
  4627. block_cnt =
  4628. (((u32) cmd->cmnd[10]) << 24) |
  4629. (((u32) cmd->cmnd[11]) << 16) |
  4630. (((u32) cmd->cmnd[12]) << 8) |
  4631. cmd->cmnd[13];
  4632. break;
  4633. default:
  4634. return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
  4635. }
  4636. last_block = first_block + block_cnt - 1;
  4637. /* check for write to non-RAID-0 */
  4638. if (is_write && dev->raid_level != 0)
  4639. return IO_ACCEL_INELIGIBLE;
  4640. /* check for invalid block or wraparound */
  4641. if (last_block >= le64_to_cpu(map->volume_blk_cnt) ||
  4642. last_block < first_block)
  4643. return IO_ACCEL_INELIGIBLE;
  4644. /* calculate stripe information for the request */
  4645. blocks_per_row = le16_to_cpu(map->data_disks_per_row) *
  4646. le16_to_cpu(map->strip_size);
  4647. strip_size = le16_to_cpu(map->strip_size);
  4648. #if BITS_PER_LONG == 32
  4649. tmpdiv = first_block;
  4650. (void) do_div(tmpdiv, blocks_per_row);
  4651. first_row = tmpdiv;
  4652. tmpdiv = last_block;
  4653. (void) do_div(tmpdiv, blocks_per_row);
  4654. last_row = tmpdiv;
  4655. first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
  4656. last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
  4657. tmpdiv = first_row_offset;
  4658. (void) do_div(tmpdiv, strip_size);
  4659. first_column = tmpdiv;
  4660. tmpdiv = last_row_offset;
  4661. (void) do_div(tmpdiv, strip_size);
  4662. last_column = tmpdiv;
  4663. #else
  4664. first_row = first_block / blocks_per_row;
  4665. last_row = last_block / blocks_per_row;
  4666. first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
  4667. last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
  4668. first_column = first_row_offset / strip_size;
  4669. last_column = last_row_offset / strip_size;
  4670. #endif
  4671. /* if this isn't a single row/column then give to the controller */
  4672. if ((first_row != last_row) || (first_column != last_column))
  4673. return IO_ACCEL_INELIGIBLE;
  4674. /* proceeding with driver mapping */
  4675. total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
  4676. le16_to_cpu(map->metadata_disks_per_row);
  4677. map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
  4678. le16_to_cpu(map->row_cnt);
  4679. map_index = (map_row * total_disks_per_row) + first_column;
  4680. switch (dev->raid_level) {
  4681. case HPSA_RAID_0:
  4682. break; /* nothing special to do */
  4683. case HPSA_RAID_1:
  4684. /* Handles load balance across RAID 1 members.
  4685. * (2-drive R1 and R10 with even # of drives.)
  4686. * Appropriate for SSDs, not optimal for HDDs
  4687. * Ensure we have the correct raid_map.
  4688. */
  4689. if (le16_to_cpu(map->layout_map_count) != 2) {
  4690. hpsa_turn_off_ioaccel_for_device(dev);
  4691. return IO_ACCEL_INELIGIBLE;
  4692. }
  4693. if (dev->offload_to_mirror)
  4694. map_index += le16_to_cpu(map->data_disks_per_row);
  4695. dev->offload_to_mirror = !dev->offload_to_mirror;
  4696. break;
  4697. case HPSA_RAID_ADM:
  4698. /* Handles N-way mirrors (R1-ADM)
  4699. * and R10 with # of drives divisible by 3.)
  4700. * Ensure we have the correct raid_map.
  4701. */
  4702. if (le16_to_cpu(map->layout_map_count) != 3) {
  4703. hpsa_turn_off_ioaccel_for_device(dev);
  4704. return IO_ACCEL_INELIGIBLE;
  4705. }
  4706. offload_to_mirror = dev->offload_to_mirror;
  4707. raid_map_helper(map, offload_to_mirror,
  4708. &map_index, &current_group);
  4709. /* set mirror group to use next time */
  4710. offload_to_mirror =
  4711. (offload_to_mirror >=
  4712. le16_to_cpu(map->layout_map_count) - 1)
  4713. ? 0 : offload_to_mirror + 1;
  4714. dev->offload_to_mirror = offload_to_mirror;
  4715. /* Avoid direct use of dev->offload_to_mirror within this
  4716. * function since multiple threads might simultaneously
  4717. * increment it beyond the range of dev->layout_map_count -1.
  4718. */
  4719. break;
  4720. case HPSA_RAID_5:
  4721. case HPSA_RAID_6:
  4722. if (le16_to_cpu(map->layout_map_count) <= 1)
  4723. break;
  4724. /* Verify first and last block are in same RAID group */
  4725. r5or6_blocks_per_row =
  4726. le16_to_cpu(map->strip_size) *
  4727. le16_to_cpu(map->data_disks_per_row);
  4728. if (r5or6_blocks_per_row == 0) {
  4729. hpsa_turn_off_ioaccel_for_device(dev);
  4730. return IO_ACCEL_INELIGIBLE;
  4731. }
  4732. stripesize = r5or6_blocks_per_row *
  4733. le16_to_cpu(map->layout_map_count);
  4734. #if BITS_PER_LONG == 32
  4735. tmpdiv = first_block;
  4736. first_group = do_div(tmpdiv, stripesize);
  4737. tmpdiv = first_group;
  4738. (void) do_div(tmpdiv, r5or6_blocks_per_row);
  4739. first_group = tmpdiv;
  4740. tmpdiv = last_block;
  4741. last_group = do_div(tmpdiv, stripesize);
  4742. tmpdiv = last_group;
  4743. (void) do_div(tmpdiv, r5or6_blocks_per_row);
  4744. last_group = tmpdiv;
  4745. #else
  4746. first_group = (first_block % stripesize) / r5or6_blocks_per_row;
  4747. last_group = (last_block % stripesize) / r5or6_blocks_per_row;
  4748. #endif
  4749. if (first_group != last_group)
  4750. return IO_ACCEL_INELIGIBLE;
  4751. /* Verify request is in a single row of RAID 5/6 */
  4752. #if BITS_PER_LONG == 32
  4753. tmpdiv = first_block;
  4754. (void) do_div(tmpdiv, stripesize);
  4755. first_row = r5or6_first_row = r0_first_row = tmpdiv;
  4756. tmpdiv = last_block;
  4757. (void) do_div(tmpdiv, stripesize);
  4758. r5or6_last_row = r0_last_row = tmpdiv;
  4759. #else
  4760. first_row = r5or6_first_row = r0_first_row =
  4761. first_block / stripesize;
  4762. r5or6_last_row = r0_last_row = last_block / stripesize;
  4763. #endif
  4764. if (r5or6_first_row != r5or6_last_row)
  4765. return IO_ACCEL_INELIGIBLE;
  4766. /* Verify request is in a single column */
  4767. #if BITS_PER_LONG == 32
  4768. tmpdiv = first_block;
  4769. first_row_offset = do_div(tmpdiv, stripesize);
  4770. tmpdiv = first_row_offset;
  4771. first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row);
  4772. r5or6_first_row_offset = first_row_offset;
  4773. tmpdiv = last_block;
  4774. r5or6_last_row_offset = do_div(tmpdiv, stripesize);
  4775. tmpdiv = r5or6_last_row_offset;
  4776. r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
  4777. tmpdiv = r5or6_first_row_offset;
  4778. (void) do_div(tmpdiv, map->strip_size);
  4779. first_column = r5or6_first_column = tmpdiv;
  4780. tmpdiv = r5or6_last_row_offset;
  4781. (void) do_div(tmpdiv, map->strip_size);
  4782. r5or6_last_column = tmpdiv;
  4783. #else
  4784. first_row_offset = r5or6_first_row_offset =
  4785. (u32)((first_block % stripesize) %
  4786. r5or6_blocks_per_row);
  4787. r5or6_last_row_offset =
  4788. (u32)((last_block % stripesize) %
  4789. r5or6_blocks_per_row);
  4790. first_column = r5or6_first_column =
  4791. r5or6_first_row_offset / le16_to_cpu(map->strip_size);
  4792. r5or6_last_column =
  4793. r5or6_last_row_offset / le16_to_cpu(map->strip_size);
  4794. #endif
  4795. if (r5or6_first_column != r5or6_last_column)
  4796. return IO_ACCEL_INELIGIBLE;
  4797. /* Request is eligible */
  4798. map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
  4799. le16_to_cpu(map->row_cnt);
  4800. map_index = (first_group *
  4801. (le16_to_cpu(map->row_cnt) * total_disks_per_row)) +
  4802. (map_row * total_disks_per_row) + first_column;
  4803. break;
  4804. default:
  4805. return IO_ACCEL_INELIGIBLE;
  4806. }
  4807. if (unlikely(map_index >= RAID_MAP_MAX_ENTRIES))
  4808. return IO_ACCEL_INELIGIBLE;
  4809. c->phys_disk = dev->phys_disk[map_index];
  4810. if (!c->phys_disk)
  4811. return IO_ACCEL_INELIGIBLE;
  4812. disk_handle = dd[map_index].ioaccel_handle;
  4813. disk_block = le64_to_cpu(map->disk_starting_blk) +
  4814. first_row * le16_to_cpu(map->strip_size) +
  4815. (first_row_offset - first_column *
  4816. le16_to_cpu(map->strip_size));
  4817. disk_block_cnt = block_cnt;
  4818. /* handle differing logical/physical block sizes */
  4819. if (map->phys_blk_shift) {
  4820. disk_block <<= map->phys_blk_shift;
  4821. disk_block_cnt <<= map->phys_blk_shift;
  4822. }
  4823. BUG_ON(disk_block_cnt > 0xffff);
  4824. /* build the new CDB for the physical disk I/O */
  4825. if (disk_block > 0xffffffff) {
  4826. cdb[0] = is_write ? WRITE_16 : READ_16;
  4827. cdb[1] = 0;
  4828. cdb[2] = (u8) (disk_block >> 56);
  4829. cdb[3] = (u8) (disk_block >> 48);
  4830. cdb[4] = (u8) (disk_block >> 40);
  4831. cdb[5] = (u8) (disk_block >> 32);
  4832. cdb[6] = (u8) (disk_block >> 24);
  4833. cdb[7] = (u8) (disk_block >> 16);
  4834. cdb[8] = (u8) (disk_block >> 8);
  4835. cdb[9] = (u8) (disk_block);
  4836. cdb[10] = (u8) (disk_block_cnt >> 24);
  4837. cdb[11] = (u8) (disk_block_cnt >> 16);
  4838. cdb[12] = (u8) (disk_block_cnt >> 8);
  4839. cdb[13] = (u8) (disk_block_cnt);
  4840. cdb[14] = 0;
  4841. cdb[15] = 0;
  4842. cdb_len = 16;
  4843. } else {
  4844. cdb[0] = is_write ? WRITE_10 : READ_10;
  4845. cdb[1] = 0;
  4846. cdb[2] = (u8) (disk_block >> 24);
  4847. cdb[3] = (u8) (disk_block >> 16);
  4848. cdb[4] = (u8) (disk_block >> 8);
  4849. cdb[5] = (u8) (disk_block);
  4850. cdb[6] = 0;
  4851. cdb[7] = (u8) (disk_block_cnt >> 8);
  4852. cdb[8] = (u8) (disk_block_cnt);
  4853. cdb[9] = 0;
  4854. cdb_len = 10;
  4855. }
  4856. return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
  4857. dev->scsi3addr,
  4858. dev->phys_disk[map_index]);
  4859. }
  4860. /*
  4861. * Submit commands down the "normal" RAID stack path
  4862. * All callers to hpsa_ciss_submit must check lockup_detected
  4863. * beforehand, before (opt.) and after calling cmd_alloc
  4864. */
  4865. static int hpsa_ciss_submit(struct ctlr_info *h,
  4866. struct CommandList *c, struct scsi_cmnd *cmd,
  4867. struct hpsa_scsi_dev_t *dev)
  4868. {
  4869. cmd->host_scribble = (unsigned char *) c;
  4870. c->cmd_type = CMD_SCSI;
  4871. c->scsi_cmd = cmd;
  4872. c->Header.ReplyQueue = 0; /* unused in simple mode */
  4873. memcpy(&c->Header.LUN.LunAddrBytes[0], &dev->scsi3addr[0], 8);
  4874. c->Header.tag = cpu_to_le64((c->cmdindex << DIRECT_LOOKUP_SHIFT));
  4875. /* Fill in the request block... */
  4876. c->Request.Timeout = 0;
  4877. BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
  4878. c->Request.CDBLen = cmd->cmd_len;
  4879. memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
  4880. switch (cmd->sc_data_direction) {
  4881. case DMA_TO_DEVICE:
  4882. c->Request.type_attr_dir =
  4883. TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_WRITE);
  4884. break;
  4885. case DMA_FROM_DEVICE:
  4886. c->Request.type_attr_dir =
  4887. TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_READ);
  4888. break;
  4889. case DMA_NONE:
  4890. c->Request.type_attr_dir =
  4891. TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_NONE);
  4892. break;
  4893. case DMA_BIDIRECTIONAL:
  4894. /* This can happen if a buggy application does a scsi passthru
  4895. * and sets both inlen and outlen to non-zero. ( see
  4896. * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
  4897. */
  4898. c->Request.type_attr_dir =
  4899. TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_RSVD);
  4900. /* This is technically wrong, and hpsa controllers should
  4901. * reject it with CMD_INVALID, which is the most correct
  4902. * response, but non-fibre backends appear to let it
  4903. * slide by, and give the same results as if this field
  4904. * were set correctly. Either way is acceptable for
  4905. * our purposes here.
  4906. */
  4907. break;
  4908. default:
  4909. dev_err(&h->pdev->dev, "unknown data direction: %d\n",
  4910. cmd->sc_data_direction);
  4911. BUG();
  4912. break;
  4913. }
  4914. if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
  4915. hpsa_cmd_resolve_and_free(h, c);
  4916. return SCSI_MLQUEUE_HOST_BUSY;
  4917. }
  4918. if (dev->in_reset) {
  4919. hpsa_cmd_resolve_and_free(h, c);
  4920. return SCSI_MLQUEUE_HOST_BUSY;
  4921. }
  4922. c->device = dev;
  4923. enqueue_cmd_and_start_io(h, c);
  4924. /* the cmd'll come back via intr handler in complete_scsi_command() */
  4925. return 0;
  4926. }
  4927. static void hpsa_cmd_init(struct ctlr_info *h, int index,
  4928. struct CommandList *c)
  4929. {
  4930. dma_addr_t cmd_dma_handle, err_dma_handle;
  4931. /* Zero out all of commandlist except the last field, refcount */
  4932. memset(c, 0, offsetof(struct CommandList, refcount));
  4933. c->Header.tag = cpu_to_le64((u64) (index << DIRECT_LOOKUP_SHIFT));
  4934. cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
  4935. c->err_info = h->errinfo_pool + index;
  4936. memset(c->err_info, 0, sizeof(*c->err_info));
  4937. err_dma_handle = h->errinfo_pool_dhandle
  4938. + index * sizeof(*c->err_info);
  4939. c->cmdindex = index;
  4940. c->busaddr = (u32) cmd_dma_handle;
  4941. c->ErrDesc.Addr = cpu_to_le64((u64) err_dma_handle);
  4942. c->ErrDesc.Len = cpu_to_le32((u32) sizeof(*c->err_info));
  4943. c->h = h;
  4944. c->scsi_cmd = SCSI_CMD_IDLE;
  4945. }
  4946. static void hpsa_preinitialize_commands(struct ctlr_info *h)
  4947. {
  4948. int i;
  4949. for (i = 0; i < h->nr_cmds; i++) {
  4950. struct CommandList *c = h->cmd_pool + i;
  4951. hpsa_cmd_init(h, i, c);
  4952. atomic_set(&c->refcount, 0);
  4953. }
  4954. }
  4955. static inline void hpsa_cmd_partial_init(struct ctlr_info *h, int index,
  4956. struct CommandList *c)
  4957. {
  4958. dma_addr_t cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
  4959. BUG_ON(c->cmdindex != index);
  4960. memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
  4961. memset(c->err_info, 0, sizeof(*c->err_info));
  4962. c->busaddr = (u32) cmd_dma_handle;
  4963. }
  4964. static int hpsa_ioaccel_submit(struct ctlr_info *h,
  4965. struct CommandList *c, struct scsi_cmnd *cmd,
  4966. bool retry)
  4967. {
  4968. struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
  4969. int rc = IO_ACCEL_INELIGIBLE;
  4970. if (!dev)
  4971. return SCSI_MLQUEUE_HOST_BUSY;
  4972. if (dev->in_reset)
  4973. return SCSI_MLQUEUE_HOST_BUSY;
  4974. if (hpsa_simple_mode)
  4975. return IO_ACCEL_INELIGIBLE;
  4976. cmd->host_scribble = (unsigned char *) c;
  4977. if (dev->offload_enabled) {
  4978. hpsa_cmd_init(h, c->cmdindex, c); /* Zeroes out all fields */
  4979. c->cmd_type = CMD_SCSI;
  4980. c->scsi_cmd = cmd;
  4981. c->device = dev;
  4982. if (retry) /* Resubmit but do not increment device->commands_outstanding. */
  4983. c->retry_pending = true;
  4984. rc = hpsa_scsi_ioaccel_raid_map(h, c);
  4985. if (rc < 0) /* scsi_dma_map failed. */
  4986. rc = SCSI_MLQUEUE_HOST_BUSY;
  4987. } else if (dev->hba_ioaccel_enabled) {
  4988. hpsa_cmd_init(h, c->cmdindex, c); /* Zeroes out all fields */
  4989. c->cmd_type = CMD_SCSI;
  4990. c->scsi_cmd = cmd;
  4991. c->device = dev;
  4992. if (retry) /* Resubmit but do not increment device->commands_outstanding. */
  4993. c->retry_pending = true;
  4994. rc = hpsa_scsi_ioaccel_direct_map(h, c);
  4995. if (rc < 0) /* scsi_dma_map failed. */
  4996. rc = SCSI_MLQUEUE_HOST_BUSY;
  4997. }
  4998. return rc;
  4999. }
  5000. static void hpsa_command_resubmit_worker(struct work_struct *work)
  5001. {
  5002. struct scsi_cmnd *cmd;
  5003. struct hpsa_scsi_dev_t *dev;
  5004. struct CommandList *c = container_of(work, struct CommandList, work);
  5005. cmd = c->scsi_cmd;
  5006. dev = cmd->device->hostdata;
  5007. if (!dev) {
  5008. cmd->result = DID_NO_CONNECT << 16;
  5009. return hpsa_cmd_free_and_done(c->h, c, cmd);
  5010. }
  5011. if (dev->in_reset) {
  5012. cmd->result = DID_RESET << 16;
  5013. return hpsa_cmd_free_and_done(c->h, c, cmd);
  5014. }
  5015. if (c->cmd_type == CMD_IOACCEL2) {
  5016. struct ctlr_info *h = c->h;
  5017. struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
  5018. int rc;
  5019. if (c2->error_data.serv_response ==
  5020. IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL) {
  5021. /* Resubmit with the retry_pending flag set. */
  5022. rc = hpsa_ioaccel_submit(h, c, cmd, true);
  5023. if (rc == 0)
  5024. return;
  5025. if (rc == SCSI_MLQUEUE_HOST_BUSY) {
  5026. /*
  5027. * If we get here, it means dma mapping failed.
  5028. * Try again via scsi mid layer, which will
  5029. * then get SCSI_MLQUEUE_HOST_BUSY.
  5030. */
  5031. cmd->result = DID_IMM_RETRY << 16;
  5032. return hpsa_cmd_free_and_done(h, c, cmd);
  5033. }
  5034. /* else, fall thru and resubmit down CISS path */
  5035. }
  5036. }
  5037. hpsa_cmd_partial_init(c->h, c->cmdindex, c);
  5038. /*
  5039. * Here we have not come in though queue_command, so we
  5040. * can set the retry_pending flag to true for a driver initiated
  5041. * retry attempt (I.E. not a SML retry).
  5042. * I.E. We are submitting a driver initiated retry.
  5043. * Note: hpsa_ciss_submit does not zero out the command fields like
  5044. * ioaccel submit does.
  5045. */
  5046. c->retry_pending = true;
  5047. if (hpsa_ciss_submit(c->h, c, cmd, dev)) {
  5048. /*
  5049. * If we get here, it means dma mapping failed. Try
  5050. * again via scsi mid layer, which will then get
  5051. * SCSI_MLQUEUE_HOST_BUSY.
  5052. *
  5053. * hpsa_ciss_submit will have already freed c
  5054. * if it encountered a dma mapping failure.
  5055. */
  5056. cmd->result = DID_IMM_RETRY << 16;
  5057. scsi_done(cmd);
  5058. }
  5059. }
  5060. /* Running in struct Scsi_Host->host_lock less mode */
  5061. static int hpsa_scsi_queue_command(struct Scsi_Host *sh, struct scsi_cmnd *cmd)
  5062. {
  5063. struct ctlr_info *h;
  5064. struct hpsa_scsi_dev_t *dev;
  5065. struct CommandList *c;
  5066. int rc = 0;
  5067. /* Get the ptr to our adapter structure out of cmd->host. */
  5068. h = sdev_to_hba(cmd->device);
  5069. BUG_ON(scsi_cmd_to_rq(cmd)->tag < 0);
  5070. dev = cmd->device->hostdata;
  5071. if (!dev) {
  5072. cmd->result = DID_NO_CONNECT << 16;
  5073. scsi_done(cmd);
  5074. return 0;
  5075. }
  5076. if (dev->removed) {
  5077. cmd->result = DID_NO_CONNECT << 16;
  5078. scsi_done(cmd);
  5079. return 0;
  5080. }
  5081. if (unlikely(lockup_detected(h))) {
  5082. cmd->result = DID_NO_CONNECT << 16;
  5083. scsi_done(cmd);
  5084. return 0;
  5085. }
  5086. if (dev->in_reset)
  5087. return SCSI_MLQUEUE_DEVICE_BUSY;
  5088. c = cmd_tagged_alloc(h, cmd);
  5089. if (c == NULL)
  5090. return SCSI_MLQUEUE_DEVICE_BUSY;
  5091. /*
  5092. * This is necessary because the SML doesn't zero out this field during
  5093. * error recovery.
  5094. */
  5095. cmd->result = 0;
  5096. /*
  5097. * Call alternate submit routine for I/O accelerated commands.
  5098. * Retries always go down the normal I/O path.
  5099. * Note: If cmd->retries is non-zero, then this is a SML
  5100. * initiated retry and not a driver initiated retry.
  5101. * This command has been obtained from cmd_tagged_alloc
  5102. * and is therefore a brand-new command.
  5103. */
  5104. if (likely(cmd->retries == 0 &&
  5105. !blk_rq_is_passthrough(scsi_cmd_to_rq(cmd)) &&
  5106. h->acciopath_status)) {
  5107. /* Submit with the retry_pending flag unset. */
  5108. rc = hpsa_ioaccel_submit(h, c, cmd, false);
  5109. if (rc == 0)
  5110. return 0;
  5111. if (rc == SCSI_MLQUEUE_HOST_BUSY) {
  5112. hpsa_cmd_resolve_and_free(h, c);
  5113. return SCSI_MLQUEUE_HOST_BUSY;
  5114. }
  5115. }
  5116. return hpsa_ciss_submit(h, c, cmd, dev);
  5117. }
  5118. static void hpsa_scan_complete(struct ctlr_info *h)
  5119. {
  5120. unsigned long flags;
  5121. spin_lock_irqsave(&h->scan_lock, flags);
  5122. h->scan_finished = 1;
  5123. wake_up(&h->scan_wait_queue);
  5124. spin_unlock_irqrestore(&h->scan_lock, flags);
  5125. }
  5126. static void hpsa_scan_start(struct Scsi_Host *sh)
  5127. {
  5128. struct ctlr_info *h = shost_to_hba(sh);
  5129. unsigned long flags;
  5130. /*
  5131. * Don't let rescans be initiated on a controller known to be locked
  5132. * up. If the controller locks up *during* a rescan, that thread is
  5133. * probably hosed, but at least we can prevent new rescan threads from
  5134. * piling up on a locked up controller.
  5135. */
  5136. if (unlikely(lockup_detected(h)))
  5137. return hpsa_scan_complete(h);
  5138. /*
  5139. * If a scan is already waiting to run, no need to add another
  5140. */
  5141. spin_lock_irqsave(&h->scan_lock, flags);
  5142. if (h->scan_waiting) {
  5143. spin_unlock_irqrestore(&h->scan_lock, flags);
  5144. return;
  5145. }
  5146. spin_unlock_irqrestore(&h->scan_lock, flags);
  5147. /* wait until any scan already in progress is finished. */
  5148. while (1) {
  5149. spin_lock_irqsave(&h->scan_lock, flags);
  5150. if (h->scan_finished)
  5151. break;
  5152. h->scan_waiting = 1;
  5153. spin_unlock_irqrestore(&h->scan_lock, flags);
  5154. wait_event(h->scan_wait_queue, h->scan_finished);
  5155. /* Note: We don't need to worry about a race between this
  5156. * thread and driver unload because the midlayer will
  5157. * have incremented the reference count, so unload won't
  5158. * happen if we're in here.
  5159. */
  5160. }
  5161. h->scan_finished = 0; /* mark scan as in progress */
  5162. h->scan_waiting = 0;
  5163. spin_unlock_irqrestore(&h->scan_lock, flags);
  5164. if (unlikely(lockup_detected(h)))
  5165. return hpsa_scan_complete(h);
  5166. /*
  5167. * Do the scan after a reset completion
  5168. */
  5169. spin_lock_irqsave(&h->reset_lock, flags);
  5170. if (h->reset_in_progress) {
  5171. h->drv_req_rescan = 1;
  5172. spin_unlock_irqrestore(&h->reset_lock, flags);
  5173. hpsa_scan_complete(h);
  5174. return;
  5175. }
  5176. spin_unlock_irqrestore(&h->reset_lock, flags);
  5177. hpsa_update_scsi_devices(h);
  5178. hpsa_scan_complete(h);
  5179. }
  5180. static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth)
  5181. {
  5182. struct hpsa_scsi_dev_t *logical_drive = sdev->hostdata;
  5183. if (!logical_drive)
  5184. return -ENODEV;
  5185. if (qdepth < 1)
  5186. qdepth = 1;
  5187. else if (qdepth > logical_drive->queue_depth)
  5188. qdepth = logical_drive->queue_depth;
  5189. return scsi_change_queue_depth(sdev, qdepth);
  5190. }
  5191. static int hpsa_scan_finished(struct Scsi_Host *sh,
  5192. unsigned long elapsed_time)
  5193. {
  5194. struct ctlr_info *h = shost_to_hba(sh);
  5195. unsigned long flags;
  5196. int finished;
  5197. spin_lock_irqsave(&h->scan_lock, flags);
  5198. finished = h->scan_finished;
  5199. spin_unlock_irqrestore(&h->scan_lock, flags);
  5200. return finished;
  5201. }
  5202. static int hpsa_scsi_host_alloc(struct ctlr_info *h)
  5203. {
  5204. struct Scsi_Host *sh;
  5205. sh = scsi_host_alloc(&hpsa_driver_template, sizeof(struct ctlr_info));
  5206. if (sh == NULL) {
  5207. dev_err(&h->pdev->dev, "scsi_host_alloc failed\n");
  5208. return -ENOMEM;
  5209. }
  5210. sh->io_port = 0;
  5211. sh->n_io_port = 0;
  5212. sh->this_id = -1;
  5213. sh->max_channel = 3;
  5214. sh->max_cmd_len = MAX_COMMAND_SIZE;
  5215. sh->max_lun = HPSA_MAX_LUN;
  5216. sh->max_id = HPSA_MAX_LUN;
  5217. sh->can_queue = h->nr_cmds - HPSA_NRESERVED_CMDS;
  5218. sh->cmd_per_lun = sh->can_queue;
  5219. sh->sg_tablesize = h->maxsgentries;
  5220. sh->transportt = hpsa_sas_transport_template;
  5221. sh->hostdata[0] = (unsigned long) h;
  5222. sh->irq = pci_irq_vector(h->pdev, 0);
  5223. sh->unique_id = sh->irq;
  5224. h->scsi_host = sh;
  5225. return 0;
  5226. }
  5227. static int hpsa_scsi_add_host(struct ctlr_info *h)
  5228. {
  5229. int rv;
  5230. rv = scsi_add_host(h->scsi_host, &h->pdev->dev);
  5231. if (rv) {
  5232. dev_err(&h->pdev->dev, "scsi_add_host failed\n");
  5233. return rv;
  5234. }
  5235. scsi_scan_host(h->scsi_host);
  5236. return 0;
  5237. }
  5238. /*
  5239. * The block layer has already gone to the trouble of picking out a unique,
  5240. * small-integer tag for this request. We use an offset from that value as
  5241. * an index to select our command block. (The offset allows us to reserve the
  5242. * low-numbered entries for our own uses.)
  5243. */
  5244. static int hpsa_get_cmd_index(struct scsi_cmnd *scmd)
  5245. {
  5246. int idx = scsi_cmd_to_rq(scmd)->tag;
  5247. if (idx < 0)
  5248. return idx;
  5249. /* Offset to leave space for internal cmds. */
  5250. return idx += HPSA_NRESERVED_CMDS;
  5251. }
  5252. /*
  5253. * Send a TEST_UNIT_READY command to the specified LUN using the specified
  5254. * reply queue; returns zero if the unit is ready, and non-zero otherwise.
  5255. */
  5256. static int hpsa_send_test_unit_ready(struct ctlr_info *h,
  5257. struct CommandList *c, unsigned char lunaddr[],
  5258. int reply_queue)
  5259. {
  5260. int rc;
  5261. /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
  5262. (void) fill_cmd(c, TEST_UNIT_READY, h,
  5263. NULL, 0, 0, lunaddr, TYPE_CMD);
  5264. rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
  5265. if (rc)
  5266. return rc;
  5267. /* no unmap needed here because no data xfer. */
  5268. /* Check if the unit is already ready. */
  5269. if (c->err_info->CommandStatus == CMD_SUCCESS)
  5270. return 0;
  5271. /*
  5272. * The first command sent after reset will receive "unit attention" to
  5273. * indicate that the LUN has been reset...this is actually what we're
  5274. * looking for (but, success is good too).
  5275. */
  5276. if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
  5277. c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
  5278. (c->err_info->SenseInfo[2] == NO_SENSE ||
  5279. c->err_info->SenseInfo[2] == UNIT_ATTENTION))
  5280. return 0;
  5281. return 1;
  5282. }
  5283. /*
  5284. * Wait for a TEST_UNIT_READY command to complete, retrying as necessary;
  5285. * returns zero when the unit is ready, and non-zero when giving up.
  5286. */
  5287. static int hpsa_wait_for_test_unit_ready(struct ctlr_info *h,
  5288. struct CommandList *c,
  5289. unsigned char lunaddr[], int reply_queue)
  5290. {
  5291. int rc;
  5292. int count = 0;
  5293. int waittime = 1; /* seconds */
  5294. /* Send test unit ready until device ready, or give up. */
  5295. for (count = 0; count < HPSA_TUR_RETRY_LIMIT; count++) {
  5296. /*
  5297. * Wait for a bit. do this first, because if we send
  5298. * the TUR right away, the reset will just abort it.
  5299. */
  5300. msleep(1000 * waittime);
  5301. rc = hpsa_send_test_unit_ready(h, c, lunaddr, reply_queue);
  5302. if (!rc)
  5303. break;
  5304. /* Increase wait time with each try, up to a point. */
  5305. if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
  5306. waittime *= 2;
  5307. dev_warn(&h->pdev->dev,
  5308. "waiting %d secs for device to become ready.\n",
  5309. waittime);
  5310. }
  5311. return rc;
  5312. }
  5313. static int wait_for_device_to_become_ready(struct ctlr_info *h,
  5314. unsigned char lunaddr[],
  5315. int reply_queue)
  5316. {
  5317. int first_queue;
  5318. int last_queue;
  5319. int rq;
  5320. int rc = 0;
  5321. struct CommandList *c;
  5322. c = cmd_alloc(h);
  5323. /*
  5324. * If no specific reply queue was requested, then send the TUR
  5325. * repeatedly, requesting a reply on each reply queue; otherwise execute
  5326. * the loop exactly once using only the specified queue.
  5327. */
  5328. if (reply_queue == DEFAULT_REPLY_QUEUE) {
  5329. first_queue = 0;
  5330. last_queue = h->nreply_queues - 1;
  5331. } else {
  5332. first_queue = reply_queue;
  5333. last_queue = reply_queue;
  5334. }
  5335. for (rq = first_queue; rq <= last_queue; rq++) {
  5336. rc = hpsa_wait_for_test_unit_ready(h, c, lunaddr, rq);
  5337. if (rc)
  5338. break;
  5339. }
  5340. if (rc)
  5341. dev_warn(&h->pdev->dev, "giving up on device.\n");
  5342. else
  5343. dev_warn(&h->pdev->dev, "device is ready.\n");
  5344. cmd_free(h, c);
  5345. return rc;
  5346. }
  5347. /* Need at least one of these error handlers to keep ../scsi/hosts.c from
  5348. * complaining. Doing a host- or bus-reset can't do anything good here.
  5349. */
  5350. static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
  5351. {
  5352. int rc = SUCCESS;
  5353. int i;
  5354. struct ctlr_info *h;
  5355. struct hpsa_scsi_dev_t *dev = NULL;
  5356. u8 reset_type;
  5357. char msg[48];
  5358. unsigned long flags;
  5359. /* find the controller to which the command to be aborted was sent */
  5360. h = sdev_to_hba(scsicmd->device);
  5361. if (h == NULL) /* paranoia */
  5362. return FAILED;
  5363. spin_lock_irqsave(&h->reset_lock, flags);
  5364. h->reset_in_progress = 1;
  5365. spin_unlock_irqrestore(&h->reset_lock, flags);
  5366. if (lockup_detected(h)) {
  5367. rc = FAILED;
  5368. goto return_reset_status;
  5369. }
  5370. dev = scsicmd->device->hostdata;
  5371. if (!dev) {
  5372. dev_err(&h->pdev->dev, "%s: device lookup failed\n", __func__);
  5373. rc = FAILED;
  5374. goto return_reset_status;
  5375. }
  5376. if (dev->devtype == TYPE_ENCLOSURE) {
  5377. rc = SUCCESS;
  5378. goto return_reset_status;
  5379. }
  5380. /* if controller locked up, we can guarantee command won't complete */
  5381. if (lockup_detected(h)) {
  5382. snprintf(msg, sizeof(msg),
  5383. "cmd %d RESET FAILED, lockup detected",
  5384. hpsa_get_cmd_index(scsicmd));
  5385. hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
  5386. rc = FAILED;
  5387. goto return_reset_status;
  5388. }
  5389. /* this reset request might be the result of a lockup; check */
  5390. if (detect_controller_lockup(h)) {
  5391. snprintf(msg, sizeof(msg),
  5392. "cmd %d RESET FAILED, new lockup detected",
  5393. hpsa_get_cmd_index(scsicmd));
  5394. hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
  5395. rc = FAILED;
  5396. goto return_reset_status;
  5397. }
  5398. /* Do not attempt on controller */
  5399. if (is_hba_lunid(dev->scsi3addr)) {
  5400. rc = SUCCESS;
  5401. goto return_reset_status;
  5402. }
  5403. if (is_logical_dev_addr_mode(dev->scsi3addr))
  5404. reset_type = HPSA_DEVICE_RESET_MSG;
  5405. else
  5406. reset_type = HPSA_PHYS_TARGET_RESET;
  5407. sprintf(msg, "resetting %s",
  5408. reset_type == HPSA_DEVICE_RESET_MSG ? "logical " : "physical ");
  5409. hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
  5410. /*
  5411. * wait to see if any commands will complete before sending reset
  5412. */
  5413. dev->in_reset = true; /* block any new cmds from OS for this device */
  5414. for (i = 0; i < 10; i++) {
  5415. if (atomic_read(&dev->commands_outstanding) > 0)
  5416. msleep(1000);
  5417. else
  5418. break;
  5419. }
  5420. /* send a reset to the SCSI LUN which the command was sent to */
  5421. rc = hpsa_do_reset(h, dev, reset_type, DEFAULT_REPLY_QUEUE);
  5422. if (rc == 0)
  5423. rc = SUCCESS;
  5424. else
  5425. rc = FAILED;
  5426. sprintf(msg, "reset %s %s",
  5427. reset_type == HPSA_DEVICE_RESET_MSG ? "logical " : "physical ",
  5428. rc == SUCCESS ? "completed successfully" : "failed");
  5429. hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
  5430. return_reset_status:
  5431. spin_lock_irqsave(&h->reset_lock, flags);
  5432. h->reset_in_progress = 0;
  5433. if (dev)
  5434. dev->in_reset = false;
  5435. spin_unlock_irqrestore(&h->reset_lock, flags);
  5436. return rc;
  5437. }
  5438. /*
  5439. * For operations with an associated SCSI command, a command block is allocated
  5440. * at init, and managed by cmd_tagged_alloc() and cmd_tagged_free() using the
  5441. * block request tag as an index into a table of entries. cmd_tagged_free() is
  5442. * the complement, although cmd_free() may be called instead.
  5443. * This function is only called for new requests from queue_command.
  5444. */
  5445. static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
  5446. struct scsi_cmnd *scmd)
  5447. {
  5448. int idx = hpsa_get_cmd_index(scmd);
  5449. struct CommandList *c = h->cmd_pool + idx;
  5450. if (idx < HPSA_NRESERVED_CMDS || idx >= h->nr_cmds) {
  5451. dev_err(&h->pdev->dev, "Bad block tag: %d not in [%d..%d]\n",
  5452. idx, HPSA_NRESERVED_CMDS, h->nr_cmds - 1);
  5453. /* The index value comes from the block layer, so if it's out of
  5454. * bounds, it's probably not our bug.
  5455. */
  5456. BUG();
  5457. }
  5458. if (unlikely(!hpsa_is_cmd_idle(c))) {
  5459. /*
  5460. * We expect that the SCSI layer will hand us a unique tag
  5461. * value. Thus, there should never be a collision here between
  5462. * two requests...because if the selected command isn't idle
  5463. * then someone is going to be very disappointed.
  5464. */
  5465. if (idx != h->last_collision_tag) { /* Print once per tag */
  5466. dev_warn(&h->pdev->dev,
  5467. "%s: tag collision (tag=%d)\n", __func__, idx);
  5468. if (scmd)
  5469. scsi_print_command(scmd);
  5470. h->last_collision_tag = idx;
  5471. }
  5472. return NULL;
  5473. }
  5474. atomic_inc(&c->refcount);
  5475. hpsa_cmd_partial_init(h, idx, c);
  5476. /*
  5477. * This is a new command obtained from queue_command so
  5478. * there have not been any driver initiated retry attempts.
  5479. */
  5480. c->retry_pending = false;
  5481. return c;
  5482. }
  5483. static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c)
  5484. {
  5485. /*
  5486. * Release our reference to the block. We don't need to do anything
  5487. * else to free it, because it is accessed by index.
  5488. */
  5489. (void)atomic_dec(&c->refcount);
  5490. }
  5491. /*
  5492. * For operations that cannot sleep, a command block is allocated at init,
  5493. * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
  5494. * which ones are free or in use. Lock must be held when calling this.
  5495. * cmd_free() is the complement.
  5496. * This function never gives up and returns NULL. If it hangs,
  5497. * another thread must call cmd_free() to free some tags.
  5498. */
  5499. static struct CommandList *cmd_alloc(struct ctlr_info *h)
  5500. {
  5501. struct CommandList *c;
  5502. int refcount, i;
  5503. int offset = 0;
  5504. /*
  5505. * There is some *extremely* small but non-zero chance that that
  5506. * multiple threads could get in here, and one thread could
  5507. * be scanning through the list of bits looking for a free
  5508. * one, but the free ones are always behind him, and other
  5509. * threads sneak in behind him and eat them before he can
  5510. * get to them, so that while there is always a free one, a
  5511. * very unlucky thread might be starved anyway, never able to
  5512. * beat the other threads. In reality, this happens so
  5513. * infrequently as to be indistinguishable from never.
  5514. *
  5515. * Note that we start allocating commands before the SCSI host structure
  5516. * is initialized. Since the search starts at bit zero, this
  5517. * all works, since we have at least one command structure available;
  5518. * however, it means that the structures with the low indexes have to be
  5519. * reserved for driver-initiated requests, while requests from the block
  5520. * layer will use the higher indexes.
  5521. */
  5522. for (;;) {
  5523. i = find_next_zero_bit(h->cmd_pool_bits,
  5524. HPSA_NRESERVED_CMDS,
  5525. offset);
  5526. if (unlikely(i >= HPSA_NRESERVED_CMDS)) {
  5527. offset = 0;
  5528. continue;
  5529. }
  5530. c = h->cmd_pool + i;
  5531. refcount = atomic_inc_return(&c->refcount);
  5532. if (unlikely(refcount > 1)) {
  5533. cmd_free(h, c); /* already in use */
  5534. offset = (i + 1) % HPSA_NRESERVED_CMDS;
  5535. continue;
  5536. }
  5537. set_bit(i, h->cmd_pool_bits);
  5538. break; /* it's ours now. */
  5539. }
  5540. hpsa_cmd_partial_init(h, i, c);
  5541. c->device = NULL;
  5542. /*
  5543. * cmd_alloc is for "internal" commands and they are never
  5544. * retried.
  5545. */
  5546. c->retry_pending = false;
  5547. return c;
  5548. }
  5549. /*
  5550. * This is the complementary operation to cmd_alloc(). Note, however, in some
  5551. * corner cases it may also be used to free blocks allocated by
  5552. * cmd_tagged_alloc() in which case the ref-count decrement does the trick and
  5553. * the clear-bit is harmless.
  5554. */
  5555. static void cmd_free(struct ctlr_info *h, struct CommandList *c)
  5556. {
  5557. if (atomic_dec_and_test(&c->refcount)) {
  5558. int i;
  5559. i = c - h->cmd_pool;
  5560. clear_bit(i, h->cmd_pool_bits);
  5561. }
  5562. }
  5563. #ifdef CONFIG_COMPAT
  5564. static int hpsa_ioctl32_passthru(struct scsi_device *dev, unsigned int cmd,
  5565. void __user *arg)
  5566. {
  5567. struct ctlr_info *h = sdev_to_hba(dev);
  5568. IOCTL32_Command_struct __user *arg32 = arg;
  5569. IOCTL_Command_struct arg64;
  5570. int err;
  5571. u32 cp;
  5572. if (!arg)
  5573. return -EINVAL;
  5574. memset(&arg64, 0, sizeof(arg64));
  5575. if (copy_from_user(&arg64, arg32, offsetof(IOCTL_Command_struct, buf)))
  5576. return -EFAULT;
  5577. if (get_user(cp, &arg32->buf))
  5578. return -EFAULT;
  5579. arg64.buf = compat_ptr(cp);
  5580. if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
  5581. return -EAGAIN;
  5582. err = hpsa_passthru_ioctl(h, &arg64);
  5583. atomic_inc(&h->passthru_cmds_avail);
  5584. if (err)
  5585. return err;
  5586. if (copy_to_user(&arg32->error_info, &arg64.error_info,
  5587. sizeof(arg32->error_info)))
  5588. return -EFAULT;
  5589. return 0;
  5590. }
  5591. static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
  5592. unsigned int cmd, void __user *arg)
  5593. {
  5594. struct ctlr_info *h = sdev_to_hba(dev);
  5595. BIG_IOCTL32_Command_struct __user *arg32 = arg;
  5596. BIG_IOCTL_Command_struct arg64;
  5597. int err;
  5598. u32 cp;
  5599. if (!arg)
  5600. return -EINVAL;
  5601. memset(&arg64, 0, sizeof(arg64));
  5602. if (copy_from_user(&arg64, arg32,
  5603. offsetof(BIG_IOCTL32_Command_struct, buf)))
  5604. return -EFAULT;
  5605. if (get_user(cp, &arg32->buf))
  5606. return -EFAULT;
  5607. arg64.buf = compat_ptr(cp);
  5608. if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
  5609. return -EAGAIN;
  5610. err = hpsa_big_passthru_ioctl(h, &arg64);
  5611. atomic_inc(&h->passthru_cmds_avail);
  5612. if (err)
  5613. return err;
  5614. if (copy_to_user(&arg32->error_info, &arg64.error_info,
  5615. sizeof(arg32->error_info)))
  5616. return -EFAULT;
  5617. return 0;
  5618. }
  5619. static int hpsa_compat_ioctl(struct scsi_device *dev, unsigned int cmd,
  5620. void __user *arg)
  5621. {
  5622. switch (cmd) {
  5623. case CCISS_GETPCIINFO:
  5624. case CCISS_GETINTINFO:
  5625. case CCISS_SETINTINFO:
  5626. case CCISS_GETNODENAME:
  5627. case CCISS_SETNODENAME:
  5628. case CCISS_GETHEARTBEAT:
  5629. case CCISS_GETBUSTYPES:
  5630. case CCISS_GETFIRMVER:
  5631. case CCISS_GETDRIVVER:
  5632. case CCISS_REVALIDVOLS:
  5633. case CCISS_DEREGDISK:
  5634. case CCISS_REGNEWDISK:
  5635. case CCISS_REGNEWD:
  5636. case CCISS_RESCANDISK:
  5637. case CCISS_GETLUNINFO:
  5638. return hpsa_ioctl(dev, cmd, arg);
  5639. case CCISS_PASSTHRU32:
  5640. return hpsa_ioctl32_passthru(dev, cmd, arg);
  5641. case CCISS_BIG_PASSTHRU32:
  5642. return hpsa_ioctl32_big_passthru(dev, cmd, arg);
  5643. default:
  5644. return -ENOIOCTLCMD;
  5645. }
  5646. }
  5647. #endif
  5648. static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
  5649. {
  5650. struct hpsa_pci_info pciinfo;
  5651. if (!argp)
  5652. return -EINVAL;
  5653. pciinfo.domain = pci_domain_nr(h->pdev->bus);
  5654. pciinfo.bus = h->pdev->bus->number;
  5655. pciinfo.dev_fn = h->pdev->devfn;
  5656. pciinfo.board_id = h->board_id;
  5657. if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
  5658. return -EFAULT;
  5659. return 0;
  5660. }
  5661. static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
  5662. {
  5663. DriverVer_type DriverVer;
  5664. unsigned char vmaj, vmin, vsubmin;
  5665. int rc;
  5666. rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
  5667. &vmaj, &vmin, &vsubmin);
  5668. if (rc != 3) {
  5669. dev_info(&h->pdev->dev, "driver version string '%s' "
  5670. "unrecognized.", HPSA_DRIVER_VERSION);
  5671. vmaj = 0;
  5672. vmin = 0;
  5673. vsubmin = 0;
  5674. }
  5675. DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
  5676. if (!argp)
  5677. return -EINVAL;
  5678. if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
  5679. return -EFAULT;
  5680. return 0;
  5681. }
  5682. static int hpsa_passthru_ioctl(struct ctlr_info *h,
  5683. IOCTL_Command_struct *iocommand)
  5684. {
  5685. struct CommandList *c;
  5686. char *buff = NULL;
  5687. u64 temp64;
  5688. int rc = 0;
  5689. if (!capable(CAP_SYS_RAWIO))
  5690. return -EPERM;
  5691. if ((iocommand->buf_size < 1) &&
  5692. (iocommand->Request.Type.Direction != XFER_NONE)) {
  5693. return -EINVAL;
  5694. }
  5695. if (iocommand->buf_size > 0) {
  5696. buff = kmalloc(iocommand->buf_size, GFP_KERNEL);
  5697. if (buff == NULL)
  5698. return -ENOMEM;
  5699. if (iocommand->Request.Type.Direction & XFER_WRITE) {
  5700. /* Copy the data into the buffer we created */
  5701. if (copy_from_user(buff, iocommand->buf,
  5702. iocommand->buf_size)) {
  5703. rc = -EFAULT;
  5704. goto out_kfree;
  5705. }
  5706. } else {
  5707. memset(buff, 0, iocommand->buf_size);
  5708. }
  5709. }
  5710. c = cmd_alloc(h);
  5711. /* Fill in the command type */
  5712. c->cmd_type = CMD_IOCTL_PEND;
  5713. c->scsi_cmd = SCSI_CMD_BUSY;
  5714. /* Fill in Command Header */
  5715. c->Header.ReplyQueue = 0; /* unused in simple mode */
  5716. if (iocommand->buf_size > 0) { /* buffer to fill */
  5717. c->Header.SGList = 1;
  5718. c->Header.SGTotal = cpu_to_le16(1);
  5719. } else { /* no buffers to fill */
  5720. c->Header.SGList = 0;
  5721. c->Header.SGTotal = cpu_to_le16(0);
  5722. }
  5723. memcpy(&c->Header.LUN, &iocommand->LUN_info, sizeof(c->Header.LUN));
  5724. /* Fill in Request block */
  5725. memcpy(&c->Request, &iocommand->Request,
  5726. sizeof(c->Request));
  5727. /* Fill in the scatter gather information */
  5728. if (iocommand->buf_size > 0) {
  5729. temp64 = dma_map_single(&h->pdev->dev, buff,
  5730. iocommand->buf_size, DMA_BIDIRECTIONAL);
  5731. if (dma_mapping_error(&h->pdev->dev, (dma_addr_t) temp64)) {
  5732. c->SG[0].Addr = cpu_to_le64(0);
  5733. c->SG[0].Len = cpu_to_le32(0);
  5734. rc = -ENOMEM;
  5735. goto out;
  5736. }
  5737. c->SG[0].Addr = cpu_to_le64(temp64);
  5738. c->SG[0].Len = cpu_to_le32(iocommand->buf_size);
  5739. c->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* not chaining */
  5740. }
  5741. rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
  5742. NO_TIMEOUT);
  5743. if (iocommand->buf_size > 0)
  5744. hpsa_pci_unmap(h->pdev, c, 1, DMA_BIDIRECTIONAL);
  5745. check_ioctl_unit_attention(h, c);
  5746. if (rc) {
  5747. rc = -EIO;
  5748. goto out;
  5749. }
  5750. /* Copy the error information out */
  5751. memcpy(&iocommand->error_info, c->err_info,
  5752. sizeof(iocommand->error_info));
  5753. if ((iocommand->Request.Type.Direction & XFER_READ) &&
  5754. iocommand->buf_size > 0) {
  5755. /* Copy the data out of the buffer we created */
  5756. if (copy_to_user(iocommand->buf, buff, iocommand->buf_size)) {
  5757. rc = -EFAULT;
  5758. goto out;
  5759. }
  5760. }
  5761. out:
  5762. cmd_free(h, c);
  5763. out_kfree:
  5764. kfree(buff);
  5765. return rc;
  5766. }
  5767. static int hpsa_big_passthru_ioctl(struct ctlr_info *h,
  5768. BIG_IOCTL_Command_struct *ioc)
  5769. {
  5770. struct CommandList *c;
  5771. unsigned char **buff = NULL;
  5772. int *buff_size = NULL;
  5773. u64 temp64;
  5774. BYTE sg_used = 0;
  5775. int status = 0;
  5776. u32 left;
  5777. u32 sz;
  5778. BYTE __user *data_ptr;
  5779. if (!capable(CAP_SYS_RAWIO))
  5780. return -EPERM;
  5781. if ((ioc->buf_size < 1) &&
  5782. (ioc->Request.Type.Direction != XFER_NONE))
  5783. return -EINVAL;
  5784. /* Check kmalloc limits using all SGs */
  5785. if (ioc->malloc_size > MAX_KMALLOC_SIZE)
  5786. return -EINVAL;
  5787. if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD)
  5788. return -EINVAL;
  5789. buff = kcalloc(SG_ENTRIES_IN_CMD, sizeof(char *), GFP_KERNEL);
  5790. if (!buff) {
  5791. status = -ENOMEM;
  5792. goto cleanup1;
  5793. }
  5794. buff_size = kmalloc_array(SG_ENTRIES_IN_CMD, sizeof(int), GFP_KERNEL);
  5795. if (!buff_size) {
  5796. status = -ENOMEM;
  5797. goto cleanup1;
  5798. }
  5799. left = ioc->buf_size;
  5800. data_ptr = ioc->buf;
  5801. while (left) {
  5802. sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
  5803. buff_size[sg_used] = sz;
  5804. buff[sg_used] = kmalloc(sz, GFP_KERNEL);
  5805. if (buff[sg_used] == NULL) {
  5806. status = -ENOMEM;
  5807. goto cleanup1;
  5808. }
  5809. if (ioc->Request.Type.Direction & XFER_WRITE) {
  5810. if (copy_from_user(buff[sg_used], data_ptr, sz)) {
  5811. status = -EFAULT;
  5812. goto cleanup1;
  5813. }
  5814. } else
  5815. memset(buff[sg_used], 0, sz);
  5816. left -= sz;
  5817. data_ptr += sz;
  5818. sg_used++;
  5819. }
  5820. c = cmd_alloc(h);
  5821. c->cmd_type = CMD_IOCTL_PEND;
  5822. c->scsi_cmd = SCSI_CMD_BUSY;
  5823. c->Header.ReplyQueue = 0;
  5824. c->Header.SGList = (u8) sg_used;
  5825. c->Header.SGTotal = cpu_to_le16(sg_used);
  5826. memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
  5827. memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
  5828. if (ioc->buf_size > 0) {
  5829. int i;
  5830. for (i = 0; i < sg_used; i++) {
  5831. temp64 = dma_map_single(&h->pdev->dev, buff[i],
  5832. buff_size[i], DMA_BIDIRECTIONAL);
  5833. if (dma_mapping_error(&h->pdev->dev,
  5834. (dma_addr_t) temp64)) {
  5835. c->SG[i].Addr = cpu_to_le64(0);
  5836. c->SG[i].Len = cpu_to_le32(0);
  5837. hpsa_pci_unmap(h->pdev, c, i,
  5838. DMA_BIDIRECTIONAL);
  5839. status = -ENOMEM;
  5840. goto cleanup0;
  5841. }
  5842. c->SG[i].Addr = cpu_to_le64(temp64);
  5843. c->SG[i].Len = cpu_to_le32(buff_size[i]);
  5844. c->SG[i].Ext = cpu_to_le32(0);
  5845. }
  5846. c->SG[--i].Ext = cpu_to_le32(HPSA_SG_LAST);
  5847. }
  5848. status = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
  5849. NO_TIMEOUT);
  5850. if (sg_used)
  5851. hpsa_pci_unmap(h->pdev, c, sg_used, DMA_BIDIRECTIONAL);
  5852. check_ioctl_unit_attention(h, c);
  5853. if (status) {
  5854. status = -EIO;
  5855. goto cleanup0;
  5856. }
  5857. /* Copy the error information out */
  5858. memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
  5859. if ((ioc->Request.Type.Direction & XFER_READ) && ioc->buf_size > 0) {
  5860. int i;
  5861. /* Copy the data out of the buffer we created */
  5862. BYTE __user *ptr = ioc->buf;
  5863. for (i = 0; i < sg_used; i++) {
  5864. if (copy_to_user(ptr, buff[i], buff_size[i])) {
  5865. status = -EFAULT;
  5866. goto cleanup0;
  5867. }
  5868. ptr += buff_size[i];
  5869. }
  5870. }
  5871. status = 0;
  5872. cleanup0:
  5873. cmd_free(h, c);
  5874. cleanup1:
  5875. if (buff) {
  5876. int i;
  5877. for (i = 0; i < sg_used; i++)
  5878. kfree(buff[i]);
  5879. kfree(buff);
  5880. }
  5881. kfree(buff_size);
  5882. return status;
  5883. }
  5884. static void check_ioctl_unit_attention(struct ctlr_info *h,
  5885. struct CommandList *c)
  5886. {
  5887. if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
  5888. c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
  5889. (void) check_for_unit_attention(h, c);
  5890. }
  5891. /*
  5892. * ioctl
  5893. */
  5894. static int hpsa_ioctl(struct scsi_device *dev, unsigned int cmd,
  5895. void __user *argp)
  5896. {
  5897. struct ctlr_info *h = sdev_to_hba(dev);
  5898. int rc;
  5899. switch (cmd) {
  5900. case CCISS_DEREGDISK:
  5901. case CCISS_REGNEWDISK:
  5902. case CCISS_REGNEWD:
  5903. hpsa_scan_start(h->scsi_host);
  5904. return 0;
  5905. case CCISS_GETPCIINFO:
  5906. return hpsa_getpciinfo_ioctl(h, argp);
  5907. case CCISS_GETDRIVVER:
  5908. return hpsa_getdrivver_ioctl(h, argp);
  5909. case CCISS_PASSTHRU: {
  5910. IOCTL_Command_struct iocommand;
  5911. if (!argp)
  5912. return -EINVAL;
  5913. if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
  5914. return -EFAULT;
  5915. if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
  5916. return -EAGAIN;
  5917. rc = hpsa_passthru_ioctl(h, &iocommand);
  5918. atomic_inc(&h->passthru_cmds_avail);
  5919. if (!rc && copy_to_user(argp, &iocommand, sizeof(iocommand)))
  5920. rc = -EFAULT;
  5921. return rc;
  5922. }
  5923. case CCISS_BIG_PASSTHRU: {
  5924. BIG_IOCTL_Command_struct ioc;
  5925. if (!argp)
  5926. return -EINVAL;
  5927. if (copy_from_user(&ioc, argp, sizeof(ioc)))
  5928. return -EFAULT;
  5929. if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
  5930. return -EAGAIN;
  5931. rc = hpsa_big_passthru_ioctl(h, &ioc);
  5932. atomic_inc(&h->passthru_cmds_avail);
  5933. if (!rc && copy_to_user(argp, &ioc, sizeof(ioc)))
  5934. rc = -EFAULT;
  5935. return rc;
  5936. }
  5937. default:
  5938. return -ENOTTY;
  5939. }
  5940. }
  5941. static void hpsa_send_host_reset(struct ctlr_info *h, u8 reset_type)
  5942. {
  5943. struct CommandList *c;
  5944. c = cmd_alloc(h);
  5945. /* fill_cmd can't fail here, no data buffer to map */
  5946. (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
  5947. RAID_CTLR_LUNID, TYPE_MSG);
  5948. c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
  5949. c->waiting = NULL;
  5950. enqueue_cmd_and_start_io(h, c);
  5951. /* Don't wait for completion, the reset won't complete. Don't free
  5952. * the command either. This is the last command we will send before
  5953. * re-initializing everything, so it doesn't matter and won't leak.
  5954. */
  5955. return;
  5956. }
  5957. static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
  5958. void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
  5959. int cmd_type)
  5960. {
  5961. enum dma_data_direction dir = DMA_NONE;
  5962. c->cmd_type = CMD_IOCTL_PEND;
  5963. c->scsi_cmd = SCSI_CMD_BUSY;
  5964. c->Header.ReplyQueue = 0;
  5965. if (buff != NULL && size > 0) {
  5966. c->Header.SGList = 1;
  5967. c->Header.SGTotal = cpu_to_le16(1);
  5968. } else {
  5969. c->Header.SGList = 0;
  5970. c->Header.SGTotal = cpu_to_le16(0);
  5971. }
  5972. memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
  5973. if (cmd_type == TYPE_CMD) {
  5974. switch (cmd) {
  5975. case HPSA_INQUIRY:
  5976. /* are we trying to read a vital product page */
  5977. if (page_code & VPD_PAGE) {
  5978. c->Request.CDB[1] = 0x01;
  5979. c->Request.CDB[2] = (page_code & 0xff);
  5980. }
  5981. c->Request.CDBLen = 6;
  5982. c->Request.type_attr_dir =
  5983. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
  5984. c->Request.Timeout = 0;
  5985. c->Request.CDB[0] = HPSA_INQUIRY;
  5986. c->Request.CDB[4] = size & 0xFF;
  5987. break;
  5988. case RECEIVE_DIAGNOSTIC:
  5989. c->Request.CDBLen = 6;
  5990. c->Request.type_attr_dir =
  5991. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
  5992. c->Request.Timeout = 0;
  5993. c->Request.CDB[0] = cmd;
  5994. c->Request.CDB[1] = 1;
  5995. c->Request.CDB[2] = 1;
  5996. c->Request.CDB[3] = (size >> 8) & 0xFF;
  5997. c->Request.CDB[4] = size & 0xFF;
  5998. break;
  5999. case HPSA_REPORT_LOG:
  6000. case HPSA_REPORT_PHYS:
  6001. /* Talking to controller so It's a physical command
  6002. mode = 00 target = 0. Nothing to write.
  6003. */
  6004. c->Request.CDBLen = 12;
  6005. c->Request.type_attr_dir =
  6006. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
  6007. c->Request.Timeout = 0;
  6008. c->Request.CDB[0] = cmd;
  6009. c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
  6010. c->Request.CDB[7] = (size >> 16) & 0xFF;
  6011. c->Request.CDB[8] = (size >> 8) & 0xFF;
  6012. c->Request.CDB[9] = size & 0xFF;
  6013. break;
  6014. case BMIC_SENSE_DIAG_OPTIONS:
  6015. c->Request.CDBLen = 16;
  6016. c->Request.type_attr_dir =
  6017. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
  6018. c->Request.Timeout = 0;
  6019. /* Spec says this should be BMIC_WRITE */
  6020. c->Request.CDB[0] = BMIC_READ;
  6021. c->Request.CDB[6] = BMIC_SENSE_DIAG_OPTIONS;
  6022. break;
  6023. case BMIC_SET_DIAG_OPTIONS:
  6024. c->Request.CDBLen = 16;
  6025. c->Request.type_attr_dir =
  6026. TYPE_ATTR_DIR(cmd_type,
  6027. ATTR_SIMPLE, XFER_WRITE);
  6028. c->Request.Timeout = 0;
  6029. c->Request.CDB[0] = BMIC_WRITE;
  6030. c->Request.CDB[6] = BMIC_SET_DIAG_OPTIONS;
  6031. break;
  6032. case HPSA_CACHE_FLUSH:
  6033. c->Request.CDBLen = 12;
  6034. c->Request.type_attr_dir =
  6035. TYPE_ATTR_DIR(cmd_type,
  6036. ATTR_SIMPLE, XFER_WRITE);
  6037. c->Request.Timeout = 0;
  6038. c->Request.CDB[0] = BMIC_WRITE;
  6039. c->Request.CDB[6] = BMIC_CACHE_FLUSH;
  6040. c->Request.CDB[7] = (size >> 8) & 0xFF;
  6041. c->Request.CDB[8] = size & 0xFF;
  6042. break;
  6043. case TEST_UNIT_READY:
  6044. c->Request.CDBLen = 6;
  6045. c->Request.type_attr_dir =
  6046. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
  6047. c->Request.Timeout = 0;
  6048. break;
  6049. case HPSA_GET_RAID_MAP:
  6050. c->Request.CDBLen = 12;
  6051. c->Request.type_attr_dir =
  6052. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
  6053. c->Request.Timeout = 0;
  6054. c->Request.CDB[0] = HPSA_CISS_READ;
  6055. c->Request.CDB[1] = cmd;
  6056. c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
  6057. c->Request.CDB[7] = (size >> 16) & 0xFF;
  6058. c->Request.CDB[8] = (size >> 8) & 0xFF;
  6059. c->Request.CDB[9] = size & 0xFF;
  6060. break;
  6061. case BMIC_SENSE_CONTROLLER_PARAMETERS:
  6062. c->Request.CDBLen = 10;
  6063. c->Request.type_attr_dir =
  6064. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
  6065. c->Request.Timeout = 0;
  6066. c->Request.CDB[0] = BMIC_READ;
  6067. c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS;
  6068. c->Request.CDB[7] = (size >> 16) & 0xFF;
  6069. c->Request.CDB[8] = (size >> 8) & 0xFF;
  6070. break;
  6071. case BMIC_IDENTIFY_PHYSICAL_DEVICE:
  6072. c->Request.CDBLen = 10;
  6073. c->Request.type_attr_dir =
  6074. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
  6075. c->Request.Timeout = 0;
  6076. c->Request.CDB[0] = BMIC_READ;
  6077. c->Request.CDB[6] = BMIC_IDENTIFY_PHYSICAL_DEVICE;
  6078. c->Request.CDB[7] = (size >> 16) & 0xFF;
  6079. c->Request.CDB[8] = (size >> 8) & 0XFF;
  6080. break;
  6081. case BMIC_SENSE_SUBSYSTEM_INFORMATION:
  6082. c->Request.CDBLen = 10;
  6083. c->Request.type_attr_dir =
  6084. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
  6085. c->Request.Timeout = 0;
  6086. c->Request.CDB[0] = BMIC_READ;
  6087. c->Request.CDB[6] = BMIC_SENSE_SUBSYSTEM_INFORMATION;
  6088. c->Request.CDB[7] = (size >> 16) & 0xFF;
  6089. c->Request.CDB[8] = (size >> 8) & 0XFF;
  6090. break;
  6091. case BMIC_SENSE_STORAGE_BOX_PARAMS:
  6092. c->Request.CDBLen = 10;
  6093. c->Request.type_attr_dir =
  6094. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
  6095. c->Request.Timeout = 0;
  6096. c->Request.CDB[0] = BMIC_READ;
  6097. c->Request.CDB[6] = BMIC_SENSE_STORAGE_BOX_PARAMS;
  6098. c->Request.CDB[7] = (size >> 16) & 0xFF;
  6099. c->Request.CDB[8] = (size >> 8) & 0XFF;
  6100. break;
  6101. case BMIC_IDENTIFY_CONTROLLER:
  6102. c->Request.CDBLen = 10;
  6103. c->Request.type_attr_dir =
  6104. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
  6105. c->Request.Timeout = 0;
  6106. c->Request.CDB[0] = BMIC_READ;
  6107. c->Request.CDB[1] = 0;
  6108. c->Request.CDB[2] = 0;
  6109. c->Request.CDB[3] = 0;
  6110. c->Request.CDB[4] = 0;
  6111. c->Request.CDB[5] = 0;
  6112. c->Request.CDB[6] = BMIC_IDENTIFY_CONTROLLER;
  6113. c->Request.CDB[7] = (size >> 16) & 0xFF;
  6114. c->Request.CDB[8] = (size >> 8) & 0XFF;
  6115. c->Request.CDB[9] = 0;
  6116. break;
  6117. default:
  6118. dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
  6119. BUG();
  6120. }
  6121. } else if (cmd_type == TYPE_MSG) {
  6122. switch (cmd) {
  6123. case HPSA_PHYS_TARGET_RESET:
  6124. c->Request.CDBLen = 16;
  6125. c->Request.type_attr_dir =
  6126. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
  6127. c->Request.Timeout = 0; /* Don't time out */
  6128. memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
  6129. c->Request.CDB[0] = HPSA_RESET;
  6130. c->Request.CDB[1] = HPSA_TARGET_RESET_TYPE;
  6131. /* Physical target reset needs no control bytes 4-7*/
  6132. c->Request.CDB[4] = 0x00;
  6133. c->Request.CDB[5] = 0x00;
  6134. c->Request.CDB[6] = 0x00;
  6135. c->Request.CDB[7] = 0x00;
  6136. break;
  6137. case HPSA_DEVICE_RESET_MSG:
  6138. c->Request.CDBLen = 16;
  6139. c->Request.type_attr_dir =
  6140. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
  6141. c->Request.Timeout = 0; /* Don't time out */
  6142. memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
  6143. c->Request.CDB[0] = cmd;
  6144. c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
  6145. /* If bytes 4-7 are zero, it means reset the */
  6146. /* LunID device */
  6147. c->Request.CDB[4] = 0x00;
  6148. c->Request.CDB[5] = 0x00;
  6149. c->Request.CDB[6] = 0x00;
  6150. c->Request.CDB[7] = 0x00;
  6151. break;
  6152. default:
  6153. dev_warn(&h->pdev->dev, "unknown message type %d\n",
  6154. cmd);
  6155. BUG();
  6156. }
  6157. } else {
  6158. dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
  6159. BUG();
  6160. }
  6161. switch (GET_DIR(c->Request.type_attr_dir)) {
  6162. case XFER_READ:
  6163. dir = DMA_FROM_DEVICE;
  6164. break;
  6165. case XFER_WRITE:
  6166. dir = DMA_TO_DEVICE;
  6167. break;
  6168. case XFER_NONE:
  6169. dir = DMA_NONE;
  6170. break;
  6171. default:
  6172. dir = DMA_BIDIRECTIONAL;
  6173. }
  6174. if (hpsa_map_one(h->pdev, c, buff, size, dir))
  6175. return -1;
  6176. return 0;
  6177. }
  6178. /*
  6179. * Map (physical) PCI mem into (virtual) kernel space
  6180. */
  6181. static void __iomem *remap_pci_mem(ulong base, ulong size)
  6182. {
  6183. ulong page_base = ((ulong) base) & PAGE_MASK;
  6184. ulong page_offs = ((ulong) base) - page_base;
  6185. void __iomem *page_remapped = ioremap(page_base,
  6186. page_offs + size);
  6187. return page_remapped ? (page_remapped + page_offs) : NULL;
  6188. }
  6189. static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
  6190. {
  6191. return h->access.command_completed(h, q);
  6192. }
  6193. static inline bool interrupt_pending(struct ctlr_info *h)
  6194. {
  6195. return h->access.intr_pending(h);
  6196. }
  6197. static inline long interrupt_not_for_us(struct ctlr_info *h)
  6198. {
  6199. return (h->access.intr_pending(h) == 0) ||
  6200. (h->interrupts_enabled == 0);
  6201. }
  6202. static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
  6203. u32 raw_tag)
  6204. {
  6205. if (unlikely(tag_index >= h->nr_cmds)) {
  6206. dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
  6207. return 1;
  6208. }
  6209. return 0;
  6210. }
  6211. static inline void finish_cmd(struct CommandList *c)
  6212. {
  6213. dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
  6214. if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
  6215. || c->cmd_type == CMD_IOACCEL2))
  6216. complete_scsi_command(c);
  6217. else if (c->cmd_type == CMD_IOCTL_PEND || c->cmd_type == IOACCEL2_TMF)
  6218. complete(c->waiting);
  6219. }
  6220. /* process completion of an indexed ("direct lookup") command */
  6221. static inline void process_indexed_cmd(struct ctlr_info *h,
  6222. u32 raw_tag)
  6223. {
  6224. u32 tag_index;
  6225. struct CommandList *c;
  6226. tag_index = raw_tag >> DIRECT_LOOKUP_SHIFT;
  6227. if (!bad_tag(h, tag_index, raw_tag)) {
  6228. c = h->cmd_pool + tag_index;
  6229. finish_cmd(c);
  6230. }
  6231. }
  6232. /* Some controllers, like p400, will give us one interrupt
  6233. * after a soft reset, even if we turned interrupts off.
  6234. * Only need to check for this in the hpsa_xxx_discard_completions
  6235. * functions.
  6236. */
  6237. static int ignore_bogus_interrupt(struct ctlr_info *h)
  6238. {
  6239. if (likely(!reset_devices))
  6240. return 0;
  6241. if (likely(h->interrupts_enabled))
  6242. return 0;
  6243. dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
  6244. "(known firmware bug.) Ignoring.\n");
  6245. return 1;
  6246. }
  6247. /*
  6248. * Convert &h->q[x] (passed to interrupt handlers) back to h.
  6249. * Relies on (h-q[x] == x) being true for x such that
  6250. * 0 <= x < MAX_REPLY_QUEUES.
  6251. */
  6252. static struct ctlr_info *queue_to_hba(u8 *queue)
  6253. {
  6254. return container_of((queue - *queue), struct ctlr_info, q[0]);
  6255. }
  6256. static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
  6257. {
  6258. struct ctlr_info *h = queue_to_hba(queue);
  6259. u8 q = *(u8 *) queue;
  6260. u32 raw_tag;
  6261. if (ignore_bogus_interrupt(h))
  6262. return IRQ_NONE;
  6263. if (interrupt_not_for_us(h))
  6264. return IRQ_NONE;
  6265. h->last_intr_timestamp = get_jiffies_64();
  6266. while (interrupt_pending(h)) {
  6267. raw_tag = get_next_completion(h, q);
  6268. while (raw_tag != FIFO_EMPTY)
  6269. raw_tag = next_command(h, q);
  6270. }
  6271. return IRQ_HANDLED;
  6272. }
  6273. static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
  6274. {
  6275. struct ctlr_info *h = queue_to_hba(queue);
  6276. u32 raw_tag;
  6277. u8 q = *(u8 *) queue;
  6278. if (ignore_bogus_interrupt(h))
  6279. return IRQ_NONE;
  6280. h->last_intr_timestamp = get_jiffies_64();
  6281. raw_tag = get_next_completion(h, q);
  6282. while (raw_tag != FIFO_EMPTY)
  6283. raw_tag = next_command(h, q);
  6284. return IRQ_HANDLED;
  6285. }
  6286. static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
  6287. {
  6288. struct ctlr_info *h = queue_to_hba((u8 *) queue);
  6289. u32 raw_tag;
  6290. u8 q = *(u8 *) queue;
  6291. if (interrupt_not_for_us(h))
  6292. return IRQ_NONE;
  6293. h->last_intr_timestamp = get_jiffies_64();
  6294. while (interrupt_pending(h)) {
  6295. raw_tag = get_next_completion(h, q);
  6296. while (raw_tag != FIFO_EMPTY) {
  6297. process_indexed_cmd(h, raw_tag);
  6298. raw_tag = next_command(h, q);
  6299. }
  6300. }
  6301. return IRQ_HANDLED;
  6302. }
  6303. static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
  6304. {
  6305. struct ctlr_info *h = queue_to_hba(queue);
  6306. u32 raw_tag;
  6307. u8 q = *(u8 *) queue;
  6308. h->last_intr_timestamp = get_jiffies_64();
  6309. raw_tag = get_next_completion(h, q);
  6310. while (raw_tag != FIFO_EMPTY) {
  6311. process_indexed_cmd(h, raw_tag);
  6312. raw_tag = next_command(h, q);
  6313. }
  6314. return IRQ_HANDLED;
  6315. }
  6316. /* Send a message CDB to the firmware. Careful, this only works
  6317. * in simple mode, not performant mode due to the tag lookup.
  6318. * We only ever use this immediately after a controller reset.
  6319. */
  6320. static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
  6321. unsigned char type)
  6322. {
  6323. struct Command {
  6324. struct CommandListHeader CommandHeader;
  6325. struct RequestBlock Request;
  6326. struct ErrDescriptor ErrorDescriptor;
  6327. };
  6328. struct Command *cmd;
  6329. static const size_t cmd_sz = sizeof(*cmd) +
  6330. sizeof(cmd->ErrorDescriptor);
  6331. dma_addr_t paddr64;
  6332. __le32 paddr32;
  6333. u32 tag;
  6334. void __iomem *vaddr;
  6335. int i, err;
  6336. vaddr = pci_ioremap_bar(pdev, 0);
  6337. if (vaddr == NULL)
  6338. return -ENOMEM;
  6339. /* The Inbound Post Queue only accepts 32-bit physical addresses for the
  6340. * CCISS commands, so they must be allocated from the lower 4GiB of
  6341. * memory.
  6342. */
  6343. err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
  6344. if (err) {
  6345. iounmap(vaddr);
  6346. return err;
  6347. }
  6348. cmd = dma_alloc_coherent(&pdev->dev, cmd_sz, &paddr64, GFP_KERNEL);
  6349. if (cmd == NULL) {
  6350. iounmap(vaddr);
  6351. return -ENOMEM;
  6352. }
  6353. /* This must fit, because of the 32-bit consistent DMA mask. Also,
  6354. * although there's no guarantee, we assume that the address is at
  6355. * least 4-byte aligned (most likely, it's page-aligned).
  6356. */
  6357. paddr32 = cpu_to_le32(paddr64);
  6358. cmd->CommandHeader.ReplyQueue = 0;
  6359. cmd->CommandHeader.SGList = 0;
  6360. cmd->CommandHeader.SGTotal = cpu_to_le16(0);
  6361. cmd->CommandHeader.tag = cpu_to_le64(paddr64);
  6362. memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
  6363. cmd->Request.CDBLen = 16;
  6364. cmd->Request.type_attr_dir =
  6365. TYPE_ATTR_DIR(TYPE_MSG, ATTR_HEADOFQUEUE, XFER_NONE);
  6366. cmd->Request.Timeout = 0; /* Don't time out */
  6367. cmd->Request.CDB[0] = opcode;
  6368. cmd->Request.CDB[1] = type;
  6369. memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
  6370. cmd->ErrorDescriptor.Addr =
  6371. cpu_to_le64((le32_to_cpu(paddr32) + sizeof(*cmd)));
  6372. cmd->ErrorDescriptor.Len = cpu_to_le32(sizeof(struct ErrorInfo));
  6373. writel(le32_to_cpu(paddr32), vaddr + SA5_REQUEST_PORT_OFFSET);
  6374. for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
  6375. tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
  6376. if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr64)
  6377. break;
  6378. msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
  6379. }
  6380. iounmap(vaddr);
  6381. /* we leak the DMA buffer here ... no choice since the controller could
  6382. * still complete the command.
  6383. */
  6384. if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
  6385. dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
  6386. opcode, type);
  6387. return -ETIMEDOUT;
  6388. }
  6389. dma_free_coherent(&pdev->dev, cmd_sz, cmd, paddr64);
  6390. if (tag & HPSA_ERROR_BIT) {
  6391. dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
  6392. opcode, type);
  6393. return -EIO;
  6394. }
  6395. dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
  6396. opcode, type);
  6397. return 0;
  6398. }
  6399. #define hpsa_noop(p) hpsa_message(p, 3, 0)
  6400. static int hpsa_controller_hard_reset(struct pci_dev *pdev,
  6401. void __iomem *vaddr, u32 use_doorbell)
  6402. {
  6403. if (use_doorbell) {
  6404. /* For everything after the P600, the PCI power state method
  6405. * of resetting the controller doesn't work, so we have this
  6406. * other way using the doorbell register.
  6407. */
  6408. dev_info(&pdev->dev, "using doorbell to reset controller\n");
  6409. writel(use_doorbell, vaddr + SA5_DOORBELL);
  6410. /* PMC hardware guys tell us we need a 10 second delay after
  6411. * doorbell reset and before any attempt to talk to the board
  6412. * at all to ensure that this actually works and doesn't fall
  6413. * over in some weird corner cases.
  6414. */
  6415. msleep(10000);
  6416. } else { /* Try to do it the PCI power state way */
  6417. /* Quoting from the Open CISS Specification: "The Power
  6418. * Management Control/Status Register (CSR) controls the power
  6419. * state of the device. The normal operating state is D0,
  6420. * CSR=00h. The software off state is D3, CSR=03h. To reset
  6421. * the controller, place the interface device in D3 then to D0,
  6422. * this causes a secondary PCI reset which will reset the
  6423. * controller." */
  6424. int rc = 0;
  6425. dev_info(&pdev->dev, "using PCI PM to reset controller\n");
  6426. /* enter the D3hot power management state */
  6427. rc = pci_set_power_state(pdev, PCI_D3hot);
  6428. if (rc)
  6429. return rc;
  6430. msleep(500);
  6431. /* enter the D0 power management state */
  6432. rc = pci_set_power_state(pdev, PCI_D0);
  6433. if (rc)
  6434. return rc;
  6435. /*
  6436. * The P600 requires a small delay when changing states.
  6437. * Otherwise we may think the board did not reset and we bail.
  6438. * This for kdump only and is particular to the P600.
  6439. */
  6440. msleep(500);
  6441. }
  6442. return 0;
  6443. }
  6444. static void init_driver_version(char *driver_version, int len)
  6445. {
  6446. memset(driver_version, 0, len);
  6447. strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
  6448. }
  6449. static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
  6450. {
  6451. char *driver_version;
  6452. int i, size = sizeof(cfgtable->driver_version);
  6453. driver_version = kmalloc(size, GFP_KERNEL);
  6454. if (!driver_version)
  6455. return -ENOMEM;
  6456. init_driver_version(driver_version, size);
  6457. for (i = 0; i < size; i++)
  6458. writeb(driver_version[i], &cfgtable->driver_version[i]);
  6459. kfree(driver_version);
  6460. return 0;
  6461. }
  6462. static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
  6463. unsigned char *driver_ver)
  6464. {
  6465. int i;
  6466. for (i = 0; i < sizeof(cfgtable->driver_version); i++)
  6467. driver_ver[i] = readb(&cfgtable->driver_version[i]);
  6468. }
  6469. static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
  6470. {
  6471. char *driver_ver, *old_driver_ver;
  6472. int rc, size = sizeof(cfgtable->driver_version);
  6473. old_driver_ver = kmalloc_array(2, size, GFP_KERNEL);
  6474. if (!old_driver_ver)
  6475. return -ENOMEM;
  6476. driver_ver = old_driver_ver + size;
  6477. /* After a reset, the 32 bytes of "driver version" in the cfgtable
  6478. * should have been changed, otherwise we know the reset failed.
  6479. */
  6480. init_driver_version(old_driver_ver, size);
  6481. read_driver_ver_from_cfgtable(cfgtable, driver_ver);
  6482. rc = !memcmp(driver_ver, old_driver_ver, size);
  6483. kfree(old_driver_ver);
  6484. return rc;
  6485. }
  6486. /* This does a hard reset of the controller using PCI power management
  6487. * states or the using the doorbell register.
  6488. */
  6489. static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev, u32 board_id)
  6490. {
  6491. u64 cfg_offset;
  6492. u32 cfg_base_addr;
  6493. u64 cfg_base_addr_index;
  6494. void __iomem *vaddr;
  6495. unsigned long paddr;
  6496. u32 misc_fw_support;
  6497. int rc;
  6498. struct CfgTable __iomem *cfgtable;
  6499. u32 use_doorbell;
  6500. u16 command_register;
  6501. /* For controllers as old as the P600, this is very nearly
  6502. * the same thing as
  6503. *
  6504. * pci_save_state(pci_dev);
  6505. * pci_set_power_state(pci_dev, PCI_D3hot);
  6506. * pci_set_power_state(pci_dev, PCI_D0);
  6507. * pci_restore_state(pci_dev);
  6508. *
  6509. * For controllers newer than the P600, the pci power state
  6510. * method of resetting doesn't work so we have another way
  6511. * using the doorbell register.
  6512. */
  6513. if (!ctlr_is_resettable(board_id)) {
  6514. dev_warn(&pdev->dev, "Controller not resettable\n");
  6515. return -ENODEV;
  6516. }
  6517. /* if controller is soft- but not hard resettable... */
  6518. if (!ctlr_is_hard_resettable(board_id))
  6519. return -ENOTSUPP; /* try soft reset later. */
  6520. /* Save the PCI command register */
  6521. pci_read_config_word(pdev, 4, &command_register);
  6522. pci_save_state(pdev);
  6523. /* find the first memory BAR, so we can find the cfg table */
  6524. rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
  6525. if (rc)
  6526. return rc;
  6527. vaddr = remap_pci_mem(paddr, 0x250);
  6528. if (!vaddr)
  6529. return -ENOMEM;
  6530. /* find cfgtable in order to check if reset via doorbell is supported */
  6531. rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
  6532. &cfg_base_addr_index, &cfg_offset);
  6533. if (rc)
  6534. goto unmap_vaddr;
  6535. cfgtable = remap_pci_mem(pci_resource_start(pdev,
  6536. cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
  6537. if (!cfgtable) {
  6538. rc = -ENOMEM;
  6539. goto unmap_vaddr;
  6540. }
  6541. rc = write_driver_ver_to_cfgtable(cfgtable);
  6542. if (rc)
  6543. goto unmap_cfgtable;
  6544. /* If reset via doorbell register is supported, use that.
  6545. * There are two such methods. Favor the newest method.
  6546. */
  6547. misc_fw_support = readl(&cfgtable->misc_fw_support);
  6548. use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
  6549. if (use_doorbell) {
  6550. use_doorbell = DOORBELL_CTLR_RESET2;
  6551. } else {
  6552. use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
  6553. if (use_doorbell) {
  6554. dev_warn(&pdev->dev,
  6555. "Soft reset not supported. Firmware update is required.\n");
  6556. rc = -ENOTSUPP; /* try soft reset */
  6557. goto unmap_cfgtable;
  6558. }
  6559. }
  6560. rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
  6561. if (rc)
  6562. goto unmap_cfgtable;
  6563. pci_restore_state(pdev);
  6564. pci_write_config_word(pdev, 4, command_register);
  6565. /* Some devices (notably the HP Smart Array 5i Controller)
  6566. need a little pause here */
  6567. msleep(HPSA_POST_RESET_PAUSE_MSECS);
  6568. rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
  6569. if (rc) {
  6570. dev_warn(&pdev->dev,
  6571. "Failed waiting for board to become ready after hard reset\n");
  6572. goto unmap_cfgtable;
  6573. }
  6574. rc = controller_reset_failed(vaddr);
  6575. if (rc < 0)
  6576. goto unmap_cfgtable;
  6577. if (rc) {
  6578. dev_warn(&pdev->dev, "Unable to successfully reset "
  6579. "controller. Will try soft reset.\n");
  6580. rc = -ENOTSUPP;
  6581. } else {
  6582. dev_info(&pdev->dev, "board ready after hard reset.\n");
  6583. }
  6584. unmap_cfgtable:
  6585. iounmap(cfgtable);
  6586. unmap_vaddr:
  6587. iounmap(vaddr);
  6588. return rc;
  6589. }
  6590. /*
  6591. * We cannot read the structure directly, for portability we must use
  6592. * the io functions.
  6593. * This is for debug only.
  6594. */
  6595. static void print_cfg_table(struct device *dev, struct CfgTable __iomem *tb)
  6596. {
  6597. #ifdef HPSA_DEBUG
  6598. int i;
  6599. char temp_name[17];
  6600. dev_info(dev, "Controller Configuration information\n");
  6601. dev_info(dev, "------------------------------------\n");
  6602. for (i = 0; i < 4; i++)
  6603. temp_name[i] = readb(&(tb->Signature[i]));
  6604. temp_name[4] = '\0';
  6605. dev_info(dev, " Signature = %s\n", temp_name);
  6606. dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
  6607. dev_info(dev, " Transport methods supported = 0x%x\n",
  6608. readl(&(tb->TransportSupport)));
  6609. dev_info(dev, " Transport methods active = 0x%x\n",
  6610. readl(&(tb->TransportActive)));
  6611. dev_info(dev, " Requested transport Method = 0x%x\n",
  6612. readl(&(tb->HostWrite.TransportRequest)));
  6613. dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
  6614. readl(&(tb->HostWrite.CoalIntDelay)));
  6615. dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
  6616. readl(&(tb->HostWrite.CoalIntCount)));
  6617. dev_info(dev, " Max outstanding commands = %d\n",
  6618. readl(&(tb->CmdsOutMax)));
  6619. dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
  6620. for (i = 0; i < 16; i++)
  6621. temp_name[i] = readb(&(tb->ServerName[i]));
  6622. temp_name[16] = '\0';
  6623. dev_info(dev, " Server Name = %s\n", temp_name);
  6624. dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
  6625. readl(&(tb->HeartBeat)));
  6626. #endif /* HPSA_DEBUG */
  6627. }
  6628. static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
  6629. {
  6630. int i, offset, mem_type, bar_type;
  6631. if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
  6632. return 0;
  6633. offset = 0;
  6634. for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
  6635. bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
  6636. if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
  6637. offset += 4;
  6638. else {
  6639. mem_type = pci_resource_flags(pdev, i) &
  6640. PCI_BASE_ADDRESS_MEM_TYPE_MASK;
  6641. switch (mem_type) {
  6642. case PCI_BASE_ADDRESS_MEM_TYPE_32:
  6643. case PCI_BASE_ADDRESS_MEM_TYPE_1M:
  6644. offset += 4; /* 32 bit */
  6645. break;
  6646. case PCI_BASE_ADDRESS_MEM_TYPE_64:
  6647. offset += 8;
  6648. break;
  6649. default: /* reserved in PCI 2.2 */
  6650. dev_warn(&pdev->dev,
  6651. "base address is invalid\n");
  6652. return -1;
  6653. }
  6654. }
  6655. if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
  6656. return i + 1;
  6657. }
  6658. return -1;
  6659. }
  6660. static void hpsa_disable_interrupt_mode(struct ctlr_info *h)
  6661. {
  6662. pci_free_irq_vectors(h->pdev);
  6663. h->msix_vectors = 0;
  6664. }
  6665. static void hpsa_setup_reply_map(struct ctlr_info *h)
  6666. {
  6667. const struct cpumask *mask;
  6668. unsigned int queue, cpu;
  6669. for (queue = 0; queue < h->msix_vectors; queue++) {
  6670. mask = pci_irq_get_affinity(h->pdev, queue);
  6671. if (!mask)
  6672. goto fallback;
  6673. for_each_cpu(cpu, mask)
  6674. h->reply_map[cpu] = queue;
  6675. }
  6676. return;
  6677. fallback:
  6678. for_each_possible_cpu(cpu)
  6679. h->reply_map[cpu] = 0;
  6680. }
  6681. /* If MSI/MSI-X is supported by the kernel we will try to enable it on
  6682. * controllers that are capable. If not, we use legacy INTx mode.
  6683. */
  6684. static int hpsa_interrupt_mode(struct ctlr_info *h)
  6685. {
  6686. unsigned int flags = PCI_IRQ_LEGACY;
  6687. int ret;
  6688. /* Some boards advertise MSI but don't really support it */
  6689. switch (h->board_id) {
  6690. case 0x40700E11:
  6691. case 0x40800E11:
  6692. case 0x40820E11:
  6693. case 0x40830E11:
  6694. break;
  6695. default:
  6696. ret = pci_alloc_irq_vectors(h->pdev, 1, MAX_REPLY_QUEUES,
  6697. PCI_IRQ_MSIX | PCI_IRQ_AFFINITY);
  6698. if (ret > 0) {
  6699. h->msix_vectors = ret;
  6700. return 0;
  6701. }
  6702. flags |= PCI_IRQ_MSI;
  6703. break;
  6704. }
  6705. ret = pci_alloc_irq_vectors(h->pdev, 1, 1, flags);
  6706. if (ret < 0)
  6707. return ret;
  6708. return 0;
  6709. }
  6710. static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id,
  6711. bool *legacy_board)
  6712. {
  6713. int i;
  6714. u32 subsystem_vendor_id, subsystem_device_id;
  6715. subsystem_vendor_id = pdev->subsystem_vendor;
  6716. subsystem_device_id = pdev->subsystem_device;
  6717. *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
  6718. subsystem_vendor_id;
  6719. if (legacy_board)
  6720. *legacy_board = false;
  6721. for (i = 0; i < ARRAY_SIZE(products); i++)
  6722. if (*board_id == products[i].board_id) {
  6723. if (products[i].access != &SA5A_access &&
  6724. products[i].access != &SA5B_access)
  6725. return i;
  6726. dev_warn(&pdev->dev,
  6727. "legacy board ID: 0x%08x\n",
  6728. *board_id);
  6729. if (legacy_board)
  6730. *legacy_board = true;
  6731. return i;
  6732. }
  6733. dev_warn(&pdev->dev, "unrecognized board ID: 0x%08x\n", *board_id);
  6734. if (legacy_board)
  6735. *legacy_board = true;
  6736. return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
  6737. }
  6738. static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
  6739. unsigned long *memory_bar)
  6740. {
  6741. int i;
  6742. for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
  6743. if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
  6744. /* addressing mode bits already removed */
  6745. *memory_bar = pci_resource_start(pdev, i);
  6746. dev_dbg(&pdev->dev, "memory BAR = %lx\n",
  6747. *memory_bar);
  6748. return 0;
  6749. }
  6750. dev_warn(&pdev->dev, "no memory BAR found\n");
  6751. return -ENODEV;
  6752. }
  6753. static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
  6754. int wait_for_ready)
  6755. {
  6756. int i, iterations;
  6757. u32 scratchpad;
  6758. if (wait_for_ready)
  6759. iterations = HPSA_BOARD_READY_ITERATIONS;
  6760. else
  6761. iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
  6762. for (i = 0; i < iterations; i++) {
  6763. scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
  6764. if (wait_for_ready) {
  6765. if (scratchpad == HPSA_FIRMWARE_READY)
  6766. return 0;
  6767. } else {
  6768. if (scratchpad != HPSA_FIRMWARE_READY)
  6769. return 0;
  6770. }
  6771. msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
  6772. }
  6773. dev_warn(&pdev->dev, "board not ready, timed out.\n");
  6774. return -ENODEV;
  6775. }
  6776. static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
  6777. u32 *cfg_base_addr, u64 *cfg_base_addr_index,
  6778. u64 *cfg_offset)
  6779. {
  6780. *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
  6781. *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
  6782. *cfg_base_addr &= (u32) 0x0000ffff;
  6783. *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
  6784. if (*cfg_base_addr_index == -1) {
  6785. dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
  6786. return -ENODEV;
  6787. }
  6788. return 0;
  6789. }
  6790. static void hpsa_free_cfgtables(struct ctlr_info *h)
  6791. {
  6792. if (h->transtable) {
  6793. iounmap(h->transtable);
  6794. h->transtable = NULL;
  6795. }
  6796. if (h->cfgtable) {
  6797. iounmap(h->cfgtable);
  6798. h->cfgtable = NULL;
  6799. }
  6800. }
  6801. /* Find and map CISS config table and transfer table
  6802. + * several items must be unmapped (freed) later
  6803. + * */
  6804. static int hpsa_find_cfgtables(struct ctlr_info *h)
  6805. {
  6806. u64 cfg_offset;
  6807. u32 cfg_base_addr;
  6808. u64 cfg_base_addr_index;
  6809. u32 trans_offset;
  6810. int rc;
  6811. rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
  6812. &cfg_base_addr_index, &cfg_offset);
  6813. if (rc)
  6814. return rc;
  6815. h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
  6816. cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
  6817. if (!h->cfgtable) {
  6818. dev_err(&h->pdev->dev, "Failed mapping cfgtable\n");
  6819. return -ENOMEM;
  6820. }
  6821. rc = write_driver_ver_to_cfgtable(h->cfgtable);
  6822. if (rc)
  6823. return rc;
  6824. /* Find performant mode table. */
  6825. trans_offset = readl(&h->cfgtable->TransMethodOffset);
  6826. h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
  6827. cfg_base_addr_index)+cfg_offset+trans_offset,
  6828. sizeof(*h->transtable));
  6829. if (!h->transtable) {
  6830. dev_err(&h->pdev->dev, "Failed mapping transfer table\n");
  6831. hpsa_free_cfgtables(h);
  6832. return -ENOMEM;
  6833. }
  6834. return 0;
  6835. }
  6836. static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
  6837. {
  6838. #define MIN_MAX_COMMANDS 16
  6839. BUILD_BUG_ON(MIN_MAX_COMMANDS <= HPSA_NRESERVED_CMDS);
  6840. h->max_commands = readl(&h->cfgtable->MaxPerformantModeCommands);
  6841. /* Limit commands in memory limited kdump scenario. */
  6842. if (reset_devices && h->max_commands > 32)
  6843. h->max_commands = 32;
  6844. if (h->max_commands < MIN_MAX_COMMANDS) {
  6845. dev_warn(&h->pdev->dev,
  6846. "Controller reports max supported commands of %d Using %d instead. Ensure that firmware is up to date.\n",
  6847. h->max_commands,
  6848. MIN_MAX_COMMANDS);
  6849. h->max_commands = MIN_MAX_COMMANDS;
  6850. }
  6851. }
  6852. /* If the controller reports that the total max sg entries is greater than 512,
  6853. * then we know that chained SG blocks work. (Original smart arrays did not
  6854. * support chained SG blocks and would return zero for max sg entries.)
  6855. */
  6856. static int hpsa_supports_chained_sg_blocks(struct ctlr_info *h)
  6857. {
  6858. return h->maxsgentries > 512;
  6859. }
  6860. /* Interrogate the hardware for some limits:
  6861. * max commands, max SG elements without chaining, and with chaining,
  6862. * SG chain block size, etc.
  6863. */
  6864. static void hpsa_find_board_params(struct ctlr_info *h)
  6865. {
  6866. hpsa_get_max_perf_mode_cmds(h);
  6867. h->nr_cmds = h->max_commands;
  6868. h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
  6869. h->fw_support = readl(&(h->cfgtable->misc_fw_support));
  6870. if (hpsa_supports_chained_sg_blocks(h)) {
  6871. /* Limit in-command s/g elements to 32 save dma'able memory. */
  6872. h->max_cmd_sg_entries = 32;
  6873. h->chainsize = h->maxsgentries - h->max_cmd_sg_entries;
  6874. h->maxsgentries--; /* save one for chain pointer */
  6875. } else {
  6876. /*
  6877. * Original smart arrays supported at most 31 s/g entries
  6878. * embedded inline in the command (trying to use more
  6879. * would lock up the controller)
  6880. */
  6881. h->max_cmd_sg_entries = 31;
  6882. h->maxsgentries = 31; /* default to traditional values */
  6883. h->chainsize = 0;
  6884. }
  6885. /* Find out what task management functions are supported and cache */
  6886. h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
  6887. if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
  6888. dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
  6889. if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
  6890. dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
  6891. if (!(HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags))
  6892. dev_warn(&h->pdev->dev, "HP SSD Smart Path aborts not supported\n");
  6893. }
  6894. static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
  6895. {
  6896. if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
  6897. dev_err(&h->pdev->dev, "not a valid CISS config table\n");
  6898. return false;
  6899. }
  6900. return true;
  6901. }
  6902. static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
  6903. {
  6904. u32 driver_support;
  6905. driver_support = readl(&(h->cfgtable->driver_support));
  6906. /* Need to enable prefetch in the SCSI core for 6400 in x86 */
  6907. #ifdef CONFIG_X86
  6908. driver_support |= ENABLE_SCSI_PREFETCH;
  6909. #endif
  6910. driver_support |= ENABLE_UNIT_ATTN;
  6911. writel(driver_support, &(h->cfgtable->driver_support));
  6912. }
  6913. /* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
  6914. * in a prefetch beyond physical memory.
  6915. */
  6916. static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
  6917. {
  6918. u32 dma_prefetch;
  6919. if (h->board_id != 0x3225103C)
  6920. return;
  6921. dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
  6922. dma_prefetch |= 0x8000;
  6923. writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
  6924. }
  6925. static int hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
  6926. {
  6927. int i;
  6928. u32 doorbell_value;
  6929. unsigned long flags;
  6930. /* wait until the clear_event_notify bit 6 is cleared by controller. */
  6931. for (i = 0; i < MAX_CLEAR_EVENT_WAIT; i++) {
  6932. spin_lock_irqsave(&h->lock, flags);
  6933. doorbell_value = readl(h->vaddr + SA5_DOORBELL);
  6934. spin_unlock_irqrestore(&h->lock, flags);
  6935. if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
  6936. goto done;
  6937. /* delay and try again */
  6938. msleep(CLEAR_EVENT_WAIT_INTERVAL);
  6939. }
  6940. return -ENODEV;
  6941. done:
  6942. return 0;
  6943. }
  6944. static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
  6945. {
  6946. int i;
  6947. u32 doorbell_value;
  6948. unsigned long flags;
  6949. /* under certain very rare conditions, this can take awhile.
  6950. * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
  6951. * as we enter this code.)
  6952. */
  6953. for (i = 0; i < MAX_MODE_CHANGE_WAIT; i++) {
  6954. if (h->remove_in_progress)
  6955. goto done;
  6956. spin_lock_irqsave(&h->lock, flags);
  6957. doorbell_value = readl(h->vaddr + SA5_DOORBELL);
  6958. spin_unlock_irqrestore(&h->lock, flags);
  6959. if (!(doorbell_value & CFGTBL_ChangeReq))
  6960. goto done;
  6961. /* delay and try again */
  6962. msleep(MODE_CHANGE_WAIT_INTERVAL);
  6963. }
  6964. return -ENODEV;
  6965. done:
  6966. return 0;
  6967. }
  6968. /* return -ENODEV or other reason on error, 0 on success */
  6969. static int hpsa_enter_simple_mode(struct ctlr_info *h)
  6970. {
  6971. u32 trans_support;
  6972. trans_support = readl(&(h->cfgtable->TransportSupport));
  6973. if (!(trans_support & SIMPLE_MODE))
  6974. return -ENOTSUPP;
  6975. h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
  6976. /* Update the field, and then ring the doorbell */
  6977. writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
  6978. writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
  6979. writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
  6980. if (hpsa_wait_for_mode_change_ack(h))
  6981. goto error;
  6982. print_cfg_table(&h->pdev->dev, h->cfgtable);
  6983. if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
  6984. goto error;
  6985. h->transMethod = CFGTBL_Trans_Simple;
  6986. return 0;
  6987. error:
  6988. dev_err(&h->pdev->dev, "failed to enter simple mode\n");
  6989. return -ENODEV;
  6990. }
  6991. /* free items allocated or mapped by hpsa_pci_init */
  6992. static void hpsa_free_pci_init(struct ctlr_info *h)
  6993. {
  6994. hpsa_free_cfgtables(h); /* pci_init 4 */
  6995. iounmap(h->vaddr); /* pci_init 3 */
  6996. h->vaddr = NULL;
  6997. hpsa_disable_interrupt_mode(h); /* pci_init 2 */
  6998. /*
  6999. * call pci_disable_device before pci_release_regions per
  7000. * Documentation/driver-api/pci/pci.rst
  7001. */
  7002. pci_disable_device(h->pdev); /* pci_init 1 */
  7003. pci_release_regions(h->pdev); /* pci_init 2 */
  7004. }
  7005. /* several items must be freed later */
  7006. static int hpsa_pci_init(struct ctlr_info *h)
  7007. {
  7008. int prod_index, err;
  7009. bool legacy_board;
  7010. prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id, &legacy_board);
  7011. if (prod_index < 0)
  7012. return prod_index;
  7013. h->product_name = products[prod_index].product_name;
  7014. h->access = *(products[prod_index].access);
  7015. h->legacy_board = legacy_board;
  7016. pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
  7017. PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
  7018. err = pci_enable_device(h->pdev);
  7019. if (err) {
  7020. dev_err(&h->pdev->dev, "failed to enable PCI device\n");
  7021. pci_disable_device(h->pdev);
  7022. return err;
  7023. }
  7024. err = pci_request_regions(h->pdev, HPSA);
  7025. if (err) {
  7026. dev_err(&h->pdev->dev,
  7027. "failed to obtain PCI resources\n");
  7028. pci_disable_device(h->pdev);
  7029. return err;
  7030. }
  7031. pci_set_master(h->pdev);
  7032. err = hpsa_interrupt_mode(h);
  7033. if (err)
  7034. goto clean1;
  7035. /* setup mapping between CPU and reply queue */
  7036. hpsa_setup_reply_map(h);
  7037. err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
  7038. if (err)
  7039. goto clean2; /* intmode+region, pci */
  7040. h->vaddr = remap_pci_mem(h->paddr, 0x250);
  7041. if (!h->vaddr) {
  7042. dev_err(&h->pdev->dev, "failed to remap PCI mem\n");
  7043. err = -ENOMEM;
  7044. goto clean2; /* intmode+region, pci */
  7045. }
  7046. err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
  7047. if (err)
  7048. goto clean3; /* vaddr, intmode+region, pci */
  7049. err = hpsa_find_cfgtables(h);
  7050. if (err)
  7051. goto clean3; /* vaddr, intmode+region, pci */
  7052. hpsa_find_board_params(h);
  7053. if (!hpsa_CISS_signature_present(h)) {
  7054. err = -ENODEV;
  7055. goto clean4; /* cfgtables, vaddr, intmode+region, pci */
  7056. }
  7057. hpsa_set_driver_support_bits(h);
  7058. hpsa_p600_dma_prefetch_quirk(h);
  7059. err = hpsa_enter_simple_mode(h);
  7060. if (err)
  7061. goto clean4; /* cfgtables, vaddr, intmode+region, pci */
  7062. return 0;
  7063. clean4: /* cfgtables, vaddr, intmode+region, pci */
  7064. hpsa_free_cfgtables(h);
  7065. clean3: /* vaddr, intmode+region, pci */
  7066. iounmap(h->vaddr);
  7067. h->vaddr = NULL;
  7068. clean2: /* intmode+region, pci */
  7069. hpsa_disable_interrupt_mode(h);
  7070. clean1:
  7071. /*
  7072. * call pci_disable_device before pci_release_regions per
  7073. * Documentation/driver-api/pci/pci.rst
  7074. */
  7075. pci_disable_device(h->pdev);
  7076. pci_release_regions(h->pdev);
  7077. return err;
  7078. }
  7079. static void hpsa_hba_inquiry(struct ctlr_info *h)
  7080. {
  7081. int rc;
  7082. #define HBA_INQUIRY_BYTE_COUNT 64
  7083. h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
  7084. if (!h->hba_inquiry_data)
  7085. return;
  7086. rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
  7087. h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
  7088. if (rc != 0) {
  7089. kfree(h->hba_inquiry_data);
  7090. h->hba_inquiry_data = NULL;
  7091. }
  7092. }
  7093. static int hpsa_init_reset_devices(struct pci_dev *pdev, u32 board_id)
  7094. {
  7095. int rc, i;
  7096. void __iomem *vaddr;
  7097. if (!reset_devices)
  7098. return 0;
  7099. /* kdump kernel is loading, we don't know in which state is
  7100. * the pci interface. The dev->enable_cnt is equal zero
  7101. * so we call enable+disable, wait a while and switch it on.
  7102. */
  7103. rc = pci_enable_device(pdev);
  7104. if (rc) {
  7105. dev_warn(&pdev->dev, "Failed to enable PCI device\n");
  7106. return -ENODEV;
  7107. }
  7108. pci_disable_device(pdev);
  7109. msleep(260); /* a randomly chosen number */
  7110. rc = pci_enable_device(pdev);
  7111. if (rc) {
  7112. dev_warn(&pdev->dev, "failed to enable device.\n");
  7113. return -ENODEV;
  7114. }
  7115. pci_set_master(pdev);
  7116. vaddr = pci_ioremap_bar(pdev, 0);
  7117. if (vaddr == NULL) {
  7118. rc = -ENOMEM;
  7119. goto out_disable;
  7120. }
  7121. writel(SA5_INTR_OFF, vaddr + SA5_REPLY_INTR_MASK_OFFSET);
  7122. iounmap(vaddr);
  7123. /* Reset the controller with a PCI power-cycle or via doorbell */
  7124. rc = hpsa_kdump_hard_reset_controller(pdev, board_id);
  7125. /* -ENOTSUPP here means we cannot reset the controller
  7126. * but it's already (and still) up and running in
  7127. * "performant mode". Or, it might be 640x, which can't reset
  7128. * due to concerns about shared bbwc between 6402/6404 pair.
  7129. */
  7130. if (rc)
  7131. goto out_disable;
  7132. /* Now try to get the controller to respond to a no-op */
  7133. dev_info(&pdev->dev, "Waiting for controller to respond to no-op\n");
  7134. for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
  7135. if (hpsa_noop(pdev) == 0)
  7136. break;
  7137. else
  7138. dev_warn(&pdev->dev, "no-op failed%s\n",
  7139. (i < 11 ? "; re-trying" : ""));
  7140. }
  7141. out_disable:
  7142. pci_disable_device(pdev);
  7143. return rc;
  7144. }
  7145. static void hpsa_free_cmd_pool(struct ctlr_info *h)
  7146. {
  7147. bitmap_free(h->cmd_pool_bits);
  7148. h->cmd_pool_bits = NULL;
  7149. if (h->cmd_pool) {
  7150. dma_free_coherent(&h->pdev->dev,
  7151. h->nr_cmds * sizeof(struct CommandList),
  7152. h->cmd_pool,
  7153. h->cmd_pool_dhandle);
  7154. h->cmd_pool = NULL;
  7155. h->cmd_pool_dhandle = 0;
  7156. }
  7157. if (h->errinfo_pool) {
  7158. dma_free_coherent(&h->pdev->dev,
  7159. h->nr_cmds * sizeof(struct ErrorInfo),
  7160. h->errinfo_pool,
  7161. h->errinfo_pool_dhandle);
  7162. h->errinfo_pool = NULL;
  7163. h->errinfo_pool_dhandle = 0;
  7164. }
  7165. }
  7166. static int hpsa_alloc_cmd_pool(struct ctlr_info *h)
  7167. {
  7168. h->cmd_pool_bits = bitmap_zalloc(h->nr_cmds, GFP_KERNEL);
  7169. h->cmd_pool = dma_alloc_coherent(&h->pdev->dev,
  7170. h->nr_cmds * sizeof(*h->cmd_pool),
  7171. &h->cmd_pool_dhandle, GFP_KERNEL);
  7172. h->errinfo_pool = dma_alloc_coherent(&h->pdev->dev,
  7173. h->nr_cmds * sizeof(*h->errinfo_pool),
  7174. &h->errinfo_pool_dhandle, GFP_KERNEL);
  7175. if ((h->cmd_pool_bits == NULL)
  7176. || (h->cmd_pool == NULL)
  7177. || (h->errinfo_pool == NULL)) {
  7178. dev_err(&h->pdev->dev, "out of memory in %s", __func__);
  7179. goto clean_up;
  7180. }
  7181. hpsa_preinitialize_commands(h);
  7182. return 0;
  7183. clean_up:
  7184. hpsa_free_cmd_pool(h);
  7185. return -ENOMEM;
  7186. }
  7187. /* clear affinity hints and free MSI-X, MSI, or legacy INTx vectors */
  7188. static void hpsa_free_irqs(struct ctlr_info *h)
  7189. {
  7190. int i;
  7191. int irq_vector = 0;
  7192. if (hpsa_simple_mode)
  7193. irq_vector = h->intr_mode;
  7194. if (!h->msix_vectors || h->intr_mode != PERF_MODE_INT) {
  7195. /* Single reply queue, only one irq to free */
  7196. free_irq(pci_irq_vector(h->pdev, irq_vector),
  7197. &h->q[h->intr_mode]);
  7198. h->q[h->intr_mode] = 0;
  7199. return;
  7200. }
  7201. for (i = 0; i < h->msix_vectors; i++) {
  7202. free_irq(pci_irq_vector(h->pdev, i), &h->q[i]);
  7203. h->q[i] = 0;
  7204. }
  7205. for (; i < MAX_REPLY_QUEUES; i++)
  7206. h->q[i] = 0;
  7207. }
  7208. /* returns 0 on success; cleans up and returns -Enn on error */
  7209. static int hpsa_request_irqs(struct ctlr_info *h,
  7210. irqreturn_t (*msixhandler)(int, void *),
  7211. irqreturn_t (*intxhandler)(int, void *))
  7212. {
  7213. int rc, i;
  7214. int irq_vector = 0;
  7215. if (hpsa_simple_mode)
  7216. irq_vector = h->intr_mode;
  7217. /*
  7218. * initialize h->q[x] = x so that interrupt handlers know which
  7219. * queue to process.
  7220. */
  7221. for (i = 0; i < MAX_REPLY_QUEUES; i++)
  7222. h->q[i] = (u8) i;
  7223. if (h->intr_mode == PERF_MODE_INT && h->msix_vectors > 0) {
  7224. /* If performant mode and MSI-X, use multiple reply queues */
  7225. for (i = 0; i < h->msix_vectors; i++) {
  7226. sprintf(h->intrname[i], "%s-msix%d", h->devname, i);
  7227. rc = request_irq(pci_irq_vector(h->pdev, i), msixhandler,
  7228. 0, h->intrname[i],
  7229. &h->q[i]);
  7230. if (rc) {
  7231. int j;
  7232. dev_err(&h->pdev->dev,
  7233. "failed to get irq %d for %s\n",
  7234. pci_irq_vector(h->pdev, i), h->devname);
  7235. for (j = 0; j < i; j++) {
  7236. free_irq(pci_irq_vector(h->pdev, j), &h->q[j]);
  7237. h->q[j] = 0;
  7238. }
  7239. for (; j < MAX_REPLY_QUEUES; j++)
  7240. h->q[j] = 0;
  7241. return rc;
  7242. }
  7243. }
  7244. } else {
  7245. /* Use single reply pool */
  7246. if (h->msix_vectors > 0 || h->pdev->msi_enabled) {
  7247. sprintf(h->intrname[0], "%s-msi%s", h->devname,
  7248. h->msix_vectors ? "x" : "");
  7249. rc = request_irq(pci_irq_vector(h->pdev, irq_vector),
  7250. msixhandler, 0,
  7251. h->intrname[0],
  7252. &h->q[h->intr_mode]);
  7253. } else {
  7254. sprintf(h->intrname[h->intr_mode],
  7255. "%s-intx", h->devname);
  7256. rc = request_irq(pci_irq_vector(h->pdev, irq_vector),
  7257. intxhandler, IRQF_SHARED,
  7258. h->intrname[0],
  7259. &h->q[h->intr_mode]);
  7260. }
  7261. }
  7262. if (rc) {
  7263. dev_err(&h->pdev->dev, "failed to get irq %d for %s\n",
  7264. pci_irq_vector(h->pdev, irq_vector), h->devname);
  7265. hpsa_free_irqs(h);
  7266. return -ENODEV;
  7267. }
  7268. return 0;
  7269. }
  7270. static int hpsa_kdump_soft_reset(struct ctlr_info *h)
  7271. {
  7272. int rc;
  7273. hpsa_send_host_reset(h, HPSA_RESET_TYPE_CONTROLLER);
  7274. dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
  7275. rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY);
  7276. if (rc) {
  7277. dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
  7278. return rc;
  7279. }
  7280. dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
  7281. rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
  7282. if (rc) {
  7283. dev_warn(&h->pdev->dev, "Board failed to become ready "
  7284. "after soft reset.\n");
  7285. return rc;
  7286. }
  7287. return 0;
  7288. }
  7289. static void hpsa_free_reply_queues(struct ctlr_info *h)
  7290. {
  7291. int i;
  7292. for (i = 0; i < h->nreply_queues; i++) {
  7293. if (!h->reply_queue[i].head)
  7294. continue;
  7295. dma_free_coherent(&h->pdev->dev,
  7296. h->reply_queue_size,
  7297. h->reply_queue[i].head,
  7298. h->reply_queue[i].busaddr);
  7299. h->reply_queue[i].head = NULL;
  7300. h->reply_queue[i].busaddr = 0;
  7301. }
  7302. h->reply_queue_size = 0;
  7303. }
  7304. static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
  7305. {
  7306. hpsa_free_performant_mode(h); /* init_one 7 */
  7307. hpsa_free_sg_chain_blocks(h); /* init_one 6 */
  7308. hpsa_free_cmd_pool(h); /* init_one 5 */
  7309. hpsa_free_irqs(h); /* init_one 4 */
  7310. scsi_host_put(h->scsi_host); /* init_one 3 */
  7311. h->scsi_host = NULL; /* init_one 3 */
  7312. hpsa_free_pci_init(h); /* init_one 2_5 */
  7313. free_percpu(h->lockup_detected); /* init_one 2 */
  7314. h->lockup_detected = NULL; /* init_one 2 */
  7315. if (h->resubmit_wq) {
  7316. destroy_workqueue(h->resubmit_wq); /* init_one 1 */
  7317. h->resubmit_wq = NULL;
  7318. }
  7319. if (h->rescan_ctlr_wq) {
  7320. destroy_workqueue(h->rescan_ctlr_wq);
  7321. h->rescan_ctlr_wq = NULL;
  7322. }
  7323. if (h->monitor_ctlr_wq) {
  7324. destroy_workqueue(h->monitor_ctlr_wq);
  7325. h->monitor_ctlr_wq = NULL;
  7326. }
  7327. kfree(h); /* init_one 1 */
  7328. }
  7329. /* Called when controller lockup detected. */
  7330. static void fail_all_outstanding_cmds(struct ctlr_info *h)
  7331. {
  7332. int i, refcount;
  7333. struct CommandList *c;
  7334. int failcount = 0;
  7335. flush_workqueue(h->resubmit_wq); /* ensure all cmds are fully built */
  7336. for (i = 0; i < h->nr_cmds; i++) {
  7337. c = h->cmd_pool + i;
  7338. refcount = atomic_inc_return(&c->refcount);
  7339. if (refcount > 1) {
  7340. c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
  7341. finish_cmd(c);
  7342. atomic_dec(&h->commands_outstanding);
  7343. failcount++;
  7344. }
  7345. cmd_free(h, c);
  7346. }
  7347. dev_warn(&h->pdev->dev,
  7348. "failed %d commands in fail_all\n", failcount);
  7349. }
  7350. static void set_lockup_detected_for_all_cpus(struct ctlr_info *h, u32 value)
  7351. {
  7352. int cpu;
  7353. for_each_online_cpu(cpu) {
  7354. u32 *lockup_detected;
  7355. lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
  7356. *lockup_detected = value;
  7357. }
  7358. wmb(); /* be sure the per-cpu variables are out to memory */
  7359. }
  7360. static void controller_lockup_detected(struct ctlr_info *h)
  7361. {
  7362. unsigned long flags;
  7363. u32 lockup_detected;
  7364. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  7365. spin_lock_irqsave(&h->lock, flags);
  7366. lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
  7367. if (!lockup_detected) {
  7368. /* no heartbeat, but controller gave us a zero. */
  7369. dev_warn(&h->pdev->dev,
  7370. "lockup detected after %d but scratchpad register is zero\n",
  7371. h->heartbeat_sample_interval / HZ);
  7372. lockup_detected = 0xffffffff;
  7373. }
  7374. set_lockup_detected_for_all_cpus(h, lockup_detected);
  7375. spin_unlock_irqrestore(&h->lock, flags);
  7376. dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x after %d\n",
  7377. lockup_detected, h->heartbeat_sample_interval / HZ);
  7378. if (lockup_detected == 0xffff0000) {
  7379. dev_warn(&h->pdev->dev, "Telling controller to do a CHKPT\n");
  7380. writel(DOORBELL_GENERATE_CHKPT, h->vaddr + SA5_DOORBELL);
  7381. }
  7382. pci_disable_device(h->pdev);
  7383. fail_all_outstanding_cmds(h);
  7384. }
  7385. static int detect_controller_lockup(struct ctlr_info *h)
  7386. {
  7387. u64 now;
  7388. u32 heartbeat;
  7389. unsigned long flags;
  7390. now = get_jiffies_64();
  7391. /* If we've received an interrupt recently, we're ok. */
  7392. if (time_after64(h->last_intr_timestamp +
  7393. (h->heartbeat_sample_interval), now))
  7394. return false;
  7395. /*
  7396. * If we've already checked the heartbeat recently, we're ok.
  7397. * This could happen if someone sends us a signal. We
  7398. * otherwise don't care about signals in this thread.
  7399. */
  7400. if (time_after64(h->last_heartbeat_timestamp +
  7401. (h->heartbeat_sample_interval), now))
  7402. return false;
  7403. /* If heartbeat has not changed since we last looked, we're not ok. */
  7404. spin_lock_irqsave(&h->lock, flags);
  7405. heartbeat = readl(&h->cfgtable->HeartBeat);
  7406. spin_unlock_irqrestore(&h->lock, flags);
  7407. if (h->last_heartbeat == heartbeat) {
  7408. controller_lockup_detected(h);
  7409. return true;
  7410. }
  7411. /* We're ok. */
  7412. h->last_heartbeat = heartbeat;
  7413. h->last_heartbeat_timestamp = now;
  7414. return false;
  7415. }
  7416. /*
  7417. * Set ioaccel status for all ioaccel volumes.
  7418. *
  7419. * Called from monitor controller worker (hpsa_event_monitor_worker)
  7420. *
  7421. * A Volume (or Volumes that comprise an Array set) may be undergoing a
  7422. * transformation, so we will be turning off ioaccel for all volumes that
  7423. * make up the Array.
  7424. */
  7425. static void hpsa_set_ioaccel_status(struct ctlr_info *h)
  7426. {
  7427. int rc;
  7428. int i;
  7429. u8 ioaccel_status;
  7430. unsigned char *buf;
  7431. struct hpsa_scsi_dev_t *device;
  7432. if (!h)
  7433. return;
  7434. buf = kmalloc(64, GFP_KERNEL);
  7435. if (!buf)
  7436. return;
  7437. /*
  7438. * Run through current device list used during I/O requests.
  7439. */
  7440. for (i = 0; i < h->ndevices; i++) {
  7441. int offload_to_be_enabled = 0;
  7442. int offload_config = 0;
  7443. device = h->dev[i];
  7444. if (!device)
  7445. continue;
  7446. if (!hpsa_vpd_page_supported(h, device->scsi3addr,
  7447. HPSA_VPD_LV_IOACCEL_STATUS))
  7448. continue;
  7449. memset(buf, 0, 64);
  7450. rc = hpsa_scsi_do_inquiry(h, device->scsi3addr,
  7451. VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS,
  7452. buf, 64);
  7453. if (rc != 0)
  7454. continue;
  7455. ioaccel_status = buf[IOACCEL_STATUS_BYTE];
  7456. /*
  7457. * Check if offload is still configured on
  7458. */
  7459. offload_config =
  7460. !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
  7461. /*
  7462. * If offload is configured on, check to see if ioaccel
  7463. * needs to be enabled.
  7464. */
  7465. if (offload_config)
  7466. offload_to_be_enabled =
  7467. !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
  7468. /*
  7469. * If ioaccel is to be re-enabled, re-enable later during the
  7470. * scan operation so the driver can get a fresh raidmap
  7471. * before turning ioaccel back on.
  7472. */
  7473. if (offload_to_be_enabled)
  7474. continue;
  7475. /*
  7476. * Immediately turn off ioaccel for any volume the
  7477. * controller tells us to. Some of the reasons could be:
  7478. * transformation - change to the LVs of an Array.
  7479. * degraded volume - component failure
  7480. */
  7481. hpsa_turn_off_ioaccel_for_device(device);
  7482. }
  7483. kfree(buf);
  7484. }
  7485. static void hpsa_ack_ctlr_events(struct ctlr_info *h)
  7486. {
  7487. char *event_type;
  7488. if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
  7489. return;
  7490. /* Ask the controller to clear the events we're handling. */
  7491. if ((h->transMethod & (CFGTBL_Trans_io_accel1
  7492. | CFGTBL_Trans_io_accel2)) &&
  7493. (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
  7494. h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
  7495. if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
  7496. event_type = "state change";
  7497. if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
  7498. event_type = "configuration change";
  7499. /* Stop sending new RAID offload reqs via the IO accelerator */
  7500. scsi_block_requests(h->scsi_host);
  7501. hpsa_set_ioaccel_status(h);
  7502. hpsa_drain_accel_commands(h);
  7503. /* Set 'accelerator path config change' bit */
  7504. dev_warn(&h->pdev->dev,
  7505. "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
  7506. h->events, event_type);
  7507. writel(h->events, &(h->cfgtable->clear_event_notify));
  7508. /* Set the "clear event notify field update" bit 6 */
  7509. writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
  7510. /* Wait until ctlr clears 'clear event notify field', bit 6 */
  7511. hpsa_wait_for_clear_event_notify_ack(h);
  7512. scsi_unblock_requests(h->scsi_host);
  7513. } else {
  7514. /* Acknowledge controller notification events. */
  7515. writel(h->events, &(h->cfgtable->clear_event_notify));
  7516. writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
  7517. hpsa_wait_for_clear_event_notify_ack(h);
  7518. }
  7519. return;
  7520. }
  7521. /* Check a register on the controller to see if there are configuration
  7522. * changes (added/changed/removed logical drives, etc.) which mean that
  7523. * we should rescan the controller for devices.
  7524. * Also check flag for driver-initiated rescan.
  7525. */
  7526. static int hpsa_ctlr_needs_rescan(struct ctlr_info *h)
  7527. {
  7528. if (h->drv_req_rescan) {
  7529. h->drv_req_rescan = 0;
  7530. return 1;
  7531. }
  7532. if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
  7533. return 0;
  7534. h->events = readl(&(h->cfgtable->event_notify));
  7535. return h->events & RESCAN_REQUIRED_EVENT_BITS;
  7536. }
  7537. /*
  7538. * Check if any of the offline devices have become ready
  7539. */
  7540. static int hpsa_offline_devices_ready(struct ctlr_info *h)
  7541. {
  7542. unsigned long flags;
  7543. struct offline_device_entry *d;
  7544. struct list_head *this, *tmp;
  7545. spin_lock_irqsave(&h->offline_device_lock, flags);
  7546. list_for_each_safe(this, tmp, &h->offline_device_list) {
  7547. d = list_entry(this, struct offline_device_entry,
  7548. offline_list);
  7549. spin_unlock_irqrestore(&h->offline_device_lock, flags);
  7550. if (!hpsa_volume_offline(h, d->scsi3addr)) {
  7551. spin_lock_irqsave(&h->offline_device_lock, flags);
  7552. list_del(&d->offline_list);
  7553. spin_unlock_irqrestore(&h->offline_device_lock, flags);
  7554. return 1;
  7555. }
  7556. spin_lock_irqsave(&h->offline_device_lock, flags);
  7557. }
  7558. spin_unlock_irqrestore(&h->offline_device_lock, flags);
  7559. return 0;
  7560. }
  7561. static int hpsa_luns_changed(struct ctlr_info *h)
  7562. {
  7563. int rc = 1; /* assume there are changes */
  7564. struct ReportLUNdata *logdev = NULL;
  7565. /* if we can't find out if lun data has changed,
  7566. * assume that it has.
  7567. */
  7568. if (!h->lastlogicals)
  7569. return rc;
  7570. logdev = kzalloc(sizeof(*logdev), GFP_KERNEL);
  7571. if (!logdev)
  7572. return rc;
  7573. if (hpsa_scsi_do_report_luns(h, 1, logdev, sizeof(*logdev), 0)) {
  7574. dev_warn(&h->pdev->dev,
  7575. "report luns failed, can't track lun changes.\n");
  7576. goto out;
  7577. }
  7578. if (memcmp(logdev, h->lastlogicals, sizeof(*logdev))) {
  7579. dev_info(&h->pdev->dev,
  7580. "Lun changes detected.\n");
  7581. memcpy(h->lastlogicals, logdev, sizeof(*logdev));
  7582. goto out;
  7583. } else
  7584. rc = 0; /* no changes detected. */
  7585. out:
  7586. kfree(logdev);
  7587. return rc;
  7588. }
  7589. static void hpsa_perform_rescan(struct ctlr_info *h)
  7590. {
  7591. struct Scsi_Host *sh = NULL;
  7592. unsigned long flags;
  7593. /*
  7594. * Do the scan after the reset
  7595. */
  7596. spin_lock_irqsave(&h->reset_lock, flags);
  7597. if (h->reset_in_progress) {
  7598. h->drv_req_rescan = 1;
  7599. spin_unlock_irqrestore(&h->reset_lock, flags);
  7600. return;
  7601. }
  7602. spin_unlock_irqrestore(&h->reset_lock, flags);
  7603. sh = scsi_host_get(h->scsi_host);
  7604. if (sh != NULL) {
  7605. hpsa_scan_start(sh);
  7606. scsi_host_put(sh);
  7607. h->drv_req_rescan = 0;
  7608. }
  7609. }
  7610. /*
  7611. * watch for controller events
  7612. */
  7613. static void hpsa_event_monitor_worker(struct work_struct *work)
  7614. {
  7615. struct ctlr_info *h = container_of(to_delayed_work(work),
  7616. struct ctlr_info, event_monitor_work);
  7617. unsigned long flags;
  7618. spin_lock_irqsave(&h->lock, flags);
  7619. if (h->remove_in_progress) {
  7620. spin_unlock_irqrestore(&h->lock, flags);
  7621. return;
  7622. }
  7623. spin_unlock_irqrestore(&h->lock, flags);
  7624. if (hpsa_ctlr_needs_rescan(h)) {
  7625. hpsa_ack_ctlr_events(h);
  7626. hpsa_perform_rescan(h);
  7627. }
  7628. spin_lock_irqsave(&h->lock, flags);
  7629. if (!h->remove_in_progress)
  7630. queue_delayed_work(h->monitor_ctlr_wq, &h->event_monitor_work,
  7631. HPSA_EVENT_MONITOR_INTERVAL);
  7632. spin_unlock_irqrestore(&h->lock, flags);
  7633. }
  7634. static void hpsa_rescan_ctlr_worker(struct work_struct *work)
  7635. {
  7636. unsigned long flags;
  7637. struct ctlr_info *h = container_of(to_delayed_work(work),
  7638. struct ctlr_info, rescan_ctlr_work);
  7639. spin_lock_irqsave(&h->lock, flags);
  7640. if (h->remove_in_progress) {
  7641. spin_unlock_irqrestore(&h->lock, flags);
  7642. return;
  7643. }
  7644. spin_unlock_irqrestore(&h->lock, flags);
  7645. if (h->drv_req_rescan || hpsa_offline_devices_ready(h)) {
  7646. hpsa_perform_rescan(h);
  7647. } else if (h->discovery_polling) {
  7648. if (hpsa_luns_changed(h)) {
  7649. dev_info(&h->pdev->dev,
  7650. "driver discovery polling rescan.\n");
  7651. hpsa_perform_rescan(h);
  7652. }
  7653. }
  7654. spin_lock_irqsave(&h->lock, flags);
  7655. if (!h->remove_in_progress)
  7656. queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
  7657. h->heartbeat_sample_interval);
  7658. spin_unlock_irqrestore(&h->lock, flags);
  7659. }
  7660. static void hpsa_monitor_ctlr_worker(struct work_struct *work)
  7661. {
  7662. unsigned long flags;
  7663. struct ctlr_info *h = container_of(to_delayed_work(work),
  7664. struct ctlr_info, monitor_ctlr_work);
  7665. detect_controller_lockup(h);
  7666. if (lockup_detected(h))
  7667. return;
  7668. spin_lock_irqsave(&h->lock, flags);
  7669. if (!h->remove_in_progress)
  7670. queue_delayed_work(h->monitor_ctlr_wq, &h->monitor_ctlr_work,
  7671. h->heartbeat_sample_interval);
  7672. spin_unlock_irqrestore(&h->lock, flags);
  7673. }
  7674. static struct workqueue_struct *hpsa_create_controller_wq(struct ctlr_info *h,
  7675. char *name)
  7676. {
  7677. struct workqueue_struct *wq = NULL;
  7678. wq = alloc_ordered_workqueue("%s_%d_hpsa", 0, name, h->ctlr);
  7679. if (!wq)
  7680. dev_err(&h->pdev->dev, "failed to create %s workqueue\n", name);
  7681. return wq;
  7682. }
  7683. static void hpda_free_ctlr_info(struct ctlr_info *h)
  7684. {
  7685. kfree(h->reply_map);
  7686. kfree(h);
  7687. }
  7688. static struct ctlr_info *hpda_alloc_ctlr_info(void)
  7689. {
  7690. struct ctlr_info *h;
  7691. h = kzalloc(sizeof(*h), GFP_KERNEL);
  7692. if (!h)
  7693. return NULL;
  7694. h->reply_map = kcalloc(nr_cpu_ids, sizeof(*h->reply_map), GFP_KERNEL);
  7695. if (!h->reply_map) {
  7696. kfree(h);
  7697. return NULL;
  7698. }
  7699. return h;
  7700. }
  7701. static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  7702. {
  7703. int rc;
  7704. struct ctlr_info *h;
  7705. int try_soft_reset = 0;
  7706. unsigned long flags;
  7707. u32 board_id;
  7708. if (number_of_controllers == 0)
  7709. printk(KERN_INFO DRIVER_NAME "\n");
  7710. rc = hpsa_lookup_board_id(pdev, &board_id, NULL);
  7711. if (rc < 0) {
  7712. dev_warn(&pdev->dev, "Board ID not found\n");
  7713. return rc;
  7714. }
  7715. rc = hpsa_init_reset_devices(pdev, board_id);
  7716. if (rc) {
  7717. if (rc != -ENOTSUPP)
  7718. return rc;
  7719. /* If the reset fails in a particular way (it has no way to do
  7720. * a proper hard reset, so returns -ENOTSUPP) we can try to do
  7721. * a soft reset once we get the controller configured up to the
  7722. * point that it can accept a command.
  7723. */
  7724. try_soft_reset = 1;
  7725. rc = 0;
  7726. }
  7727. reinit_after_soft_reset:
  7728. /* Command structures must be aligned on a 32-byte boundary because
  7729. * the 5 lower bits of the address are used by the hardware. and by
  7730. * the driver. See comments in hpsa.h for more info.
  7731. */
  7732. BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
  7733. h = hpda_alloc_ctlr_info();
  7734. if (!h) {
  7735. dev_err(&pdev->dev, "Failed to allocate controller head\n");
  7736. return -ENOMEM;
  7737. }
  7738. h->pdev = pdev;
  7739. h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
  7740. INIT_LIST_HEAD(&h->offline_device_list);
  7741. spin_lock_init(&h->lock);
  7742. spin_lock_init(&h->offline_device_lock);
  7743. spin_lock_init(&h->scan_lock);
  7744. spin_lock_init(&h->reset_lock);
  7745. atomic_set(&h->passthru_cmds_avail, HPSA_MAX_CONCURRENT_PASSTHRUS);
  7746. /* Allocate and clear per-cpu variable lockup_detected */
  7747. h->lockup_detected = alloc_percpu(u32);
  7748. if (!h->lockup_detected) {
  7749. dev_err(&h->pdev->dev, "Failed to allocate lockup detector\n");
  7750. rc = -ENOMEM;
  7751. goto clean1; /* aer/h */
  7752. }
  7753. set_lockup_detected_for_all_cpus(h, 0);
  7754. rc = hpsa_pci_init(h);
  7755. if (rc)
  7756. goto clean2; /* lu, aer/h */
  7757. /* relies on h-> settings made by hpsa_pci_init, including
  7758. * interrupt_mode h->intr */
  7759. rc = hpsa_scsi_host_alloc(h);
  7760. if (rc)
  7761. goto clean2_5; /* pci, lu, aer/h */
  7762. sprintf(h->devname, HPSA "%d", h->scsi_host->host_no);
  7763. h->ctlr = number_of_controllers;
  7764. number_of_controllers++;
  7765. /* configure PCI DMA stuff */
  7766. rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
  7767. if (rc != 0) {
  7768. rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
  7769. if (rc != 0) {
  7770. dev_err(&pdev->dev, "no suitable DMA available\n");
  7771. goto clean3; /* shost, pci, lu, aer/h */
  7772. }
  7773. }
  7774. /* make sure the board interrupts are off */
  7775. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  7776. rc = hpsa_request_irqs(h, do_hpsa_intr_msi, do_hpsa_intr_intx);
  7777. if (rc)
  7778. goto clean3; /* shost, pci, lu, aer/h */
  7779. rc = hpsa_alloc_cmd_pool(h);
  7780. if (rc)
  7781. goto clean4; /* irq, shost, pci, lu, aer/h */
  7782. rc = hpsa_alloc_sg_chain_blocks(h);
  7783. if (rc)
  7784. goto clean5; /* cmd, irq, shost, pci, lu, aer/h */
  7785. init_waitqueue_head(&h->scan_wait_queue);
  7786. init_waitqueue_head(&h->event_sync_wait_queue);
  7787. mutex_init(&h->reset_mutex);
  7788. h->scan_finished = 1; /* no scan currently in progress */
  7789. h->scan_waiting = 0;
  7790. pci_set_drvdata(pdev, h);
  7791. h->ndevices = 0;
  7792. spin_lock_init(&h->devlock);
  7793. rc = hpsa_put_ctlr_into_performant_mode(h);
  7794. if (rc)
  7795. goto clean6; /* sg, cmd, irq, shost, pci, lu, aer/h */
  7796. /* create the resubmit workqueue */
  7797. h->rescan_ctlr_wq = hpsa_create_controller_wq(h, "rescan");
  7798. if (!h->rescan_ctlr_wq) {
  7799. rc = -ENOMEM;
  7800. goto clean7;
  7801. }
  7802. h->resubmit_wq = hpsa_create_controller_wq(h, "resubmit");
  7803. if (!h->resubmit_wq) {
  7804. rc = -ENOMEM;
  7805. goto clean7; /* aer/h */
  7806. }
  7807. h->monitor_ctlr_wq = hpsa_create_controller_wq(h, "monitor");
  7808. if (!h->monitor_ctlr_wq) {
  7809. rc = -ENOMEM;
  7810. goto clean7;
  7811. }
  7812. /*
  7813. * At this point, the controller is ready to take commands.
  7814. * Now, if reset_devices and the hard reset didn't work, try
  7815. * the soft reset and see if that works.
  7816. */
  7817. if (try_soft_reset) {
  7818. /* This is kind of gross. We may or may not get a completion
  7819. * from the soft reset command, and if we do, then the value
  7820. * from the fifo may or may not be valid. So, we wait 10 secs
  7821. * after the reset throwing away any completions we get during
  7822. * that time. Unregister the interrupt handler and register
  7823. * fake ones to scoop up any residual completions.
  7824. */
  7825. spin_lock_irqsave(&h->lock, flags);
  7826. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  7827. spin_unlock_irqrestore(&h->lock, flags);
  7828. hpsa_free_irqs(h);
  7829. rc = hpsa_request_irqs(h, hpsa_msix_discard_completions,
  7830. hpsa_intx_discard_completions);
  7831. if (rc) {
  7832. dev_warn(&h->pdev->dev,
  7833. "Failed to request_irq after soft reset.\n");
  7834. /*
  7835. * cannot goto clean7 or free_irqs will be called
  7836. * again. Instead, do its work
  7837. */
  7838. hpsa_free_performant_mode(h); /* clean7 */
  7839. hpsa_free_sg_chain_blocks(h); /* clean6 */
  7840. hpsa_free_cmd_pool(h); /* clean5 */
  7841. /*
  7842. * skip hpsa_free_irqs(h) clean4 since that
  7843. * was just called before request_irqs failed
  7844. */
  7845. goto clean3;
  7846. }
  7847. rc = hpsa_kdump_soft_reset(h);
  7848. if (rc)
  7849. /* Neither hard nor soft reset worked, we're hosed. */
  7850. goto clean7;
  7851. dev_info(&h->pdev->dev, "Board READY.\n");
  7852. dev_info(&h->pdev->dev,
  7853. "Waiting for stale completions to drain.\n");
  7854. h->access.set_intr_mask(h, HPSA_INTR_ON);
  7855. msleep(10000);
  7856. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  7857. rc = controller_reset_failed(h->cfgtable);
  7858. if (rc)
  7859. dev_info(&h->pdev->dev,
  7860. "Soft reset appears to have failed.\n");
  7861. /* since the controller's reset, we have to go back and re-init
  7862. * everything. Easiest to just forget what we've done and do it
  7863. * all over again.
  7864. */
  7865. hpsa_undo_allocations_after_kdump_soft_reset(h);
  7866. try_soft_reset = 0;
  7867. if (rc)
  7868. /* don't goto clean, we already unallocated */
  7869. return -ENODEV;
  7870. goto reinit_after_soft_reset;
  7871. }
  7872. /* Enable Accelerated IO path at driver layer */
  7873. h->acciopath_status = 1;
  7874. /* Disable discovery polling.*/
  7875. h->discovery_polling = 0;
  7876. /* Turn the interrupts on so we can service requests */
  7877. h->access.set_intr_mask(h, HPSA_INTR_ON);
  7878. hpsa_hba_inquiry(h);
  7879. h->lastlogicals = kzalloc(sizeof(*(h->lastlogicals)), GFP_KERNEL);
  7880. if (!h->lastlogicals)
  7881. dev_info(&h->pdev->dev,
  7882. "Can't track change to report lun data\n");
  7883. /* hook into SCSI subsystem */
  7884. rc = hpsa_scsi_add_host(h);
  7885. if (rc)
  7886. goto clean8; /* lastlogicals, perf, sg, cmd, irq, shost, pci, lu, aer/h */
  7887. /* Monitor the controller for firmware lockups */
  7888. h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
  7889. INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
  7890. schedule_delayed_work(&h->monitor_ctlr_work,
  7891. h->heartbeat_sample_interval);
  7892. INIT_DELAYED_WORK(&h->rescan_ctlr_work, hpsa_rescan_ctlr_worker);
  7893. queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
  7894. h->heartbeat_sample_interval);
  7895. INIT_DELAYED_WORK(&h->event_monitor_work, hpsa_event_monitor_worker);
  7896. schedule_delayed_work(&h->event_monitor_work,
  7897. HPSA_EVENT_MONITOR_INTERVAL);
  7898. return 0;
  7899. clean8: /* lastlogicals, perf, sg, cmd, irq, shost, pci, lu, aer/h */
  7900. kfree(h->lastlogicals);
  7901. clean7: /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
  7902. hpsa_free_performant_mode(h);
  7903. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  7904. clean6: /* sg, cmd, irq, pci, lockup, wq/aer/h */
  7905. hpsa_free_sg_chain_blocks(h);
  7906. clean5: /* cmd, irq, shost, pci, lu, aer/h */
  7907. hpsa_free_cmd_pool(h);
  7908. clean4: /* irq, shost, pci, lu, aer/h */
  7909. hpsa_free_irqs(h);
  7910. clean3: /* shost, pci, lu, aer/h */
  7911. scsi_host_put(h->scsi_host);
  7912. h->scsi_host = NULL;
  7913. clean2_5: /* pci, lu, aer/h */
  7914. hpsa_free_pci_init(h);
  7915. clean2: /* lu, aer/h */
  7916. if (h->lockup_detected) {
  7917. free_percpu(h->lockup_detected);
  7918. h->lockup_detected = NULL;
  7919. }
  7920. clean1: /* wq/aer/h */
  7921. if (h->resubmit_wq) {
  7922. destroy_workqueue(h->resubmit_wq);
  7923. h->resubmit_wq = NULL;
  7924. }
  7925. if (h->rescan_ctlr_wq) {
  7926. destroy_workqueue(h->rescan_ctlr_wq);
  7927. h->rescan_ctlr_wq = NULL;
  7928. }
  7929. if (h->monitor_ctlr_wq) {
  7930. destroy_workqueue(h->monitor_ctlr_wq);
  7931. h->monitor_ctlr_wq = NULL;
  7932. }
  7933. hpda_free_ctlr_info(h);
  7934. return rc;
  7935. }
  7936. static void hpsa_flush_cache(struct ctlr_info *h)
  7937. {
  7938. char *flush_buf;
  7939. struct CommandList *c;
  7940. int rc;
  7941. if (unlikely(lockup_detected(h)))
  7942. return;
  7943. flush_buf = kzalloc(4, GFP_KERNEL);
  7944. if (!flush_buf)
  7945. return;
  7946. c = cmd_alloc(h);
  7947. if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
  7948. RAID_CTLR_LUNID, TYPE_CMD)) {
  7949. goto out;
  7950. }
  7951. rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_TO_DEVICE,
  7952. DEFAULT_TIMEOUT);
  7953. if (rc)
  7954. goto out;
  7955. if (c->err_info->CommandStatus != 0)
  7956. out:
  7957. dev_warn(&h->pdev->dev,
  7958. "error flushing cache on controller\n");
  7959. cmd_free(h, c);
  7960. kfree(flush_buf);
  7961. }
  7962. /* Make controller gather fresh report lun data each time we
  7963. * send down a report luns request
  7964. */
  7965. static void hpsa_disable_rld_caching(struct ctlr_info *h)
  7966. {
  7967. u32 *options;
  7968. struct CommandList *c;
  7969. int rc;
  7970. /* Don't bother trying to set diag options if locked up */
  7971. if (unlikely(h->lockup_detected))
  7972. return;
  7973. options = kzalloc(sizeof(*options), GFP_KERNEL);
  7974. if (!options)
  7975. return;
  7976. c = cmd_alloc(h);
  7977. /* first, get the current diag options settings */
  7978. if (fill_cmd(c, BMIC_SENSE_DIAG_OPTIONS, h, options, 4, 0,
  7979. RAID_CTLR_LUNID, TYPE_CMD))
  7980. goto errout;
  7981. rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE,
  7982. NO_TIMEOUT);
  7983. if ((rc != 0) || (c->err_info->CommandStatus != 0))
  7984. goto errout;
  7985. /* Now, set the bit for disabling the RLD caching */
  7986. *options |= HPSA_DIAG_OPTS_DISABLE_RLD_CACHING;
  7987. if (fill_cmd(c, BMIC_SET_DIAG_OPTIONS, h, options, 4, 0,
  7988. RAID_CTLR_LUNID, TYPE_CMD))
  7989. goto errout;
  7990. rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_TO_DEVICE,
  7991. NO_TIMEOUT);
  7992. if ((rc != 0) || (c->err_info->CommandStatus != 0))
  7993. goto errout;
  7994. /* Now verify that it got set: */
  7995. if (fill_cmd(c, BMIC_SENSE_DIAG_OPTIONS, h, options, 4, 0,
  7996. RAID_CTLR_LUNID, TYPE_CMD))
  7997. goto errout;
  7998. rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE,
  7999. NO_TIMEOUT);
  8000. if ((rc != 0) || (c->err_info->CommandStatus != 0))
  8001. goto errout;
  8002. if (*options & HPSA_DIAG_OPTS_DISABLE_RLD_CACHING)
  8003. goto out;
  8004. errout:
  8005. dev_err(&h->pdev->dev,
  8006. "Error: failed to disable report lun data caching.\n");
  8007. out:
  8008. cmd_free(h, c);
  8009. kfree(options);
  8010. }
  8011. static void __hpsa_shutdown(struct pci_dev *pdev)
  8012. {
  8013. struct ctlr_info *h;
  8014. h = pci_get_drvdata(pdev);
  8015. /* Turn board interrupts off and send the flush cache command
  8016. * sendcmd will turn off interrupt, and send the flush...
  8017. * To write all data in the battery backed cache to disks
  8018. */
  8019. hpsa_flush_cache(h);
  8020. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  8021. hpsa_free_irqs(h); /* init_one 4 */
  8022. hpsa_disable_interrupt_mode(h); /* pci_init 2 */
  8023. }
  8024. static void hpsa_shutdown(struct pci_dev *pdev)
  8025. {
  8026. __hpsa_shutdown(pdev);
  8027. pci_disable_device(pdev);
  8028. }
  8029. static void hpsa_free_device_info(struct ctlr_info *h)
  8030. {
  8031. int i;
  8032. for (i = 0; i < h->ndevices; i++) {
  8033. kfree(h->dev[i]);
  8034. h->dev[i] = NULL;
  8035. }
  8036. }
  8037. static void hpsa_remove_one(struct pci_dev *pdev)
  8038. {
  8039. struct ctlr_info *h;
  8040. unsigned long flags;
  8041. if (pci_get_drvdata(pdev) == NULL) {
  8042. dev_err(&pdev->dev, "unable to remove device\n");
  8043. return;
  8044. }
  8045. h = pci_get_drvdata(pdev);
  8046. /* Get rid of any controller monitoring work items */
  8047. spin_lock_irqsave(&h->lock, flags);
  8048. h->remove_in_progress = 1;
  8049. spin_unlock_irqrestore(&h->lock, flags);
  8050. cancel_delayed_work_sync(&h->monitor_ctlr_work);
  8051. cancel_delayed_work_sync(&h->rescan_ctlr_work);
  8052. cancel_delayed_work_sync(&h->event_monitor_work);
  8053. destroy_workqueue(h->rescan_ctlr_wq);
  8054. destroy_workqueue(h->resubmit_wq);
  8055. destroy_workqueue(h->monitor_ctlr_wq);
  8056. hpsa_delete_sas_host(h);
  8057. /*
  8058. * Call before disabling interrupts.
  8059. * scsi_remove_host can trigger I/O operations especially
  8060. * when multipath is enabled. There can be SYNCHRONIZE CACHE
  8061. * operations which cannot complete and will hang the system.
  8062. */
  8063. if (h->scsi_host)
  8064. scsi_remove_host(h->scsi_host); /* init_one 8 */
  8065. /* includes hpsa_free_irqs - init_one 4 */
  8066. /* includes hpsa_disable_interrupt_mode - pci_init 2 */
  8067. __hpsa_shutdown(pdev);
  8068. hpsa_free_device_info(h); /* scan */
  8069. kfree(h->hba_inquiry_data); /* init_one 10 */
  8070. h->hba_inquiry_data = NULL; /* init_one 10 */
  8071. hpsa_free_ioaccel2_sg_chain_blocks(h);
  8072. hpsa_free_performant_mode(h); /* init_one 7 */
  8073. hpsa_free_sg_chain_blocks(h); /* init_one 6 */
  8074. hpsa_free_cmd_pool(h); /* init_one 5 */
  8075. kfree(h->lastlogicals);
  8076. /* hpsa_free_irqs already called via hpsa_shutdown init_one 4 */
  8077. scsi_host_put(h->scsi_host); /* init_one 3 */
  8078. h->scsi_host = NULL; /* init_one 3 */
  8079. /* includes hpsa_disable_interrupt_mode - pci_init 2 */
  8080. hpsa_free_pci_init(h); /* init_one 2.5 */
  8081. free_percpu(h->lockup_detected); /* init_one 2 */
  8082. h->lockup_detected = NULL; /* init_one 2 */
  8083. /* (void) pci_disable_pcie_error_reporting(pdev); */ /* init_one 1 */
  8084. hpda_free_ctlr_info(h); /* init_one 1 */
  8085. }
  8086. static int __maybe_unused hpsa_suspend(
  8087. __attribute__((unused)) struct device *dev)
  8088. {
  8089. return -ENOSYS;
  8090. }
  8091. static int __maybe_unused hpsa_resume
  8092. (__attribute__((unused)) struct device *dev)
  8093. {
  8094. return -ENOSYS;
  8095. }
  8096. static SIMPLE_DEV_PM_OPS(hpsa_pm_ops, hpsa_suspend, hpsa_resume);
  8097. static struct pci_driver hpsa_pci_driver = {
  8098. .name = HPSA,
  8099. .probe = hpsa_init_one,
  8100. .remove = hpsa_remove_one,
  8101. .id_table = hpsa_pci_device_id, /* id_table */
  8102. .shutdown = hpsa_shutdown,
  8103. .driver.pm = &hpsa_pm_ops,
  8104. };
  8105. /* Fill in bucket_map[], given nsgs (the max number of
  8106. * scatter gather elements supported) and bucket[],
  8107. * which is an array of 8 integers. The bucket[] array
  8108. * contains 8 different DMA transfer sizes (in 16
  8109. * byte increments) which the controller uses to fetch
  8110. * commands. This function fills in bucket_map[], which
  8111. * maps a given number of scatter gather elements to one of
  8112. * the 8 DMA transfer sizes. The point of it is to allow the
  8113. * controller to only do as much DMA as needed to fetch the
  8114. * command, with the DMA transfer size encoded in the lower
  8115. * bits of the command address.
  8116. */
  8117. static void calc_bucket_map(int bucket[], int num_buckets,
  8118. int nsgs, int min_blocks, u32 *bucket_map)
  8119. {
  8120. int i, j, b, size;
  8121. /* Note, bucket_map must have nsgs+1 entries. */
  8122. for (i = 0; i <= nsgs; i++) {
  8123. /* Compute size of a command with i SG entries */
  8124. size = i + min_blocks;
  8125. b = num_buckets; /* Assume the biggest bucket */
  8126. /* Find the bucket that is just big enough */
  8127. for (j = 0; j < num_buckets; j++) {
  8128. if (bucket[j] >= size) {
  8129. b = j;
  8130. break;
  8131. }
  8132. }
  8133. /* for a command with i SG entries, use bucket b. */
  8134. bucket_map[i] = b;
  8135. }
  8136. }
  8137. /*
  8138. * return -ENODEV on err, 0 on success (or no action)
  8139. * allocates numerous items that must be freed later
  8140. */
  8141. static int hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
  8142. {
  8143. int i;
  8144. unsigned long register_value;
  8145. unsigned long transMethod = CFGTBL_Trans_Performant |
  8146. (trans_support & CFGTBL_Trans_use_short_tags) |
  8147. CFGTBL_Trans_enable_directed_msix |
  8148. (trans_support & (CFGTBL_Trans_io_accel1 |
  8149. CFGTBL_Trans_io_accel2));
  8150. struct access_method access = SA5_performant_access;
  8151. /* This is a bit complicated. There are 8 registers on
  8152. * the controller which we write to to tell it 8 different
  8153. * sizes of commands which there may be. It's a way of
  8154. * reducing the DMA done to fetch each command. Encoded into
  8155. * each command's tag are 3 bits which communicate to the controller
  8156. * which of the eight sizes that command fits within. The size of
  8157. * each command depends on how many scatter gather entries there are.
  8158. * Each SG entry requires 16 bytes. The eight registers are programmed
  8159. * with the number of 16-byte blocks a command of that size requires.
  8160. * The smallest command possible requires 5 such 16 byte blocks.
  8161. * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
  8162. * blocks. Note, this only extends to the SG entries contained
  8163. * within the command block, and does not extend to chained blocks
  8164. * of SG elements. bft[] contains the eight values we write to
  8165. * the registers. They are not evenly distributed, but have more
  8166. * sizes for small commands, and fewer sizes for larger commands.
  8167. */
  8168. int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
  8169. #define MIN_IOACCEL2_BFT_ENTRY 5
  8170. #define HPSA_IOACCEL2_HEADER_SZ 4
  8171. int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
  8172. 13, 14, 15, 16, 17, 18, 19,
  8173. HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
  8174. BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
  8175. BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
  8176. BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
  8177. 16 * MIN_IOACCEL2_BFT_ENTRY);
  8178. BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
  8179. BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
  8180. /* 5 = 1 s/g entry or 4k
  8181. * 6 = 2 s/g entry or 8k
  8182. * 8 = 4 s/g entry or 16k
  8183. * 10 = 6 s/g entry or 24k
  8184. */
  8185. /* If the controller supports either ioaccel method then
  8186. * we can also use the RAID stack submit path that does not
  8187. * perform the superfluous readl() after each command submission.
  8188. */
  8189. if (trans_support & (CFGTBL_Trans_io_accel1 | CFGTBL_Trans_io_accel2))
  8190. access = SA5_performant_access_no_read;
  8191. /* Controller spec: zero out this buffer. */
  8192. for (i = 0; i < h->nreply_queues; i++)
  8193. memset(h->reply_queue[i].head, 0, h->reply_queue_size);
  8194. bft[7] = SG_ENTRIES_IN_CMD + 4;
  8195. calc_bucket_map(bft, ARRAY_SIZE(bft),
  8196. SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
  8197. for (i = 0; i < 8; i++)
  8198. writel(bft[i], &h->transtable->BlockFetch[i]);
  8199. /* size of controller ring buffer */
  8200. writel(h->max_commands, &h->transtable->RepQSize);
  8201. writel(h->nreply_queues, &h->transtable->RepQCount);
  8202. writel(0, &h->transtable->RepQCtrAddrLow32);
  8203. writel(0, &h->transtable->RepQCtrAddrHigh32);
  8204. for (i = 0; i < h->nreply_queues; i++) {
  8205. writel(0, &h->transtable->RepQAddr[i].upper);
  8206. writel(h->reply_queue[i].busaddr,
  8207. &h->transtable->RepQAddr[i].lower);
  8208. }
  8209. writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
  8210. writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
  8211. /*
  8212. * enable outbound interrupt coalescing in accelerator mode;
  8213. */
  8214. if (trans_support & CFGTBL_Trans_io_accel1) {
  8215. access = SA5_ioaccel_mode1_access;
  8216. writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
  8217. writel(4, &h->cfgtable->HostWrite.CoalIntCount);
  8218. } else
  8219. if (trans_support & CFGTBL_Trans_io_accel2)
  8220. access = SA5_ioaccel_mode2_access;
  8221. writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
  8222. if (hpsa_wait_for_mode_change_ack(h)) {
  8223. dev_err(&h->pdev->dev,
  8224. "performant mode problem - doorbell timeout\n");
  8225. return -ENODEV;
  8226. }
  8227. register_value = readl(&(h->cfgtable->TransportActive));
  8228. if (!(register_value & CFGTBL_Trans_Performant)) {
  8229. dev_err(&h->pdev->dev,
  8230. "performant mode problem - transport not active\n");
  8231. return -ENODEV;
  8232. }
  8233. /* Change the access methods to the performant access methods */
  8234. h->access = access;
  8235. h->transMethod = transMethod;
  8236. if (!((trans_support & CFGTBL_Trans_io_accel1) ||
  8237. (trans_support & CFGTBL_Trans_io_accel2)))
  8238. return 0;
  8239. if (trans_support & CFGTBL_Trans_io_accel1) {
  8240. /* Set up I/O accelerator mode */
  8241. for (i = 0; i < h->nreply_queues; i++) {
  8242. writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
  8243. h->reply_queue[i].current_entry =
  8244. readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
  8245. }
  8246. bft[7] = h->ioaccel_maxsg + 8;
  8247. calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
  8248. h->ioaccel1_blockFetchTable);
  8249. /* initialize all reply queue entries to unused */
  8250. for (i = 0; i < h->nreply_queues; i++)
  8251. memset(h->reply_queue[i].head,
  8252. (u8) IOACCEL_MODE1_REPLY_UNUSED,
  8253. h->reply_queue_size);
  8254. /* set all the constant fields in the accelerator command
  8255. * frames once at init time to save CPU cycles later.
  8256. */
  8257. for (i = 0; i < h->nr_cmds; i++) {
  8258. struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
  8259. cp->function = IOACCEL1_FUNCTION_SCSIIO;
  8260. cp->err_info = (u32) (h->errinfo_pool_dhandle +
  8261. (i * sizeof(struct ErrorInfo)));
  8262. cp->err_info_len = sizeof(struct ErrorInfo);
  8263. cp->sgl_offset = IOACCEL1_SGLOFFSET;
  8264. cp->host_context_flags =
  8265. cpu_to_le16(IOACCEL1_HCFLAGS_CISS_FORMAT);
  8266. cp->timeout_sec = 0;
  8267. cp->ReplyQueue = 0;
  8268. cp->tag =
  8269. cpu_to_le64((i << DIRECT_LOOKUP_SHIFT));
  8270. cp->host_addr =
  8271. cpu_to_le64(h->ioaccel_cmd_pool_dhandle +
  8272. (i * sizeof(struct io_accel1_cmd)));
  8273. }
  8274. } else if (trans_support & CFGTBL_Trans_io_accel2) {
  8275. u64 cfg_offset, cfg_base_addr_index;
  8276. u32 bft2_offset, cfg_base_addr;
  8277. hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
  8278. &cfg_base_addr_index, &cfg_offset);
  8279. BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
  8280. bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
  8281. calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
  8282. 4, h->ioaccel2_blockFetchTable);
  8283. bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
  8284. BUILD_BUG_ON(offsetof(struct CfgTable,
  8285. io_accel_request_size_offset) != 0xb8);
  8286. h->ioaccel2_bft2_regs =
  8287. remap_pci_mem(pci_resource_start(h->pdev,
  8288. cfg_base_addr_index) +
  8289. cfg_offset + bft2_offset,
  8290. ARRAY_SIZE(bft2) *
  8291. sizeof(*h->ioaccel2_bft2_regs));
  8292. for (i = 0; i < ARRAY_SIZE(bft2); i++)
  8293. writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
  8294. }
  8295. writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
  8296. if (hpsa_wait_for_mode_change_ack(h)) {
  8297. dev_err(&h->pdev->dev,
  8298. "performant mode problem - enabling ioaccel mode\n");
  8299. return -ENODEV;
  8300. }
  8301. return 0;
  8302. }
  8303. /* Free ioaccel1 mode command blocks and block fetch table */
  8304. static void hpsa_free_ioaccel1_cmd_and_bft(struct ctlr_info *h)
  8305. {
  8306. if (h->ioaccel_cmd_pool) {
  8307. dma_free_coherent(&h->pdev->dev,
  8308. h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
  8309. h->ioaccel_cmd_pool,
  8310. h->ioaccel_cmd_pool_dhandle);
  8311. h->ioaccel_cmd_pool = NULL;
  8312. h->ioaccel_cmd_pool_dhandle = 0;
  8313. }
  8314. kfree(h->ioaccel1_blockFetchTable);
  8315. h->ioaccel1_blockFetchTable = NULL;
  8316. }
  8317. /* Allocate ioaccel1 mode command blocks and block fetch table */
  8318. static int hpsa_alloc_ioaccel1_cmd_and_bft(struct ctlr_info *h)
  8319. {
  8320. h->ioaccel_maxsg =
  8321. readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
  8322. if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
  8323. h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
  8324. /* Command structures must be aligned on a 128-byte boundary
  8325. * because the 7 lower bits of the address are used by the
  8326. * hardware.
  8327. */
  8328. BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
  8329. IOACCEL1_COMMANDLIST_ALIGNMENT);
  8330. h->ioaccel_cmd_pool =
  8331. dma_alloc_coherent(&h->pdev->dev,
  8332. h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
  8333. &h->ioaccel_cmd_pool_dhandle, GFP_KERNEL);
  8334. h->ioaccel1_blockFetchTable =
  8335. kmalloc(((h->ioaccel_maxsg + 1) *
  8336. sizeof(u32)), GFP_KERNEL);
  8337. if ((h->ioaccel_cmd_pool == NULL) ||
  8338. (h->ioaccel1_blockFetchTable == NULL))
  8339. goto clean_up;
  8340. memset(h->ioaccel_cmd_pool, 0,
  8341. h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
  8342. return 0;
  8343. clean_up:
  8344. hpsa_free_ioaccel1_cmd_and_bft(h);
  8345. return -ENOMEM;
  8346. }
  8347. /* Free ioaccel2 mode command blocks and block fetch table */
  8348. static void hpsa_free_ioaccel2_cmd_and_bft(struct ctlr_info *h)
  8349. {
  8350. hpsa_free_ioaccel2_sg_chain_blocks(h);
  8351. if (h->ioaccel2_cmd_pool) {
  8352. dma_free_coherent(&h->pdev->dev,
  8353. h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
  8354. h->ioaccel2_cmd_pool,
  8355. h->ioaccel2_cmd_pool_dhandle);
  8356. h->ioaccel2_cmd_pool = NULL;
  8357. h->ioaccel2_cmd_pool_dhandle = 0;
  8358. }
  8359. kfree(h->ioaccel2_blockFetchTable);
  8360. h->ioaccel2_blockFetchTable = NULL;
  8361. }
  8362. /* Allocate ioaccel2 mode command blocks and block fetch table */
  8363. static int hpsa_alloc_ioaccel2_cmd_and_bft(struct ctlr_info *h)
  8364. {
  8365. int rc;
  8366. /* Allocate ioaccel2 mode command blocks and block fetch table */
  8367. h->ioaccel_maxsg =
  8368. readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
  8369. if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
  8370. h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
  8371. BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
  8372. IOACCEL2_COMMANDLIST_ALIGNMENT);
  8373. h->ioaccel2_cmd_pool =
  8374. dma_alloc_coherent(&h->pdev->dev,
  8375. h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
  8376. &h->ioaccel2_cmd_pool_dhandle, GFP_KERNEL);
  8377. h->ioaccel2_blockFetchTable =
  8378. kmalloc(((h->ioaccel_maxsg + 1) *
  8379. sizeof(u32)), GFP_KERNEL);
  8380. if ((h->ioaccel2_cmd_pool == NULL) ||
  8381. (h->ioaccel2_blockFetchTable == NULL)) {
  8382. rc = -ENOMEM;
  8383. goto clean_up;
  8384. }
  8385. rc = hpsa_allocate_ioaccel2_sg_chain_blocks(h);
  8386. if (rc)
  8387. goto clean_up;
  8388. memset(h->ioaccel2_cmd_pool, 0,
  8389. h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
  8390. return 0;
  8391. clean_up:
  8392. hpsa_free_ioaccel2_cmd_and_bft(h);
  8393. return rc;
  8394. }
  8395. /* Free items allocated by hpsa_put_ctlr_into_performant_mode */
  8396. static void hpsa_free_performant_mode(struct ctlr_info *h)
  8397. {
  8398. kfree(h->blockFetchTable);
  8399. h->blockFetchTable = NULL;
  8400. hpsa_free_reply_queues(h);
  8401. hpsa_free_ioaccel1_cmd_and_bft(h);
  8402. hpsa_free_ioaccel2_cmd_and_bft(h);
  8403. }
  8404. /* return -ENODEV on error, 0 on success (or no action)
  8405. * allocates numerous items that must be freed later
  8406. */
  8407. static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
  8408. {
  8409. u32 trans_support;
  8410. unsigned long transMethod = CFGTBL_Trans_Performant |
  8411. CFGTBL_Trans_use_short_tags;
  8412. int i, rc;
  8413. if (hpsa_simple_mode)
  8414. return 0;
  8415. trans_support = readl(&(h->cfgtable->TransportSupport));
  8416. if (!(trans_support & PERFORMANT_MODE))
  8417. return 0;
  8418. /* Check for I/O accelerator mode support */
  8419. if (trans_support & CFGTBL_Trans_io_accel1) {
  8420. transMethod |= CFGTBL_Trans_io_accel1 |
  8421. CFGTBL_Trans_enable_directed_msix;
  8422. rc = hpsa_alloc_ioaccel1_cmd_and_bft(h);
  8423. if (rc)
  8424. return rc;
  8425. } else if (trans_support & CFGTBL_Trans_io_accel2) {
  8426. transMethod |= CFGTBL_Trans_io_accel2 |
  8427. CFGTBL_Trans_enable_directed_msix;
  8428. rc = hpsa_alloc_ioaccel2_cmd_and_bft(h);
  8429. if (rc)
  8430. return rc;
  8431. }
  8432. h->nreply_queues = h->msix_vectors > 0 ? h->msix_vectors : 1;
  8433. hpsa_get_max_perf_mode_cmds(h);
  8434. /* Performant mode ring buffer and supporting data structures */
  8435. h->reply_queue_size = h->max_commands * sizeof(u64);
  8436. for (i = 0; i < h->nreply_queues; i++) {
  8437. h->reply_queue[i].head = dma_alloc_coherent(&h->pdev->dev,
  8438. h->reply_queue_size,
  8439. &h->reply_queue[i].busaddr,
  8440. GFP_KERNEL);
  8441. if (!h->reply_queue[i].head) {
  8442. rc = -ENOMEM;
  8443. goto clean1; /* rq, ioaccel */
  8444. }
  8445. h->reply_queue[i].size = h->max_commands;
  8446. h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
  8447. h->reply_queue[i].current_entry = 0;
  8448. }
  8449. /* Need a block fetch table for performant mode */
  8450. h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
  8451. sizeof(u32)), GFP_KERNEL);
  8452. if (!h->blockFetchTable) {
  8453. rc = -ENOMEM;
  8454. goto clean1; /* rq, ioaccel */
  8455. }
  8456. rc = hpsa_enter_performant_mode(h, trans_support);
  8457. if (rc)
  8458. goto clean2; /* bft, rq, ioaccel */
  8459. return 0;
  8460. clean2: /* bft, rq, ioaccel */
  8461. kfree(h->blockFetchTable);
  8462. h->blockFetchTable = NULL;
  8463. clean1: /* rq, ioaccel */
  8464. hpsa_free_reply_queues(h);
  8465. hpsa_free_ioaccel1_cmd_and_bft(h);
  8466. hpsa_free_ioaccel2_cmd_and_bft(h);
  8467. return rc;
  8468. }
  8469. static int is_accelerated_cmd(struct CommandList *c)
  8470. {
  8471. return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2;
  8472. }
  8473. static void hpsa_drain_accel_commands(struct ctlr_info *h)
  8474. {
  8475. struct CommandList *c = NULL;
  8476. int i, accel_cmds_out;
  8477. int refcount;
  8478. do { /* wait for all outstanding ioaccel commands to drain out */
  8479. accel_cmds_out = 0;
  8480. for (i = 0; i < h->nr_cmds; i++) {
  8481. c = h->cmd_pool + i;
  8482. refcount = atomic_inc_return(&c->refcount);
  8483. if (refcount > 1) /* Command is allocated */
  8484. accel_cmds_out += is_accelerated_cmd(c);
  8485. cmd_free(h, c);
  8486. }
  8487. if (accel_cmds_out <= 0)
  8488. break;
  8489. msleep(100);
  8490. } while (1);
  8491. }
  8492. static struct hpsa_sas_phy *hpsa_alloc_sas_phy(
  8493. struct hpsa_sas_port *hpsa_sas_port)
  8494. {
  8495. struct hpsa_sas_phy *hpsa_sas_phy;
  8496. struct sas_phy *phy;
  8497. hpsa_sas_phy = kzalloc(sizeof(*hpsa_sas_phy), GFP_KERNEL);
  8498. if (!hpsa_sas_phy)
  8499. return NULL;
  8500. phy = sas_phy_alloc(hpsa_sas_port->parent_node->parent_dev,
  8501. hpsa_sas_port->next_phy_index);
  8502. if (!phy) {
  8503. kfree(hpsa_sas_phy);
  8504. return NULL;
  8505. }
  8506. hpsa_sas_port->next_phy_index++;
  8507. hpsa_sas_phy->phy = phy;
  8508. hpsa_sas_phy->parent_port = hpsa_sas_port;
  8509. return hpsa_sas_phy;
  8510. }
  8511. static void hpsa_free_sas_phy(struct hpsa_sas_phy *hpsa_sas_phy)
  8512. {
  8513. struct sas_phy *phy = hpsa_sas_phy->phy;
  8514. sas_port_delete_phy(hpsa_sas_phy->parent_port->port, phy);
  8515. if (hpsa_sas_phy->added_to_port)
  8516. list_del(&hpsa_sas_phy->phy_list_entry);
  8517. sas_phy_delete(phy);
  8518. kfree(hpsa_sas_phy);
  8519. }
  8520. static int hpsa_sas_port_add_phy(struct hpsa_sas_phy *hpsa_sas_phy)
  8521. {
  8522. int rc;
  8523. struct hpsa_sas_port *hpsa_sas_port;
  8524. struct sas_phy *phy;
  8525. struct sas_identify *identify;
  8526. hpsa_sas_port = hpsa_sas_phy->parent_port;
  8527. phy = hpsa_sas_phy->phy;
  8528. identify = &phy->identify;
  8529. memset(identify, 0, sizeof(*identify));
  8530. identify->sas_address = hpsa_sas_port->sas_address;
  8531. identify->device_type = SAS_END_DEVICE;
  8532. identify->initiator_port_protocols = SAS_PROTOCOL_STP;
  8533. identify->target_port_protocols = SAS_PROTOCOL_STP;
  8534. phy->minimum_linkrate_hw = SAS_LINK_RATE_UNKNOWN;
  8535. phy->maximum_linkrate_hw = SAS_LINK_RATE_UNKNOWN;
  8536. phy->minimum_linkrate = SAS_LINK_RATE_UNKNOWN;
  8537. phy->maximum_linkrate = SAS_LINK_RATE_UNKNOWN;
  8538. phy->negotiated_linkrate = SAS_LINK_RATE_UNKNOWN;
  8539. rc = sas_phy_add(hpsa_sas_phy->phy);
  8540. if (rc)
  8541. return rc;
  8542. sas_port_add_phy(hpsa_sas_port->port, hpsa_sas_phy->phy);
  8543. list_add_tail(&hpsa_sas_phy->phy_list_entry,
  8544. &hpsa_sas_port->phy_list_head);
  8545. hpsa_sas_phy->added_to_port = true;
  8546. return 0;
  8547. }
  8548. static int
  8549. hpsa_sas_port_add_rphy(struct hpsa_sas_port *hpsa_sas_port,
  8550. struct sas_rphy *rphy)
  8551. {
  8552. struct sas_identify *identify;
  8553. identify = &rphy->identify;
  8554. identify->sas_address = hpsa_sas_port->sas_address;
  8555. identify->initiator_port_protocols = SAS_PROTOCOL_STP;
  8556. identify->target_port_protocols = SAS_PROTOCOL_STP;
  8557. return sas_rphy_add(rphy);
  8558. }
  8559. static struct hpsa_sas_port
  8560. *hpsa_alloc_sas_port(struct hpsa_sas_node *hpsa_sas_node,
  8561. u64 sas_address)
  8562. {
  8563. int rc;
  8564. struct hpsa_sas_port *hpsa_sas_port;
  8565. struct sas_port *port;
  8566. hpsa_sas_port = kzalloc(sizeof(*hpsa_sas_port), GFP_KERNEL);
  8567. if (!hpsa_sas_port)
  8568. return NULL;
  8569. INIT_LIST_HEAD(&hpsa_sas_port->phy_list_head);
  8570. hpsa_sas_port->parent_node = hpsa_sas_node;
  8571. port = sas_port_alloc_num(hpsa_sas_node->parent_dev);
  8572. if (!port)
  8573. goto free_hpsa_port;
  8574. rc = sas_port_add(port);
  8575. if (rc)
  8576. goto free_sas_port;
  8577. hpsa_sas_port->port = port;
  8578. hpsa_sas_port->sas_address = sas_address;
  8579. list_add_tail(&hpsa_sas_port->port_list_entry,
  8580. &hpsa_sas_node->port_list_head);
  8581. return hpsa_sas_port;
  8582. free_sas_port:
  8583. sas_port_free(port);
  8584. free_hpsa_port:
  8585. kfree(hpsa_sas_port);
  8586. return NULL;
  8587. }
  8588. static void hpsa_free_sas_port(struct hpsa_sas_port *hpsa_sas_port)
  8589. {
  8590. struct hpsa_sas_phy *hpsa_sas_phy;
  8591. struct hpsa_sas_phy *next;
  8592. list_for_each_entry_safe(hpsa_sas_phy, next,
  8593. &hpsa_sas_port->phy_list_head, phy_list_entry)
  8594. hpsa_free_sas_phy(hpsa_sas_phy);
  8595. sas_port_delete(hpsa_sas_port->port);
  8596. list_del(&hpsa_sas_port->port_list_entry);
  8597. kfree(hpsa_sas_port);
  8598. }
  8599. static struct hpsa_sas_node *hpsa_alloc_sas_node(struct device *parent_dev)
  8600. {
  8601. struct hpsa_sas_node *hpsa_sas_node;
  8602. hpsa_sas_node = kzalloc(sizeof(*hpsa_sas_node), GFP_KERNEL);
  8603. if (hpsa_sas_node) {
  8604. hpsa_sas_node->parent_dev = parent_dev;
  8605. INIT_LIST_HEAD(&hpsa_sas_node->port_list_head);
  8606. }
  8607. return hpsa_sas_node;
  8608. }
  8609. static void hpsa_free_sas_node(struct hpsa_sas_node *hpsa_sas_node)
  8610. {
  8611. struct hpsa_sas_port *hpsa_sas_port;
  8612. struct hpsa_sas_port *next;
  8613. if (!hpsa_sas_node)
  8614. return;
  8615. list_for_each_entry_safe(hpsa_sas_port, next,
  8616. &hpsa_sas_node->port_list_head, port_list_entry)
  8617. hpsa_free_sas_port(hpsa_sas_port);
  8618. kfree(hpsa_sas_node);
  8619. }
  8620. static struct hpsa_scsi_dev_t
  8621. *hpsa_find_device_by_sas_rphy(struct ctlr_info *h,
  8622. struct sas_rphy *rphy)
  8623. {
  8624. int i;
  8625. struct hpsa_scsi_dev_t *device;
  8626. for (i = 0; i < h->ndevices; i++) {
  8627. device = h->dev[i];
  8628. if (!device->sas_port)
  8629. continue;
  8630. if (device->sas_port->rphy == rphy)
  8631. return device;
  8632. }
  8633. return NULL;
  8634. }
  8635. static int hpsa_add_sas_host(struct ctlr_info *h)
  8636. {
  8637. int rc;
  8638. struct device *parent_dev;
  8639. struct hpsa_sas_node *hpsa_sas_node;
  8640. struct hpsa_sas_port *hpsa_sas_port;
  8641. struct hpsa_sas_phy *hpsa_sas_phy;
  8642. parent_dev = &h->scsi_host->shost_dev;
  8643. hpsa_sas_node = hpsa_alloc_sas_node(parent_dev);
  8644. if (!hpsa_sas_node)
  8645. return -ENOMEM;
  8646. hpsa_sas_port = hpsa_alloc_sas_port(hpsa_sas_node, h->sas_address);
  8647. if (!hpsa_sas_port) {
  8648. rc = -ENODEV;
  8649. goto free_sas_node;
  8650. }
  8651. hpsa_sas_phy = hpsa_alloc_sas_phy(hpsa_sas_port);
  8652. if (!hpsa_sas_phy) {
  8653. rc = -ENODEV;
  8654. goto free_sas_port;
  8655. }
  8656. rc = hpsa_sas_port_add_phy(hpsa_sas_phy);
  8657. if (rc)
  8658. goto free_sas_phy;
  8659. h->sas_host = hpsa_sas_node;
  8660. return 0;
  8661. free_sas_phy:
  8662. sas_phy_free(hpsa_sas_phy->phy);
  8663. kfree(hpsa_sas_phy);
  8664. free_sas_port:
  8665. hpsa_free_sas_port(hpsa_sas_port);
  8666. free_sas_node:
  8667. hpsa_free_sas_node(hpsa_sas_node);
  8668. return rc;
  8669. }
  8670. static void hpsa_delete_sas_host(struct ctlr_info *h)
  8671. {
  8672. hpsa_free_sas_node(h->sas_host);
  8673. }
  8674. static int hpsa_add_sas_device(struct hpsa_sas_node *hpsa_sas_node,
  8675. struct hpsa_scsi_dev_t *device)
  8676. {
  8677. int rc;
  8678. struct hpsa_sas_port *hpsa_sas_port;
  8679. struct sas_rphy *rphy;
  8680. hpsa_sas_port = hpsa_alloc_sas_port(hpsa_sas_node, device->sas_address);
  8681. if (!hpsa_sas_port)
  8682. return -ENOMEM;
  8683. rphy = sas_end_device_alloc(hpsa_sas_port->port);
  8684. if (!rphy) {
  8685. rc = -ENODEV;
  8686. goto free_sas_port;
  8687. }
  8688. hpsa_sas_port->rphy = rphy;
  8689. device->sas_port = hpsa_sas_port;
  8690. rc = hpsa_sas_port_add_rphy(hpsa_sas_port, rphy);
  8691. if (rc)
  8692. goto free_sas_rphy;
  8693. return 0;
  8694. free_sas_rphy:
  8695. sas_rphy_free(rphy);
  8696. free_sas_port:
  8697. hpsa_free_sas_port(hpsa_sas_port);
  8698. device->sas_port = NULL;
  8699. return rc;
  8700. }
  8701. static void hpsa_remove_sas_device(struct hpsa_scsi_dev_t *device)
  8702. {
  8703. if (device->sas_port) {
  8704. hpsa_free_sas_port(device->sas_port);
  8705. device->sas_port = NULL;
  8706. }
  8707. }
  8708. static int
  8709. hpsa_sas_get_linkerrors(struct sas_phy *phy)
  8710. {
  8711. return 0;
  8712. }
  8713. static int
  8714. hpsa_sas_get_enclosure_identifier(struct sas_rphy *rphy, u64 *identifier)
  8715. {
  8716. struct Scsi_Host *shost = phy_to_shost(rphy);
  8717. struct ctlr_info *h;
  8718. struct hpsa_scsi_dev_t *sd;
  8719. if (!shost)
  8720. return -ENXIO;
  8721. h = shost_to_hba(shost);
  8722. if (!h)
  8723. return -ENXIO;
  8724. sd = hpsa_find_device_by_sas_rphy(h, rphy);
  8725. if (!sd)
  8726. return -ENXIO;
  8727. *identifier = sd->eli;
  8728. return 0;
  8729. }
  8730. static int
  8731. hpsa_sas_get_bay_identifier(struct sas_rphy *rphy)
  8732. {
  8733. return -ENXIO;
  8734. }
  8735. static int
  8736. hpsa_sas_phy_reset(struct sas_phy *phy, int hard_reset)
  8737. {
  8738. return 0;
  8739. }
  8740. static int
  8741. hpsa_sas_phy_enable(struct sas_phy *phy, int enable)
  8742. {
  8743. return 0;
  8744. }
  8745. static int
  8746. hpsa_sas_phy_setup(struct sas_phy *phy)
  8747. {
  8748. return 0;
  8749. }
  8750. static void
  8751. hpsa_sas_phy_release(struct sas_phy *phy)
  8752. {
  8753. }
  8754. static int
  8755. hpsa_sas_phy_speed(struct sas_phy *phy, struct sas_phy_linkrates *rates)
  8756. {
  8757. return -EINVAL;
  8758. }
  8759. static struct sas_function_template hpsa_sas_transport_functions = {
  8760. .get_linkerrors = hpsa_sas_get_linkerrors,
  8761. .get_enclosure_identifier = hpsa_sas_get_enclosure_identifier,
  8762. .get_bay_identifier = hpsa_sas_get_bay_identifier,
  8763. .phy_reset = hpsa_sas_phy_reset,
  8764. .phy_enable = hpsa_sas_phy_enable,
  8765. .phy_setup = hpsa_sas_phy_setup,
  8766. .phy_release = hpsa_sas_phy_release,
  8767. .set_phy_speed = hpsa_sas_phy_speed,
  8768. };
  8769. /*
  8770. * This is it. Register the PCI driver information for the cards we control
  8771. * the OS will call our registered routines when it finds one of our cards.
  8772. */
  8773. static int __init hpsa_init(void)
  8774. {
  8775. int rc;
  8776. hpsa_sas_transport_template =
  8777. sas_attach_transport(&hpsa_sas_transport_functions);
  8778. if (!hpsa_sas_transport_template)
  8779. return -ENODEV;
  8780. rc = pci_register_driver(&hpsa_pci_driver);
  8781. if (rc)
  8782. sas_release_transport(hpsa_sas_transport_template);
  8783. return rc;
  8784. }
  8785. static void __exit hpsa_cleanup(void)
  8786. {
  8787. pci_unregister_driver(&hpsa_pci_driver);
  8788. sas_release_transport(hpsa_sas_transport_template);
  8789. }
  8790. static void __attribute__((unused)) verify_offsets(void)
  8791. {
  8792. #define VERIFY_OFFSET(member, offset) \
  8793. BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset)
  8794. VERIFY_OFFSET(structure_size, 0);
  8795. VERIFY_OFFSET(volume_blk_size, 4);
  8796. VERIFY_OFFSET(volume_blk_cnt, 8);
  8797. VERIFY_OFFSET(phys_blk_shift, 16);
  8798. VERIFY_OFFSET(parity_rotation_shift, 17);
  8799. VERIFY_OFFSET(strip_size, 18);
  8800. VERIFY_OFFSET(disk_starting_blk, 20);
  8801. VERIFY_OFFSET(disk_blk_cnt, 28);
  8802. VERIFY_OFFSET(data_disks_per_row, 36);
  8803. VERIFY_OFFSET(metadata_disks_per_row, 38);
  8804. VERIFY_OFFSET(row_cnt, 40);
  8805. VERIFY_OFFSET(layout_map_count, 42);
  8806. VERIFY_OFFSET(flags, 44);
  8807. VERIFY_OFFSET(dekindex, 46);
  8808. /* VERIFY_OFFSET(reserved, 48 */
  8809. VERIFY_OFFSET(data, 64);
  8810. #undef VERIFY_OFFSET
  8811. #define VERIFY_OFFSET(member, offset) \
  8812. BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
  8813. VERIFY_OFFSET(IU_type, 0);
  8814. VERIFY_OFFSET(direction, 1);
  8815. VERIFY_OFFSET(reply_queue, 2);
  8816. /* VERIFY_OFFSET(reserved1, 3); */
  8817. VERIFY_OFFSET(scsi_nexus, 4);
  8818. VERIFY_OFFSET(Tag, 8);
  8819. VERIFY_OFFSET(cdb, 16);
  8820. VERIFY_OFFSET(cciss_lun, 32);
  8821. VERIFY_OFFSET(data_len, 40);
  8822. VERIFY_OFFSET(cmd_priority_task_attr, 44);
  8823. VERIFY_OFFSET(sg_count, 45);
  8824. /* VERIFY_OFFSET(reserved3 */
  8825. VERIFY_OFFSET(err_ptr, 48);
  8826. VERIFY_OFFSET(err_len, 56);
  8827. /* VERIFY_OFFSET(reserved4 */
  8828. VERIFY_OFFSET(sg, 64);
  8829. #undef VERIFY_OFFSET
  8830. #define VERIFY_OFFSET(member, offset) \
  8831. BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
  8832. VERIFY_OFFSET(dev_handle, 0x00);
  8833. VERIFY_OFFSET(reserved1, 0x02);
  8834. VERIFY_OFFSET(function, 0x03);
  8835. VERIFY_OFFSET(reserved2, 0x04);
  8836. VERIFY_OFFSET(err_info, 0x0C);
  8837. VERIFY_OFFSET(reserved3, 0x10);
  8838. VERIFY_OFFSET(err_info_len, 0x12);
  8839. VERIFY_OFFSET(reserved4, 0x13);
  8840. VERIFY_OFFSET(sgl_offset, 0x14);
  8841. VERIFY_OFFSET(reserved5, 0x15);
  8842. VERIFY_OFFSET(transfer_len, 0x1C);
  8843. VERIFY_OFFSET(reserved6, 0x20);
  8844. VERIFY_OFFSET(io_flags, 0x24);
  8845. VERIFY_OFFSET(reserved7, 0x26);
  8846. VERIFY_OFFSET(LUN, 0x34);
  8847. VERIFY_OFFSET(control, 0x3C);
  8848. VERIFY_OFFSET(CDB, 0x40);
  8849. VERIFY_OFFSET(reserved8, 0x50);
  8850. VERIFY_OFFSET(host_context_flags, 0x60);
  8851. VERIFY_OFFSET(timeout_sec, 0x62);
  8852. VERIFY_OFFSET(ReplyQueue, 0x64);
  8853. VERIFY_OFFSET(reserved9, 0x65);
  8854. VERIFY_OFFSET(tag, 0x68);
  8855. VERIFY_OFFSET(host_addr, 0x70);
  8856. VERIFY_OFFSET(CISS_LUN, 0x78);
  8857. VERIFY_OFFSET(SG, 0x78 + 8);
  8858. #undef VERIFY_OFFSET
  8859. }
  8860. module_init(hpsa_init);
  8861. module_exit(hpsa_cleanup);