be.h 5.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright 2017 Broadcom. All Rights Reserved.
  4. * The term "Broadcom" refers to Broadcom Limited and/or its subsidiaries.
  5. *
  6. * Contact Information:
  7. * [email protected]
  8. */
  9. #ifndef BEISCSI_H
  10. #define BEISCSI_H
  11. #include <linux/pci.h>
  12. #include <linux/if_vlan.h>
  13. #include <linux/irq_poll.h>
  14. #define FW_VER_LEN 32
  15. #define MCC_Q_LEN 128
  16. #define MCC_CQ_LEN 256
  17. #define MAX_MCC_CMD 16
  18. /* BladeEngine Generation numbers */
  19. #define BE_GEN2 2
  20. #define BE_GEN3 3
  21. #define BE_GEN4 4
  22. struct be_dma_mem {
  23. void *va;
  24. dma_addr_t dma;
  25. u32 size;
  26. };
  27. struct be_queue_info {
  28. struct be_dma_mem dma_mem;
  29. u16 len;
  30. u16 entry_size; /* Size of an element in the queue */
  31. u16 id;
  32. u16 tail, head;
  33. bool created;
  34. u16 used; /* Number of valid elements in the queue */
  35. };
  36. static inline u32 MODULO(u16 val, u16 limit)
  37. {
  38. WARN_ON(limit & (limit - 1));
  39. return val & (limit - 1);
  40. }
  41. static inline void index_inc(u16 *index, u16 limit)
  42. {
  43. *index = MODULO((*index + 1), limit);
  44. }
  45. static inline void *queue_head_node(struct be_queue_info *q)
  46. {
  47. return q->dma_mem.va + q->head * q->entry_size;
  48. }
  49. static inline void *queue_get_wrb(struct be_queue_info *q, unsigned int wrb_num)
  50. {
  51. return q->dma_mem.va + wrb_num * q->entry_size;
  52. }
  53. static inline void *queue_tail_node(struct be_queue_info *q)
  54. {
  55. return q->dma_mem.va + q->tail * q->entry_size;
  56. }
  57. static inline void queue_head_inc(struct be_queue_info *q)
  58. {
  59. index_inc(&q->head, q->len);
  60. }
  61. static inline void queue_tail_inc(struct be_queue_info *q)
  62. {
  63. index_inc(&q->tail, q->len);
  64. }
  65. /*ISCSI */
  66. struct be_aic_obj { /* Adaptive interrupt coalescing (AIC) info */
  67. unsigned long jiffies;
  68. u32 eq_prev; /* Used to calculate eqe */
  69. u32 prev_eqd;
  70. #define BEISCSI_EQ_DELAY_MIN 0
  71. #define BEISCSI_EQ_DELAY_DEF 32
  72. #define BEISCSI_EQ_DELAY_MAX 128
  73. };
  74. struct be_eq_obj {
  75. u32 cq_count;
  76. struct be_queue_info q;
  77. struct beiscsi_hba *phba;
  78. struct be_queue_info *cq;
  79. struct work_struct mcc_work; /* Work Item */
  80. struct irq_poll iopoll;
  81. };
  82. struct be_mcc_obj {
  83. struct be_queue_info q;
  84. struct be_queue_info cq;
  85. };
  86. struct beiscsi_mcc_tag_state {
  87. unsigned long tag_state;
  88. #define MCC_TAG_STATE_RUNNING 0
  89. #define MCC_TAG_STATE_TIMEOUT 1
  90. #define MCC_TAG_STATE_ASYNC 2
  91. #define MCC_TAG_STATE_IGNORE 3
  92. void (*cbfn)(struct beiscsi_hba *, unsigned int);
  93. struct be_dma_mem tag_mem_state;
  94. };
  95. struct be_ctrl_info {
  96. u8 __iomem *csr;
  97. u8 __iomem *db; /* Door Bell */
  98. u8 __iomem *pcicfg; /* PCI config space */
  99. struct pci_dev *pdev;
  100. /* Mbox used for cmd request/response */
  101. struct mutex mbox_lock; /* For serializing mbox cmds to BE card */
  102. struct be_dma_mem mbox_mem;
  103. /* Mbox mem is adjusted to align to 16 bytes. The allocated addr
  104. * is stored for freeing purpose */
  105. struct be_dma_mem mbox_mem_alloced;
  106. /* MCC Rings */
  107. struct be_mcc_obj mcc_obj;
  108. spinlock_t mcc_lock; /* For serializing mcc cmds to BE card */
  109. wait_queue_head_t mcc_wait[MAX_MCC_CMD + 1];
  110. unsigned int mcc_tag[MAX_MCC_CMD];
  111. unsigned int mcc_tag_status[MAX_MCC_CMD + 1];
  112. unsigned short mcc_alloc_index;
  113. unsigned short mcc_free_index;
  114. unsigned int mcc_tag_available;
  115. struct beiscsi_mcc_tag_state ptag_state[MAX_MCC_CMD + 1];
  116. };
  117. #include "be_cmds.h"
  118. /* WRB index mask for MCC_Q_LEN queue entries */
  119. #define MCC_Q_WRB_IDX_MASK CQE_STATUS_WRB_MASK
  120. #define MCC_Q_WRB_IDX_SHIFT CQE_STATUS_WRB_SHIFT
  121. /* TAG is from 1...MAX_MCC_CMD, MASK includes MAX_MCC_CMD */
  122. #define MCC_Q_CMD_TAG_MASK ((MAX_MCC_CMD << 1) - 1)
  123. #define PAGE_SHIFT_4K 12
  124. #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K)
  125. /* Returns number of pages spanned by the data starting at the given addr */
  126. #define PAGES_4K_SPANNED(_address, size) \
  127. ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \
  128. (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
  129. /* Returns bit offset within a DWORD of a bitfield */
  130. #define AMAP_BIT_OFFSET(_struct, field) \
  131. (((size_t)&(((_struct *)0)->field))%32)
  132. /* Returns the bit mask of the field that is NOT shifted into location. */
  133. static inline u32 amap_mask(u32 bitsize)
  134. {
  135. return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1);
  136. }
  137. static inline void amap_set(void *ptr, u32 dw_offset, u32 mask,
  138. u32 offset, u32 value)
  139. {
  140. u32 *dw = (u32 *) ptr + dw_offset;
  141. *dw &= ~(mask << offset);
  142. *dw |= (mask & value) << offset;
  143. }
  144. #define AMAP_SET_BITS(_struct, field, ptr, val) \
  145. amap_set(ptr, \
  146. offsetof(_struct, field)/32, \
  147. amap_mask(sizeof(((_struct *)0)->field)), \
  148. AMAP_BIT_OFFSET(_struct, field), \
  149. val)
  150. static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset)
  151. {
  152. u32 *dw = ptr;
  153. return mask & (*(dw + dw_offset) >> offset);
  154. }
  155. #define AMAP_GET_BITS(_struct, field, ptr) \
  156. amap_get(ptr, \
  157. offsetof(_struct, field)/32, \
  158. amap_mask(sizeof(((_struct *)0)->field)), \
  159. AMAP_BIT_OFFSET(_struct, field))
  160. #define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len)
  161. #define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len)
  162. static inline void swap_dws(void *wrb, int len)
  163. {
  164. #ifdef __BIG_ENDIAN
  165. u32 *dw = wrb;
  166. WARN_ON(len % 4);
  167. do {
  168. *dw = cpu_to_le32(*dw);
  169. dw++;
  170. len -= 4;
  171. } while (len);
  172. #endif /* __BIG_ENDIAN */
  173. }
  174. #endif /* BEISCSI_H */