src.c 34 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Adaptec AAC series RAID controller driver
  4. * (c) Copyright 2001 Red Hat Inc.
  5. *
  6. * based on the old aacraid driver that is..
  7. * Adaptec aacraid device driver for Linux.
  8. *
  9. * Copyright (c) 2000-2010 Adaptec, Inc.
  10. * 2010-2015 PMC-Sierra, Inc. ([email protected])
  11. * 2016-2017 Microsemi Corp. ([email protected])
  12. *
  13. * Module Name:
  14. * src.c
  15. *
  16. * Abstract: Hardware Device Interface for PMC SRC based controllers
  17. */
  18. #include <linux/kernel.h>
  19. #include <linux/init.h>
  20. #include <linux/types.h>
  21. #include <linux/pci.h>
  22. #include <linux/spinlock.h>
  23. #include <linux/slab.h>
  24. #include <linux/blkdev.h>
  25. #include <linux/delay.h>
  26. #include <linux/completion.h>
  27. #include <linux/time.h>
  28. #include <linux/interrupt.h>
  29. #include <scsi/scsi_host.h>
  30. #include "aacraid.h"
  31. static int aac_src_get_sync_status(struct aac_dev *dev);
  32. static irqreturn_t aac_src_intr_message(int irq, void *dev_id)
  33. {
  34. struct aac_msix_ctx *ctx;
  35. struct aac_dev *dev;
  36. unsigned long bellbits, bellbits_shifted;
  37. int vector_no;
  38. int isFastResponse, mode;
  39. u32 index, handle;
  40. ctx = (struct aac_msix_ctx *)dev_id;
  41. dev = ctx->dev;
  42. vector_no = ctx->vector_no;
  43. if (dev->msi_enabled) {
  44. mode = AAC_INT_MODE_MSI;
  45. if (vector_no == 0) {
  46. bellbits = src_readl(dev, MUnit.ODR_MSI);
  47. if (bellbits & 0x40000)
  48. mode |= AAC_INT_MODE_AIF;
  49. if (bellbits & 0x1000)
  50. mode |= AAC_INT_MODE_SYNC;
  51. }
  52. } else {
  53. mode = AAC_INT_MODE_INTX;
  54. bellbits = src_readl(dev, MUnit.ODR_R);
  55. if (bellbits & PmDoorBellResponseSent) {
  56. bellbits = PmDoorBellResponseSent;
  57. src_writel(dev, MUnit.ODR_C, bellbits);
  58. src_readl(dev, MUnit.ODR_C);
  59. } else {
  60. bellbits_shifted = (bellbits >> SRC_ODR_SHIFT);
  61. src_writel(dev, MUnit.ODR_C, bellbits);
  62. src_readl(dev, MUnit.ODR_C);
  63. if (bellbits_shifted & DoorBellAifPending)
  64. mode |= AAC_INT_MODE_AIF;
  65. else if (bellbits_shifted & OUTBOUNDDOORBELL_0)
  66. mode |= AAC_INT_MODE_SYNC;
  67. }
  68. }
  69. if (mode & AAC_INT_MODE_SYNC) {
  70. unsigned long sflags;
  71. struct list_head *entry;
  72. int send_it = 0;
  73. extern int aac_sync_mode;
  74. if (!aac_sync_mode && !dev->msi_enabled) {
  75. src_writel(dev, MUnit.ODR_C, bellbits);
  76. src_readl(dev, MUnit.ODR_C);
  77. }
  78. if (dev->sync_fib) {
  79. if (dev->sync_fib->callback)
  80. dev->sync_fib->callback(dev->sync_fib->callback_data,
  81. dev->sync_fib);
  82. spin_lock_irqsave(&dev->sync_fib->event_lock, sflags);
  83. if (dev->sync_fib->flags & FIB_CONTEXT_FLAG_WAIT) {
  84. dev->management_fib_count--;
  85. complete(&dev->sync_fib->event_wait);
  86. }
  87. spin_unlock_irqrestore(&dev->sync_fib->event_lock,
  88. sflags);
  89. spin_lock_irqsave(&dev->sync_lock, sflags);
  90. if (!list_empty(&dev->sync_fib_list)) {
  91. entry = dev->sync_fib_list.next;
  92. dev->sync_fib = list_entry(entry,
  93. struct fib,
  94. fiblink);
  95. list_del(entry);
  96. send_it = 1;
  97. } else {
  98. dev->sync_fib = NULL;
  99. }
  100. spin_unlock_irqrestore(&dev->sync_lock, sflags);
  101. if (send_it) {
  102. aac_adapter_sync_cmd(dev, SEND_SYNCHRONOUS_FIB,
  103. (u32)dev->sync_fib->hw_fib_pa,
  104. 0, 0, 0, 0, 0,
  105. NULL, NULL, NULL, NULL, NULL);
  106. }
  107. }
  108. if (!dev->msi_enabled)
  109. mode = 0;
  110. }
  111. if (mode & AAC_INT_MODE_AIF) {
  112. /* handle AIF */
  113. if (dev->sa_firmware) {
  114. u32 events = src_readl(dev, MUnit.SCR0);
  115. aac_intr_normal(dev, events, 1, 0, NULL);
  116. writel(events, &dev->IndexRegs->Mailbox[0]);
  117. src_writel(dev, MUnit.IDR, 1 << 23);
  118. } else {
  119. if (dev->aif_thread && dev->fsa_dev)
  120. aac_intr_normal(dev, 0, 2, 0, NULL);
  121. }
  122. if (dev->msi_enabled)
  123. aac_src_access_devreg(dev, AAC_CLEAR_AIF_BIT);
  124. mode = 0;
  125. }
  126. if (mode) {
  127. index = dev->host_rrq_idx[vector_no];
  128. for (;;) {
  129. isFastResponse = 0;
  130. /* remove toggle bit (31) */
  131. handle = le32_to_cpu((dev->host_rrq[index])
  132. & 0x7fffffff);
  133. /* check fast response bits (30, 1) */
  134. if (handle & 0x40000000)
  135. isFastResponse = 1;
  136. handle &= 0x0000ffff;
  137. if (handle == 0)
  138. break;
  139. handle >>= 2;
  140. if (dev->msi_enabled && dev->max_msix > 1)
  141. atomic_dec(&dev->rrq_outstanding[vector_no]);
  142. aac_intr_normal(dev, handle, 0, isFastResponse, NULL);
  143. dev->host_rrq[index++] = 0;
  144. if (index == (vector_no + 1) * dev->vector_cap)
  145. index = vector_no * dev->vector_cap;
  146. dev->host_rrq_idx[vector_no] = index;
  147. }
  148. mode = 0;
  149. }
  150. return IRQ_HANDLED;
  151. }
  152. /**
  153. * aac_src_disable_interrupt - Disable interrupts
  154. * @dev: Adapter
  155. */
  156. static void aac_src_disable_interrupt(struct aac_dev *dev)
  157. {
  158. src_writel(dev, MUnit.OIMR, dev->OIMR = 0xffffffff);
  159. }
  160. /**
  161. * aac_src_enable_interrupt_message - Enable interrupts
  162. * @dev: Adapter
  163. */
  164. static void aac_src_enable_interrupt_message(struct aac_dev *dev)
  165. {
  166. aac_src_access_devreg(dev, AAC_ENABLE_INTERRUPT);
  167. }
  168. /**
  169. * src_sync_cmd - send a command and wait
  170. * @dev: Adapter
  171. * @command: Command to execute
  172. * @p1: first parameter
  173. * @p2: second parameter
  174. * @p3: third parameter
  175. * @p4: forth parameter
  176. * @p5: fifth parameter
  177. * @p6: sixth parameter
  178. * @status: adapter status
  179. * @r1: first return value
  180. * @r2: second return valu
  181. * @r3: third return value
  182. * @r4: forth return value
  183. *
  184. * This routine will send a synchronous command to the adapter and wait
  185. * for its completion.
  186. */
  187. static int src_sync_cmd(struct aac_dev *dev, u32 command,
  188. u32 p1, u32 p2, u32 p3, u32 p4, u32 p5, u32 p6,
  189. u32 *status, u32 * r1, u32 * r2, u32 * r3, u32 * r4)
  190. {
  191. unsigned long start;
  192. unsigned long delay;
  193. int ok;
  194. /*
  195. * Write the command into Mailbox 0
  196. */
  197. writel(command, &dev->IndexRegs->Mailbox[0]);
  198. /*
  199. * Write the parameters into Mailboxes 1 - 6
  200. */
  201. writel(p1, &dev->IndexRegs->Mailbox[1]);
  202. writel(p2, &dev->IndexRegs->Mailbox[2]);
  203. writel(p3, &dev->IndexRegs->Mailbox[3]);
  204. writel(p4, &dev->IndexRegs->Mailbox[4]);
  205. /*
  206. * Clear the synch command doorbell to start on a clean slate.
  207. */
  208. if (!dev->msi_enabled)
  209. src_writel(dev,
  210. MUnit.ODR_C,
  211. OUTBOUNDDOORBELL_0 << SRC_ODR_SHIFT);
  212. /*
  213. * Disable doorbell interrupts
  214. */
  215. src_writel(dev, MUnit.OIMR, dev->OIMR = 0xffffffff);
  216. /*
  217. * Force the completion of the mask register write before issuing
  218. * the interrupt.
  219. */
  220. src_readl(dev, MUnit.OIMR);
  221. /*
  222. * Signal that there is a new synch command
  223. */
  224. src_writel(dev, MUnit.IDR, INBOUNDDOORBELL_0 << SRC_IDR_SHIFT);
  225. if ((!dev->sync_mode || command != SEND_SYNCHRONOUS_FIB) &&
  226. !dev->in_soft_reset) {
  227. ok = 0;
  228. start = jiffies;
  229. if (command == IOP_RESET_ALWAYS) {
  230. /* Wait up to 10 sec */
  231. delay = 10*HZ;
  232. } else {
  233. /* Wait up to 5 minutes */
  234. delay = 300*HZ;
  235. }
  236. while (time_before(jiffies, start+delay)) {
  237. udelay(5); /* Delay 5 microseconds to let Mon960 get info. */
  238. /*
  239. * Mon960 will set doorbell0 bit when it has completed the command.
  240. */
  241. if (aac_src_get_sync_status(dev) & OUTBOUNDDOORBELL_0) {
  242. /*
  243. * Clear the doorbell.
  244. */
  245. if (dev->msi_enabled)
  246. aac_src_access_devreg(dev,
  247. AAC_CLEAR_SYNC_BIT);
  248. else
  249. src_writel(dev,
  250. MUnit.ODR_C,
  251. OUTBOUNDDOORBELL_0 << SRC_ODR_SHIFT);
  252. ok = 1;
  253. break;
  254. }
  255. /*
  256. * Yield the processor in case we are slow
  257. */
  258. msleep(1);
  259. }
  260. if (unlikely(ok != 1)) {
  261. /*
  262. * Restore interrupt mask even though we timed out
  263. */
  264. aac_adapter_enable_int(dev);
  265. return -ETIMEDOUT;
  266. }
  267. /*
  268. * Pull the synch status from Mailbox 0.
  269. */
  270. if (status)
  271. *status = readl(&dev->IndexRegs->Mailbox[0]);
  272. if (r1)
  273. *r1 = readl(&dev->IndexRegs->Mailbox[1]);
  274. if (r2)
  275. *r2 = readl(&dev->IndexRegs->Mailbox[2]);
  276. if (r3)
  277. *r3 = readl(&dev->IndexRegs->Mailbox[3]);
  278. if (r4)
  279. *r4 = readl(&dev->IndexRegs->Mailbox[4]);
  280. if (command == GET_COMM_PREFERRED_SETTINGS)
  281. dev->max_msix =
  282. readl(&dev->IndexRegs->Mailbox[5]) & 0xFFFF;
  283. /*
  284. * Clear the synch command doorbell.
  285. */
  286. if (!dev->msi_enabled)
  287. src_writel(dev,
  288. MUnit.ODR_C,
  289. OUTBOUNDDOORBELL_0 << SRC_ODR_SHIFT);
  290. }
  291. /*
  292. * Restore interrupt mask
  293. */
  294. aac_adapter_enable_int(dev);
  295. return 0;
  296. }
  297. /**
  298. * aac_src_interrupt_adapter - interrupt adapter
  299. * @dev: Adapter
  300. *
  301. * Send an interrupt to the i960 and breakpoint it.
  302. */
  303. static void aac_src_interrupt_adapter(struct aac_dev *dev)
  304. {
  305. src_sync_cmd(dev, BREAKPOINT_REQUEST,
  306. 0, 0, 0, 0, 0, 0,
  307. NULL, NULL, NULL, NULL, NULL);
  308. }
  309. /**
  310. * aac_src_notify_adapter - send an event to the adapter
  311. * @dev: Adapter
  312. * @event: Event to send
  313. *
  314. * Notify the i960 that something it probably cares about has
  315. * happened.
  316. */
  317. static void aac_src_notify_adapter(struct aac_dev *dev, u32 event)
  318. {
  319. switch (event) {
  320. case AdapNormCmdQue:
  321. src_writel(dev, MUnit.ODR_C,
  322. INBOUNDDOORBELL_1 << SRC_ODR_SHIFT);
  323. break;
  324. case HostNormRespNotFull:
  325. src_writel(dev, MUnit.ODR_C,
  326. INBOUNDDOORBELL_4 << SRC_ODR_SHIFT);
  327. break;
  328. case AdapNormRespQue:
  329. src_writel(dev, MUnit.ODR_C,
  330. INBOUNDDOORBELL_2 << SRC_ODR_SHIFT);
  331. break;
  332. case HostNormCmdNotFull:
  333. src_writel(dev, MUnit.ODR_C,
  334. INBOUNDDOORBELL_3 << SRC_ODR_SHIFT);
  335. break;
  336. case FastIo:
  337. src_writel(dev, MUnit.ODR_C,
  338. INBOUNDDOORBELL_6 << SRC_ODR_SHIFT);
  339. break;
  340. case AdapPrintfDone:
  341. src_writel(dev, MUnit.ODR_C,
  342. INBOUNDDOORBELL_5 << SRC_ODR_SHIFT);
  343. break;
  344. default:
  345. BUG();
  346. break;
  347. }
  348. }
  349. /**
  350. * aac_src_start_adapter - activate adapter
  351. * @dev: Adapter
  352. *
  353. * Start up processing on an i960 based AAC adapter
  354. */
  355. static void aac_src_start_adapter(struct aac_dev *dev)
  356. {
  357. union aac_init *init;
  358. int i;
  359. /* reset host_rrq_idx first */
  360. for (i = 0; i < dev->max_msix; i++) {
  361. dev->host_rrq_idx[i] = i * dev->vector_cap;
  362. atomic_set(&dev->rrq_outstanding[i], 0);
  363. }
  364. atomic_set(&dev->msix_counter, 0);
  365. dev->fibs_pushed_no = 0;
  366. init = dev->init;
  367. if (dev->comm_interface == AAC_COMM_MESSAGE_TYPE3) {
  368. init->r8.host_elapsed_seconds =
  369. cpu_to_le32(ktime_get_real_seconds());
  370. src_sync_cmd(dev, INIT_STRUCT_BASE_ADDRESS,
  371. lower_32_bits(dev->init_pa),
  372. upper_32_bits(dev->init_pa),
  373. sizeof(struct _r8) +
  374. (AAC_MAX_HRRQ - 1) * sizeof(struct _rrq),
  375. 0, 0, 0, NULL, NULL, NULL, NULL, NULL);
  376. } else {
  377. init->r7.host_elapsed_seconds =
  378. cpu_to_le32(ktime_get_real_seconds());
  379. // We can only use a 32 bit address here
  380. src_sync_cmd(dev, INIT_STRUCT_BASE_ADDRESS,
  381. (u32)(ulong)dev->init_pa, 0, 0, 0, 0, 0,
  382. NULL, NULL, NULL, NULL, NULL);
  383. }
  384. }
  385. /**
  386. * aac_src_check_health
  387. * @dev: device to check if healthy
  388. *
  389. * Will attempt to determine if the specified adapter is alive and
  390. * capable of handling requests, returning 0 if alive.
  391. */
  392. static int aac_src_check_health(struct aac_dev *dev)
  393. {
  394. u32 status = src_readl(dev, MUnit.OMR);
  395. /*
  396. * Check to see if the board panic'd.
  397. */
  398. if (unlikely(status & KERNEL_PANIC))
  399. goto err_blink;
  400. /*
  401. * Check to see if the board failed any self tests.
  402. */
  403. if (unlikely(status & SELF_TEST_FAILED))
  404. goto err_out;
  405. /*
  406. * Check to see if the board failed any self tests.
  407. */
  408. if (unlikely(status & MONITOR_PANIC))
  409. goto err_out;
  410. /*
  411. * Wait for the adapter to be up and running.
  412. */
  413. if (unlikely(!(status & KERNEL_UP_AND_RUNNING)))
  414. return -3;
  415. /*
  416. * Everything is OK
  417. */
  418. return 0;
  419. err_out:
  420. return -1;
  421. err_blink:
  422. return (status >> 16) & 0xFF;
  423. }
  424. static inline u32 aac_get_vector(struct aac_dev *dev)
  425. {
  426. return atomic_inc_return(&dev->msix_counter)%dev->max_msix;
  427. }
  428. /**
  429. * aac_src_deliver_message
  430. * @fib: fib to issue
  431. *
  432. * Will send a fib, returning 0 if successful.
  433. */
  434. static int aac_src_deliver_message(struct fib *fib)
  435. {
  436. struct aac_dev *dev = fib->dev;
  437. struct aac_queue *q = &dev->queues->queue[AdapNormCmdQueue];
  438. u32 fibsize;
  439. dma_addr_t address;
  440. struct aac_fib_xporthdr *pFibX;
  441. int native_hba;
  442. #if !defined(writeq)
  443. unsigned long flags;
  444. #endif
  445. u16 vector_no;
  446. struct scsi_cmnd *scmd;
  447. u32 blk_tag;
  448. struct Scsi_Host *shost = dev->scsi_host_ptr;
  449. struct blk_mq_queue_map *qmap;
  450. atomic_inc(&q->numpending);
  451. native_hba = (fib->flags & FIB_CONTEXT_FLAG_NATIVE_HBA) ? 1 : 0;
  452. if (dev->msi_enabled && dev->max_msix > 1 &&
  453. (native_hba || fib->hw_fib_va->header.Command != AifRequest)) {
  454. if ((dev->comm_interface == AAC_COMM_MESSAGE_TYPE3)
  455. && dev->sa_firmware)
  456. vector_no = aac_get_vector(dev);
  457. else {
  458. if (!fib->vector_no || !fib->callback_data) {
  459. if (shost && dev->use_map_queue) {
  460. qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
  461. vector_no = qmap->mq_map[raw_smp_processor_id()];
  462. }
  463. /*
  464. * We hardcode the vector_no for
  465. * reserved commands as a valid shost is
  466. * absent during the init
  467. */
  468. else
  469. vector_no = 0;
  470. } else {
  471. scmd = (struct scsi_cmnd *)fib->callback_data;
  472. blk_tag = blk_mq_unique_tag(scsi_cmd_to_rq(scmd));
  473. vector_no = blk_mq_unique_tag_to_hwq(blk_tag);
  474. }
  475. }
  476. if (native_hba) {
  477. if (fib->flags & FIB_CONTEXT_FLAG_NATIVE_HBA_TMF) {
  478. struct aac_hba_tm_req *tm_req;
  479. tm_req = (struct aac_hba_tm_req *)
  480. fib->hw_fib_va;
  481. if (tm_req->iu_type ==
  482. HBA_IU_TYPE_SCSI_TM_REQ) {
  483. ((struct aac_hba_tm_req *)
  484. fib->hw_fib_va)->reply_qid
  485. = vector_no;
  486. ((struct aac_hba_tm_req *)
  487. fib->hw_fib_va)->request_id
  488. += (vector_no << 16);
  489. } else {
  490. ((struct aac_hba_reset_req *)
  491. fib->hw_fib_va)->reply_qid
  492. = vector_no;
  493. ((struct aac_hba_reset_req *)
  494. fib->hw_fib_va)->request_id
  495. += (vector_no << 16);
  496. }
  497. } else {
  498. ((struct aac_hba_cmd_req *)
  499. fib->hw_fib_va)->reply_qid
  500. = vector_no;
  501. ((struct aac_hba_cmd_req *)
  502. fib->hw_fib_va)->request_id
  503. += (vector_no << 16);
  504. }
  505. } else {
  506. fib->hw_fib_va->header.Handle += (vector_no << 16);
  507. }
  508. } else {
  509. vector_no = 0;
  510. }
  511. atomic_inc(&dev->rrq_outstanding[vector_no]);
  512. if (native_hba) {
  513. address = fib->hw_fib_pa;
  514. fibsize = (fib->hbacmd_size + 127) / 128 - 1;
  515. if (fibsize > 31)
  516. fibsize = 31;
  517. address |= fibsize;
  518. #if defined(writeq)
  519. src_writeq(dev, MUnit.IQN_L, (u64)address);
  520. #else
  521. spin_lock_irqsave(&fib->dev->iq_lock, flags);
  522. src_writel(dev, MUnit.IQN_H,
  523. upper_32_bits(address) & 0xffffffff);
  524. src_writel(dev, MUnit.IQN_L, address & 0xffffffff);
  525. spin_unlock_irqrestore(&fib->dev->iq_lock, flags);
  526. #endif
  527. } else {
  528. if (dev->comm_interface == AAC_COMM_MESSAGE_TYPE2 ||
  529. dev->comm_interface == AAC_COMM_MESSAGE_TYPE3) {
  530. /* Calculate the amount to the fibsize bits */
  531. fibsize = (le16_to_cpu(fib->hw_fib_va->header.Size)
  532. + 127) / 128 - 1;
  533. /* New FIB header, 32-bit */
  534. address = fib->hw_fib_pa;
  535. fib->hw_fib_va->header.StructType = FIB_MAGIC2;
  536. fib->hw_fib_va->header.SenderFibAddress =
  537. cpu_to_le32((u32)address);
  538. fib->hw_fib_va->header.u.TimeStamp = 0;
  539. WARN_ON(upper_32_bits(address) != 0L);
  540. } else {
  541. /* Calculate the amount to the fibsize bits */
  542. fibsize = (sizeof(struct aac_fib_xporthdr) +
  543. le16_to_cpu(fib->hw_fib_va->header.Size)
  544. + 127) / 128 - 1;
  545. /* Fill XPORT header */
  546. pFibX = (struct aac_fib_xporthdr *)
  547. ((unsigned char *)fib->hw_fib_va -
  548. sizeof(struct aac_fib_xporthdr));
  549. pFibX->Handle = fib->hw_fib_va->header.Handle;
  550. pFibX->HostAddress =
  551. cpu_to_le64((u64)fib->hw_fib_pa);
  552. pFibX->Size = cpu_to_le32(
  553. le16_to_cpu(fib->hw_fib_va->header.Size));
  554. address = fib->hw_fib_pa -
  555. (u64)sizeof(struct aac_fib_xporthdr);
  556. }
  557. if (fibsize > 31)
  558. fibsize = 31;
  559. address |= fibsize;
  560. #if defined(writeq)
  561. src_writeq(dev, MUnit.IQ_L, (u64)address);
  562. #else
  563. spin_lock_irqsave(&fib->dev->iq_lock, flags);
  564. src_writel(dev, MUnit.IQ_H,
  565. upper_32_bits(address) & 0xffffffff);
  566. src_writel(dev, MUnit.IQ_L, address & 0xffffffff);
  567. spin_unlock_irqrestore(&fib->dev->iq_lock, flags);
  568. #endif
  569. }
  570. return 0;
  571. }
  572. /**
  573. * aac_src_ioremap
  574. * @dev: device ioremap
  575. * @size: mapping resize request
  576. *
  577. */
  578. static int aac_src_ioremap(struct aac_dev *dev, u32 size)
  579. {
  580. if (!size) {
  581. iounmap(dev->regs.src.bar1);
  582. dev->regs.src.bar1 = NULL;
  583. iounmap(dev->regs.src.bar0);
  584. dev->base = dev->regs.src.bar0 = NULL;
  585. return 0;
  586. }
  587. dev->regs.src.bar1 = ioremap(pci_resource_start(dev->pdev, 2),
  588. AAC_MIN_SRC_BAR1_SIZE);
  589. dev->base = NULL;
  590. if (dev->regs.src.bar1 == NULL)
  591. return -1;
  592. dev->base = dev->regs.src.bar0 = ioremap(dev->base_start, size);
  593. if (dev->base == NULL) {
  594. iounmap(dev->regs.src.bar1);
  595. dev->regs.src.bar1 = NULL;
  596. return -1;
  597. }
  598. dev->IndexRegs = &((struct src_registers __iomem *)
  599. dev->base)->u.tupelo.IndexRegs;
  600. return 0;
  601. }
  602. /**
  603. * aac_srcv_ioremap
  604. * @dev: device ioremap
  605. * @size: mapping resize request
  606. *
  607. */
  608. static int aac_srcv_ioremap(struct aac_dev *dev, u32 size)
  609. {
  610. if (!size) {
  611. iounmap(dev->regs.src.bar0);
  612. dev->base = dev->regs.src.bar0 = NULL;
  613. return 0;
  614. }
  615. dev->regs.src.bar1 =
  616. ioremap(pci_resource_start(dev->pdev, 2), AAC_MIN_SRCV_BAR1_SIZE);
  617. dev->base = NULL;
  618. if (dev->regs.src.bar1 == NULL)
  619. return -1;
  620. dev->base = dev->regs.src.bar0 = ioremap(dev->base_start, size);
  621. if (dev->base == NULL) {
  622. iounmap(dev->regs.src.bar1);
  623. dev->regs.src.bar1 = NULL;
  624. return -1;
  625. }
  626. dev->IndexRegs = &((struct src_registers __iomem *)
  627. dev->base)->u.denali.IndexRegs;
  628. return 0;
  629. }
  630. void aac_set_intx_mode(struct aac_dev *dev)
  631. {
  632. if (dev->msi_enabled) {
  633. aac_src_access_devreg(dev, AAC_ENABLE_INTX);
  634. dev->msi_enabled = 0;
  635. msleep(5000); /* Delay 5 seconds */
  636. }
  637. }
  638. static void aac_clear_omr(struct aac_dev *dev)
  639. {
  640. u32 omr_value = 0;
  641. omr_value = src_readl(dev, MUnit.OMR);
  642. /*
  643. * Check for PCI Errors or Kernel Panic
  644. */
  645. if ((omr_value == INVALID_OMR) || (omr_value & KERNEL_PANIC))
  646. omr_value = 0;
  647. /*
  648. * Preserve MSIX Value if any
  649. */
  650. src_writel(dev, MUnit.OMR, omr_value & AAC_INT_MODE_MSIX);
  651. src_readl(dev, MUnit.OMR);
  652. }
  653. static void aac_dump_fw_fib_iop_reset(struct aac_dev *dev)
  654. {
  655. __le32 supported_options3;
  656. if (!aac_fib_dump)
  657. return;
  658. supported_options3 = dev->supplement_adapter_info.supported_options3;
  659. if (!(supported_options3 & AAC_OPTION_SUPPORTED3_IOP_RESET_FIB_DUMP))
  660. return;
  661. aac_adapter_sync_cmd(dev, IOP_RESET_FW_FIB_DUMP,
  662. 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL);
  663. }
  664. static bool aac_is_ctrl_up_and_running(struct aac_dev *dev)
  665. {
  666. bool ctrl_up = true;
  667. unsigned long status, start;
  668. bool is_up = false;
  669. start = jiffies;
  670. do {
  671. schedule();
  672. status = src_readl(dev, MUnit.OMR);
  673. if (status == 0xffffffff)
  674. status = 0;
  675. if (status & KERNEL_BOOTING) {
  676. start = jiffies;
  677. continue;
  678. }
  679. if (time_after(jiffies, start+HZ*SOFT_RESET_TIME)) {
  680. ctrl_up = false;
  681. break;
  682. }
  683. is_up = status & KERNEL_UP_AND_RUNNING;
  684. } while (!is_up);
  685. return ctrl_up;
  686. }
  687. static void aac_src_drop_io(struct aac_dev *dev)
  688. {
  689. if (!dev->soft_reset_support)
  690. return;
  691. aac_adapter_sync_cmd(dev, DROP_IO,
  692. 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL);
  693. }
  694. static void aac_notify_fw_of_iop_reset(struct aac_dev *dev)
  695. {
  696. aac_adapter_sync_cmd(dev, IOP_RESET_ALWAYS, 0, 0, 0, 0, 0, 0, NULL,
  697. NULL, NULL, NULL, NULL);
  698. aac_src_drop_io(dev);
  699. }
  700. static void aac_send_iop_reset(struct aac_dev *dev)
  701. {
  702. aac_dump_fw_fib_iop_reset(dev);
  703. aac_notify_fw_of_iop_reset(dev);
  704. aac_set_intx_mode(dev);
  705. aac_clear_omr(dev);
  706. src_writel(dev, MUnit.IDR, IOP_SRC_RESET_MASK);
  707. msleep(5000);
  708. }
  709. static void aac_send_hardware_soft_reset(struct aac_dev *dev)
  710. {
  711. u_int32_t val;
  712. aac_clear_omr(dev);
  713. val = readl(((char *)(dev->base) + IBW_SWR_OFFSET));
  714. val |= 0x01;
  715. writel(val, ((char *)(dev->base) + IBW_SWR_OFFSET));
  716. msleep_interruptible(20000);
  717. }
  718. static int aac_src_restart_adapter(struct aac_dev *dev, int bled, u8 reset_type)
  719. {
  720. bool is_ctrl_up;
  721. int ret = 0;
  722. if (bled < 0)
  723. goto invalid_out;
  724. if (bled)
  725. dev_err(&dev->pdev->dev, "adapter kernel panic'd %x.\n", bled);
  726. /*
  727. * When there is a BlinkLED, IOP_RESET has not effect
  728. */
  729. if (bled >= 2 && dev->sa_firmware && reset_type & HW_IOP_RESET)
  730. reset_type &= ~HW_IOP_RESET;
  731. dev->a_ops.adapter_enable_int = aac_src_disable_interrupt;
  732. dev_err(&dev->pdev->dev, "Controller reset type is %d\n", reset_type);
  733. if (reset_type & HW_IOP_RESET) {
  734. dev_info(&dev->pdev->dev, "Issuing IOP reset\n");
  735. aac_send_iop_reset(dev);
  736. /*
  737. * Creates a delay or wait till up and running comes thru
  738. */
  739. is_ctrl_up = aac_is_ctrl_up_and_running(dev);
  740. if (!is_ctrl_up)
  741. dev_err(&dev->pdev->dev, "IOP reset failed\n");
  742. else {
  743. dev_info(&dev->pdev->dev, "IOP reset succeeded\n");
  744. goto set_startup;
  745. }
  746. }
  747. if (!dev->sa_firmware) {
  748. dev_err(&dev->pdev->dev, "ARC Reset attempt failed\n");
  749. ret = -ENODEV;
  750. goto out;
  751. }
  752. if (reset_type & HW_SOFT_RESET) {
  753. dev_info(&dev->pdev->dev, "Issuing SOFT reset\n");
  754. aac_send_hardware_soft_reset(dev);
  755. dev->msi_enabled = 0;
  756. is_ctrl_up = aac_is_ctrl_up_and_running(dev);
  757. if (!is_ctrl_up) {
  758. dev_err(&dev->pdev->dev, "SOFT reset failed\n");
  759. ret = -ENODEV;
  760. goto out;
  761. } else
  762. dev_info(&dev->pdev->dev, "SOFT reset succeeded\n");
  763. }
  764. set_startup:
  765. if (startup_timeout < 300)
  766. startup_timeout = 300;
  767. out:
  768. return ret;
  769. invalid_out:
  770. if (src_readl(dev, MUnit.OMR) & KERNEL_PANIC)
  771. ret = -ENODEV;
  772. goto out;
  773. }
  774. /**
  775. * aac_src_select_comm - Select communications method
  776. * @dev: Adapter
  777. * @comm: communications method
  778. */
  779. static int aac_src_select_comm(struct aac_dev *dev, int comm)
  780. {
  781. switch (comm) {
  782. case AAC_COMM_MESSAGE:
  783. dev->a_ops.adapter_intr = aac_src_intr_message;
  784. dev->a_ops.adapter_deliver = aac_src_deliver_message;
  785. break;
  786. default:
  787. return 1;
  788. }
  789. return 0;
  790. }
  791. /**
  792. * aac_src_init - initialize an Cardinal Frey Bar card
  793. * @dev: device to configure
  794. *
  795. */
  796. int aac_src_init(struct aac_dev *dev)
  797. {
  798. unsigned long start;
  799. unsigned long status;
  800. int restart = 0;
  801. int instance = dev->id;
  802. const char *name = dev->name;
  803. dev->a_ops.adapter_ioremap = aac_src_ioremap;
  804. dev->a_ops.adapter_comm = aac_src_select_comm;
  805. dev->base_size = AAC_MIN_SRC_BAR0_SIZE;
  806. if (aac_adapter_ioremap(dev, dev->base_size)) {
  807. printk(KERN_WARNING "%s: unable to map adapter.\n", name);
  808. goto error_iounmap;
  809. }
  810. /* Failure to reset here is an option ... */
  811. dev->a_ops.adapter_sync_cmd = src_sync_cmd;
  812. dev->a_ops.adapter_enable_int = aac_src_disable_interrupt;
  813. if (dev->init_reset) {
  814. dev->init_reset = false;
  815. if (!aac_src_restart_adapter(dev, 0, IOP_HWSOFT_RESET))
  816. ++restart;
  817. }
  818. /*
  819. * Check to see if the board panic'd while booting.
  820. */
  821. status = src_readl(dev, MUnit.OMR);
  822. if (status & KERNEL_PANIC) {
  823. if (aac_src_restart_adapter(dev,
  824. aac_src_check_health(dev), IOP_HWSOFT_RESET))
  825. goto error_iounmap;
  826. ++restart;
  827. }
  828. /*
  829. * Check to see if the board failed any self tests.
  830. */
  831. status = src_readl(dev, MUnit.OMR);
  832. if (status & SELF_TEST_FAILED) {
  833. printk(KERN_ERR "%s%d: adapter self-test failed.\n",
  834. dev->name, instance);
  835. goto error_iounmap;
  836. }
  837. /*
  838. * Check to see if the monitor panic'd while booting.
  839. */
  840. if (status & MONITOR_PANIC) {
  841. printk(KERN_ERR "%s%d: adapter monitor panic.\n",
  842. dev->name, instance);
  843. goto error_iounmap;
  844. }
  845. start = jiffies;
  846. /*
  847. * Wait for the adapter to be up and running. Wait up to 3 minutes
  848. */
  849. while (!((status = src_readl(dev, MUnit.OMR)) &
  850. KERNEL_UP_AND_RUNNING)) {
  851. if ((restart &&
  852. (status & (KERNEL_PANIC|SELF_TEST_FAILED|MONITOR_PANIC))) ||
  853. time_after(jiffies, start+HZ*startup_timeout)) {
  854. printk(KERN_ERR "%s%d: adapter kernel failed to start, init status = %lx.\n",
  855. dev->name, instance, status);
  856. goto error_iounmap;
  857. }
  858. if (!restart &&
  859. ((status & (KERNEL_PANIC|SELF_TEST_FAILED|MONITOR_PANIC)) ||
  860. time_after(jiffies, start + HZ *
  861. ((startup_timeout > 60)
  862. ? (startup_timeout - 60)
  863. : (startup_timeout / 2))))) {
  864. if (likely(!aac_src_restart_adapter(dev,
  865. aac_src_check_health(dev), IOP_HWSOFT_RESET)))
  866. start = jiffies;
  867. ++restart;
  868. }
  869. msleep(1);
  870. }
  871. if (restart && aac_commit)
  872. aac_commit = 1;
  873. /*
  874. * Fill in the common function dispatch table.
  875. */
  876. dev->a_ops.adapter_interrupt = aac_src_interrupt_adapter;
  877. dev->a_ops.adapter_disable_int = aac_src_disable_interrupt;
  878. dev->a_ops.adapter_enable_int = aac_src_disable_interrupt;
  879. dev->a_ops.adapter_notify = aac_src_notify_adapter;
  880. dev->a_ops.adapter_sync_cmd = src_sync_cmd;
  881. dev->a_ops.adapter_check_health = aac_src_check_health;
  882. dev->a_ops.adapter_restart = aac_src_restart_adapter;
  883. dev->a_ops.adapter_start = aac_src_start_adapter;
  884. /*
  885. * First clear out all interrupts. Then enable the one's that we
  886. * can handle.
  887. */
  888. aac_adapter_comm(dev, AAC_COMM_MESSAGE);
  889. aac_adapter_disable_int(dev);
  890. src_writel(dev, MUnit.ODR_C, 0xffffffff);
  891. aac_adapter_enable_int(dev);
  892. if (aac_init_adapter(dev) == NULL)
  893. goto error_iounmap;
  894. if (dev->comm_interface != AAC_COMM_MESSAGE_TYPE1)
  895. goto error_iounmap;
  896. dev->msi = !pci_enable_msi(dev->pdev);
  897. dev->aac_msix[0].vector_no = 0;
  898. dev->aac_msix[0].dev = dev;
  899. if (request_irq(dev->pdev->irq, dev->a_ops.adapter_intr,
  900. IRQF_SHARED, "aacraid", &(dev->aac_msix[0])) < 0) {
  901. if (dev->msi)
  902. pci_disable_msi(dev->pdev);
  903. printk(KERN_ERR "%s%d: Interrupt unavailable.\n",
  904. name, instance);
  905. goto error_iounmap;
  906. }
  907. dev->dbg_base = pci_resource_start(dev->pdev, 2);
  908. dev->dbg_base_mapped = dev->regs.src.bar1;
  909. dev->dbg_size = AAC_MIN_SRC_BAR1_SIZE;
  910. dev->a_ops.adapter_enable_int = aac_src_enable_interrupt_message;
  911. aac_adapter_enable_int(dev);
  912. if (!dev->sync_mode) {
  913. /*
  914. * Tell the adapter that all is configured, and it can
  915. * start accepting requests
  916. */
  917. aac_src_start_adapter(dev);
  918. }
  919. return 0;
  920. error_iounmap:
  921. return -1;
  922. }
  923. static int aac_src_wait_sync(struct aac_dev *dev, int *status)
  924. {
  925. unsigned long start = jiffies;
  926. unsigned long usecs = 0;
  927. int delay = 5 * HZ;
  928. int rc = 1;
  929. while (time_before(jiffies, start+delay)) {
  930. /*
  931. * Delay 5 microseconds to let Mon960 get info.
  932. */
  933. udelay(5);
  934. /*
  935. * Mon960 will set doorbell0 bit when it has completed the
  936. * command.
  937. */
  938. if (aac_src_get_sync_status(dev) & OUTBOUNDDOORBELL_0) {
  939. /*
  940. * Clear: the doorbell.
  941. */
  942. if (dev->msi_enabled)
  943. aac_src_access_devreg(dev, AAC_CLEAR_SYNC_BIT);
  944. else
  945. src_writel(dev, MUnit.ODR_C,
  946. OUTBOUNDDOORBELL_0 << SRC_ODR_SHIFT);
  947. rc = 0;
  948. break;
  949. }
  950. /*
  951. * Yield the processor in case we are slow
  952. */
  953. usecs = 1 * USEC_PER_MSEC;
  954. usleep_range(usecs, usecs + 50);
  955. }
  956. /*
  957. * Pull the synch status from Mailbox 0.
  958. */
  959. if (status && !rc) {
  960. status[0] = readl(&dev->IndexRegs->Mailbox[0]);
  961. status[1] = readl(&dev->IndexRegs->Mailbox[1]);
  962. status[2] = readl(&dev->IndexRegs->Mailbox[2]);
  963. status[3] = readl(&dev->IndexRegs->Mailbox[3]);
  964. status[4] = readl(&dev->IndexRegs->Mailbox[4]);
  965. }
  966. return rc;
  967. }
  968. /**
  969. * aac_src_soft_reset - perform soft reset to speed up
  970. * access
  971. *
  972. * Assumptions: That the controller is in a state where we can
  973. * bring it back to life with an init struct. We can only use
  974. * fast sync commands, as the timeout is 5 seconds.
  975. *
  976. * @dev: device to configure
  977. *
  978. */
  979. static int aac_src_soft_reset(struct aac_dev *dev)
  980. {
  981. u32 status_omr = src_readl(dev, MUnit.OMR);
  982. u32 status[5];
  983. int rc = 1;
  984. int state = 0;
  985. char *state_str[7] = {
  986. "GET_ADAPTER_PROPERTIES Failed",
  987. "GET_ADAPTER_PROPERTIES timeout",
  988. "SOFT_RESET not supported",
  989. "DROP_IO Failed",
  990. "DROP_IO timeout",
  991. "Check Health failed"
  992. };
  993. if (status_omr == INVALID_OMR)
  994. return 1; // pcie hosed
  995. if (!(status_omr & KERNEL_UP_AND_RUNNING))
  996. return 1; // not up and running
  997. /*
  998. * We go into soft reset mode to allow us to handle response
  999. */
  1000. dev->in_soft_reset = 1;
  1001. dev->msi_enabled = status_omr & AAC_INT_MODE_MSIX;
  1002. /* Get adapter properties */
  1003. rc = aac_adapter_sync_cmd(dev, GET_ADAPTER_PROPERTIES, 0, 0, 0,
  1004. 0, 0, 0, status+0, status+1, status+2, status+3, status+4);
  1005. if (rc)
  1006. goto out;
  1007. state++;
  1008. if (aac_src_wait_sync(dev, status)) {
  1009. rc = 1;
  1010. goto out;
  1011. }
  1012. state++;
  1013. if (!(status[1] & le32_to_cpu(AAC_OPT_EXTENDED) &&
  1014. (status[4] & le32_to_cpu(AAC_EXTOPT_SOFT_RESET)))) {
  1015. rc = 2;
  1016. goto out;
  1017. }
  1018. if ((status[1] & le32_to_cpu(AAC_OPT_EXTENDED)) &&
  1019. (status[4] & le32_to_cpu(AAC_EXTOPT_SA_FIRMWARE)))
  1020. dev->sa_firmware = 1;
  1021. state++;
  1022. rc = aac_adapter_sync_cmd(dev, DROP_IO, 0, 0, 0, 0, 0, 0,
  1023. status+0, status+1, status+2, status+3, status+4);
  1024. if (rc)
  1025. goto out;
  1026. state++;
  1027. if (aac_src_wait_sync(dev, status)) {
  1028. rc = 3;
  1029. goto out;
  1030. }
  1031. if (status[1])
  1032. dev_err(&dev->pdev->dev, "%s: %d outstanding I/O pending\n",
  1033. __func__, status[1]);
  1034. state++;
  1035. rc = aac_src_check_health(dev);
  1036. out:
  1037. dev->in_soft_reset = 0;
  1038. dev->msi_enabled = 0;
  1039. if (rc)
  1040. dev_err(&dev->pdev->dev, "%s: %s status = %d", __func__,
  1041. state_str[state], rc);
  1042. return rc;
  1043. }
  1044. /**
  1045. * aac_srcv_init - initialize an SRCv card
  1046. * @dev: device to configure
  1047. *
  1048. */
  1049. int aac_srcv_init(struct aac_dev *dev)
  1050. {
  1051. unsigned long start;
  1052. unsigned long status;
  1053. int restart = 0;
  1054. int instance = dev->id;
  1055. const char *name = dev->name;
  1056. dev->a_ops.adapter_ioremap = aac_srcv_ioremap;
  1057. dev->a_ops.adapter_comm = aac_src_select_comm;
  1058. dev->base_size = AAC_MIN_SRCV_BAR0_SIZE;
  1059. if (aac_adapter_ioremap(dev, dev->base_size)) {
  1060. printk(KERN_WARNING "%s: unable to map adapter.\n", name);
  1061. goto error_iounmap;
  1062. }
  1063. /* Failure to reset here is an option ... */
  1064. dev->a_ops.adapter_sync_cmd = src_sync_cmd;
  1065. dev->a_ops.adapter_enable_int = aac_src_disable_interrupt;
  1066. if (dev->init_reset) {
  1067. dev->init_reset = false;
  1068. if (aac_src_soft_reset(dev)) {
  1069. aac_src_restart_adapter(dev, 0, IOP_HWSOFT_RESET);
  1070. ++restart;
  1071. }
  1072. }
  1073. /*
  1074. * Check to see if flash update is running.
  1075. * Wait for the adapter to be up and running. Wait up to 5 minutes
  1076. */
  1077. status = src_readl(dev, MUnit.OMR);
  1078. if (status & FLASH_UPD_PENDING) {
  1079. start = jiffies;
  1080. do {
  1081. status = src_readl(dev, MUnit.OMR);
  1082. if (time_after(jiffies, start+HZ*FWUPD_TIMEOUT)) {
  1083. printk(KERN_ERR "%s%d: adapter flash update failed.\n",
  1084. dev->name, instance);
  1085. goto error_iounmap;
  1086. }
  1087. } while (!(status & FLASH_UPD_SUCCESS) &&
  1088. !(status & FLASH_UPD_FAILED));
  1089. /* Delay 10 seconds.
  1090. * Because right now FW is doing a soft reset,
  1091. * do not read scratch pad register at this time
  1092. */
  1093. ssleep(10);
  1094. }
  1095. /*
  1096. * Check to see if the board panic'd while booting.
  1097. */
  1098. status = src_readl(dev, MUnit.OMR);
  1099. if (status & KERNEL_PANIC) {
  1100. if (aac_src_restart_adapter(dev,
  1101. aac_src_check_health(dev), IOP_HWSOFT_RESET))
  1102. goto error_iounmap;
  1103. ++restart;
  1104. }
  1105. /*
  1106. * Check to see if the board failed any self tests.
  1107. */
  1108. status = src_readl(dev, MUnit.OMR);
  1109. if (status & SELF_TEST_FAILED) {
  1110. printk(KERN_ERR "%s%d: adapter self-test failed.\n", dev->name, instance);
  1111. goto error_iounmap;
  1112. }
  1113. /*
  1114. * Check to see if the monitor panic'd while booting.
  1115. */
  1116. if (status & MONITOR_PANIC) {
  1117. printk(KERN_ERR "%s%d: adapter monitor panic.\n", dev->name, instance);
  1118. goto error_iounmap;
  1119. }
  1120. start = jiffies;
  1121. /*
  1122. * Wait for the adapter to be up and running. Wait up to 3 minutes
  1123. */
  1124. do {
  1125. status = src_readl(dev, MUnit.OMR);
  1126. if (status == INVALID_OMR)
  1127. status = 0;
  1128. if ((restart &&
  1129. (status & (KERNEL_PANIC|SELF_TEST_FAILED|MONITOR_PANIC))) ||
  1130. time_after(jiffies, start+HZ*startup_timeout)) {
  1131. printk(KERN_ERR "%s%d: adapter kernel failed to start, init status = %lx.\n",
  1132. dev->name, instance, status);
  1133. goto error_iounmap;
  1134. }
  1135. if (!restart &&
  1136. ((status & (KERNEL_PANIC|SELF_TEST_FAILED|MONITOR_PANIC)) ||
  1137. time_after(jiffies, start + HZ *
  1138. ((startup_timeout > 60)
  1139. ? (startup_timeout - 60)
  1140. : (startup_timeout / 2))))) {
  1141. if (likely(!aac_src_restart_adapter(dev,
  1142. aac_src_check_health(dev), IOP_HWSOFT_RESET)))
  1143. start = jiffies;
  1144. ++restart;
  1145. }
  1146. msleep(1);
  1147. } while (!(status & KERNEL_UP_AND_RUNNING));
  1148. if (restart && aac_commit)
  1149. aac_commit = 1;
  1150. /*
  1151. * Fill in the common function dispatch table.
  1152. */
  1153. dev->a_ops.adapter_interrupt = aac_src_interrupt_adapter;
  1154. dev->a_ops.adapter_disable_int = aac_src_disable_interrupt;
  1155. dev->a_ops.adapter_enable_int = aac_src_disable_interrupt;
  1156. dev->a_ops.adapter_notify = aac_src_notify_adapter;
  1157. dev->a_ops.adapter_sync_cmd = src_sync_cmd;
  1158. dev->a_ops.adapter_check_health = aac_src_check_health;
  1159. dev->a_ops.adapter_restart = aac_src_restart_adapter;
  1160. dev->a_ops.adapter_start = aac_src_start_adapter;
  1161. /*
  1162. * First clear out all interrupts. Then enable the one's that we
  1163. * can handle.
  1164. */
  1165. aac_adapter_comm(dev, AAC_COMM_MESSAGE);
  1166. aac_adapter_disable_int(dev);
  1167. src_writel(dev, MUnit.ODR_C, 0xffffffff);
  1168. aac_adapter_enable_int(dev);
  1169. if (aac_init_adapter(dev) == NULL)
  1170. goto error_iounmap;
  1171. if ((dev->comm_interface != AAC_COMM_MESSAGE_TYPE2) &&
  1172. (dev->comm_interface != AAC_COMM_MESSAGE_TYPE3))
  1173. goto error_iounmap;
  1174. if (dev->msi_enabled)
  1175. aac_src_access_devreg(dev, AAC_ENABLE_MSIX);
  1176. if (aac_acquire_irq(dev))
  1177. goto error_iounmap;
  1178. dev->dbg_base = pci_resource_start(dev->pdev, 2);
  1179. dev->dbg_base_mapped = dev->regs.src.bar1;
  1180. dev->dbg_size = AAC_MIN_SRCV_BAR1_SIZE;
  1181. dev->a_ops.adapter_enable_int = aac_src_enable_interrupt_message;
  1182. aac_adapter_enable_int(dev);
  1183. if (!dev->sync_mode) {
  1184. /*
  1185. * Tell the adapter that all is configured, and it can
  1186. * start accepting requests
  1187. */
  1188. aac_src_start_adapter(dev);
  1189. }
  1190. return 0;
  1191. error_iounmap:
  1192. return -1;
  1193. }
  1194. void aac_src_access_devreg(struct aac_dev *dev, int mode)
  1195. {
  1196. u_int32_t val;
  1197. switch (mode) {
  1198. case AAC_ENABLE_INTERRUPT:
  1199. src_writel(dev,
  1200. MUnit.OIMR,
  1201. dev->OIMR = (dev->msi_enabled ?
  1202. AAC_INT_ENABLE_TYPE1_MSIX :
  1203. AAC_INT_ENABLE_TYPE1_INTX));
  1204. break;
  1205. case AAC_DISABLE_INTERRUPT:
  1206. src_writel(dev,
  1207. MUnit.OIMR,
  1208. dev->OIMR = AAC_INT_DISABLE_ALL);
  1209. break;
  1210. case AAC_ENABLE_MSIX:
  1211. /* set bit 6 */
  1212. val = src_readl(dev, MUnit.IDR);
  1213. val |= 0x40;
  1214. src_writel(dev, MUnit.IDR, val);
  1215. src_readl(dev, MUnit.IDR);
  1216. /* unmask int. */
  1217. val = PMC_ALL_INTERRUPT_BITS;
  1218. src_writel(dev, MUnit.IOAR, val);
  1219. val = src_readl(dev, MUnit.OIMR);
  1220. src_writel(dev,
  1221. MUnit.OIMR,
  1222. val & (~(PMC_GLOBAL_INT_BIT2 | PMC_GLOBAL_INT_BIT0)));
  1223. break;
  1224. case AAC_DISABLE_MSIX:
  1225. /* reset bit 6 */
  1226. val = src_readl(dev, MUnit.IDR);
  1227. val &= ~0x40;
  1228. src_writel(dev, MUnit.IDR, val);
  1229. src_readl(dev, MUnit.IDR);
  1230. break;
  1231. case AAC_CLEAR_AIF_BIT:
  1232. /* set bit 5 */
  1233. val = src_readl(dev, MUnit.IDR);
  1234. val |= 0x20;
  1235. src_writel(dev, MUnit.IDR, val);
  1236. src_readl(dev, MUnit.IDR);
  1237. break;
  1238. case AAC_CLEAR_SYNC_BIT:
  1239. /* set bit 4 */
  1240. val = src_readl(dev, MUnit.IDR);
  1241. val |= 0x10;
  1242. src_writel(dev, MUnit.IDR, val);
  1243. src_readl(dev, MUnit.IDR);
  1244. break;
  1245. case AAC_ENABLE_INTX:
  1246. /* set bit 7 */
  1247. val = src_readl(dev, MUnit.IDR);
  1248. val |= 0x80;
  1249. src_writel(dev, MUnit.IDR, val);
  1250. src_readl(dev, MUnit.IDR);
  1251. /* unmask int. */
  1252. val = PMC_ALL_INTERRUPT_BITS;
  1253. src_writel(dev, MUnit.IOAR, val);
  1254. src_readl(dev, MUnit.IOAR);
  1255. val = src_readl(dev, MUnit.OIMR);
  1256. src_writel(dev, MUnit.OIMR,
  1257. val & (~(PMC_GLOBAL_INT_BIT2)));
  1258. break;
  1259. default:
  1260. break;
  1261. }
  1262. }
  1263. static int aac_src_get_sync_status(struct aac_dev *dev)
  1264. {
  1265. int msix_val = 0;
  1266. int legacy_val = 0;
  1267. msix_val = src_readl(dev, MUnit.ODR_MSI) & SRC_MSI_READ_MASK ? 1 : 0;
  1268. if (!dev->msi_enabled) {
  1269. /*
  1270. * if Legacy int status indicates cmd is not complete
  1271. * sample MSIx register to see if it indiactes cmd complete,
  1272. * if yes set the controller in MSIx mode and consider cmd
  1273. * completed
  1274. */
  1275. legacy_val = src_readl(dev, MUnit.ODR_R) >> SRC_ODR_SHIFT;
  1276. if (!(legacy_val & 1) && msix_val)
  1277. dev->msi_enabled = 1;
  1278. return legacy_val;
  1279. }
  1280. return msix_val;
  1281. }