rtc-zynqmp.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Xilinx Zynq Ultrascale+ MPSoC Real Time Clock Driver
  4. *
  5. * Copyright (C) 2015 Xilinx, Inc.
  6. *
  7. */
  8. #include <linux/clk.h>
  9. #include <linux/delay.h>
  10. #include <linux/init.h>
  11. #include <linux/io.h>
  12. #include <linux/module.h>
  13. #include <linux/of.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/rtc.h>
  16. /* RTC Registers */
  17. #define RTC_SET_TM_WR 0x00
  18. #define RTC_SET_TM_RD 0x04
  19. #define RTC_CALIB_WR 0x08
  20. #define RTC_CALIB_RD 0x0C
  21. #define RTC_CUR_TM 0x10
  22. #define RTC_CUR_TICK 0x14
  23. #define RTC_ALRM 0x18
  24. #define RTC_INT_STS 0x20
  25. #define RTC_INT_MASK 0x24
  26. #define RTC_INT_EN 0x28
  27. #define RTC_INT_DIS 0x2C
  28. #define RTC_CTRL 0x40
  29. #define RTC_FR_EN BIT(20)
  30. #define RTC_FR_DATSHIFT 16
  31. #define RTC_TICK_MASK 0xFFFF
  32. #define RTC_INT_SEC BIT(0)
  33. #define RTC_INT_ALRM BIT(1)
  34. #define RTC_OSC_EN BIT(24)
  35. #define RTC_BATT_EN BIT(31)
  36. #define RTC_CALIB_DEF 0x7FFF
  37. #define RTC_CALIB_MASK 0x1FFFFF
  38. #define RTC_ALRM_MASK BIT(1)
  39. #define RTC_MSEC 1000
  40. #define RTC_FR_MASK 0xF0000
  41. #define RTC_FR_MAX_TICKS 16
  42. #define RTC_PPB 1000000000LL
  43. #define RTC_MIN_OFFSET -32768000
  44. #define RTC_MAX_OFFSET 32767000
  45. struct xlnx_rtc_dev {
  46. struct rtc_device *rtc;
  47. void __iomem *reg_base;
  48. int alarm_irq;
  49. int sec_irq;
  50. struct clk *rtc_clk;
  51. unsigned int freq;
  52. };
  53. static int xlnx_rtc_set_time(struct device *dev, struct rtc_time *tm)
  54. {
  55. struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
  56. unsigned long new_time;
  57. /*
  58. * The value written will be updated after 1 sec into the
  59. * seconds read register, so we need to program time +1 sec
  60. * to get the correct time on read.
  61. */
  62. new_time = rtc_tm_to_time64(tm) + 1;
  63. writel(new_time, xrtcdev->reg_base + RTC_SET_TM_WR);
  64. /*
  65. * Clear the rtc interrupt status register after setting the
  66. * time. During a read_time function, the code should read the
  67. * RTC_INT_STATUS register and if bit 0 is still 0, it means
  68. * that one second has not elapsed yet since RTC was set and
  69. * the current time should be read from SET_TIME_READ register;
  70. * otherwise, CURRENT_TIME register is read to report the time
  71. */
  72. writel(RTC_INT_SEC, xrtcdev->reg_base + RTC_INT_STS);
  73. return 0;
  74. }
  75. static int xlnx_rtc_read_time(struct device *dev, struct rtc_time *tm)
  76. {
  77. u32 status;
  78. unsigned long read_time;
  79. struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
  80. status = readl(xrtcdev->reg_base + RTC_INT_STS);
  81. if (status & RTC_INT_SEC) {
  82. /*
  83. * RTC has updated the CURRENT_TIME with the time written into
  84. * SET_TIME_WRITE register.
  85. */
  86. read_time = readl(xrtcdev->reg_base + RTC_CUR_TM);
  87. } else {
  88. /*
  89. * Time written in SET_TIME_WRITE has not yet updated into
  90. * the seconds read register, so read the time from the
  91. * SET_TIME_WRITE instead of CURRENT_TIME register.
  92. * Since we add +1 sec while writing, we need to -1 sec while
  93. * reading.
  94. */
  95. read_time = readl(xrtcdev->reg_base + RTC_SET_TM_RD) - 1;
  96. }
  97. rtc_time64_to_tm(read_time, tm);
  98. return 0;
  99. }
  100. static int xlnx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  101. {
  102. struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
  103. rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_ALRM), &alrm->time);
  104. alrm->enabled = readl(xrtcdev->reg_base + RTC_INT_MASK) & RTC_INT_ALRM;
  105. return 0;
  106. }
  107. static int xlnx_rtc_alarm_irq_enable(struct device *dev, u32 enabled)
  108. {
  109. struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
  110. unsigned int status;
  111. ulong timeout;
  112. timeout = jiffies + msecs_to_jiffies(RTC_MSEC);
  113. if (enabled) {
  114. while (1) {
  115. status = readl(xrtcdev->reg_base + RTC_INT_STS);
  116. if (!((status & RTC_ALRM_MASK) == RTC_ALRM_MASK))
  117. break;
  118. if (time_after_eq(jiffies, timeout)) {
  119. dev_err(dev, "Time out occur, while clearing alarm status bit\n");
  120. return -ETIMEDOUT;
  121. }
  122. writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_STS);
  123. }
  124. writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_EN);
  125. } else {
  126. writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_DIS);
  127. }
  128. return 0;
  129. }
  130. static int xlnx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  131. {
  132. struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
  133. unsigned long alarm_time;
  134. alarm_time = rtc_tm_to_time64(&alrm->time);
  135. writel((u32)alarm_time, (xrtcdev->reg_base + RTC_ALRM));
  136. xlnx_rtc_alarm_irq_enable(dev, alrm->enabled);
  137. return 0;
  138. }
  139. static void xlnx_init_rtc(struct xlnx_rtc_dev *xrtcdev)
  140. {
  141. u32 rtc_ctrl;
  142. /* Enable RTC switch to battery when VCC_PSAUX is not available */
  143. rtc_ctrl = readl(xrtcdev->reg_base + RTC_CTRL);
  144. rtc_ctrl |= RTC_BATT_EN;
  145. writel(rtc_ctrl, xrtcdev->reg_base + RTC_CTRL);
  146. }
  147. static int xlnx_rtc_read_offset(struct device *dev, long *offset)
  148. {
  149. struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
  150. unsigned long long rtc_ppb = RTC_PPB;
  151. unsigned int tick_mult = do_div(rtc_ppb, xrtcdev->freq);
  152. unsigned int calibval;
  153. long offset_val;
  154. calibval = readl(xrtcdev->reg_base + RTC_CALIB_RD);
  155. /* Offset with seconds ticks */
  156. offset_val = calibval & RTC_TICK_MASK;
  157. offset_val = offset_val - RTC_CALIB_DEF;
  158. offset_val = offset_val * tick_mult;
  159. /* Offset with fractional ticks */
  160. if (calibval & RTC_FR_EN)
  161. offset_val += ((calibval & RTC_FR_MASK) >> RTC_FR_DATSHIFT)
  162. * (tick_mult / RTC_FR_MAX_TICKS);
  163. *offset = offset_val;
  164. return 0;
  165. }
  166. static int xlnx_rtc_set_offset(struct device *dev, long offset)
  167. {
  168. struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
  169. unsigned long long rtc_ppb = RTC_PPB;
  170. unsigned int tick_mult = do_div(rtc_ppb, xrtcdev->freq);
  171. unsigned char fract_tick = 0;
  172. unsigned int calibval;
  173. short int max_tick;
  174. int fract_offset;
  175. if (offset < RTC_MIN_OFFSET || offset > RTC_MAX_OFFSET)
  176. return -ERANGE;
  177. /* Number ticks for given offset */
  178. max_tick = div_s64_rem(offset, tick_mult, &fract_offset);
  179. /* Number fractional ticks for given offset */
  180. if (fract_offset) {
  181. if (fract_offset < 0) {
  182. fract_offset = fract_offset + tick_mult;
  183. max_tick--;
  184. }
  185. if (fract_offset > (tick_mult / RTC_FR_MAX_TICKS)) {
  186. for (fract_tick = 1; fract_tick < 16; fract_tick++) {
  187. if (fract_offset <=
  188. (fract_tick *
  189. (tick_mult / RTC_FR_MAX_TICKS)))
  190. break;
  191. }
  192. }
  193. }
  194. /* Zynqmp RTC uses second and fractional tick
  195. * counters for compensation
  196. */
  197. calibval = max_tick + RTC_CALIB_DEF;
  198. if (fract_tick)
  199. calibval |= RTC_FR_EN;
  200. calibval |= (fract_tick << RTC_FR_DATSHIFT);
  201. writel(calibval, (xrtcdev->reg_base + RTC_CALIB_WR));
  202. return 0;
  203. }
  204. static const struct rtc_class_ops xlnx_rtc_ops = {
  205. .set_time = xlnx_rtc_set_time,
  206. .read_time = xlnx_rtc_read_time,
  207. .read_alarm = xlnx_rtc_read_alarm,
  208. .set_alarm = xlnx_rtc_set_alarm,
  209. .alarm_irq_enable = xlnx_rtc_alarm_irq_enable,
  210. .read_offset = xlnx_rtc_read_offset,
  211. .set_offset = xlnx_rtc_set_offset,
  212. };
  213. static irqreturn_t xlnx_rtc_interrupt(int irq, void *id)
  214. {
  215. struct xlnx_rtc_dev *xrtcdev = (struct xlnx_rtc_dev *)id;
  216. unsigned int status;
  217. status = readl(xrtcdev->reg_base + RTC_INT_STS);
  218. /* Check if interrupt asserted */
  219. if (!(status & (RTC_INT_SEC | RTC_INT_ALRM)))
  220. return IRQ_NONE;
  221. /* Disable RTC_INT_ALRM interrupt only */
  222. writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_DIS);
  223. if (status & RTC_INT_ALRM)
  224. rtc_update_irq(xrtcdev->rtc, 1, RTC_IRQF | RTC_AF);
  225. return IRQ_HANDLED;
  226. }
  227. static int xlnx_rtc_probe(struct platform_device *pdev)
  228. {
  229. struct xlnx_rtc_dev *xrtcdev;
  230. int ret;
  231. xrtcdev = devm_kzalloc(&pdev->dev, sizeof(*xrtcdev), GFP_KERNEL);
  232. if (!xrtcdev)
  233. return -ENOMEM;
  234. platform_set_drvdata(pdev, xrtcdev);
  235. xrtcdev->rtc = devm_rtc_allocate_device(&pdev->dev);
  236. if (IS_ERR(xrtcdev->rtc))
  237. return PTR_ERR(xrtcdev->rtc);
  238. xrtcdev->rtc->ops = &xlnx_rtc_ops;
  239. xrtcdev->rtc->range_max = U32_MAX;
  240. xrtcdev->reg_base = devm_platform_ioremap_resource(pdev, 0);
  241. if (IS_ERR(xrtcdev->reg_base))
  242. return PTR_ERR(xrtcdev->reg_base);
  243. xrtcdev->alarm_irq = platform_get_irq_byname(pdev, "alarm");
  244. if (xrtcdev->alarm_irq < 0)
  245. return xrtcdev->alarm_irq;
  246. ret = devm_request_irq(&pdev->dev, xrtcdev->alarm_irq,
  247. xlnx_rtc_interrupt, 0,
  248. dev_name(&pdev->dev), xrtcdev);
  249. if (ret) {
  250. dev_err(&pdev->dev, "request irq failed\n");
  251. return ret;
  252. }
  253. xrtcdev->sec_irq = platform_get_irq_byname(pdev, "sec");
  254. if (xrtcdev->sec_irq < 0)
  255. return xrtcdev->sec_irq;
  256. ret = devm_request_irq(&pdev->dev, xrtcdev->sec_irq,
  257. xlnx_rtc_interrupt, 0,
  258. dev_name(&pdev->dev), xrtcdev);
  259. if (ret) {
  260. dev_err(&pdev->dev, "request irq failed\n");
  261. return ret;
  262. }
  263. /* Getting the rtc_clk info */
  264. xrtcdev->rtc_clk = devm_clk_get_optional(&pdev->dev, "rtc_clk");
  265. if (IS_ERR(xrtcdev->rtc_clk)) {
  266. if (PTR_ERR(xrtcdev->rtc_clk) != -EPROBE_DEFER)
  267. dev_warn(&pdev->dev, "Device clock not found.\n");
  268. }
  269. xrtcdev->freq = clk_get_rate(xrtcdev->rtc_clk);
  270. if (!xrtcdev->freq) {
  271. ret = of_property_read_u32(pdev->dev.of_node, "calibration",
  272. &xrtcdev->freq);
  273. if (ret)
  274. xrtcdev->freq = RTC_CALIB_DEF;
  275. }
  276. ret = readl(xrtcdev->reg_base + RTC_CALIB_RD);
  277. if (!ret)
  278. writel(xrtcdev->freq, (xrtcdev->reg_base + RTC_CALIB_WR));
  279. xlnx_init_rtc(xrtcdev);
  280. device_init_wakeup(&pdev->dev, 1);
  281. return devm_rtc_register_device(xrtcdev->rtc);
  282. }
  283. static int xlnx_rtc_remove(struct platform_device *pdev)
  284. {
  285. xlnx_rtc_alarm_irq_enable(&pdev->dev, 0);
  286. device_init_wakeup(&pdev->dev, 0);
  287. return 0;
  288. }
  289. static int __maybe_unused xlnx_rtc_suspend(struct device *dev)
  290. {
  291. struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
  292. if (device_may_wakeup(dev))
  293. enable_irq_wake(xrtcdev->alarm_irq);
  294. else
  295. xlnx_rtc_alarm_irq_enable(dev, 0);
  296. return 0;
  297. }
  298. static int __maybe_unused xlnx_rtc_resume(struct device *dev)
  299. {
  300. struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
  301. if (device_may_wakeup(dev))
  302. disable_irq_wake(xrtcdev->alarm_irq);
  303. else
  304. xlnx_rtc_alarm_irq_enable(dev, 1);
  305. return 0;
  306. }
  307. static SIMPLE_DEV_PM_OPS(xlnx_rtc_pm_ops, xlnx_rtc_suspend, xlnx_rtc_resume);
  308. static const struct of_device_id xlnx_rtc_of_match[] = {
  309. {.compatible = "xlnx,zynqmp-rtc" },
  310. { }
  311. };
  312. MODULE_DEVICE_TABLE(of, xlnx_rtc_of_match);
  313. static struct platform_driver xlnx_rtc_driver = {
  314. .probe = xlnx_rtc_probe,
  315. .remove = xlnx_rtc_remove,
  316. .driver = {
  317. .name = KBUILD_MODNAME,
  318. .pm = &xlnx_rtc_pm_ops,
  319. .of_match_table = xlnx_rtc_of_match,
  320. },
  321. };
  322. module_platform_driver(xlnx_rtc_driver);
  323. MODULE_DESCRIPTION("Xilinx Zynq MPSoC RTC driver");
  324. MODULE_AUTHOR("Xilinx Inc.");
  325. MODULE_LICENSE("GPL v2");