rtc-rs5c348.c 6.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * A SPI driver for the Ricoh RS5C348 RTC
  4. *
  5. * Copyright (C) 2006 Atsushi Nemoto <[email protected]>
  6. *
  7. * The board specific init code should provide characteristics of this
  8. * device:
  9. * Mode 1 (High-Active, Shift-Then-Sample), High Avtive CS
  10. */
  11. #include <linux/bcd.h>
  12. #include <linux/delay.h>
  13. #include <linux/device.h>
  14. #include <linux/errno.h>
  15. #include <linux/init.h>
  16. #include <linux/kernel.h>
  17. #include <linux/string.h>
  18. #include <linux/slab.h>
  19. #include <linux/rtc.h>
  20. #include <linux/workqueue.h>
  21. #include <linux/spi/spi.h>
  22. #include <linux/module.h>
  23. #define RS5C348_REG_SECS 0
  24. #define RS5C348_REG_MINS 1
  25. #define RS5C348_REG_HOURS 2
  26. #define RS5C348_REG_WDAY 3
  27. #define RS5C348_REG_DAY 4
  28. #define RS5C348_REG_MONTH 5
  29. #define RS5C348_REG_YEAR 6
  30. #define RS5C348_REG_CTL1 14
  31. #define RS5C348_REG_CTL2 15
  32. #define RS5C348_SECS_MASK 0x7f
  33. #define RS5C348_MINS_MASK 0x7f
  34. #define RS5C348_HOURS_MASK 0x3f
  35. #define RS5C348_WDAY_MASK 0x03
  36. #define RS5C348_DAY_MASK 0x3f
  37. #define RS5C348_MONTH_MASK 0x1f
  38. #define RS5C348_BIT_PM 0x20 /* REG_HOURS */
  39. #define RS5C348_BIT_Y2K 0x80 /* REG_MONTH */
  40. #define RS5C348_BIT_24H 0x20 /* REG_CTL1 */
  41. #define RS5C348_BIT_XSTP 0x10 /* REG_CTL2 */
  42. #define RS5C348_BIT_VDET 0x40 /* REG_CTL2 */
  43. #define RS5C348_CMD_W(addr) (((addr) << 4) | 0x08) /* single write */
  44. #define RS5C348_CMD_R(addr) (((addr) << 4) | 0x0c) /* single read */
  45. #define RS5C348_CMD_MW(addr) (((addr) << 4) | 0x00) /* burst write */
  46. #define RS5C348_CMD_MR(addr) (((addr) << 4) | 0x04) /* burst read */
  47. struct rs5c348_plat_data {
  48. struct rtc_device *rtc;
  49. int rtc_24h;
  50. };
  51. static int
  52. rs5c348_rtc_set_time(struct device *dev, struct rtc_time *tm)
  53. {
  54. struct spi_device *spi = to_spi_device(dev);
  55. struct rs5c348_plat_data *pdata = dev_get_platdata(&spi->dev);
  56. u8 txbuf[5+7], *txp;
  57. int ret;
  58. ret = spi_w8r8(spi, RS5C348_CMD_R(RS5C348_REG_CTL2));
  59. if (ret < 0)
  60. return ret;
  61. if (ret & RS5C348_BIT_XSTP) {
  62. txbuf[0] = RS5C348_CMD_W(RS5C348_REG_CTL2);
  63. txbuf[1] = 0;
  64. ret = spi_write_then_read(spi, txbuf, 2, NULL, 0);
  65. if (ret < 0)
  66. return ret;
  67. }
  68. /* Transfer 5 bytes before writing SEC. This gives 31us for carry. */
  69. txp = txbuf;
  70. txbuf[0] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */
  71. txbuf[1] = 0; /* dummy */
  72. txbuf[2] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */
  73. txbuf[3] = 0; /* dummy */
  74. txbuf[4] = RS5C348_CMD_MW(RS5C348_REG_SECS); /* cmd, sec, ... */
  75. txp = &txbuf[5];
  76. txp[RS5C348_REG_SECS] = bin2bcd(tm->tm_sec);
  77. txp[RS5C348_REG_MINS] = bin2bcd(tm->tm_min);
  78. if (pdata->rtc_24h) {
  79. txp[RS5C348_REG_HOURS] = bin2bcd(tm->tm_hour);
  80. } else {
  81. /* hour 0 is AM12, noon is PM12 */
  82. txp[RS5C348_REG_HOURS] = bin2bcd((tm->tm_hour + 11) % 12 + 1) |
  83. (tm->tm_hour >= 12 ? RS5C348_BIT_PM : 0);
  84. }
  85. txp[RS5C348_REG_WDAY] = bin2bcd(tm->tm_wday);
  86. txp[RS5C348_REG_DAY] = bin2bcd(tm->tm_mday);
  87. txp[RS5C348_REG_MONTH] = bin2bcd(tm->tm_mon + 1) |
  88. (tm->tm_year >= 100 ? RS5C348_BIT_Y2K : 0);
  89. txp[RS5C348_REG_YEAR] = bin2bcd(tm->tm_year % 100);
  90. /* write in one transfer to avoid data inconsistency */
  91. ret = spi_write_then_read(spi, txbuf, sizeof(txbuf), NULL, 0);
  92. udelay(62); /* Tcsr 62us */
  93. return ret;
  94. }
  95. static int
  96. rs5c348_rtc_read_time(struct device *dev, struct rtc_time *tm)
  97. {
  98. struct spi_device *spi = to_spi_device(dev);
  99. struct rs5c348_plat_data *pdata = dev_get_platdata(&spi->dev);
  100. u8 txbuf[5], rxbuf[7];
  101. int ret;
  102. ret = spi_w8r8(spi, RS5C348_CMD_R(RS5C348_REG_CTL2));
  103. if (ret < 0)
  104. return ret;
  105. if (ret & RS5C348_BIT_VDET)
  106. dev_warn(&spi->dev, "voltage-low detected.\n");
  107. if (ret & RS5C348_BIT_XSTP) {
  108. dev_warn(&spi->dev, "oscillator-stop detected.\n");
  109. return -EINVAL;
  110. }
  111. /* Transfer 5 byte befores reading SEC. This gives 31us for carry. */
  112. txbuf[0] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */
  113. txbuf[1] = 0; /* dummy */
  114. txbuf[2] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */
  115. txbuf[3] = 0; /* dummy */
  116. txbuf[4] = RS5C348_CMD_MR(RS5C348_REG_SECS); /* cmd, sec, ... */
  117. /* read in one transfer to avoid data inconsistency */
  118. ret = spi_write_then_read(spi, txbuf, sizeof(txbuf),
  119. rxbuf, sizeof(rxbuf));
  120. udelay(62); /* Tcsr 62us */
  121. if (ret < 0)
  122. return ret;
  123. tm->tm_sec = bcd2bin(rxbuf[RS5C348_REG_SECS] & RS5C348_SECS_MASK);
  124. tm->tm_min = bcd2bin(rxbuf[RS5C348_REG_MINS] & RS5C348_MINS_MASK);
  125. tm->tm_hour = bcd2bin(rxbuf[RS5C348_REG_HOURS] & RS5C348_HOURS_MASK);
  126. if (!pdata->rtc_24h) {
  127. if (rxbuf[RS5C348_REG_HOURS] & RS5C348_BIT_PM) {
  128. tm->tm_hour -= 20;
  129. tm->tm_hour %= 12;
  130. tm->tm_hour += 12;
  131. } else
  132. tm->tm_hour %= 12;
  133. }
  134. tm->tm_wday = bcd2bin(rxbuf[RS5C348_REG_WDAY] & RS5C348_WDAY_MASK);
  135. tm->tm_mday = bcd2bin(rxbuf[RS5C348_REG_DAY] & RS5C348_DAY_MASK);
  136. tm->tm_mon =
  137. bcd2bin(rxbuf[RS5C348_REG_MONTH] & RS5C348_MONTH_MASK) - 1;
  138. /* year is 1900 + tm->tm_year */
  139. tm->tm_year = bcd2bin(rxbuf[RS5C348_REG_YEAR]) +
  140. ((rxbuf[RS5C348_REG_MONTH] & RS5C348_BIT_Y2K) ? 100 : 0);
  141. return 0;
  142. }
  143. static const struct rtc_class_ops rs5c348_rtc_ops = {
  144. .read_time = rs5c348_rtc_read_time,
  145. .set_time = rs5c348_rtc_set_time,
  146. };
  147. static int rs5c348_probe(struct spi_device *spi)
  148. {
  149. int ret;
  150. struct rtc_device *rtc;
  151. struct rs5c348_plat_data *pdata;
  152. pdata = devm_kzalloc(&spi->dev, sizeof(struct rs5c348_plat_data),
  153. GFP_KERNEL);
  154. if (!pdata)
  155. return -ENOMEM;
  156. spi->dev.platform_data = pdata;
  157. /* Check D7 of SECOND register */
  158. ret = spi_w8r8(spi, RS5C348_CMD_R(RS5C348_REG_SECS));
  159. if (ret < 0 || (ret & 0x80)) {
  160. dev_err(&spi->dev, "not found.\n");
  161. return ret;
  162. }
  163. dev_info(&spi->dev, "spiclk %u KHz.\n",
  164. (spi->max_speed_hz + 500) / 1000);
  165. ret = spi_w8r8(spi, RS5C348_CMD_R(RS5C348_REG_CTL1));
  166. if (ret < 0)
  167. return ret;
  168. if (ret & RS5C348_BIT_24H)
  169. pdata->rtc_24h = 1;
  170. rtc = devm_rtc_allocate_device(&spi->dev);
  171. if (IS_ERR(rtc))
  172. return PTR_ERR(rtc);
  173. pdata->rtc = rtc;
  174. rtc->ops = &rs5c348_rtc_ops;
  175. return devm_rtc_register_device(rtc);
  176. }
  177. static struct spi_driver rs5c348_driver = {
  178. .driver = {
  179. .name = "rtc-rs5c348",
  180. },
  181. .probe = rs5c348_probe,
  182. };
  183. module_spi_driver(rs5c348_driver);
  184. MODULE_AUTHOR("Atsushi Nemoto <[email protected]>");
  185. MODULE_DESCRIPTION("Ricoh RS5C348 RTC driver");
  186. MODULE_LICENSE("GPL");
  187. MODULE_ALIAS("spi:rtc-rs5c348");