rtc-mxc_v2.c 9.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Real Time Clock (RTC) Driver for i.MX53
  4. * Copyright (c) 2004-2011 Freescale Semiconductor, Inc.
  5. * Copyright (c) 2017 Beckhoff Automation GmbH & Co. KG
  6. */
  7. #include <linux/clk.h>
  8. #include <linux/io.h>
  9. #include <linux/module.h>
  10. #include <linux/mod_devicetable.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/pm_wakeirq.h>
  13. #include <linux/rtc.h>
  14. #define SRTC_LPPDR_INIT 0x41736166 /* init for glitch detect */
  15. #define SRTC_LPCR_EN_LP BIT(3) /* lp enable */
  16. #define SRTC_LPCR_WAE BIT(4) /* lp wakeup alarm enable */
  17. #define SRTC_LPCR_ALP BIT(7) /* lp alarm flag */
  18. #define SRTC_LPCR_NSA BIT(11) /* lp non secure access */
  19. #define SRTC_LPCR_NVE BIT(14) /* lp non valid state exit bit */
  20. #define SRTC_LPCR_IE BIT(15) /* lp init state exit bit */
  21. #define SRTC_LPSR_ALP BIT(3) /* lp alarm flag */
  22. #define SRTC_LPSR_NVES BIT(14) /* lp non-valid state exit status */
  23. #define SRTC_LPSR_IES BIT(15) /* lp init state exit status */
  24. #define SRTC_LPSCMR 0x00 /* LP Secure Counter MSB Reg */
  25. #define SRTC_LPSCLR 0x04 /* LP Secure Counter LSB Reg */
  26. #define SRTC_LPSAR 0x08 /* LP Secure Alarm Reg */
  27. #define SRTC_LPCR 0x10 /* LP Control Reg */
  28. #define SRTC_LPSR 0x14 /* LP Status Reg */
  29. #define SRTC_LPPDR 0x18 /* LP Power Supply Glitch Detector Reg */
  30. /* max. number of retries to read registers, 120 was max during test */
  31. #define REG_READ_TIMEOUT 2000
  32. struct mxc_rtc_data {
  33. struct rtc_device *rtc;
  34. void __iomem *ioaddr;
  35. struct clk *clk;
  36. spinlock_t lock; /* protects register access */
  37. int irq;
  38. };
  39. /*
  40. * This function does write synchronization for writes to the lp srtc block.
  41. * To take care of the asynchronous CKIL clock, all writes from the IP domain
  42. * will be synchronized to the CKIL domain.
  43. * The caller should hold the pdata->lock
  44. */
  45. static void mxc_rtc_sync_lp_locked(struct device *dev, void __iomem *ioaddr)
  46. {
  47. unsigned int i;
  48. /* Wait for 3 CKIL cycles */
  49. for (i = 0; i < 3; i++) {
  50. const u32 count = readl(ioaddr + SRTC_LPSCLR);
  51. unsigned int timeout = REG_READ_TIMEOUT;
  52. while ((readl(ioaddr + SRTC_LPSCLR)) == count) {
  53. if (!--timeout) {
  54. dev_err_once(dev, "SRTC_LPSCLR stuck! Check your hw.\n");
  55. return;
  56. }
  57. }
  58. }
  59. }
  60. /* This function is the RTC interrupt service routine. */
  61. static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id)
  62. {
  63. struct device *dev = dev_id;
  64. struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
  65. void __iomem *ioaddr = pdata->ioaddr;
  66. u32 lp_status;
  67. u32 lp_cr;
  68. spin_lock(&pdata->lock);
  69. if (clk_enable(pdata->clk)) {
  70. spin_unlock(&pdata->lock);
  71. return IRQ_NONE;
  72. }
  73. lp_status = readl(ioaddr + SRTC_LPSR);
  74. lp_cr = readl(ioaddr + SRTC_LPCR);
  75. /* update irq data & counter */
  76. if (lp_status & SRTC_LPSR_ALP) {
  77. if (lp_cr & SRTC_LPCR_ALP)
  78. rtc_update_irq(pdata->rtc, 1, RTC_AF | RTC_IRQF);
  79. /* disable further lp alarm interrupts */
  80. lp_cr &= ~(SRTC_LPCR_ALP | SRTC_LPCR_WAE);
  81. }
  82. /* Update interrupt enables */
  83. writel(lp_cr, ioaddr + SRTC_LPCR);
  84. /* clear interrupt status */
  85. writel(lp_status, ioaddr + SRTC_LPSR);
  86. mxc_rtc_sync_lp_locked(dev, ioaddr);
  87. clk_disable(pdata->clk);
  88. spin_unlock(&pdata->lock);
  89. return IRQ_HANDLED;
  90. }
  91. /*
  92. * Enable clk and aquire spinlock
  93. * @return 0 if successful; non-zero otherwise.
  94. */
  95. static int mxc_rtc_lock(struct mxc_rtc_data *const pdata)
  96. {
  97. int ret;
  98. spin_lock_irq(&pdata->lock);
  99. ret = clk_enable(pdata->clk);
  100. if (ret) {
  101. spin_unlock_irq(&pdata->lock);
  102. return ret;
  103. }
  104. return 0;
  105. }
  106. static int mxc_rtc_unlock(struct mxc_rtc_data *const pdata)
  107. {
  108. clk_disable(pdata->clk);
  109. spin_unlock_irq(&pdata->lock);
  110. return 0;
  111. }
  112. /*
  113. * This function reads the current RTC time into tm in Gregorian date.
  114. *
  115. * @param tm contains the RTC time value upon return
  116. *
  117. * @return 0 if successful; non-zero otherwise.
  118. */
  119. static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm)
  120. {
  121. struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
  122. const int clk_failed = clk_enable(pdata->clk);
  123. if (!clk_failed) {
  124. const time64_t now = readl(pdata->ioaddr + SRTC_LPSCMR);
  125. rtc_time64_to_tm(now, tm);
  126. clk_disable(pdata->clk);
  127. return 0;
  128. }
  129. return clk_failed;
  130. }
  131. /*
  132. * This function sets the internal RTC time based on tm in Gregorian date.
  133. *
  134. * @param tm the time value to be set in the RTC
  135. *
  136. * @return 0 if successful; non-zero otherwise.
  137. */
  138. static int mxc_rtc_set_time(struct device *dev, struct rtc_time *tm)
  139. {
  140. struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
  141. time64_t time = rtc_tm_to_time64(tm);
  142. int ret;
  143. ret = mxc_rtc_lock(pdata);
  144. if (ret)
  145. return ret;
  146. writel(time, pdata->ioaddr + SRTC_LPSCMR);
  147. mxc_rtc_sync_lp_locked(dev, pdata->ioaddr);
  148. return mxc_rtc_unlock(pdata);
  149. }
  150. /*
  151. * This function reads the current alarm value into the passed in \b alrm
  152. * argument. It updates the \b alrm's pending field value based on the whether
  153. * an alarm interrupt occurs or not.
  154. *
  155. * @param alrm contains the RTC alarm value upon return
  156. *
  157. * @return 0 if successful; non-zero otherwise.
  158. */
  159. static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  160. {
  161. struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
  162. void __iomem *ioaddr = pdata->ioaddr;
  163. int ret;
  164. ret = mxc_rtc_lock(pdata);
  165. if (ret)
  166. return ret;
  167. rtc_time64_to_tm(readl(ioaddr + SRTC_LPSAR), &alrm->time);
  168. alrm->pending = !!(readl(ioaddr + SRTC_LPSR) & SRTC_LPSR_ALP);
  169. return mxc_rtc_unlock(pdata);
  170. }
  171. /*
  172. * Enable/Disable alarm interrupt
  173. * The caller should hold the pdata->lock
  174. */
  175. static void mxc_rtc_alarm_irq_enable_locked(struct mxc_rtc_data *pdata,
  176. unsigned int enable)
  177. {
  178. u32 lp_cr = readl(pdata->ioaddr + SRTC_LPCR);
  179. if (enable)
  180. lp_cr |= (SRTC_LPCR_ALP | SRTC_LPCR_WAE);
  181. else
  182. lp_cr &= ~(SRTC_LPCR_ALP | SRTC_LPCR_WAE);
  183. writel(lp_cr, pdata->ioaddr + SRTC_LPCR);
  184. }
  185. static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
  186. {
  187. struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
  188. int ret = mxc_rtc_lock(pdata);
  189. if (ret)
  190. return ret;
  191. mxc_rtc_alarm_irq_enable_locked(pdata, enable);
  192. return mxc_rtc_unlock(pdata);
  193. }
  194. /*
  195. * This function sets the RTC alarm based on passed in alrm.
  196. *
  197. * @param alrm the alarm value to be set in the RTC
  198. *
  199. * @return 0 if successful; non-zero otherwise.
  200. */
  201. static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  202. {
  203. const time64_t time = rtc_tm_to_time64(&alrm->time);
  204. struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
  205. int ret = mxc_rtc_lock(pdata);
  206. if (ret)
  207. return ret;
  208. writel((u32)time, pdata->ioaddr + SRTC_LPSAR);
  209. /* clear alarm interrupt status bit */
  210. writel(SRTC_LPSR_ALP, pdata->ioaddr + SRTC_LPSR);
  211. mxc_rtc_sync_lp_locked(dev, pdata->ioaddr);
  212. mxc_rtc_alarm_irq_enable_locked(pdata, alrm->enabled);
  213. mxc_rtc_sync_lp_locked(dev, pdata->ioaddr);
  214. mxc_rtc_unlock(pdata);
  215. return ret;
  216. }
  217. static const struct rtc_class_ops mxc_rtc_ops = {
  218. .read_time = mxc_rtc_read_time,
  219. .set_time = mxc_rtc_set_time,
  220. .read_alarm = mxc_rtc_read_alarm,
  221. .set_alarm = mxc_rtc_set_alarm,
  222. .alarm_irq_enable = mxc_rtc_alarm_irq_enable,
  223. };
  224. static int mxc_rtc_wait_for_flag(void __iomem *ioaddr, int flag)
  225. {
  226. unsigned int timeout = REG_READ_TIMEOUT;
  227. while (!(readl(ioaddr) & flag)) {
  228. if (!--timeout)
  229. return -EBUSY;
  230. }
  231. return 0;
  232. }
  233. static int mxc_rtc_probe(struct platform_device *pdev)
  234. {
  235. struct mxc_rtc_data *pdata;
  236. void __iomem *ioaddr;
  237. int ret = 0;
  238. pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
  239. if (!pdata)
  240. return -ENOMEM;
  241. pdata->ioaddr = devm_platform_ioremap_resource(pdev, 0);
  242. if (IS_ERR(pdata->ioaddr))
  243. return PTR_ERR(pdata->ioaddr);
  244. ioaddr = pdata->ioaddr;
  245. pdata->clk = devm_clk_get(&pdev->dev, NULL);
  246. if (IS_ERR(pdata->clk)) {
  247. dev_err(&pdev->dev, "unable to get rtc clock!\n");
  248. return PTR_ERR(pdata->clk);
  249. }
  250. spin_lock_init(&pdata->lock);
  251. pdata->irq = platform_get_irq(pdev, 0);
  252. if (pdata->irq < 0)
  253. return pdata->irq;
  254. device_init_wakeup(&pdev->dev, 1);
  255. ret = dev_pm_set_wake_irq(&pdev->dev, pdata->irq);
  256. if (ret)
  257. dev_err(&pdev->dev, "failed to enable irq wake\n");
  258. ret = clk_prepare_enable(pdata->clk);
  259. if (ret)
  260. return ret;
  261. /* initialize glitch detect */
  262. writel(SRTC_LPPDR_INIT, ioaddr + SRTC_LPPDR);
  263. /* clear lp interrupt status */
  264. writel(0xFFFFFFFF, ioaddr + SRTC_LPSR);
  265. /* move out of init state */
  266. writel((SRTC_LPCR_IE | SRTC_LPCR_NSA), ioaddr + SRTC_LPCR);
  267. ret = mxc_rtc_wait_for_flag(ioaddr + SRTC_LPSR, SRTC_LPSR_IES);
  268. if (ret) {
  269. dev_err(&pdev->dev, "Timeout waiting for SRTC_LPSR_IES\n");
  270. clk_disable_unprepare(pdata->clk);
  271. return ret;
  272. }
  273. /* move out of non-valid state */
  274. writel((SRTC_LPCR_IE | SRTC_LPCR_NVE | SRTC_LPCR_NSA |
  275. SRTC_LPCR_EN_LP), ioaddr + SRTC_LPCR);
  276. ret = mxc_rtc_wait_for_flag(ioaddr + SRTC_LPSR, SRTC_LPSR_NVES);
  277. if (ret) {
  278. dev_err(&pdev->dev, "Timeout waiting for SRTC_LPSR_NVES\n");
  279. clk_disable_unprepare(pdata->clk);
  280. return ret;
  281. }
  282. pdata->rtc = devm_rtc_allocate_device(&pdev->dev);
  283. if (IS_ERR(pdata->rtc)) {
  284. clk_disable_unprepare(pdata->clk);
  285. return PTR_ERR(pdata->rtc);
  286. }
  287. pdata->rtc->ops = &mxc_rtc_ops;
  288. pdata->rtc->range_max = U32_MAX;
  289. clk_disable(pdata->clk);
  290. platform_set_drvdata(pdev, pdata);
  291. ret =
  292. devm_request_irq(&pdev->dev, pdata->irq, mxc_rtc_interrupt, 0,
  293. pdev->name, &pdev->dev);
  294. if (ret < 0) {
  295. dev_err(&pdev->dev, "interrupt not available.\n");
  296. clk_unprepare(pdata->clk);
  297. return ret;
  298. }
  299. ret = devm_rtc_register_device(pdata->rtc);
  300. if (ret < 0)
  301. clk_unprepare(pdata->clk);
  302. return ret;
  303. }
  304. static int mxc_rtc_remove(struct platform_device *pdev)
  305. {
  306. struct mxc_rtc_data *pdata = platform_get_drvdata(pdev);
  307. clk_disable_unprepare(pdata->clk);
  308. return 0;
  309. }
  310. static const struct of_device_id mxc_ids[] = {
  311. { .compatible = "fsl,imx53-rtc", },
  312. {}
  313. };
  314. MODULE_DEVICE_TABLE(of, mxc_ids);
  315. static struct platform_driver mxc_rtc_driver = {
  316. .driver = {
  317. .name = "mxc_rtc_v2",
  318. .of_match_table = mxc_ids,
  319. },
  320. .probe = mxc_rtc_probe,
  321. .remove = mxc_rtc_remove,
  322. };
  323. module_platform_driver(mxc_rtc_driver);
  324. MODULE_AUTHOR("Freescale Semiconductor, Inc.");
  325. MODULE_DESCRIPTION("Real Time Clock (RTC) Driver for i.MX53");
  326. MODULE_LICENSE("GPL");