rtc-mt7622.c 9.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Driver for MediaTek SoC based RTC
  4. *
  5. * Copyright (C) 2017 Sean Wang <[email protected]>
  6. */
  7. #include <linux/clk.h>
  8. #include <linux/interrupt.h>
  9. #include <linux/module.h>
  10. #include <linux/of_address.h>
  11. #include <linux/of_device.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/rtc.h>
  14. #define MTK_RTC_DEV KBUILD_MODNAME
  15. #define MTK_RTC_PWRCHK1 0x4
  16. #define RTC_PWRCHK1_MAGIC 0xc6
  17. #define MTK_RTC_PWRCHK2 0x8
  18. #define RTC_PWRCHK2_MAGIC 0x9a
  19. #define MTK_RTC_KEY 0xc
  20. #define RTC_KEY_MAGIC 0x59
  21. #define MTK_RTC_PROT1 0x10
  22. #define RTC_PROT1_MAGIC 0xa3
  23. #define MTK_RTC_PROT2 0x14
  24. #define RTC_PROT2_MAGIC 0x57
  25. #define MTK_RTC_PROT3 0x18
  26. #define RTC_PROT3_MAGIC 0x67
  27. #define MTK_RTC_PROT4 0x1c
  28. #define RTC_PROT4_MAGIC 0xd2
  29. #define MTK_RTC_CTL 0x20
  30. #define RTC_RC_STOP BIT(0)
  31. #define MTK_RTC_DEBNCE 0x2c
  32. #define RTC_DEBNCE_MASK GENMASK(2, 0)
  33. #define MTK_RTC_INT 0x30
  34. #define RTC_INT_AL_STA BIT(4)
  35. /*
  36. * Ranges from 0x40 to 0x78 provide RTC time setup for year, month,
  37. * day of month, day of week, hour, minute and second.
  38. */
  39. #define MTK_RTC_TREG(_t, _f) (0x40 + (0x4 * (_f)) + ((_t) * 0x20))
  40. #define MTK_RTC_AL_CTL 0x7c
  41. #define RTC_AL_EN BIT(0)
  42. #define RTC_AL_ALL GENMASK(7, 0)
  43. /*
  44. * The offset is used in the translation for the year between in struct
  45. * rtc_time and in hardware register MTK_RTC_TREG(x,MTK_YEA)
  46. */
  47. #define MTK_RTC_TM_YR_OFFSET 100
  48. /*
  49. * The lowest value for the valid tm_year. RTC hardware would take incorrectly
  50. * tm_year 100 as not a leap year and thus it is also required being excluded
  51. * from the valid options.
  52. */
  53. #define MTK_RTC_TM_YR_L (MTK_RTC_TM_YR_OFFSET + 1)
  54. /*
  55. * The most year the RTC can hold is 99 and the next to 99 in year register
  56. * would be wraparound to 0, for MT7622.
  57. */
  58. #define MTK_RTC_HW_YR_LIMIT 99
  59. /* The highest value for the valid tm_year */
  60. #define MTK_RTC_TM_YR_H (MTK_RTC_TM_YR_OFFSET + MTK_RTC_HW_YR_LIMIT)
  61. /* Simple macro helps to check whether the hardware supports the tm_year */
  62. #define MTK_RTC_TM_YR_VALID(_y) ((_y) >= MTK_RTC_TM_YR_L && \
  63. (_y) <= MTK_RTC_TM_YR_H)
  64. /* Types of the function the RTC provides are time counter and alarm. */
  65. enum {
  66. MTK_TC,
  67. MTK_AL,
  68. };
  69. /* Indexes are used for the pointer to relevant registers in MTK_RTC_TREG */
  70. enum {
  71. MTK_YEA,
  72. MTK_MON,
  73. MTK_DOM,
  74. MTK_DOW,
  75. MTK_HOU,
  76. MTK_MIN,
  77. MTK_SEC
  78. };
  79. struct mtk_rtc {
  80. struct rtc_device *rtc;
  81. void __iomem *base;
  82. int irq;
  83. struct clk *clk;
  84. };
  85. static void mtk_w32(struct mtk_rtc *rtc, u32 reg, u32 val)
  86. {
  87. writel_relaxed(val, rtc->base + reg);
  88. }
  89. static u32 mtk_r32(struct mtk_rtc *rtc, u32 reg)
  90. {
  91. return readl_relaxed(rtc->base + reg);
  92. }
  93. static void mtk_rmw(struct mtk_rtc *rtc, u32 reg, u32 mask, u32 set)
  94. {
  95. u32 val;
  96. val = mtk_r32(rtc, reg);
  97. val &= ~mask;
  98. val |= set;
  99. mtk_w32(rtc, reg, val);
  100. }
  101. static void mtk_set(struct mtk_rtc *rtc, u32 reg, u32 val)
  102. {
  103. mtk_rmw(rtc, reg, 0, val);
  104. }
  105. static void mtk_clr(struct mtk_rtc *rtc, u32 reg, u32 val)
  106. {
  107. mtk_rmw(rtc, reg, val, 0);
  108. }
  109. static void mtk_rtc_hw_init(struct mtk_rtc *hw)
  110. {
  111. /* The setup of the init sequence is for allowing RTC got to work */
  112. mtk_w32(hw, MTK_RTC_PWRCHK1, RTC_PWRCHK1_MAGIC);
  113. mtk_w32(hw, MTK_RTC_PWRCHK2, RTC_PWRCHK2_MAGIC);
  114. mtk_w32(hw, MTK_RTC_KEY, RTC_KEY_MAGIC);
  115. mtk_w32(hw, MTK_RTC_PROT1, RTC_PROT1_MAGIC);
  116. mtk_w32(hw, MTK_RTC_PROT2, RTC_PROT2_MAGIC);
  117. mtk_w32(hw, MTK_RTC_PROT3, RTC_PROT3_MAGIC);
  118. mtk_w32(hw, MTK_RTC_PROT4, RTC_PROT4_MAGIC);
  119. mtk_rmw(hw, MTK_RTC_DEBNCE, RTC_DEBNCE_MASK, 0);
  120. mtk_clr(hw, MTK_RTC_CTL, RTC_RC_STOP);
  121. }
  122. static void mtk_rtc_get_alarm_or_time(struct mtk_rtc *hw, struct rtc_time *tm,
  123. int time_alarm)
  124. {
  125. u32 year, mon, mday, wday, hour, min, sec;
  126. /*
  127. * Read again until the field of the second is not changed which
  128. * ensures all fields in the consistent state. Note that MTK_SEC must
  129. * be read first. In this way, it guarantees the others remain not
  130. * changed when the results for two MTK_SEC consecutive reads are same.
  131. */
  132. do {
  133. sec = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_SEC));
  134. min = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_MIN));
  135. hour = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_HOU));
  136. wday = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_DOW));
  137. mday = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_DOM));
  138. mon = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_MON));
  139. year = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_YEA));
  140. } while (sec != mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_SEC)));
  141. tm->tm_sec = sec;
  142. tm->tm_min = min;
  143. tm->tm_hour = hour;
  144. tm->tm_wday = wday;
  145. tm->tm_mday = mday;
  146. tm->tm_mon = mon - 1;
  147. /* Rebase to the absolute year which userspace queries */
  148. tm->tm_year = year + MTK_RTC_TM_YR_OFFSET;
  149. }
  150. static void mtk_rtc_set_alarm_or_time(struct mtk_rtc *hw, struct rtc_time *tm,
  151. int time_alarm)
  152. {
  153. u32 year;
  154. /* Rebase to the relative year which RTC hardware requires */
  155. year = tm->tm_year - MTK_RTC_TM_YR_OFFSET;
  156. mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_YEA), year);
  157. mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_MON), tm->tm_mon + 1);
  158. mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_DOW), tm->tm_wday);
  159. mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_DOM), tm->tm_mday);
  160. mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_HOU), tm->tm_hour);
  161. mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_MIN), tm->tm_min);
  162. mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_SEC), tm->tm_sec);
  163. }
  164. static irqreturn_t mtk_rtc_alarmirq(int irq, void *id)
  165. {
  166. struct mtk_rtc *hw = (struct mtk_rtc *)id;
  167. u32 irq_sta;
  168. irq_sta = mtk_r32(hw, MTK_RTC_INT);
  169. if (irq_sta & RTC_INT_AL_STA) {
  170. /* Stop alarm also implicitly disables the alarm interrupt */
  171. mtk_w32(hw, MTK_RTC_AL_CTL, 0);
  172. rtc_update_irq(hw->rtc, 1, RTC_IRQF | RTC_AF);
  173. /* Ack alarm interrupt status */
  174. mtk_w32(hw, MTK_RTC_INT, RTC_INT_AL_STA);
  175. return IRQ_HANDLED;
  176. }
  177. return IRQ_NONE;
  178. }
  179. static int mtk_rtc_gettime(struct device *dev, struct rtc_time *tm)
  180. {
  181. struct mtk_rtc *hw = dev_get_drvdata(dev);
  182. mtk_rtc_get_alarm_or_time(hw, tm, MTK_TC);
  183. return 0;
  184. }
  185. static int mtk_rtc_settime(struct device *dev, struct rtc_time *tm)
  186. {
  187. struct mtk_rtc *hw = dev_get_drvdata(dev);
  188. if (!MTK_RTC_TM_YR_VALID(tm->tm_year))
  189. return -EINVAL;
  190. /* Stop time counter before setting a new one*/
  191. mtk_set(hw, MTK_RTC_CTL, RTC_RC_STOP);
  192. mtk_rtc_set_alarm_or_time(hw, tm, MTK_TC);
  193. /* Restart the time counter */
  194. mtk_clr(hw, MTK_RTC_CTL, RTC_RC_STOP);
  195. return 0;
  196. }
  197. static int mtk_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
  198. {
  199. struct mtk_rtc *hw = dev_get_drvdata(dev);
  200. struct rtc_time *alrm_tm = &wkalrm->time;
  201. mtk_rtc_get_alarm_or_time(hw, alrm_tm, MTK_AL);
  202. wkalrm->enabled = !!(mtk_r32(hw, MTK_RTC_AL_CTL) & RTC_AL_EN);
  203. wkalrm->pending = !!(mtk_r32(hw, MTK_RTC_INT) & RTC_INT_AL_STA);
  204. return 0;
  205. }
  206. static int mtk_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
  207. {
  208. struct mtk_rtc *hw = dev_get_drvdata(dev);
  209. struct rtc_time *alrm_tm = &wkalrm->time;
  210. if (!MTK_RTC_TM_YR_VALID(alrm_tm->tm_year))
  211. return -EINVAL;
  212. /*
  213. * Stop the alarm also implicitly including disables interrupt before
  214. * setting a new one.
  215. */
  216. mtk_clr(hw, MTK_RTC_AL_CTL, RTC_AL_EN);
  217. /*
  218. * Avoid contention between mtk_rtc_setalarm and IRQ handler so that
  219. * disabling the interrupt and awaiting for pending IRQ handler to
  220. * complete.
  221. */
  222. synchronize_irq(hw->irq);
  223. mtk_rtc_set_alarm_or_time(hw, alrm_tm, MTK_AL);
  224. /* Restart the alarm with the new setup */
  225. mtk_w32(hw, MTK_RTC_AL_CTL, RTC_AL_ALL);
  226. return 0;
  227. }
  228. static const struct rtc_class_ops mtk_rtc_ops = {
  229. .read_time = mtk_rtc_gettime,
  230. .set_time = mtk_rtc_settime,
  231. .read_alarm = mtk_rtc_getalarm,
  232. .set_alarm = mtk_rtc_setalarm,
  233. };
  234. static const struct of_device_id mtk_rtc_match[] = {
  235. { .compatible = "mediatek,mt7622-rtc" },
  236. { .compatible = "mediatek,soc-rtc" },
  237. {},
  238. };
  239. MODULE_DEVICE_TABLE(of, mtk_rtc_match);
  240. static int mtk_rtc_probe(struct platform_device *pdev)
  241. {
  242. struct mtk_rtc *hw;
  243. int ret;
  244. hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
  245. if (!hw)
  246. return -ENOMEM;
  247. platform_set_drvdata(pdev, hw);
  248. hw->base = devm_platform_ioremap_resource(pdev, 0);
  249. if (IS_ERR(hw->base))
  250. return PTR_ERR(hw->base);
  251. hw->clk = devm_clk_get(&pdev->dev, "rtc");
  252. if (IS_ERR(hw->clk)) {
  253. dev_err(&pdev->dev, "No clock\n");
  254. return PTR_ERR(hw->clk);
  255. }
  256. ret = clk_prepare_enable(hw->clk);
  257. if (ret)
  258. return ret;
  259. hw->irq = platform_get_irq(pdev, 0);
  260. if (hw->irq < 0) {
  261. ret = hw->irq;
  262. goto err;
  263. }
  264. ret = devm_request_irq(&pdev->dev, hw->irq, mtk_rtc_alarmirq,
  265. 0, dev_name(&pdev->dev), hw);
  266. if (ret) {
  267. dev_err(&pdev->dev, "Can't request IRQ\n");
  268. goto err;
  269. }
  270. mtk_rtc_hw_init(hw);
  271. device_init_wakeup(&pdev->dev, true);
  272. hw->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
  273. &mtk_rtc_ops, THIS_MODULE);
  274. if (IS_ERR(hw->rtc)) {
  275. ret = PTR_ERR(hw->rtc);
  276. dev_err(&pdev->dev, "Unable to register device\n");
  277. goto err;
  278. }
  279. return 0;
  280. err:
  281. clk_disable_unprepare(hw->clk);
  282. return ret;
  283. }
  284. static int mtk_rtc_remove(struct platform_device *pdev)
  285. {
  286. struct mtk_rtc *hw = platform_get_drvdata(pdev);
  287. clk_disable_unprepare(hw->clk);
  288. return 0;
  289. }
  290. #ifdef CONFIG_PM_SLEEP
  291. static int mtk_rtc_suspend(struct device *dev)
  292. {
  293. struct mtk_rtc *hw = dev_get_drvdata(dev);
  294. if (device_may_wakeup(dev))
  295. enable_irq_wake(hw->irq);
  296. return 0;
  297. }
  298. static int mtk_rtc_resume(struct device *dev)
  299. {
  300. struct mtk_rtc *hw = dev_get_drvdata(dev);
  301. if (device_may_wakeup(dev))
  302. disable_irq_wake(hw->irq);
  303. return 0;
  304. }
  305. static SIMPLE_DEV_PM_OPS(mtk_rtc_pm_ops, mtk_rtc_suspend, mtk_rtc_resume);
  306. #define MTK_RTC_PM_OPS (&mtk_rtc_pm_ops)
  307. #else /* CONFIG_PM */
  308. #define MTK_RTC_PM_OPS NULL
  309. #endif /* CONFIG_PM */
  310. static struct platform_driver mtk_rtc_driver = {
  311. .probe = mtk_rtc_probe,
  312. .remove = mtk_rtc_remove,
  313. .driver = {
  314. .name = MTK_RTC_DEV,
  315. .of_match_table = mtk_rtc_match,
  316. .pm = MTK_RTC_PM_OPS,
  317. },
  318. };
  319. module_platform_driver(mtk_rtc_driver);
  320. MODULE_DESCRIPTION("MediaTek SoC based RTC Driver");
  321. MODULE_AUTHOR("Sean Wang <[email protected]>");
  322. MODULE_LICENSE("GPL");