rtc-msc313.c 6.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Real time clocks driver for MStar/SigmaStar ARMv7 SoCs.
  4. * Based on "Real Time Clock driver for msb252x." that was contained
  5. * in various MStar kernels.
  6. *
  7. * (C) 2019 Daniel Palmer
  8. * (C) 2021 Romain Perier
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/delay.h>
  12. #include <linux/io.h>
  13. #include <linux/module.h>
  14. #include <linux/mod_devicetable.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/rtc.h>
  17. /* Registers */
  18. #define REG_RTC_CTRL 0x00
  19. #define REG_RTC_FREQ_CW_L 0x04
  20. #define REG_RTC_FREQ_CW_H 0x08
  21. #define REG_RTC_LOAD_VAL_L 0x0C
  22. #define REG_RTC_LOAD_VAL_H 0x10
  23. #define REG_RTC_MATCH_VAL_L 0x14
  24. #define REG_RTC_MATCH_VAL_H 0x18
  25. #define REG_RTC_STATUS_INT 0x1C
  26. #define REG_RTC_CNT_VAL_L 0x20
  27. #define REG_RTC_CNT_VAL_H 0x24
  28. /* Control bits for REG_RTC_CTRL */
  29. #define SOFT_RSTZ_BIT BIT(0)
  30. #define CNT_EN_BIT BIT(1)
  31. #define WRAP_EN_BIT BIT(2)
  32. #define LOAD_EN_BIT BIT(3)
  33. #define READ_EN_BIT BIT(4)
  34. #define INT_MASK_BIT BIT(5)
  35. #define INT_FORCE_BIT BIT(6)
  36. #define INT_CLEAR_BIT BIT(7)
  37. /* Control bits for REG_RTC_STATUS_INT */
  38. #define RAW_INT_BIT BIT(0)
  39. #define ALM_INT_BIT BIT(1)
  40. struct msc313_rtc {
  41. struct rtc_device *rtc_dev;
  42. void __iomem *rtc_base;
  43. };
  44. static int msc313_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
  45. {
  46. struct msc313_rtc *priv = dev_get_drvdata(dev);
  47. unsigned long seconds;
  48. seconds = readw(priv->rtc_base + REG_RTC_MATCH_VAL_L)
  49. | ((unsigned long)readw(priv->rtc_base + REG_RTC_MATCH_VAL_H) << 16);
  50. rtc_time64_to_tm(seconds, &alarm->time);
  51. if (!(readw(priv->rtc_base + REG_RTC_CTRL) & INT_MASK_BIT))
  52. alarm->enabled = 1;
  53. return 0;
  54. }
  55. static int msc313_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
  56. {
  57. struct msc313_rtc *priv = dev_get_drvdata(dev);
  58. u16 reg;
  59. reg = readw(priv->rtc_base + REG_RTC_CTRL);
  60. if (enabled)
  61. reg &= ~INT_MASK_BIT;
  62. else
  63. reg |= INT_MASK_BIT;
  64. writew(reg, priv->rtc_base + REG_RTC_CTRL);
  65. return 0;
  66. }
  67. static int msc313_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
  68. {
  69. struct msc313_rtc *priv = dev_get_drvdata(dev);
  70. unsigned long seconds;
  71. seconds = rtc_tm_to_time64(&alarm->time);
  72. writew((seconds & 0xFFFF), priv->rtc_base + REG_RTC_MATCH_VAL_L);
  73. writew((seconds >> 16) & 0xFFFF, priv->rtc_base + REG_RTC_MATCH_VAL_H);
  74. msc313_rtc_alarm_irq_enable(dev, alarm->enabled);
  75. return 0;
  76. }
  77. static bool msc313_rtc_get_enabled(struct msc313_rtc *priv)
  78. {
  79. return readw(priv->rtc_base + REG_RTC_CTRL) & CNT_EN_BIT;
  80. }
  81. static void msc313_rtc_set_enabled(struct msc313_rtc *priv)
  82. {
  83. u16 reg;
  84. reg = readw(priv->rtc_base + REG_RTC_CTRL);
  85. reg |= CNT_EN_BIT;
  86. writew(reg, priv->rtc_base + REG_RTC_CTRL);
  87. }
  88. static int msc313_rtc_read_time(struct device *dev, struct rtc_time *tm)
  89. {
  90. struct msc313_rtc *priv = dev_get_drvdata(dev);
  91. u32 seconds;
  92. u16 reg;
  93. if (!msc313_rtc_get_enabled(priv))
  94. return -EINVAL;
  95. reg = readw(priv->rtc_base + REG_RTC_CTRL);
  96. writew(reg | READ_EN_BIT, priv->rtc_base + REG_RTC_CTRL);
  97. /* Wait for HW latch done */
  98. while (readw(priv->rtc_base + REG_RTC_CTRL) & READ_EN_BIT)
  99. udelay(1);
  100. seconds = readw(priv->rtc_base + REG_RTC_CNT_VAL_L)
  101. | ((unsigned long)readw(priv->rtc_base + REG_RTC_CNT_VAL_H) << 16);
  102. rtc_time64_to_tm(seconds, tm);
  103. return 0;
  104. }
  105. static int msc313_rtc_set_time(struct device *dev, struct rtc_time *tm)
  106. {
  107. struct msc313_rtc *priv = dev_get_drvdata(dev);
  108. unsigned long seconds;
  109. u16 reg;
  110. seconds = rtc_tm_to_time64(tm);
  111. writew(seconds & 0xFFFF, priv->rtc_base + REG_RTC_LOAD_VAL_L);
  112. writew((seconds >> 16) & 0xFFFF, priv->rtc_base + REG_RTC_LOAD_VAL_H);
  113. /* Enable load for loading value into internal RTC counter */
  114. reg = readw(priv->rtc_base + REG_RTC_CTRL);
  115. writew(reg | LOAD_EN_BIT, priv->rtc_base + REG_RTC_CTRL);
  116. /* Wait for HW latch done */
  117. while (readw(priv->rtc_base + REG_RTC_CTRL) & LOAD_EN_BIT)
  118. udelay(1);
  119. msc313_rtc_set_enabled(priv);
  120. return 0;
  121. }
  122. static const struct rtc_class_ops msc313_rtc_ops = {
  123. .read_time = msc313_rtc_read_time,
  124. .set_time = msc313_rtc_set_time,
  125. .read_alarm = msc313_rtc_read_alarm,
  126. .set_alarm = msc313_rtc_set_alarm,
  127. .alarm_irq_enable = msc313_rtc_alarm_irq_enable,
  128. };
  129. static irqreturn_t msc313_rtc_interrupt(s32 irq, void *dev_id)
  130. {
  131. struct msc313_rtc *priv = dev_get_drvdata(dev_id);
  132. u16 reg;
  133. reg = readw(priv->rtc_base + REG_RTC_STATUS_INT);
  134. if (!(reg & ALM_INT_BIT))
  135. return IRQ_NONE;
  136. reg = readw(priv->rtc_base + REG_RTC_CTRL);
  137. reg |= INT_CLEAR_BIT;
  138. reg &= ~INT_FORCE_BIT;
  139. writew(reg, priv->rtc_base + REG_RTC_CTRL);
  140. rtc_update_irq(priv->rtc_dev, 1, RTC_IRQF | RTC_AF);
  141. return IRQ_HANDLED;
  142. }
  143. static int msc313_rtc_probe(struct platform_device *pdev)
  144. {
  145. struct device *dev = &pdev->dev;
  146. struct msc313_rtc *priv;
  147. unsigned long rate;
  148. struct clk *clk;
  149. int ret;
  150. int irq;
  151. priv = devm_kzalloc(&pdev->dev, sizeof(struct msc313_rtc), GFP_KERNEL);
  152. if (!priv)
  153. return -ENOMEM;
  154. priv->rtc_base = devm_platform_ioremap_resource(pdev, 0);
  155. if (IS_ERR(priv->rtc_base))
  156. return PTR_ERR(priv->rtc_base);
  157. irq = platform_get_irq(pdev, 0);
  158. if (irq < 0)
  159. return -EINVAL;
  160. priv->rtc_dev = devm_rtc_allocate_device(dev);
  161. if (IS_ERR(priv->rtc_dev))
  162. return PTR_ERR(priv->rtc_dev);
  163. priv->rtc_dev->ops = &msc313_rtc_ops;
  164. priv->rtc_dev->range_max = U32_MAX;
  165. ret = devm_request_irq(dev, irq, msc313_rtc_interrupt, IRQF_SHARED,
  166. dev_name(&pdev->dev), &pdev->dev);
  167. if (ret) {
  168. dev_err(dev, "Could not request IRQ\n");
  169. return ret;
  170. }
  171. clk = devm_clk_get_enabled(dev, NULL);
  172. if (IS_ERR(clk)) {
  173. dev_err(dev, "No input reference clock\n");
  174. return PTR_ERR(clk);
  175. }
  176. rate = clk_get_rate(clk);
  177. writew(rate & 0xFFFF, priv->rtc_base + REG_RTC_FREQ_CW_L);
  178. writew((rate >> 16) & 0xFFFF, priv->rtc_base + REG_RTC_FREQ_CW_H);
  179. platform_set_drvdata(pdev, priv);
  180. return devm_rtc_register_device(priv->rtc_dev);
  181. }
  182. static const struct of_device_id msc313_rtc_of_match_table[] = {
  183. { .compatible = "mstar,msc313-rtc" },
  184. { }
  185. };
  186. MODULE_DEVICE_TABLE(of, msc313_rtc_of_match_table);
  187. static struct platform_driver msc313_rtc_driver = {
  188. .probe = msc313_rtc_probe,
  189. .driver = {
  190. .name = "msc313-rtc",
  191. .of_match_table = msc313_rtc_of_match_table,
  192. },
  193. };
  194. module_platform_driver(msc313_rtc_driver);
  195. MODULE_AUTHOR("Daniel Palmer <[email protected]>");
  196. MODULE_AUTHOR("Romain Perier <[email protected]>");
  197. MODULE_DESCRIPTION("MStar RTC Driver");
  198. MODULE_LICENSE("GPL v2");