pwm-keembay.c 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Intel Keem Bay PWM driver
  4. *
  5. * Copyright (C) 2020 Intel Corporation
  6. * Authors: Lai Poey Seng <[email protected]>
  7. * Vineetha G. Jaya Kumaran <[email protected]>
  8. *
  9. * Limitations:
  10. * - Upon disabling a channel, the currently running
  11. * period will not be completed. However, upon
  12. * reconfiguration of the duty cycle/period, the
  13. * currently running period will be completed first.
  14. */
  15. #include <linux/bitfield.h>
  16. #include <linux/clk.h>
  17. #include <linux/io.h>
  18. #include <linux/mod_devicetable.h>
  19. #include <linux/module.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/pwm.h>
  22. #include <linux/regmap.h>
  23. #define KMB_TOTAL_PWM_CHANNELS 6
  24. #define KMB_PWM_COUNT_MAX U16_MAX
  25. #define KMB_PWM_EN_BIT BIT(31)
  26. /* Mask */
  27. #define KMB_PWM_HIGH_MASK GENMASK(31, 16)
  28. #define KMB_PWM_LOW_MASK GENMASK(15, 0)
  29. #define KMB_PWM_LEADIN_MASK GENMASK(30, 0)
  30. /* PWM Register offset */
  31. #define KMB_PWM_LEADIN_OFFSET(ch) (0x00 + 4 * (ch))
  32. #define KMB_PWM_HIGHLOW_OFFSET(ch) (0x20 + 4 * (ch))
  33. struct keembay_pwm {
  34. struct pwm_chip chip;
  35. struct device *dev;
  36. struct clk *clk;
  37. void __iomem *base;
  38. };
  39. static inline struct keembay_pwm *to_keembay_pwm_dev(struct pwm_chip *chip)
  40. {
  41. return container_of(chip, struct keembay_pwm, chip);
  42. }
  43. static void keembay_clk_unprepare(void *data)
  44. {
  45. clk_disable_unprepare(data);
  46. }
  47. static int keembay_clk_enable(struct device *dev, struct clk *clk)
  48. {
  49. int ret;
  50. ret = clk_prepare_enable(clk);
  51. if (ret)
  52. return ret;
  53. return devm_add_action_or_reset(dev, keembay_clk_unprepare, clk);
  54. }
  55. /*
  56. * With gcc 10, CONFIG_CC_OPTIMIZE_FOR_SIZE and only "inline" instead of
  57. * "__always_inline" this fails to compile because the compiler doesn't notice
  58. * for all valid masks (e.g. KMB_PWM_LEADIN_MASK) that they are ok.
  59. */
  60. static __always_inline void keembay_pwm_update_bits(struct keembay_pwm *priv, u32 mask,
  61. u32 val, u32 offset)
  62. {
  63. u32 buff = readl(priv->base + offset);
  64. buff = u32_replace_bits(buff, val, mask);
  65. writel(buff, priv->base + offset);
  66. }
  67. static void keembay_pwm_enable(struct keembay_pwm *priv, int ch)
  68. {
  69. keembay_pwm_update_bits(priv, KMB_PWM_EN_BIT, 1,
  70. KMB_PWM_LEADIN_OFFSET(ch));
  71. }
  72. static void keembay_pwm_disable(struct keembay_pwm *priv, int ch)
  73. {
  74. keembay_pwm_update_bits(priv, KMB_PWM_EN_BIT, 0,
  75. KMB_PWM_LEADIN_OFFSET(ch));
  76. }
  77. static int keembay_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
  78. struct pwm_state *state)
  79. {
  80. struct keembay_pwm *priv = to_keembay_pwm_dev(chip);
  81. unsigned long long high, low;
  82. unsigned long clk_rate;
  83. u32 highlow;
  84. clk_rate = clk_get_rate(priv->clk);
  85. /* Read channel enabled status */
  86. highlow = readl(priv->base + KMB_PWM_LEADIN_OFFSET(pwm->hwpwm));
  87. if (highlow & KMB_PWM_EN_BIT)
  88. state->enabled = true;
  89. else
  90. state->enabled = false;
  91. /* Read period and duty cycle */
  92. highlow = readl(priv->base + KMB_PWM_HIGHLOW_OFFSET(pwm->hwpwm));
  93. low = FIELD_GET(KMB_PWM_LOW_MASK, highlow) * NSEC_PER_SEC;
  94. high = FIELD_GET(KMB_PWM_HIGH_MASK, highlow) * NSEC_PER_SEC;
  95. state->duty_cycle = DIV_ROUND_UP_ULL(high, clk_rate);
  96. state->period = DIV_ROUND_UP_ULL(high + low, clk_rate);
  97. state->polarity = PWM_POLARITY_NORMAL;
  98. return 0;
  99. }
  100. static int keembay_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
  101. const struct pwm_state *state)
  102. {
  103. struct keembay_pwm *priv = to_keembay_pwm_dev(chip);
  104. struct pwm_state current_state;
  105. unsigned long long div;
  106. unsigned long clk_rate;
  107. u32 pwm_count = 0;
  108. u16 high, low;
  109. if (state->polarity != PWM_POLARITY_NORMAL)
  110. return -EINVAL;
  111. /*
  112. * Configure the pwm repeat count as infinite at (15:0) and leadin
  113. * low time as 0 at (30:16), which is in terms of clock cycles.
  114. */
  115. keembay_pwm_update_bits(priv, KMB_PWM_LEADIN_MASK, 0,
  116. KMB_PWM_LEADIN_OFFSET(pwm->hwpwm));
  117. keembay_pwm_get_state(chip, pwm, &current_state);
  118. if (!state->enabled) {
  119. if (current_state.enabled)
  120. keembay_pwm_disable(priv, pwm->hwpwm);
  121. return 0;
  122. }
  123. /*
  124. * The upper 16 bits and lower 16 bits of the KMB_PWM_HIGHLOW_OFFSET
  125. * register contain the high time and low time of waveform accordingly.
  126. * All the values are in terms of clock cycles.
  127. */
  128. clk_rate = clk_get_rate(priv->clk);
  129. div = clk_rate * state->duty_cycle;
  130. div = DIV_ROUND_DOWN_ULL(div, NSEC_PER_SEC);
  131. if (div > KMB_PWM_COUNT_MAX)
  132. return -ERANGE;
  133. high = div;
  134. div = clk_rate * state->period;
  135. div = DIV_ROUND_DOWN_ULL(div, NSEC_PER_SEC);
  136. div = div - high;
  137. if (div > KMB_PWM_COUNT_MAX)
  138. return -ERANGE;
  139. low = div;
  140. pwm_count = FIELD_PREP(KMB_PWM_HIGH_MASK, high) |
  141. FIELD_PREP(KMB_PWM_LOW_MASK, low);
  142. writel(pwm_count, priv->base + KMB_PWM_HIGHLOW_OFFSET(pwm->hwpwm));
  143. if (state->enabled && !current_state.enabled)
  144. keembay_pwm_enable(priv, pwm->hwpwm);
  145. return 0;
  146. }
  147. static const struct pwm_ops keembay_pwm_ops = {
  148. .owner = THIS_MODULE,
  149. .apply = keembay_pwm_apply,
  150. .get_state = keembay_pwm_get_state,
  151. };
  152. static int keembay_pwm_probe(struct platform_device *pdev)
  153. {
  154. struct device *dev = &pdev->dev;
  155. struct keembay_pwm *priv;
  156. int ret;
  157. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  158. if (!priv)
  159. return -ENOMEM;
  160. priv->clk = devm_clk_get(dev, NULL);
  161. if (IS_ERR(priv->clk))
  162. return dev_err_probe(dev, PTR_ERR(priv->clk), "Failed to get clock\n");
  163. priv->base = devm_platform_ioremap_resource(pdev, 0);
  164. if (IS_ERR(priv->base))
  165. return PTR_ERR(priv->base);
  166. ret = keembay_clk_enable(dev, priv->clk);
  167. if (ret)
  168. return ret;
  169. priv->chip.dev = dev;
  170. priv->chip.ops = &keembay_pwm_ops;
  171. priv->chip.npwm = KMB_TOTAL_PWM_CHANNELS;
  172. ret = devm_pwmchip_add(dev, &priv->chip);
  173. if (ret)
  174. return dev_err_probe(dev, ret, "Failed to add PWM chip\n");
  175. return 0;
  176. }
  177. static const struct of_device_id keembay_pwm_of_match[] = {
  178. { .compatible = "intel,keembay-pwm" },
  179. { }
  180. };
  181. MODULE_DEVICE_TABLE(of, keembay_pwm_of_match);
  182. static struct platform_driver keembay_pwm_driver = {
  183. .probe = keembay_pwm_probe,
  184. .driver = {
  185. .name = "pwm-keembay",
  186. .of_match_table = keembay_pwm_of_match,
  187. },
  188. };
  189. module_platform_driver(keembay_pwm_driver);
  190. MODULE_ALIAS("platform:pwm-keembay");
  191. MODULE_DESCRIPTION("Intel Keem Bay PWM driver");
  192. MODULE_LICENSE("GPL v2");