pwm-hibvt.c 7.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * PWM Controller Driver for HiSilicon BVT SoCs
  4. *
  5. * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
  6. */
  7. #include <linux/bitops.h>
  8. #include <linux/clk.h>
  9. #include <linux/delay.h>
  10. #include <linux/io.h>
  11. #include <linux/module.h>
  12. #include <linux/of_device.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/pwm.h>
  15. #include <linux/reset.h>
  16. #define PWM_CFG0_ADDR(x) (((x) * 0x20) + 0x0)
  17. #define PWM_CFG1_ADDR(x) (((x) * 0x20) + 0x4)
  18. #define PWM_CFG2_ADDR(x) (((x) * 0x20) + 0x8)
  19. #define PWM_CTRL_ADDR(x) (((x) * 0x20) + 0xC)
  20. #define PWM_ENABLE_SHIFT 0
  21. #define PWM_ENABLE_MASK BIT(0)
  22. #define PWM_POLARITY_SHIFT 1
  23. #define PWM_POLARITY_MASK BIT(1)
  24. #define PWM_KEEP_SHIFT 2
  25. #define PWM_KEEP_MASK BIT(2)
  26. #define PWM_PERIOD_MASK GENMASK(31, 0)
  27. #define PWM_DUTY_MASK GENMASK(31, 0)
  28. struct hibvt_pwm_chip {
  29. struct pwm_chip chip;
  30. struct clk *clk;
  31. void __iomem *base;
  32. struct reset_control *rstc;
  33. const struct hibvt_pwm_soc *soc;
  34. };
  35. struct hibvt_pwm_soc {
  36. u32 num_pwms;
  37. bool quirk_force_enable;
  38. };
  39. static const struct hibvt_pwm_soc hi3516cv300_soc_info = {
  40. .num_pwms = 4,
  41. };
  42. static const struct hibvt_pwm_soc hi3519v100_soc_info = {
  43. .num_pwms = 8,
  44. };
  45. static const struct hibvt_pwm_soc hi3559v100_shub_soc_info = {
  46. .num_pwms = 8,
  47. .quirk_force_enable = true,
  48. };
  49. static const struct hibvt_pwm_soc hi3559v100_soc_info = {
  50. .num_pwms = 2,
  51. .quirk_force_enable = true,
  52. };
  53. static inline struct hibvt_pwm_chip *to_hibvt_pwm_chip(struct pwm_chip *chip)
  54. {
  55. return container_of(chip, struct hibvt_pwm_chip, chip);
  56. }
  57. static void hibvt_pwm_set_bits(void __iomem *base, u32 offset,
  58. u32 mask, u32 data)
  59. {
  60. void __iomem *address = base + offset;
  61. u32 value;
  62. value = readl(address);
  63. value &= ~mask;
  64. value |= (data & mask);
  65. writel(value, address);
  66. }
  67. static void hibvt_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
  68. {
  69. struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
  70. hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),
  71. PWM_ENABLE_MASK, 0x1);
  72. }
  73. static void hibvt_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
  74. {
  75. struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
  76. hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),
  77. PWM_ENABLE_MASK, 0x0);
  78. }
  79. static void hibvt_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
  80. int duty_cycle_ns, int period_ns)
  81. {
  82. struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
  83. u32 freq, period, duty;
  84. freq = div_u64(clk_get_rate(hi_pwm_chip->clk), 1000000);
  85. period = div_u64(freq * period_ns, 1000);
  86. duty = div_u64(period * duty_cycle_ns, period_ns);
  87. hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG0_ADDR(pwm->hwpwm),
  88. PWM_PERIOD_MASK, period);
  89. hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG1_ADDR(pwm->hwpwm),
  90. PWM_DUTY_MASK, duty);
  91. }
  92. static void hibvt_pwm_set_polarity(struct pwm_chip *chip,
  93. struct pwm_device *pwm,
  94. enum pwm_polarity polarity)
  95. {
  96. struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
  97. if (polarity == PWM_POLARITY_INVERSED)
  98. hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),
  99. PWM_POLARITY_MASK, (0x1 << PWM_POLARITY_SHIFT));
  100. else
  101. hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),
  102. PWM_POLARITY_MASK, (0x0 << PWM_POLARITY_SHIFT));
  103. }
  104. static int hibvt_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
  105. struct pwm_state *state)
  106. {
  107. struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
  108. void __iomem *base;
  109. u32 freq, value;
  110. freq = div_u64(clk_get_rate(hi_pwm_chip->clk), 1000000);
  111. base = hi_pwm_chip->base;
  112. value = readl(base + PWM_CFG0_ADDR(pwm->hwpwm));
  113. state->period = div_u64(value * 1000, freq);
  114. value = readl(base + PWM_CFG1_ADDR(pwm->hwpwm));
  115. state->duty_cycle = div_u64(value * 1000, freq);
  116. value = readl(base + PWM_CTRL_ADDR(pwm->hwpwm));
  117. state->enabled = (PWM_ENABLE_MASK & value);
  118. state->polarity = (PWM_POLARITY_MASK & value) ? PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL;
  119. return 0;
  120. }
  121. static int hibvt_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
  122. const struct pwm_state *state)
  123. {
  124. struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
  125. if (state->polarity != pwm->state.polarity)
  126. hibvt_pwm_set_polarity(chip, pwm, state->polarity);
  127. if (state->period != pwm->state.period ||
  128. state->duty_cycle != pwm->state.duty_cycle) {
  129. hibvt_pwm_config(chip, pwm, state->duty_cycle, state->period);
  130. /*
  131. * Some implementations require the PWM to be enabled twice
  132. * each time the duty cycle is refreshed.
  133. */
  134. if (hi_pwm_chip->soc->quirk_force_enable && state->enabled)
  135. hibvt_pwm_enable(chip, pwm);
  136. }
  137. if (state->enabled != pwm->state.enabled) {
  138. if (state->enabled)
  139. hibvt_pwm_enable(chip, pwm);
  140. else
  141. hibvt_pwm_disable(chip, pwm);
  142. }
  143. return 0;
  144. }
  145. static const struct pwm_ops hibvt_pwm_ops = {
  146. .get_state = hibvt_pwm_get_state,
  147. .apply = hibvt_pwm_apply,
  148. .owner = THIS_MODULE,
  149. };
  150. static int hibvt_pwm_probe(struct platform_device *pdev)
  151. {
  152. const struct hibvt_pwm_soc *soc =
  153. of_device_get_match_data(&pdev->dev);
  154. struct hibvt_pwm_chip *pwm_chip;
  155. int ret, i;
  156. pwm_chip = devm_kzalloc(&pdev->dev, sizeof(*pwm_chip), GFP_KERNEL);
  157. if (pwm_chip == NULL)
  158. return -ENOMEM;
  159. pwm_chip->clk = devm_clk_get(&pdev->dev, NULL);
  160. if (IS_ERR(pwm_chip->clk)) {
  161. dev_err(&pdev->dev, "getting clock failed with %ld\n",
  162. PTR_ERR(pwm_chip->clk));
  163. return PTR_ERR(pwm_chip->clk);
  164. }
  165. pwm_chip->chip.ops = &hibvt_pwm_ops;
  166. pwm_chip->chip.dev = &pdev->dev;
  167. pwm_chip->chip.npwm = soc->num_pwms;
  168. pwm_chip->soc = soc;
  169. pwm_chip->base = devm_platform_ioremap_resource(pdev, 0);
  170. if (IS_ERR(pwm_chip->base))
  171. return PTR_ERR(pwm_chip->base);
  172. ret = clk_prepare_enable(pwm_chip->clk);
  173. if (ret < 0)
  174. return ret;
  175. pwm_chip->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
  176. if (IS_ERR(pwm_chip->rstc)) {
  177. clk_disable_unprepare(pwm_chip->clk);
  178. return PTR_ERR(pwm_chip->rstc);
  179. }
  180. reset_control_assert(pwm_chip->rstc);
  181. msleep(30);
  182. reset_control_deassert(pwm_chip->rstc);
  183. ret = pwmchip_add(&pwm_chip->chip);
  184. if (ret < 0) {
  185. clk_disable_unprepare(pwm_chip->clk);
  186. return ret;
  187. }
  188. for (i = 0; i < pwm_chip->chip.npwm; i++) {
  189. hibvt_pwm_set_bits(pwm_chip->base, PWM_CTRL_ADDR(i),
  190. PWM_KEEP_MASK, (0x1 << PWM_KEEP_SHIFT));
  191. }
  192. platform_set_drvdata(pdev, pwm_chip);
  193. return 0;
  194. }
  195. static int hibvt_pwm_remove(struct platform_device *pdev)
  196. {
  197. struct hibvt_pwm_chip *pwm_chip;
  198. pwm_chip = platform_get_drvdata(pdev);
  199. pwmchip_remove(&pwm_chip->chip);
  200. reset_control_assert(pwm_chip->rstc);
  201. msleep(30);
  202. reset_control_deassert(pwm_chip->rstc);
  203. clk_disable_unprepare(pwm_chip->clk);
  204. return 0;
  205. }
  206. static const struct of_device_id hibvt_pwm_of_match[] = {
  207. { .compatible = "hisilicon,hi3516cv300-pwm",
  208. .data = &hi3516cv300_soc_info },
  209. { .compatible = "hisilicon,hi3519v100-pwm",
  210. .data = &hi3519v100_soc_info },
  211. { .compatible = "hisilicon,hi3559v100-shub-pwm",
  212. .data = &hi3559v100_shub_soc_info },
  213. { .compatible = "hisilicon,hi3559v100-pwm",
  214. .data = &hi3559v100_soc_info },
  215. { }
  216. };
  217. MODULE_DEVICE_TABLE(of, hibvt_pwm_of_match);
  218. static struct platform_driver hibvt_pwm_driver = {
  219. .driver = {
  220. .name = "hibvt-pwm",
  221. .of_match_table = hibvt_pwm_of_match,
  222. },
  223. .probe = hibvt_pwm_probe,
  224. .remove = hibvt_pwm_remove,
  225. };
  226. module_platform_driver(hibvt_pwm_driver);
  227. MODULE_AUTHOR("Jian Yuan");
  228. MODULE_DESCRIPTION("HiSilicon BVT SoCs PWM driver");
  229. MODULE_LICENSE("GPL");