pwm-brcmstb.c 7.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Broadcom BCM7038 PWM driver
  4. * Author: Florian Fainelli
  5. *
  6. * Copyright (C) 2015 Broadcom Corporation
  7. */
  8. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  9. #include <linux/clk.h>
  10. #include <linux/export.h>
  11. #include <linux/init.h>
  12. #include <linux/io.h>
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/of.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/pwm.h>
  18. #include <linux/spinlock.h>
  19. #define PWM_CTRL 0x00
  20. #define CTRL_START BIT(0)
  21. #define CTRL_OEB BIT(1)
  22. #define CTRL_FORCE_HIGH BIT(2)
  23. #define CTRL_OPENDRAIN BIT(3)
  24. #define CTRL_CHAN_OFFS 4
  25. #define PWM_CTRL2 0x04
  26. #define CTRL2_OUT_SELECT BIT(0)
  27. #define PWM_CH_SIZE 0x8
  28. #define PWM_CWORD_MSB(ch) (0x08 + ((ch) * PWM_CH_SIZE))
  29. #define PWM_CWORD_LSB(ch) (0x0c + ((ch) * PWM_CH_SIZE))
  30. /* Number of bits for the CWORD value */
  31. #define CWORD_BIT_SIZE 16
  32. /*
  33. * Maximum control word value allowed when variable-frequency PWM is used as a
  34. * clock for the constant-frequency PMW.
  35. */
  36. #define CONST_VAR_F_MAX 32768
  37. #define CONST_VAR_F_MIN 1
  38. #define PWM_ON(ch) (0x18 + ((ch) * PWM_CH_SIZE))
  39. #define PWM_ON_MIN 1
  40. #define PWM_PERIOD(ch) (0x1c + ((ch) * PWM_CH_SIZE))
  41. #define PWM_PERIOD_MIN 0
  42. #define PWM_ON_PERIOD_MAX 0xff
  43. struct brcmstb_pwm {
  44. void __iomem *base;
  45. struct clk *clk;
  46. struct pwm_chip chip;
  47. };
  48. static inline u32 brcmstb_pwm_readl(struct brcmstb_pwm *p,
  49. unsigned int offset)
  50. {
  51. if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
  52. return __raw_readl(p->base + offset);
  53. else
  54. return readl_relaxed(p->base + offset);
  55. }
  56. static inline void brcmstb_pwm_writel(struct brcmstb_pwm *p, u32 value,
  57. unsigned int offset)
  58. {
  59. if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
  60. __raw_writel(value, p->base + offset);
  61. else
  62. writel_relaxed(value, p->base + offset);
  63. }
  64. static inline struct brcmstb_pwm *to_brcmstb_pwm(struct pwm_chip *chip)
  65. {
  66. return container_of(chip, struct brcmstb_pwm, chip);
  67. }
  68. /*
  69. * Fv is derived from the variable frequency output. The variable frequency
  70. * output is configured using this formula:
  71. *
  72. * W = cword, if cword < 2 ^ 15 else 16-bit 2's complement of cword
  73. *
  74. * Fv = W x 2 ^ -16 x 27Mhz (reference clock)
  75. *
  76. * The period is: (period + 1) / Fv and "on" time is on / (period + 1)
  77. *
  78. * The PWM core framework specifies that the "duty_ns" parameter is in fact the
  79. * "on" time, so this translates directly into our HW programming here.
  80. */
  81. static int brcmstb_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
  82. u64 duty_ns, u64 period_ns)
  83. {
  84. struct brcmstb_pwm *p = to_brcmstb_pwm(chip);
  85. unsigned long pc, dc, cword = CONST_VAR_F_MAX;
  86. unsigned int channel = pwm->hwpwm;
  87. u32 value;
  88. /*
  89. * If asking for a duty_ns equal to period_ns, we need to substract
  90. * the period value by 1 to make it shorter than the "on" time and
  91. * produce a flat 100% duty cycle signal, and max out the "on" time
  92. */
  93. if (duty_ns == period_ns) {
  94. dc = PWM_ON_PERIOD_MAX;
  95. pc = PWM_ON_PERIOD_MAX - 1;
  96. goto done;
  97. }
  98. while (1) {
  99. u64 rate;
  100. /*
  101. * Calculate the base rate from base frequency and current
  102. * cword
  103. */
  104. rate = (u64)clk_get_rate(p->clk) * (u64)cword;
  105. rate >>= CWORD_BIT_SIZE;
  106. pc = mul_u64_u64_div_u64(period_ns, rate, NSEC_PER_SEC);
  107. dc = mul_u64_u64_div_u64(duty_ns + 1, rate, NSEC_PER_SEC);
  108. /*
  109. * We can be called with separate duty and period updates,
  110. * so do not reject dc == 0 right away
  111. */
  112. if (pc == PWM_PERIOD_MIN || (dc < PWM_ON_MIN && duty_ns))
  113. return -EINVAL;
  114. /* We converged on a calculation */
  115. if (pc <= PWM_ON_PERIOD_MAX && dc <= PWM_ON_PERIOD_MAX)
  116. break;
  117. /*
  118. * The cword needs to be a power of 2 for the variable
  119. * frequency generator to output a 50% duty cycle variable
  120. * frequency which is used as input clock to the fixed
  121. * frequency generator.
  122. */
  123. cword >>= 1;
  124. /*
  125. * Desired periods are too large, we do not have a divider
  126. * for them
  127. */
  128. if (cword < CONST_VAR_F_MIN)
  129. return -EINVAL;
  130. }
  131. done:
  132. /*
  133. * Configure the defined "cword" value to have the variable frequency
  134. * generator output a base frequency for the constant frequency
  135. * generator to derive from.
  136. */
  137. brcmstb_pwm_writel(p, cword >> 8, PWM_CWORD_MSB(channel));
  138. brcmstb_pwm_writel(p, cword & 0xff, PWM_CWORD_LSB(channel));
  139. /* Select constant frequency signal output */
  140. value = brcmstb_pwm_readl(p, PWM_CTRL2);
  141. value |= CTRL2_OUT_SELECT << (channel * CTRL_CHAN_OFFS);
  142. brcmstb_pwm_writel(p, value, PWM_CTRL2);
  143. /* Configure on and period value */
  144. brcmstb_pwm_writel(p, pc, PWM_PERIOD(channel));
  145. brcmstb_pwm_writel(p, dc, PWM_ON(channel));
  146. return 0;
  147. }
  148. static inline void brcmstb_pwm_enable_set(struct brcmstb_pwm *p,
  149. unsigned int channel, bool enable)
  150. {
  151. unsigned int shift = channel * CTRL_CHAN_OFFS;
  152. u32 value;
  153. value = brcmstb_pwm_readl(p, PWM_CTRL);
  154. if (enable) {
  155. value &= ~(CTRL_OEB << shift);
  156. value |= (CTRL_START | CTRL_OPENDRAIN) << shift;
  157. } else {
  158. value &= ~((CTRL_START | CTRL_OPENDRAIN) << shift);
  159. value |= CTRL_OEB << shift;
  160. }
  161. brcmstb_pwm_writel(p, value, PWM_CTRL);
  162. }
  163. static int brcmstb_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
  164. const struct pwm_state *state)
  165. {
  166. struct brcmstb_pwm *p = to_brcmstb_pwm(chip);
  167. int err;
  168. if (state->polarity != PWM_POLARITY_NORMAL)
  169. return -EINVAL;
  170. if (!state->enabled) {
  171. if (pwm->state.enabled)
  172. brcmstb_pwm_enable_set(p, pwm->hwpwm, false);
  173. return 0;
  174. }
  175. err = brcmstb_pwm_config(chip, pwm, state->duty_cycle, state->period);
  176. if (err)
  177. return err;
  178. if (!pwm->state.enabled)
  179. brcmstb_pwm_enable_set(p, pwm->hwpwm, true);
  180. return 0;
  181. }
  182. static const struct pwm_ops brcmstb_pwm_ops = {
  183. .apply = brcmstb_pwm_apply,
  184. .owner = THIS_MODULE,
  185. };
  186. static const struct of_device_id brcmstb_pwm_of_match[] = {
  187. { .compatible = "brcm,bcm7038-pwm", },
  188. { /* sentinel */ }
  189. };
  190. MODULE_DEVICE_TABLE(of, brcmstb_pwm_of_match);
  191. static int brcmstb_pwm_probe(struct platform_device *pdev)
  192. {
  193. struct brcmstb_pwm *p;
  194. int ret;
  195. p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
  196. if (!p)
  197. return -ENOMEM;
  198. p->clk = devm_clk_get(&pdev->dev, NULL);
  199. if (IS_ERR(p->clk)) {
  200. dev_err(&pdev->dev, "failed to obtain clock\n");
  201. return PTR_ERR(p->clk);
  202. }
  203. ret = clk_prepare_enable(p->clk);
  204. if (ret < 0) {
  205. dev_err(&pdev->dev, "failed to enable clock: %d\n", ret);
  206. return ret;
  207. }
  208. platform_set_drvdata(pdev, p);
  209. p->chip.dev = &pdev->dev;
  210. p->chip.ops = &brcmstb_pwm_ops;
  211. p->chip.npwm = 2;
  212. p->base = devm_platform_ioremap_resource(pdev, 0);
  213. if (IS_ERR(p->base)) {
  214. ret = PTR_ERR(p->base);
  215. goto out_clk;
  216. }
  217. ret = pwmchip_add(&p->chip);
  218. if (ret) {
  219. dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
  220. goto out_clk;
  221. }
  222. return 0;
  223. out_clk:
  224. clk_disable_unprepare(p->clk);
  225. return ret;
  226. }
  227. static int brcmstb_pwm_remove(struct platform_device *pdev)
  228. {
  229. struct brcmstb_pwm *p = platform_get_drvdata(pdev);
  230. pwmchip_remove(&p->chip);
  231. clk_disable_unprepare(p->clk);
  232. return 0;
  233. }
  234. #ifdef CONFIG_PM_SLEEP
  235. static int brcmstb_pwm_suspend(struct device *dev)
  236. {
  237. struct brcmstb_pwm *p = dev_get_drvdata(dev);
  238. clk_disable_unprepare(p->clk);
  239. return 0;
  240. }
  241. static int brcmstb_pwm_resume(struct device *dev)
  242. {
  243. struct brcmstb_pwm *p = dev_get_drvdata(dev);
  244. clk_prepare_enable(p->clk);
  245. return 0;
  246. }
  247. #endif
  248. static SIMPLE_DEV_PM_OPS(brcmstb_pwm_pm_ops, brcmstb_pwm_suspend,
  249. brcmstb_pwm_resume);
  250. static struct platform_driver brcmstb_pwm_driver = {
  251. .probe = brcmstb_pwm_probe,
  252. .remove = brcmstb_pwm_remove,
  253. .driver = {
  254. .name = "pwm-brcmstb",
  255. .of_match_table = brcmstb_pwm_of_match,
  256. .pm = &brcmstb_pwm_pm_ops,
  257. },
  258. };
  259. module_platform_driver(brcmstb_pwm_driver);
  260. MODULE_AUTHOR("Florian Fainelli <[email protected]>");
  261. MODULE_DESCRIPTION("Broadcom STB PWM driver");
  262. MODULE_ALIAS("platform:pwm-brcmstb");
  263. MODULE_LICENSE("GPL");