ps3-lpm.c 30 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * PS3 Logical Performance Monitor.
  4. *
  5. * Copyright (C) 2007 Sony Computer Entertainment Inc.
  6. * Copyright 2007 Sony Corp.
  7. */
  8. #include <linux/slab.h>
  9. #include <linux/kernel.h>
  10. #include <linux/module.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/uaccess.h>
  13. #include <asm/smp.h>
  14. #include <asm/time.h>
  15. #include <asm/ps3.h>
  16. #include <asm/lv1call.h>
  17. #include <asm/cell-pmu.h>
  18. /* BOOKMARK tag macros */
  19. #define PS3_PM_BOOKMARK_START 0x8000000000000000ULL
  20. #define PS3_PM_BOOKMARK_STOP 0x4000000000000000ULL
  21. #define PS3_PM_BOOKMARK_TAG_KERNEL 0x1000000000000000ULL
  22. #define PS3_PM_BOOKMARK_TAG_USER 0x3000000000000000ULL
  23. #define PS3_PM_BOOKMARK_TAG_MASK_HI 0xF000000000000000ULL
  24. #define PS3_PM_BOOKMARK_TAG_MASK_LO 0x0F00000000000000ULL
  25. /* CBE PM CONTROL register macros */
  26. #define PS3_PM_CONTROL_PPU_TH0_BOOKMARK 0x00001000
  27. #define PS3_PM_CONTROL_PPU_TH1_BOOKMARK 0x00000800
  28. #define PS3_PM_CONTROL_PPU_COUNT_MODE_MASK 0x000C0000
  29. #define PS3_PM_CONTROL_PPU_COUNT_MODE_PROBLEM 0x00080000
  30. #define PS3_WRITE_PM_MASK 0xFFFFFFFFFFFFFFFFULL
  31. /* CBE PM START STOP register macros */
  32. #define PS3_PM_START_STOP_PPU_TH0_BOOKMARK_START 0x02000000
  33. #define PS3_PM_START_STOP_PPU_TH1_BOOKMARK_START 0x01000000
  34. #define PS3_PM_START_STOP_PPU_TH0_BOOKMARK_STOP 0x00020000
  35. #define PS3_PM_START_STOP_PPU_TH1_BOOKMARK_STOP 0x00010000
  36. #define PS3_PM_START_STOP_START_MASK 0xFF000000
  37. #define PS3_PM_START_STOP_STOP_MASK 0x00FF0000
  38. /* CBE PM COUNTER register macres */
  39. #define PS3_PM_COUNTER_MASK_HI 0xFFFFFFFF00000000ULL
  40. #define PS3_PM_COUNTER_MASK_LO 0x00000000FFFFFFFFULL
  41. /* BASE SIGNAL GROUP NUMBER macros */
  42. #define PM_ISLAND2_BASE_SIGNAL_GROUP_NUMBER 0
  43. #define PM_ISLAND2_SIGNAL_GROUP_NUMBER1 6
  44. #define PM_ISLAND2_SIGNAL_GROUP_NUMBER2 7
  45. #define PM_ISLAND3_BASE_SIGNAL_GROUP_NUMBER 7
  46. #define PM_ISLAND4_BASE_SIGNAL_GROUP_NUMBER 15
  47. #define PM_SPU_TRIGGER_SIGNAL_GROUP_NUMBER 17
  48. #define PM_SPU_EVENT_SIGNAL_GROUP_NUMBER 18
  49. #define PM_ISLAND5_BASE_SIGNAL_GROUP_NUMBER 18
  50. #define PM_ISLAND6_BASE_SIGNAL_GROUP_NUMBER 24
  51. #define PM_ISLAND7_BASE_SIGNAL_GROUP_NUMBER 49
  52. #define PM_ISLAND8_BASE_SIGNAL_GROUP_NUMBER 52
  53. #define PM_SIG_GROUP_SPU 41
  54. #define PM_SIG_GROUP_SPU_TRIGGER 42
  55. #define PM_SIG_GROUP_SPU_EVENT 43
  56. #define PM_SIG_GROUP_MFC_MAX 60
  57. /**
  58. * struct ps3_lpm_shadow_regs - Performance monitor shadow registers.
  59. *
  60. * @pm_control: Shadow of the processor's pm_control register.
  61. * @pm_start_stop: Shadow of the processor's pm_start_stop register.
  62. * @group_control: Shadow of the processor's group_control register.
  63. * @debug_bus_control: Shadow of the processor's debug_bus_control register.
  64. *
  65. * The logical performance monitor provides a write-only interface to
  66. * these processor registers. These shadow variables cache the processor
  67. * register values for reading.
  68. *
  69. * The initial value of the shadow registers at lpm creation is
  70. * PS3_LPM_SHADOW_REG_INIT.
  71. */
  72. struct ps3_lpm_shadow_regs {
  73. u64 pm_control;
  74. u64 pm_start_stop;
  75. u64 group_control;
  76. u64 debug_bus_control;
  77. };
  78. #define PS3_LPM_SHADOW_REG_INIT 0xFFFFFFFF00000000ULL
  79. /**
  80. * struct ps3_lpm_priv - Private lpm device data.
  81. *
  82. * @open: An atomic variable indicating the lpm driver has been opened.
  83. * @rights: The lpm rigths granted by the system policy module. A logical
  84. * OR of enum ps3_lpm_rights.
  85. * @node_id: The node id of a BE processor whose performance monitor this
  86. * lpar has the right to use.
  87. * @pu_id: The lv1 id of the logical PU.
  88. * @lpm_id: The lv1 id of this lpm instance.
  89. * @outlet_id: The outlet created by lv1 for this lpm instance.
  90. * @tb_count: The number of bytes of data held in the lv1 trace buffer.
  91. * @tb_cache: Kernel buffer to receive the data from the lv1 trace buffer.
  92. * Must be 128 byte aligned.
  93. * @tb_cache_size: Size of the kernel @tb_cache buffer. Must be 128 byte
  94. * aligned.
  95. * @tb_cache_internal: An unaligned buffer allocated by this driver to be
  96. * used for the trace buffer cache when ps3_lpm_open() is called with a
  97. * NULL tb_cache argument. Otherwise unused.
  98. * @shadow: Processor register shadow of type struct ps3_lpm_shadow_regs.
  99. * @sbd: The struct ps3_system_bus_device attached to this driver.
  100. *
  101. * The trace buffer is a buffer allocated and used internally to the lv1
  102. * hypervisor to collect trace data. The trace buffer cache is a guest
  103. * buffer that accepts the trace data from the trace buffer.
  104. */
  105. struct ps3_lpm_priv {
  106. atomic_t open;
  107. u64 rights;
  108. u64 node_id;
  109. u64 pu_id;
  110. u64 lpm_id;
  111. u64 outlet_id;
  112. u64 tb_count;
  113. void *tb_cache;
  114. u64 tb_cache_size;
  115. void *tb_cache_internal;
  116. struct ps3_lpm_shadow_regs shadow;
  117. struct ps3_system_bus_device *sbd;
  118. };
  119. enum {
  120. PS3_LPM_DEFAULT_TB_CACHE_SIZE = 0x4000,
  121. };
  122. /**
  123. * lpm_priv - Static instance of the lpm data.
  124. *
  125. * Since the exported routines don't support the notion of a device
  126. * instance we need to hold the instance in this static variable
  127. * and then only allow at most one instance at a time to be created.
  128. */
  129. static struct ps3_lpm_priv *lpm_priv;
  130. static struct device *sbd_core(void)
  131. {
  132. BUG_ON(!lpm_priv || !lpm_priv->sbd);
  133. return &lpm_priv->sbd->core;
  134. }
  135. /**
  136. * use_start_stop_bookmark - Enable the PPU bookmark trace.
  137. *
  138. * And it enables PPU bookmark triggers ONLY if the other triggers are not set.
  139. * The start/stop bookmarks are inserted at ps3_enable_pm() and ps3_disable_pm()
  140. * to start/stop LPM.
  141. *
  142. * Used to get good quality of the performance counter.
  143. */
  144. enum {use_start_stop_bookmark = 1,};
  145. void ps3_set_bookmark(u64 bookmark)
  146. {
  147. /*
  148. * As per the PPE book IV, to avoid bookmark loss there must
  149. * not be a traced branch within 10 cycles of setting the
  150. * SPRN_BKMK register. The actual text is unclear if 'within'
  151. * includes cycles before the call.
  152. */
  153. asm volatile("nop;nop;nop;nop;nop;nop;nop;nop;nop;");
  154. mtspr(SPRN_BKMK, bookmark);
  155. asm volatile("nop;nop;nop;nop;nop;nop;nop;nop;nop;");
  156. }
  157. EXPORT_SYMBOL_GPL(ps3_set_bookmark);
  158. void ps3_set_pm_bookmark(u64 tag, u64 incident, u64 th_id)
  159. {
  160. u64 bookmark;
  161. bookmark = (get_tb() & 0x00000000FFFFFFFFULL) |
  162. PS3_PM_BOOKMARK_TAG_KERNEL;
  163. bookmark = ((tag << 56) & PS3_PM_BOOKMARK_TAG_MASK_LO) |
  164. (incident << 48) | (th_id << 32) | bookmark;
  165. ps3_set_bookmark(bookmark);
  166. }
  167. EXPORT_SYMBOL_GPL(ps3_set_pm_bookmark);
  168. /**
  169. * ps3_read_phys_ctr - Read physical counter registers.
  170. *
  171. * Each physical counter can act as one 32 bit counter or as two 16 bit
  172. * counters.
  173. */
  174. u32 ps3_read_phys_ctr(u32 cpu, u32 phys_ctr)
  175. {
  176. int result;
  177. u64 counter0415;
  178. u64 counter2637;
  179. if (phys_ctr >= NR_PHYS_CTRS) {
  180. dev_dbg(sbd_core(), "%s:%u: phys_ctr too big: %u\n", __func__,
  181. __LINE__, phys_ctr);
  182. return 0;
  183. }
  184. result = lv1_set_lpm_counter(lpm_priv->lpm_id, 0, 0, 0, 0, &counter0415,
  185. &counter2637);
  186. if (result) {
  187. dev_err(sbd_core(), "%s:%u: lv1_set_lpm_counter failed: "
  188. "phys_ctr %u, %s\n", __func__, __LINE__, phys_ctr,
  189. ps3_result(result));
  190. return 0;
  191. }
  192. switch (phys_ctr) {
  193. case 0:
  194. return counter0415 >> 32;
  195. case 1:
  196. return counter0415 & PS3_PM_COUNTER_MASK_LO;
  197. case 2:
  198. return counter2637 >> 32;
  199. case 3:
  200. return counter2637 & PS3_PM_COUNTER_MASK_LO;
  201. default:
  202. BUG();
  203. }
  204. return 0;
  205. }
  206. EXPORT_SYMBOL_GPL(ps3_read_phys_ctr);
  207. /**
  208. * ps3_write_phys_ctr - Write physical counter registers.
  209. *
  210. * Each physical counter can act as one 32 bit counter or as two 16 bit
  211. * counters.
  212. */
  213. void ps3_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val)
  214. {
  215. u64 counter0415;
  216. u64 counter0415_mask;
  217. u64 counter2637;
  218. u64 counter2637_mask;
  219. int result;
  220. if (phys_ctr >= NR_PHYS_CTRS) {
  221. dev_dbg(sbd_core(), "%s:%u: phys_ctr too big: %u\n", __func__,
  222. __LINE__, phys_ctr);
  223. return;
  224. }
  225. switch (phys_ctr) {
  226. case 0:
  227. counter0415 = (u64)val << 32;
  228. counter0415_mask = PS3_PM_COUNTER_MASK_HI;
  229. counter2637 = 0x0;
  230. counter2637_mask = 0x0;
  231. break;
  232. case 1:
  233. counter0415 = (u64)val;
  234. counter0415_mask = PS3_PM_COUNTER_MASK_LO;
  235. counter2637 = 0x0;
  236. counter2637_mask = 0x0;
  237. break;
  238. case 2:
  239. counter0415 = 0x0;
  240. counter0415_mask = 0x0;
  241. counter2637 = (u64)val << 32;
  242. counter2637_mask = PS3_PM_COUNTER_MASK_HI;
  243. break;
  244. case 3:
  245. counter0415 = 0x0;
  246. counter0415_mask = 0x0;
  247. counter2637 = (u64)val;
  248. counter2637_mask = PS3_PM_COUNTER_MASK_LO;
  249. break;
  250. default:
  251. BUG();
  252. }
  253. result = lv1_set_lpm_counter(lpm_priv->lpm_id,
  254. counter0415, counter0415_mask,
  255. counter2637, counter2637_mask,
  256. &counter0415, &counter2637);
  257. if (result)
  258. dev_err(sbd_core(), "%s:%u: lv1_set_lpm_counter failed: "
  259. "phys_ctr %u, val %u, %s\n", __func__, __LINE__,
  260. phys_ctr, val, ps3_result(result));
  261. }
  262. EXPORT_SYMBOL_GPL(ps3_write_phys_ctr);
  263. /**
  264. * ps3_read_ctr - Read counter.
  265. *
  266. * Read 16 or 32 bits depending on the current size of the counter.
  267. * Counters 4, 5, 6 & 7 are always 16 bit.
  268. */
  269. u32 ps3_read_ctr(u32 cpu, u32 ctr)
  270. {
  271. u32 val;
  272. u32 phys_ctr = ctr & (NR_PHYS_CTRS - 1);
  273. val = ps3_read_phys_ctr(cpu, phys_ctr);
  274. if (ps3_get_ctr_size(cpu, phys_ctr) == 16)
  275. val = (ctr < NR_PHYS_CTRS) ? (val >> 16) : (val & 0xffff);
  276. return val;
  277. }
  278. EXPORT_SYMBOL_GPL(ps3_read_ctr);
  279. /**
  280. * ps3_write_ctr - Write counter.
  281. *
  282. * Write 16 or 32 bits depending on the current size of the counter.
  283. * Counters 4, 5, 6 & 7 are always 16 bit.
  284. */
  285. void ps3_write_ctr(u32 cpu, u32 ctr, u32 val)
  286. {
  287. u32 phys_ctr;
  288. u32 phys_val;
  289. phys_ctr = ctr & (NR_PHYS_CTRS - 1);
  290. if (ps3_get_ctr_size(cpu, phys_ctr) == 16) {
  291. phys_val = ps3_read_phys_ctr(cpu, phys_ctr);
  292. if (ctr < NR_PHYS_CTRS)
  293. val = (val << 16) | (phys_val & 0xffff);
  294. else
  295. val = (val & 0xffff) | (phys_val & 0xffff0000);
  296. }
  297. ps3_write_phys_ctr(cpu, phys_ctr, val);
  298. }
  299. EXPORT_SYMBOL_GPL(ps3_write_ctr);
  300. /**
  301. * ps3_read_pm07_control - Read counter control registers.
  302. *
  303. * Each logical counter has a corresponding control register.
  304. */
  305. u32 ps3_read_pm07_control(u32 cpu, u32 ctr)
  306. {
  307. return 0;
  308. }
  309. EXPORT_SYMBOL_GPL(ps3_read_pm07_control);
  310. /**
  311. * ps3_write_pm07_control - Write counter control registers.
  312. *
  313. * Each logical counter has a corresponding control register.
  314. */
  315. void ps3_write_pm07_control(u32 cpu, u32 ctr, u32 val)
  316. {
  317. int result;
  318. static const u64 mask = 0xFFFFFFFFFFFFFFFFULL;
  319. u64 old_value;
  320. if (ctr >= NR_CTRS) {
  321. dev_dbg(sbd_core(), "%s:%u: ctr too big: %u\n", __func__,
  322. __LINE__, ctr);
  323. return;
  324. }
  325. result = lv1_set_lpm_counter_control(lpm_priv->lpm_id, ctr, val, mask,
  326. &old_value);
  327. if (result)
  328. dev_err(sbd_core(), "%s:%u: lv1_set_lpm_counter_control "
  329. "failed: ctr %u, %s\n", __func__, __LINE__, ctr,
  330. ps3_result(result));
  331. }
  332. EXPORT_SYMBOL_GPL(ps3_write_pm07_control);
  333. /**
  334. * ps3_read_pm - Read Other LPM control registers.
  335. */
  336. u32 ps3_read_pm(u32 cpu, enum pm_reg_name reg)
  337. {
  338. int result = 0;
  339. u64 val = 0;
  340. switch (reg) {
  341. case pm_control:
  342. return lpm_priv->shadow.pm_control;
  343. case trace_address:
  344. return CBE_PM_TRACE_BUF_EMPTY;
  345. case pm_start_stop:
  346. return lpm_priv->shadow.pm_start_stop;
  347. case pm_interval:
  348. result = lv1_set_lpm_interval(lpm_priv->lpm_id, 0, 0, &val);
  349. if (result) {
  350. val = 0;
  351. dev_dbg(sbd_core(), "%s:%u: lv1 set_interval failed: "
  352. "reg %u, %s\n", __func__, __LINE__, reg,
  353. ps3_result(result));
  354. }
  355. return (u32)val;
  356. case group_control:
  357. return lpm_priv->shadow.group_control;
  358. case debug_bus_control:
  359. return lpm_priv->shadow.debug_bus_control;
  360. case pm_status:
  361. result = lv1_get_lpm_interrupt_status(lpm_priv->lpm_id,
  362. &val);
  363. if (result) {
  364. val = 0;
  365. dev_dbg(sbd_core(), "%s:%u: lv1 get_lpm_status failed: "
  366. "reg %u, %s\n", __func__, __LINE__, reg,
  367. ps3_result(result));
  368. }
  369. return (u32)val;
  370. case ext_tr_timer:
  371. return 0;
  372. default:
  373. dev_dbg(sbd_core(), "%s:%u: unknown reg: %d\n", __func__,
  374. __LINE__, reg);
  375. BUG();
  376. break;
  377. }
  378. return 0;
  379. }
  380. EXPORT_SYMBOL_GPL(ps3_read_pm);
  381. /**
  382. * ps3_write_pm - Write Other LPM control registers.
  383. */
  384. void ps3_write_pm(u32 cpu, enum pm_reg_name reg, u32 val)
  385. {
  386. int result = 0;
  387. u64 dummy;
  388. switch (reg) {
  389. case group_control:
  390. if (val != lpm_priv->shadow.group_control)
  391. result = lv1_set_lpm_group_control(lpm_priv->lpm_id,
  392. val,
  393. PS3_WRITE_PM_MASK,
  394. &dummy);
  395. lpm_priv->shadow.group_control = val;
  396. break;
  397. case debug_bus_control:
  398. if (val != lpm_priv->shadow.debug_bus_control)
  399. result = lv1_set_lpm_debug_bus_control(lpm_priv->lpm_id,
  400. val,
  401. PS3_WRITE_PM_MASK,
  402. &dummy);
  403. lpm_priv->shadow.debug_bus_control = val;
  404. break;
  405. case pm_control:
  406. if (use_start_stop_bookmark)
  407. val |= (PS3_PM_CONTROL_PPU_TH0_BOOKMARK |
  408. PS3_PM_CONTROL_PPU_TH1_BOOKMARK);
  409. if (val != lpm_priv->shadow.pm_control)
  410. result = lv1_set_lpm_general_control(lpm_priv->lpm_id,
  411. val,
  412. PS3_WRITE_PM_MASK,
  413. 0, 0, &dummy,
  414. &dummy);
  415. lpm_priv->shadow.pm_control = val;
  416. break;
  417. case pm_interval:
  418. result = lv1_set_lpm_interval(lpm_priv->lpm_id, val,
  419. PS3_WRITE_PM_MASK, &dummy);
  420. break;
  421. case pm_start_stop:
  422. if (val != lpm_priv->shadow.pm_start_stop)
  423. result = lv1_set_lpm_trigger_control(lpm_priv->lpm_id,
  424. val,
  425. PS3_WRITE_PM_MASK,
  426. &dummy);
  427. lpm_priv->shadow.pm_start_stop = val;
  428. break;
  429. case trace_address:
  430. case ext_tr_timer:
  431. case pm_status:
  432. break;
  433. default:
  434. dev_dbg(sbd_core(), "%s:%u: unknown reg: %d\n", __func__,
  435. __LINE__, reg);
  436. BUG();
  437. break;
  438. }
  439. if (result)
  440. dev_err(sbd_core(), "%s:%u: lv1 set_control failed: "
  441. "reg %u, %s\n", __func__, __LINE__, reg,
  442. ps3_result(result));
  443. }
  444. EXPORT_SYMBOL_GPL(ps3_write_pm);
  445. /**
  446. * ps3_get_ctr_size - Get the size of a physical counter.
  447. *
  448. * Returns either 16 or 32.
  449. */
  450. u32 ps3_get_ctr_size(u32 cpu, u32 phys_ctr)
  451. {
  452. u32 pm_ctrl;
  453. if (phys_ctr >= NR_PHYS_CTRS) {
  454. dev_dbg(sbd_core(), "%s:%u: phys_ctr too big: %u\n", __func__,
  455. __LINE__, phys_ctr);
  456. return 0;
  457. }
  458. pm_ctrl = ps3_read_pm(cpu, pm_control);
  459. return (pm_ctrl & CBE_PM_16BIT_CTR(phys_ctr)) ? 16 : 32;
  460. }
  461. EXPORT_SYMBOL_GPL(ps3_get_ctr_size);
  462. /**
  463. * ps3_set_ctr_size - Set the size of a physical counter to 16 or 32 bits.
  464. */
  465. void ps3_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size)
  466. {
  467. u32 pm_ctrl;
  468. if (phys_ctr >= NR_PHYS_CTRS) {
  469. dev_dbg(sbd_core(), "%s:%u: phys_ctr too big: %u\n", __func__,
  470. __LINE__, phys_ctr);
  471. return;
  472. }
  473. pm_ctrl = ps3_read_pm(cpu, pm_control);
  474. switch (ctr_size) {
  475. case 16:
  476. pm_ctrl |= CBE_PM_16BIT_CTR(phys_ctr);
  477. ps3_write_pm(cpu, pm_control, pm_ctrl);
  478. break;
  479. case 32:
  480. pm_ctrl &= ~CBE_PM_16BIT_CTR(phys_ctr);
  481. ps3_write_pm(cpu, pm_control, pm_ctrl);
  482. break;
  483. default:
  484. BUG();
  485. }
  486. }
  487. EXPORT_SYMBOL_GPL(ps3_set_ctr_size);
  488. static u64 pm_translate_signal_group_number_on_island2(u64 subgroup)
  489. {
  490. if (subgroup == 2)
  491. subgroup = 3;
  492. if (subgroup <= 6)
  493. return PM_ISLAND2_BASE_SIGNAL_GROUP_NUMBER + subgroup;
  494. else if (subgroup == 7)
  495. return PM_ISLAND2_SIGNAL_GROUP_NUMBER1;
  496. else
  497. return PM_ISLAND2_SIGNAL_GROUP_NUMBER2;
  498. }
  499. static u64 pm_translate_signal_group_number_on_island3(u64 subgroup)
  500. {
  501. switch (subgroup) {
  502. case 2:
  503. case 3:
  504. case 4:
  505. subgroup += 2;
  506. break;
  507. case 5:
  508. subgroup = 8;
  509. break;
  510. default:
  511. break;
  512. }
  513. return PM_ISLAND3_BASE_SIGNAL_GROUP_NUMBER + subgroup;
  514. }
  515. static u64 pm_translate_signal_group_number_on_island4(u64 subgroup)
  516. {
  517. return PM_ISLAND4_BASE_SIGNAL_GROUP_NUMBER + subgroup;
  518. }
  519. static u64 pm_translate_signal_group_number_on_island5(u64 subgroup)
  520. {
  521. switch (subgroup) {
  522. case 3:
  523. subgroup = 4;
  524. break;
  525. case 4:
  526. subgroup = 6;
  527. break;
  528. default:
  529. break;
  530. }
  531. return PM_ISLAND5_BASE_SIGNAL_GROUP_NUMBER + subgroup;
  532. }
  533. static u64 pm_translate_signal_group_number_on_island6(u64 subgroup,
  534. u64 subsubgroup)
  535. {
  536. switch (subgroup) {
  537. case 3:
  538. case 4:
  539. case 5:
  540. subgroup += 1;
  541. break;
  542. default:
  543. break;
  544. }
  545. switch (subsubgroup) {
  546. case 4:
  547. case 5:
  548. case 6:
  549. subsubgroup += 2;
  550. break;
  551. case 7:
  552. case 8:
  553. case 9:
  554. case 10:
  555. subsubgroup += 4;
  556. break;
  557. case 11:
  558. case 12:
  559. case 13:
  560. subsubgroup += 5;
  561. break;
  562. default:
  563. break;
  564. }
  565. if (subgroup <= 5)
  566. return (PM_ISLAND6_BASE_SIGNAL_GROUP_NUMBER + subgroup);
  567. else
  568. return (PM_ISLAND6_BASE_SIGNAL_GROUP_NUMBER + subgroup
  569. + subsubgroup - 1);
  570. }
  571. static u64 pm_translate_signal_group_number_on_island7(u64 subgroup)
  572. {
  573. return PM_ISLAND7_BASE_SIGNAL_GROUP_NUMBER + subgroup;
  574. }
  575. static u64 pm_translate_signal_group_number_on_island8(u64 subgroup)
  576. {
  577. return PM_ISLAND8_BASE_SIGNAL_GROUP_NUMBER + subgroup;
  578. }
  579. static u64 pm_signal_group_to_ps3_lv1_signal_group(u64 group)
  580. {
  581. u64 island;
  582. u64 subgroup;
  583. u64 subsubgroup;
  584. subgroup = 0;
  585. subsubgroup = 0;
  586. island = 0;
  587. if (group < 1000) {
  588. if (group < 100) {
  589. if (20 <= group && group < 30) {
  590. island = 2;
  591. subgroup = group - 20;
  592. } else if (30 <= group && group < 40) {
  593. island = 3;
  594. subgroup = group - 30;
  595. } else if (40 <= group && group < 50) {
  596. island = 4;
  597. subgroup = group - 40;
  598. } else if (50 <= group && group < 60) {
  599. island = 5;
  600. subgroup = group - 50;
  601. } else if (60 <= group && group < 70) {
  602. island = 6;
  603. subgroup = group - 60;
  604. } else if (70 <= group && group < 80) {
  605. island = 7;
  606. subgroup = group - 70;
  607. } else if (80 <= group && group < 90) {
  608. island = 8;
  609. subgroup = group - 80;
  610. }
  611. } else if (200 <= group && group < 300) {
  612. island = 2;
  613. subgroup = group - 200;
  614. } else if (600 <= group && group < 700) {
  615. island = 6;
  616. subgroup = 5;
  617. subsubgroup = group - 650;
  618. }
  619. } else if (6000 <= group && group < 7000) {
  620. island = 6;
  621. subgroup = 5;
  622. subsubgroup = group - 6500;
  623. }
  624. switch (island) {
  625. case 2:
  626. return pm_translate_signal_group_number_on_island2(subgroup);
  627. case 3:
  628. return pm_translate_signal_group_number_on_island3(subgroup);
  629. case 4:
  630. return pm_translate_signal_group_number_on_island4(subgroup);
  631. case 5:
  632. return pm_translate_signal_group_number_on_island5(subgroup);
  633. case 6:
  634. return pm_translate_signal_group_number_on_island6(subgroup,
  635. subsubgroup);
  636. case 7:
  637. return pm_translate_signal_group_number_on_island7(subgroup);
  638. case 8:
  639. return pm_translate_signal_group_number_on_island8(subgroup);
  640. default:
  641. dev_dbg(sbd_core(), "%s:%u: island not found: %llu\n", __func__,
  642. __LINE__, group);
  643. BUG();
  644. break;
  645. }
  646. return 0;
  647. }
  648. static u64 pm_bus_word_to_ps3_lv1_bus_word(u8 word)
  649. {
  650. switch (word) {
  651. case 1:
  652. return 0xF000;
  653. case 2:
  654. return 0x0F00;
  655. case 4:
  656. return 0x00F0;
  657. case 8:
  658. default:
  659. return 0x000F;
  660. }
  661. }
  662. static int __ps3_set_signal(u64 lv1_signal_group, u64 bus_select,
  663. u64 signal_select, u64 attr1, u64 attr2, u64 attr3)
  664. {
  665. int ret;
  666. ret = lv1_set_lpm_signal(lpm_priv->lpm_id, lv1_signal_group, bus_select,
  667. signal_select, attr1, attr2, attr3);
  668. if (ret)
  669. dev_err(sbd_core(),
  670. "%s:%u: error:%d 0x%llx 0x%llx 0x%llx 0x%llx 0x%llx 0x%llx\n",
  671. __func__, __LINE__, ret, lv1_signal_group, bus_select,
  672. signal_select, attr1, attr2, attr3);
  673. return ret;
  674. }
  675. int ps3_set_signal(u64 signal_group, u8 signal_bit, u16 sub_unit,
  676. u8 bus_word)
  677. {
  678. int ret;
  679. u64 lv1_signal_group;
  680. u64 bus_select;
  681. u64 signal_select;
  682. u64 attr1, attr2, attr3;
  683. if (signal_group == 0)
  684. return __ps3_set_signal(0, 0, 0, 0, 0, 0);
  685. lv1_signal_group =
  686. pm_signal_group_to_ps3_lv1_signal_group(signal_group);
  687. bus_select = pm_bus_word_to_ps3_lv1_bus_word(bus_word);
  688. switch (signal_group) {
  689. case PM_SIG_GROUP_SPU_TRIGGER:
  690. signal_select = 1;
  691. signal_select = signal_select << (63 - signal_bit);
  692. break;
  693. case PM_SIG_GROUP_SPU_EVENT:
  694. signal_select = 1;
  695. signal_select = (signal_select << (63 - signal_bit)) | 0x3;
  696. break;
  697. default:
  698. signal_select = 0;
  699. break;
  700. }
  701. /*
  702. * 0: physical object.
  703. * 1: logical object.
  704. * This parameter is only used for the PPE and SPE signals.
  705. */
  706. attr1 = 1;
  707. /*
  708. * This parameter is used to specify the target physical/logical
  709. * PPE/SPE object.
  710. */
  711. if (PM_SIG_GROUP_SPU <= signal_group &&
  712. signal_group < PM_SIG_GROUP_MFC_MAX)
  713. attr2 = sub_unit;
  714. else
  715. attr2 = lpm_priv->pu_id;
  716. /*
  717. * This parameter is only used for setting the SPE signal.
  718. */
  719. attr3 = 0;
  720. ret = __ps3_set_signal(lv1_signal_group, bus_select, signal_select,
  721. attr1, attr2, attr3);
  722. if (ret)
  723. dev_err(sbd_core(), "%s:%u: __ps3_set_signal failed: %d\n",
  724. __func__, __LINE__, ret);
  725. return ret;
  726. }
  727. EXPORT_SYMBOL_GPL(ps3_set_signal);
  728. u32 ps3_get_hw_thread_id(int cpu)
  729. {
  730. return get_hard_smp_processor_id(cpu);
  731. }
  732. EXPORT_SYMBOL_GPL(ps3_get_hw_thread_id);
  733. /**
  734. * ps3_enable_pm - Enable the entire performance monitoring unit.
  735. *
  736. * When we enable the LPM, all pending writes to counters get committed.
  737. */
  738. void ps3_enable_pm(u32 cpu)
  739. {
  740. int result;
  741. u64 tmp;
  742. int insert_bookmark = 0;
  743. lpm_priv->tb_count = 0;
  744. if (use_start_stop_bookmark) {
  745. if (!(lpm_priv->shadow.pm_start_stop &
  746. (PS3_PM_START_STOP_START_MASK
  747. | PS3_PM_START_STOP_STOP_MASK))) {
  748. result = lv1_set_lpm_trigger_control(lpm_priv->lpm_id,
  749. (PS3_PM_START_STOP_PPU_TH0_BOOKMARK_START |
  750. PS3_PM_START_STOP_PPU_TH1_BOOKMARK_START |
  751. PS3_PM_START_STOP_PPU_TH0_BOOKMARK_STOP |
  752. PS3_PM_START_STOP_PPU_TH1_BOOKMARK_STOP),
  753. 0xFFFFFFFFFFFFFFFFULL, &tmp);
  754. if (result)
  755. dev_err(sbd_core(), "%s:%u: "
  756. "lv1_set_lpm_trigger_control failed: "
  757. "%s\n", __func__, __LINE__,
  758. ps3_result(result));
  759. insert_bookmark = !result;
  760. }
  761. }
  762. result = lv1_start_lpm(lpm_priv->lpm_id);
  763. if (result)
  764. dev_err(sbd_core(), "%s:%u: lv1_start_lpm failed: %s\n",
  765. __func__, __LINE__, ps3_result(result));
  766. if (use_start_stop_bookmark && !result && insert_bookmark)
  767. ps3_set_bookmark(get_tb() | PS3_PM_BOOKMARK_START);
  768. }
  769. EXPORT_SYMBOL_GPL(ps3_enable_pm);
  770. /**
  771. * ps3_disable_pm - Disable the entire performance monitoring unit.
  772. */
  773. void ps3_disable_pm(u32 cpu)
  774. {
  775. int result;
  776. u64 tmp;
  777. ps3_set_bookmark(get_tb() | PS3_PM_BOOKMARK_STOP);
  778. result = lv1_stop_lpm(lpm_priv->lpm_id, &tmp);
  779. if (result) {
  780. if (result != LV1_WRONG_STATE)
  781. dev_err(sbd_core(), "%s:%u: lv1_stop_lpm failed: %s\n",
  782. __func__, __LINE__, ps3_result(result));
  783. return;
  784. }
  785. lpm_priv->tb_count = tmp;
  786. dev_dbg(sbd_core(), "%s:%u: tb_count %llu (%llxh)\n", __func__, __LINE__,
  787. lpm_priv->tb_count, lpm_priv->tb_count);
  788. }
  789. EXPORT_SYMBOL_GPL(ps3_disable_pm);
  790. /**
  791. * ps3_lpm_copy_tb - Copy data from the trace buffer to a kernel buffer.
  792. * @offset: Offset in bytes from the start of the trace buffer.
  793. * @buf: Copy destination.
  794. * @count: Maximum count of bytes to copy.
  795. * @bytes_copied: Pointer to a variable that will receive the number of
  796. * bytes copied to @buf.
  797. *
  798. * On error @buf will contain any successfully copied trace buffer data
  799. * and bytes_copied will be set to the number of bytes successfully copied.
  800. */
  801. int ps3_lpm_copy_tb(unsigned long offset, void *buf, unsigned long count,
  802. unsigned long *bytes_copied)
  803. {
  804. int result;
  805. *bytes_copied = 0;
  806. if (!lpm_priv->tb_cache)
  807. return -EPERM;
  808. if (offset >= lpm_priv->tb_count)
  809. return 0;
  810. count = min_t(u64, count, lpm_priv->tb_count - offset);
  811. while (*bytes_copied < count) {
  812. const unsigned long request = count - *bytes_copied;
  813. u64 tmp;
  814. result = lv1_copy_lpm_trace_buffer(lpm_priv->lpm_id, offset,
  815. request, &tmp);
  816. if (result) {
  817. dev_dbg(sbd_core(), "%s:%u: 0x%lx bytes at 0x%lx\n",
  818. __func__, __LINE__, request, offset);
  819. dev_err(sbd_core(), "%s:%u: lv1_copy_lpm_trace_buffer "
  820. "failed: %s\n", __func__, __LINE__,
  821. ps3_result(result));
  822. return result == LV1_WRONG_STATE ? -EBUSY : -EINVAL;
  823. }
  824. memcpy(buf, lpm_priv->tb_cache, tmp);
  825. buf += tmp;
  826. *bytes_copied += tmp;
  827. offset += tmp;
  828. }
  829. dev_dbg(sbd_core(), "%s:%u: copied %lxh bytes\n", __func__, __LINE__,
  830. *bytes_copied);
  831. return 0;
  832. }
  833. EXPORT_SYMBOL_GPL(ps3_lpm_copy_tb);
  834. /**
  835. * ps3_lpm_copy_tb_to_user - Copy data from the trace buffer to a user buffer.
  836. * @offset: Offset in bytes from the start of the trace buffer.
  837. * @buf: A __user copy destination.
  838. * @count: Maximum count of bytes to copy.
  839. * @bytes_copied: Pointer to a variable that will receive the number of
  840. * bytes copied to @buf.
  841. *
  842. * On error @buf will contain any successfully copied trace buffer data
  843. * and bytes_copied will be set to the number of bytes successfully copied.
  844. */
  845. int ps3_lpm_copy_tb_to_user(unsigned long offset, void __user *buf,
  846. unsigned long count, unsigned long *bytes_copied)
  847. {
  848. int result;
  849. *bytes_copied = 0;
  850. if (!lpm_priv->tb_cache)
  851. return -EPERM;
  852. if (offset >= lpm_priv->tb_count)
  853. return 0;
  854. count = min_t(u64, count, lpm_priv->tb_count - offset);
  855. while (*bytes_copied < count) {
  856. const unsigned long request = count - *bytes_copied;
  857. u64 tmp;
  858. result = lv1_copy_lpm_trace_buffer(lpm_priv->lpm_id, offset,
  859. request, &tmp);
  860. if (result) {
  861. dev_dbg(sbd_core(), "%s:%u: 0x%lx bytes at 0x%lx\n",
  862. __func__, __LINE__, request, offset);
  863. dev_err(sbd_core(), "%s:%u: lv1_copy_lpm_trace_buffer "
  864. "failed: %s\n", __func__, __LINE__,
  865. ps3_result(result));
  866. return result == LV1_WRONG_STATE ? -EBUSY : -EINVAL;
  867. }
  868. result = copy_to_user(buf, lpm_priv->tb_cache, tmp);
  869. if (result) {
  870. dev_dbg(sbd_core(), "%s:%u: 0x%llx bytes at 0x%p\n",
  871. __func__, __LINE__, tmp, buf);
  872. dev_err(sbd_core(), "%s:%u: copy_to_user failed: %d\n",
  873. __func__, __LINE__, result);
  874. return -EFAULT;
  875. }
  876. buf += tmp;
  877. *bytes_copied += tmp;
  878. offset += tmp;
  879. }
  880. dev_dbg(sbd_core(), "%s:%u: copied %lxh bytes\n", __func__, __LINE__,
  881. *bytes_copied);
  882. return 0;
  883. }
  884. EXPORT_SYMBOL_GPL(ps3_lpm_copy_tb_to_user);
  885. /**
  886. * ps3_get_and_clear_pm_interrupts -
  887. *
  888. * Clearing interrupts for the entire performance monitoring unit.
  889. * Reading pm_status clears the interrupt bits.
  890. */
  891. u32 ps3_get_and_clear_pm_interrupts(u32 cpu)
  892. {
  893. return ps3_read_pm(cpu, pm_status);
  894. }
  895. EXPORT_SYMBOL_GPL(ps3_get_and_clear_pm_interrupts);
  896. /**
  897. * ps3_enable_pm_interrupts -
  898. *
  899. * Enabling interrupts for the entire performance monitoring unit.
  900. * Enables the interrupt bits in the pm_status register.
  901. */
  902. void ps3_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask)
  903. {
  904. if (mask)
  905. ps3_write_pm(cpu, pm_status, mask);
  906. }
  907. EXPORT_SYMBOL_GPL(ps3_enable_pm_interrupts);
  908. /**
  909. * ps3_enable_pm_interrupts -
  910. *
  911. * Disabling interrupts for the entire performance monitoring unit.
  912. */
  913. void ps3_disable_pm_interrupts(u32 cpu)
  914. {
  915. ps3_get_and_clear_pm_interrupts(cpu);
  916. ps3_write_pm(cpu, pm_status, 0);
  917. }
  918. EXPORT_SYMBOL_GPL(ps3_disable_pm_interrupts);
  919. /**
  920. * ps3_lpm_open - Open the logical performance monitor device.
  921. * @tb_type: Specifies the type of trace buffer lv1 should use for this lpm
  922. * instance, specified by one of enum ps3_lpm_tb_type.
  923. * @tb_cache: Optional user supplied buffer to use as the trace buffer cache.
  924. * If NULL, the driver will allocate and manage an internal buffer.
  925. * Unused when when @tb_type is PS3_LPM_TB_TYPE_NONE.
  926. * @tb_cache_size: The size in bytes of the user supplied @tb_cache buffer.
  927. * Unused when @tb_cache is NULL or @tb_type is PS3_LPM_TB_TYPE_NONE.
  928. */
  929. int ps3_lpm_open(enum ps3_lpm_tb_type tb_type, void *tb_cache,
  930. u64 tb_cache_size)
  931. {
  932. int result;
  933. u64 tb_size;
  934. BUG_ON(!lpm_priv);
  935. BUG_ON(tb_type != PS3_LPM_TB_TYPE_NONE
  936. && tb_type != PS3_LPM_TB_TYPE_INTERNAL);
  937. if (tb_type == PS3_LPM_TB_TYPE_NONE && tb_cache)
  938. dev_dbg(sbd_core(), "%s:%u: bad in vals\n", __func__, __LINE__);
  939. if (!atomic_add_unless(&lpm_priv->open, 1, 1)) {
  940. dev_dbg(sbd_core(), "%s:%u: busy\n", __func__, __LINE__);
  941. return -EBUSY;
  942. }
  943. /* Note tb_cache needs 128 byte alignment. */
  944. if (tb_type == PS3_LPM_TB_TYPE_NONE) {
  945. lpm_priv->tb_cache_size = 0;
  946. lpm_priv->tb_cache_internal = NULL;
  947. lpm_priv->tb_cache = NULL;
  948. } else if (tb_cache) {
  949. if (tb_cache != (void *)ALIGN((unsigned long)tb_cache, 128)
  950. || tb_cache_size != ALIGN(tb_cache_size, 128)) {
  951. dev_err(sbd_core(), "%s:%u: unaligned tb_cache\n",
  952. __func__, __LINE__);
  953. result = -EINVAL;
  954. goto fail_align;
  955. }
  956. lpm_priv->tb_cache_size = tb_cache_size;
  957. lpm_priv->tb_cache_internal = NULL;
  958. lpm_priv->tb_cache = tb_cache;
  959. } else {
  960. lpm_priv->tb_cache_size = PS3_LPM_DEFAULT_TB_CACHE_SIZE;
  961. lpm_priv->tb_cache_internal = kzalloc(
  962. lpm_priv->tb_cache_size + 127, GFP_KERNEL);
  963. if (!lpm_priv->tb_cache_internal) {
  964. result = -ENOMEM;
  965. goto fail_malloc;
  966. }
  967. lpm_priv->tb_cache = (void *)ALIGN(
  968. (unsigned long)lpm_priv->tb_cache_internal, 128);
  969. }
  970. result = lv1_construct_lpm(lpm_priv->node_id, tb_type, 0, 0,
  971. ps3_mm_phys_to_lpar(__pa(lpm_priv->tb_cache)),
  972. lpm_priv->tb_cache_size, &lpm_priv->lpm_id,
  973. &lpm_priv->outlet_id, &tb_size);
  974. if (result) {
  975. dev_err(sbd_core(), "%s:%u: lv1_construct_lpm failed: %s\n",
  976. __func__, __LINE__, ps3_result(result));
  977. result = -EINVAL;
  978. goto fail_construct;
  979. }
  980. lpm_priv->shadow.pm_control = PS3_LPM_SHADOW_REG_INIT;
  981. lpm_priv->shadow.pm_start_stop = PS3_LPM_SHADOW_REG_INIT;
  982. lpm_priv->shadow.group_control = PS3_LPM_SHADOW_REG_INIT;
  983. lpm_priv->shadow.debug_bus_control = PS3_LPM_SHADOW_REG_INIT;
  984. dev_dbg(sbd_core(), "%s:%u: lpm_id 0x%llx, outlet_id 0x%llx, "
  985. "tb_size 0x%llx\n", __func__, __LINE__, lpm_priv->lpm_id,
  986. lpm_priv->outlet_id, tb_size);
  987. return 0;
  988. fail_construct:
  989. kfree(lpm_priv->tb_cache_internal);
  990. lpm_priv->tb_cache_internal = NULL;
  991. fail_malloc:
  992. fail_align:
  993. atomic_dec(&lpm_priv->open);
  994. return result;
  995. }
  996. EXPORT_SYMBOL_GPL(ps3_lpm_open);
  997. /**
  998. * ps3_lpm_close - Close the lpm device.
  999. *
  1000. */
  1001. int ps3_lpm_close(void)
  1002. {
  1003. dev_dbg(sbd_core(), "%s:%u\n", __func__, __LINE__);
  1004. lv1_destruct_lpm(lpm_priv->lpm_id);
  1005. lpm_priv->lpm_id = 0;
  1006. kfree(lpm_priv->tb_cache_internal);
  1007. lpm_priv->tb_cache_internal = NULL;
  1008. atomic_dec(&lpm_priv->open);
  1009. return 0;
  1010. }
  1011. EXPORT_SYMBOL_GPL(ps3_lpm_close);
  1012. static int ps3_lpm_probe(struct ps3_system_bus_device *dev)
  1013. {
  1014. dev_dbg(&dev->core, " -> %s:%u\n", __func__, __LINE__);
  1015. if (lpm_priv) {
  1016. dev_info(&dev->core, "%s:%u: called twice\n",
  1017. __func__, __LINE__);
  1018. return -EBUSY;
  1019. }
  1020. lpm_priv = kzalloc(sizeof(*lpm_priv), GFP_KERNEL);
  1021. if (!lpm_priv)
  1022. return -ENOMEM;
  1023. lpm_priv->sbd = dev;
  1024. lpm_priv->node_id = dev->lpm.node_id;
  1025. lpm_priv->pu_id = dev->lpm.pu_id;
  1026. lpm_priv->rights = dev->lpm.rights;
  1027. dev_info(&dev->core, " <- %s:%u:\n", __func__, __LINE__);
  1028. return 0;
  1029. }
  1030. static void ps3_lpm_remove(struct ps3_system_bus_device *dev)
  1031. {
  1032. dev_dbg(&dev->core, " -> %s:%u:\n", __func__, __LINE__);
  1033. ps3_lpm_close();
  1034. kfree(lpm_priv);
  1035. lpm_priv = NULL;
  1036. dev_info(&dev->core, " <- %s:%u:\n", __func__, __LINE__);
  1037. }
  1038. static struct ps3_system_bus_driver ps3_lpm_driver = {
  1039. .match_id = PS3_MATCH_ID_LPM,
  1040. .core.name = "ps3-lpm",
  1041. .core.owner = THIS_MODULE,
  1042. .probe = ps3_lpm_probe,
  1043. .remove = ps3_lpm_remove,
  1044. .shutdown = ps3_lpm_remove,
  1045. };
  1046. static int __init ps3_lpm_init(void)
  1047. {
  1048. pr_debug("%s:%d:\n", __func__, __LINE__);
  1049. return ps3_system_bus_driver_register(&ps3_lpm_driver);
  1050. }
  1051. static void __exit ps3_lpm_exit(void)
  1052. {
  1053. pr_debug("%s:%d:\n", __func__, __LINE__);
  1054. ps3_system_bus_driver_unregister(&ps3_lpm_driver);
  1055. }
  1056. module_init(ps3_lpm_init);
  1057. module_exit(ps3_lpm_exit);
  1058. MODULE_LICENSE("GPL v2");
  1059. MODULE_DESCRIPTION("PS3 Logical Performance Monitor Driver");
  1060. MODULE_AUTHOR("Sony Corporation");
  1061. MODULE_ALIAS(PS3_MODULE_ALIAS_LPM);