phy-qcom-ufs-qmp-v4-lahaina.h 25 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. */
  5. #ifndef UFS_QCOM_PHY_QMP_V4_H_
  6. #define UFS_QCOM_PHY_QMP_V4_H_
  7. #include "phy-qcom-ufs-i.h"
  8. /* QCOM UFS PHY control registers */
  9. #define COM_BASE 0x000
  10. #define COM_SIZE 0x1C0
  11. #define PHY_BASE 0xC00
  12. #define PHY_SIZE 0x200
  13. #define PCS2_BASE 0x200
  14. #define PCS2_SIZE 0x40
  15. #define TX_BASE(n) (0x400 + (0x400 * n))
  16. #define TX_SIZE 0x188
  17. #define RX_BASE(n) (0x600 + (0x400 * n))
  18. #define RX_SIZE 0x200
  19. #define COM_OFF(x) (COM_BASE + x)
  20. #define PHY_OFF(x) (PHY_BASE + x)
  21. #define TX_OFF(n, x) (TX_BASE(n) + x)
  22. #define RX_OFF(n, x) (RX_BASE(n) + x)
  23. /* UFS PHY QSERDES COM registers */
  24. #define QSERDES_COM_SYSCLK_EN_SEL COM_OFF(0x94)
  25. #define QSERDES_COM_HSCLK_SEL COM_OFF(0x158)
  26. #define QSERDES_COM_HSCLK_HS_SWITCH_SEL COM_OFF(0x15C)
  27. #define QSERDES_COM_LOCK_CMP_EN COM_OFF(0xA4)
  28. #define QSERDES_COM_VCO_TUNE_MAP COM_OFF(0x10C)
  29. #define QSERDES_COM_PLL_IVCO COM_OFF(0x58)
  30. #define QSERDES_COM_VCO_TUNE_INITVAL2 COM_OFF(0x124)
  31. #define QSERDES_COM_BIN_VCOCAL_HSCLK_SEL COM_OFF(0x1BC)
  32. #define QSERDES_COM_DEC_START_MODE0 COM_OFF(0xBC)
  33. #define QSERDES_COM_CP_CTRL_MODE0 COM_OFF(0x74)
  34. #define QSERDES_COM_PLL_RCTRL_MODE0 COM_OFF(0x7C)
  35. #define QSERDES_COM_PLL_CCTRL_MODE0 COM_OFF(0x84)
  36. #define QSERDES_COM_LOCK_CMP1_MODE0 COM_OFF(0xAC)
  37. #define QSERDES_COM_LOCK_CMP2_MODE0 COM_OFF(0xB0)
  38. #define QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 COM_OFF(0x1AC)
  39. #define QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 COM_OFF(0x1B0)
  40. #define QSERDES_COM_DEC_START_MODE1 COM_OFF(0xC4)
  41. #define QSERDES_COM_CP_CTRL_MODE1 COM_OFF(0x78)
  42. #define QSERDES_COM_PLL_RCTRL_MODE1 COM_OFF(0x80)
  43. #define QSERDES_COM_PLL_CCTRL_MODE1 COM_OFF(0x88)
  44. #define QSERDES_COM_LOCK_CMP1_MODE1 COM_OFF(0xB4)
  45. #define QSERDES_COM_LOCK_CMP2_MODE1 COM_OFF(0xB8)
  46. #define QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 COM_OFF(0x1B4)
  47. #define QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 COM_OFF(0x1B8)
  48. #define QSERDES_COM_CMN_IPTRIM COM_OFF(0x60)
  49. /* UFS PHY registers */
  50. #define UFS_PHY_PHY_START PHY_OFF(0x00)
  51. #define UFS_PHY_POWER_DOWN_CONTROL PHY_OFF(0x04)
  52. #define UFS_PHY_SW_RESET PHY_OFF(0x08)
  53. #define UFS_PHY_PCS_READY_STATUS PHY_OFF(0x180)
  54. #define UFS_PHY_LINECFG_DISABLE PHY_OFF(0x148)
  55. #define UFS_PHY_MULTI_LANE_CTRL1 PHY_OFF(0x1E0)
  56. #define UFS_PHY_RX_SIGDET_CTRL2 PHY_OFF(0x158)
  57. #define UFS_PHY_TX_LARGE_AMP_DRV_LVL PHY_OFF(0x30)
  58. #define UFS_PHY_TX_SMALL_AMP_DRV_LVL PHY_OFF(0x38)
  59. #define UFS_PHY_TX_MID_TERM_CTRL1 PHY_OFF(0x1D8)
  60. #define UFS_PHY_DEBUG_BUS_CLKSEL PHY_OFF(0x124)
  61. #define UFS_PHY_PLL_CNTL PHY_OFF(0x2C)
  62. #define UFS_PHY_TIMER_20US_CORECLK_STEPS_MSB PHY_OFF(0x0C)
  63. #define UFS_PHY_TIMER_20US_CORECLK_STEPS_LSB PHY_OFF(0x10)
  64. #define UFS_PHY_TX_PWM_GEAR_BAND PHY_OFF(0x160)
  65. #define UFS_PHY_TX_HS_GEAR_BAND PHY_OFF(0x168)
  66. #define UFS_PHY_TX_HSGEAR_CAPABILITY PHY_OFF(0x74)
  67. #define UFS_PHY_RX_HSGEAR_CAPABILITY PHY_OFF(0xB4)
  68. #define UFS_PHY_RX_MIN_HIBERN8_TIME PHY_OFF(0x150)
  69. #define UFS_PHY_BIST_FIXED_PAT_CTRL PHY_OFF(0x60)
  70. #define UFS_PHY_RX_SIGDET_CTRL1 PHY_OFF(0x154)
  71. /* UFS PHY TX registers */
  72. #define QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND0_1 TX_OFF(0, 0x178)
  73. #define QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND0_1 TX_OFF(0, 0x17C)
  74. #define QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND0_1 TX_OFF(0, 0x180)
  75. #define QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND0_1 TX_OFF(0, 0x184)
  76. #define QSERDES_TX0_LANE_MODE_1 TX_OFF(0, 0x84)
  77. #define QSERDES_TX0_LANE_MODE_3 TX_OFF(0, 0x8C)
  78. #define QSERDES_TX0_RES_CODE_LANE_OFFSET_TX TX_OFF(0, 0x3C)
  79. #define QSERDES_TX0_RES_CODE_LANE_OFFSET_RX TX_OFF(0, 0x40)
  80. #define QSERDES_TX0_TRAN_DRVR_EMP_EN TX_OFF(0, 0xC0)
  81. #define QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND0_1 TX_OFF(1, 0x178)
  82. #define QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND0_1 TX_OFF(1, 0x17C)
  83. #define QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND0_1 TX_OFF(1, 0x180)
  84. #define QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND0_1 TX_OFF(1, 0x184)
  85. #define QSERDES_TX1_LANE_MODE_1 TX_OFF(1, 0x84)
  86. #define QSERDES_TX1_LANE_MODE_3 TX_OFF(1, 0x8C)
  87. #define QSERDES_TX1_RES_CODE_LANE_OFFSET_TX TX_OFF(1, 0x3C)
  88. #define QSERDES_TX1_RES_CODE_LANE_OFFSET_RX TX_OFF(1, 0x40)
  89. #define QSERDES_TX1_TRAN_DRVR_EMP_EN TX_OFF(1, 0xC0)
  90. /* UFS PHY RX registers */
  91. #define QSERDES_RX0_SIGDET_LVL RX_OFF(0, 0x120)
  92. #define QSERDES_RX0_SIGDET_CNTRL RX_OFF(0, 0x11C)
  93. #define QSERDES_RX0_SIGDET_DEGLITCH_CNTRL RX_OFF(0, 0x124)
  94. #define QSERDES_RX0_RX_BAND RX_OFF(0, 0x128)
  95. #define QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN RX_OFF(0, 0x30)
  96. #define QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE RX_OFF(0, 0x34)
  97. #define QSERDES_RX0_UCDR_PI_CONTROLS RX_OFF(0, 0x44)
  98. #define QSERDES_RX0_UCDR_FASTLOCK_COUNT_LOW RX_OFF(0, 0x3C)
  99. #define QSERDES_RX0_UCDR_PI_CTRL2 RX_OFF(0, 0x48)
  100. #define QSERDES_RX0_RX_TERM_BW RX_OFF(0, 0x80)
  101. #define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL1 RX_OFF(0, 0xE8)
  102. #define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2 RX_OFF(0, 0xEC)
  103. #define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3 RX_OFF(0, 0xF0)
  104. #define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4 RX_OFF(0, 0xF4)
  105. #define QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1 RX_OFF(0, 0x110)
  106. #define QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2 RX_OFF(0, 0x114)
  107. #define QSERDES_RX0_RX_IDAC_MEASURE_TIME RX_OFF(0, 0x100)
  108. #define QSERDES_RX0_RX_IDAC_TSETTLE_LOW RX_OFF(0, 0xF8)
  109. #define QSERDES_RX0_RX_IDAC_TSETTLE_HIGH RX_OFF(0, 0xFC)
  110. #define QSERDES_RX0_RX_MODE_00_LOW RX_OFF(0, 0x15C)
  111. #define QSERDES_RX0_RX_MODE_00_HIGH RX_OFF(0, 0x160)
  112. #define QSERDES_RX0_RX_MODE_00_HIGH2 RX_OFF(0, 0x164)
  113. #define QSERDES_RX0_RX_MODE_00_HIGH3 RX_OFF(0, 0x168)
  114. #define QSERDES_RX0_RX_MODE_00_HIGH4 RX_OFF(0, 0x16C)
  115. #define QSERDES_RX0_RX_MODE_01_LOW RX_OFF(0, 0x170)
  116. #define QSERDES_RX0_RX_MODE_01_HIGH RX_OFF(0, 0x174)
  117. #define QSERDES_RX0_RX_MODE_01_HIGH2 RX_OFF(0, 0x178)
  118. #define QSERDES_RX0_RX_MODE_01_HIGH3 RX_OFF(0, 0x17C)
  119. #define QSERDES_RX0_RX_MODE_01_HIGH4 RX_OFF(0, 0x180)
  120. #define QSERDES_RX0_RX_MODE_10_LOW RX_OFF(0, 0x184)
  121. #define QSERDES_RX0_RX_MODE_10_HIGH RX_OFF(0, 0x188)
  122. #define QSERDES_RX0_RX_MODE_10_HIGH2 RX_OFF(0, 0x18C)
  123. #define QSERDES_RX0_RX_MODE_10_HIGH3 RX_OFF(0, 0x190)
  124. #define QSERDES_RX0_RX_MODE_10_HIGH4 RX_OFF(0, 0x194)
  125. #define QSERDES_RX0_DCC_CTRL1 RX_OFF(0, 0x1A8)
  126. #define QSERDES_RX0_GM_CAL RX_OFF(0, 0xDC)
  127. #define QSERDES_RX0_AC_JTAG_ENABLE RX_OFF(0, 0x68)
  128. #define QSERDES_RX0_UCDR_FO_GAIN RX_OFF(0, 0x08)
  129. #define QSERDES_RX0_UCDR_SO_GAIN RX_OFF(0, 0x14)
  130. #define QSERDES_RX0_RX_INTERFACE_MODE RX_OFF(0, 0x134)
  131. #define QSERDES_RX1_SIGDET_LVL RX_OFF(1, 0x120)
  132. #define QSERDES_RX1_SIGDET_CNTRL RX_OFF(1, 0x11C)
  133. #define QSERDES_RX1_SIGDET_DEGLITCH_CNTRL RX_OFF(1, 0x124)
  134. #define QSERDES_RX1_RX_BAND RX_OFF(1, 0x128)
  135. #define QSERDES_RX1_UCDR_FASTLOCK_FO_GAIN RX_OFF(1, 0x30)
  136. #define QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE RX_OFF(1, 0x34)
  137. #define QSERDES_RX1_UCDR_PI_CONTROLS RX_OFF(1, 0x44)
  138. #define QSERDES_RX1_UCDR_FASTLOCK_COUNT_LOW RX_OFF(1, 0x3C)
  139. #define QSERDES_RX1_UCDR_PI_CTRL2 RX_OFF(1, 0x48)
  140. #define QSERDES_RX1_RX_TERM_BW RX_OFF(1, 0x80)
  141. #define QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL1 RX_OFF(1, 0xE8)
  142. #define QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2 RX_OFF(1, 0xEC)
  143. #define QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3 RX_OFF(1, 0xF0)
  144. #define QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4 RX_OFF(1, 0xF4)
  145. #define QSERDES_RX1_RX_EQ_OFFSET_ADAPTOR_CNTRL1 RX_OFF(1, 0x110)
  146. #define QSERDES_RX1_RX_OFFSET_ADAPTOR_CNTRL2 RX_OFF(1, 0x114)
  147. #define QSERDES_RX1_RX_IDAC_MEASURE_TIME RX_OFF(1, 0x100)
  148. #define QSERDES_RX1_RX_IDAC_TSETTLE_LOW RX_OFF(1, 0xF8)
  149. #define QSERDES_RX1_RX_IDAC_TSETTLE_HIGH RX_OFF(1, 0xFC)
  150. #define QSERDES_RX1_RX_MODE_00_LOW RX_OFF(1, 0x15C)
  151. #define QSERDES_RX1_RX_MODE_00_HIGH RX_OFF(1, 0x160)
  152. #define QSERDES_RX1_RX_MODE_00_HIGH2 RX_OFF(1, 0x164)
  153. #define QSERDES_RX1_RX_MODE_00_HIGH3 RX_OFF(1, 0x168)
  154. #define QSERDES_RX1_RX_MODE_00_HIGH4 RX_OFF(1, 0x16C)
  155. #define QSERDES_RX1_RX_MODE_01_LOW RX_OFF(1, 0x170)
  156. #define QSERDES_RX1_RX_MODE_01_HIGH RX_OFF(1, 0x174)
  157. #define QSERDES_RX1_RX_MODE_01_HIGH2 RX_OFF(1, 0x178)
  158. #define QSERDES_RX1_RX_MODE_01_HIGH3 RX_OFF(1, 0x17C)
  159. #define QSERDES_RX1_RX_MODE_01_HIGH4 RX_OFF(1, 0x180)
  160. #define QSERDES_RX1_RX_MODE_10_LOW RX_OFF(1, 0x184)
  161. #define QSERDES_RX1_RX_MODE_10_HIGH RX_OFF(1, 0x188)
  162. #define QSERDES_RX1_RX_MODE_10_HIGH2 RX_OFF(1, 0x18C)
  163. #define QSERDES_RX1_RX_MODE_10_HIGH3 RX_OFF(1, 0x190)
  164. #define QSERDES_RX1_RX_MODE_10_HIGH4 RX_OFF(1, 0x194)
  165. #define QSERDES_RX1_DCC_CTRL1 RX_OFF(1, 0x1A8)
  166. #define QSERDES_RX1_GM_CAL RX_OFF(1, 0xDC)
  167. #define QSERDES_RX1_AC_JTAG_ENABLE RX_OFF(1, 0x68)
  168. #define QSERDES_RX1_UCDR_FO_GAIN RX_OFF(1, 0x08)
  169. #define QSERDES_RX1_UCDR_SO_GAIN RX_OFF(1, 0x14)
  170. #define QSERDES_RX1_RX_INTERFACE_MODE RX_OFF(1, 0x134)
  171. #define UFS_PHY_RX_LINECFG_DISABLE_BIT BIT(1)
  172. #define QSERDES_RX_INTERFACE_MODE_CLOCK_EDGE_BIT BIT(5)
  173. /*
  174. * This structure represents the v4 specific phy.
  175. * common_cfg MUST remain the first field in this structure
  176. * in case extra fields are added. This way, when calling
  177. * get_ufs_qcom_phy() of generic phy, we can extract the
  178. * common phy structure (struct ufs_qcom_phy) out of it
  179. * regardless of the relevant specific phy.
  180. */
  181. struct ufs_qcom_phy_qmp_v4 {
  182. struct ufs_qcom_phy common_cfg;
  183. };
  184. static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = {
  185. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),
  186. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0xD9),
  187. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_SEL, 0x11),
  188. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_HS_SWITCH_SEL, 0x00),
  189. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_EN, 0x42),
  190. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x02),
  191. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IVCO, 0x0F),
  192. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
  193. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
  194. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE0, 0x82),
  195. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE0, 0x14),
  196. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE0, 0x18),
  197. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE0, 0x18),
  198. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE0, 0xFF),
  199. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE0, 0x19),
  200. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xAC),
  201. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1E),
  202. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE1, 0x98),
  203. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE1, 0x14),
  204. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE1, 0x18),
  205. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE1, 0x18),
  206. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE1, 0x65),
  207. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE1, 0x1E),
  208. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xDD),
  209. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
  210. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
  211. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
  212. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
  213. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
  214. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_LANE_MODE_1, 0xE5),
  215. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x09),
  216. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_RES_CODE_LANE_OFFSET_RX, 0x09),
  217. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_TRAN_DRVR_EMP_EN, 0x0C),
  218. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_SIGDET_LVL, 0x24),
  219. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_SIGDET_CNTRL, 0x0F),
  220. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x1E),
  221. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_BAND, 0x18),
  222. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN, 0x0A),
  223. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x5A),
  224. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_PI_CONTROLS, 0xF1),
  225. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FASTLOCK_COUNT_LOW, 0x80),
  226. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_PI_CTRL2, 0x81),
  227. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FO_GAIN, 0x0E),
  228. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_GAIN, 0x04),
  229. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_TERM_BW, 0x6F),
  230. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL1, 0x04),
  231. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x00),
  232. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x4A),
  233. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x0A),
  234. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
  235. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
  236. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_IDAC_MEASURE_TIME, 0x20),
  237. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0x80),
  238. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x01),
  239. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_LOW, 0xBF),
  240. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH, 0xBF),
  241. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH2, 0x7F),
  242. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH3, 0x7F),
  243. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH4, 0x2D),
  244. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_01_LOW, 0x6D),
  245. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_01_HIGH, 0x6D),
  246. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_01_HIGH2, 0xED),
  247. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_01_HIGH3, 0x3B),
  248. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_01_HIGH4, 0x3C),
  249. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_10_LOW, 0xE0),
  250. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_10_HIGH, 0xC8),
  251. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_10_HIGH2, 0xC8),
  252. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_10_HIGH3, 0x3B),
  253. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_10_HIGH4, 0xB7),
  254. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_DCC_CTRL1, 0x0C),
  255. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_GM_CAL, 0x0F),
  256. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x6D),
  257. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x10),
  258. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x02),
  259. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_MID_TERM_CTRL1, 0x43),
  260. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_DEBUG_BUS_CLKSEL, 0x1F),
  261. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_HIBERN8_TIME, 0xFF),
  262. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_BIST_FIXED_PAT_CTRL, 0x0A),
  263. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL1, 0x0E),
  264. };
  265. static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_no_g4[] = {
  266. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),
  267. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0xD9),
  268. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_SEL, 0x11),
  269. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_HS_SWITCH_SEL, 0x00),
  270. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_EN, 0x42),
  271. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x02),
  272. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IVCO, 0x0F),
  273. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
  274. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
  275. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE0, 0x82),
  276. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE0, 0x14),
  277. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE0, 0x18),
  278. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE0, 0x18),
  279. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE0, 0xFF),
  280. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE0, 0x19),
  281. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xAC),
  282. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1E),
  283. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE1, 0x98),
  284. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE1, 0x14),
  285. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE1, 0x18),
  286. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE1, 0x18),
  287. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE1, 0x65),
  288. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE1, 0x1E),
  289. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xDD),
  290. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
  291. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
  292. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
  293. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
  294. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
  295. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_LANE_MODE_1, 0xF5),
  296. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_LANE_MODE_3, 0x3F),
  297. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x09),
  298. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_RES_CODE_LANE_OFFSET_RX, 0x09),
  299. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_TRAN_DRVR_EMP_EN, 0x0C),
  300. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_SIGDET_LVL, 0x24),
  301. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_SIGDET_CNTRL, 0x0F),
  302. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x1E),
  303. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_BAND, 0x18),
  304. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN, 0x0A),
  305. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x5A),
  306. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_PI_CONTROLS, 0xF1),
  307. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FASTLOCK_COUNT_LOW, 0x80),
  308. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_PI_CTRL2, 0x80),
  309. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FO_GAIN, 0x0E),
  310. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_GAIN, 0x04),
  311. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_TERM_BW, 0x1B),
  312. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL1, 0x04),
  313. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x06),
  314. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
  315. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1A),
  316. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
  317. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
  318. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_IDAC_MEASURE_TIME, 0x10),
  319. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xC0),
  320. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
  321. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_LOW, 0x6D),
  322. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH, 0x6D),
  323. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH2, 0xED),
  324. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH3, 0x3B),
  325. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00_HIGH4, 0x3C),
  326. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_01_LOW, 0xE0),
  327. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_01_HIGH, 0xC8),
  328. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_01_HIGH2, 0xC8),
  329. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_01_HIGH3, 0x3B),
  330. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_01_HIGH4, 0xB7),
  331. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_10_LOW, 0xE0),
  332. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_10_HIGH, 0xC8),
  333. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_10_HIGH2, 0xC8),
  334. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_10_HIGH3, 0x3B),
  335. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_10_HIGH4, 0xB7),
  336. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_DCC_CTRL1, 0x0C),
  337. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x6D),
  338. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x0A),
  339. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x02),
  340. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_MID_TERM_CTRL1, 0x43),
  341. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_DEBUG_BUS_CLKSEL, 0x1F),
  342. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_HIBERN8_TIME, 0xFF),
  343. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_PLL_CNTL, 0x03),
  344. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
  345. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_20US_CORECLK_STEPS_LSB, 0xD8),
  346. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_PWM_GEAR_BAND, 0xAA),
  347. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_HS_GEAR_BAND, 0x06),
  348. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_HSGEAR_CAPABILITY, 0x03),
  349. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HSGEAR_CAPABILITY, 0x03),
  350. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL1, 0x0E),
  351. };
  352. static struct ufs_qcom_phy_calibration phy_cal_table_2nd_lane[] = {
  353. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
  354. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
  355. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
  356. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
  357. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_LANE_MODE_1, 0xE5),
  358. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_RES_CODE_LANE_OFFSET_TX, 0x09),
  359. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_RES_CODE_LANE_OFFSET_RX, 0x09),
  360. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_TRAN_DRVR_EMP_EN, 0x0C),
  361. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_SIGDET_LVL, 0x24),
  362. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_SIGDET_CNTRL, 0x0F),
  363. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_SIGDET_DEGLITCH_CNTRL, 0x1E),
  364. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_BAND, 0x18),
  365. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FASTLOCK_FO_GAIN, 0x0A),
  366. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE, 0x5A),
  367. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_PI_CONTROLS, 0xF1),
  368. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FASTLOCK_COUNT_LOW, 0x80),
  369. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_PI_CTRL2, 0x81),
  370. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FO_GAIN, 0x0E),
  371. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SO_GAIN, 0x04),
  372. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_TERM_BW, 0x6F),
  373. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL1, 0x04),
  374. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2, 0x00),
  375. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3, 0x4A),
  376. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4, 0x0A),
  377. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
  378. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
  379. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_IDAC_MEASURE_TIME, 0x20),
  380. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_IDAC_TSETTLE_LOW, 0x80),
  381. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_IDAC_TSETTLE_HIGH, 0x01),
  382. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_LOW, 0xBF),
  383. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH, 0xBF),
  384. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH2, 0x7F),
  385. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH3, 0x7F),
  386. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH4, 0x2D),
  387. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_01_LOW, 0x6D),
  388. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_01_HIGH, 0x6D),
  389. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_01_HIGH2, 0xED),
  390. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_01_HIGH3, 0x3B),
  391. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_01_HIGH4, 0x3C),
  392. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_LOW, 0xE0),
  393. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_HIGH, 0xC8),
  394. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_HIGH2, 0xC8),
  395. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_HIGH3, 0x3B),
  396. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_HIGH4, 0xB7),
  397. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_DCC_CTRL1, 0x0C),
  398. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_GM_CAL, 0x0F),
  399. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_MULTI_LANE_CTRL1, 0x02),
  400. };
  401. static struct ufs_qcom_phy_calibration phy_cal_table_2nd_lane_no_g4[] = {
  402. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
  403. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
  404. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
  405. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
  406. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_LANE_MODE_1, 0xF5),
  407. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_LANE_MODE_3, 0x3F),
  408. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_RES_CODE_LANE_OFFSET_TX, 0x09),
  409. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_RES_CODE_LANE_OFFSET_RX, 0x09),
  410. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_TRAN_DRVR_EMP_EN, 0x0C),
  411. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_SIGDET_LVL, 0x24),
  412. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_SIGDET_CNTRL, 0x0F),
  413. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_SIGDET_DEGLITCH_CNTRL, 0x1E),
  414. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_BAND, 0x18),
  415. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FASTLOCK_FO_GAIN, 0x0A),
  416. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE, 0x5A),
  417. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_PI_CONTROLS, 0xF1),
  418. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FASTLOCK_COUNT_LOW, 0x80),
  419. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_PI_CTRL2, 0x80),
  420. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FO_GAIN, 0x0E),
  421. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SO_GAIN, 0x04),
  422. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_TERM_BW, 0x1B),
  423. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL1, 0x04),
  424. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2, 0x06),
  425. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3, 0x04),
  426. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4, 0x1A),
  427. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
  428. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
  429. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_IDAC_MEASURE_TIME, 0x10),
  430. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_IDAC_TSETTLE_LOW, 0xC0),
  431. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_IDAC_TSETTLE_HIGH, 0x00),
  432. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_LOW, 0x6D),
  433. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH, 0x6D),
  434. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH2, 0xED),
  435. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH3, 0x3B),
  436. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00_HIGH4, 0x3C),
  437. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_01_LOW, 0xE0),
  438. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_01_HIGH, 0xC8),
  439. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_01_HIGH2, 0xC8),
  440. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_01_HIGH3, 0x3B),
  441. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_01_HIGH4, 0xB7),
  442. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_LOW, 0xE0),
  443. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_HIGH, 0xC8),
  444. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_HIGH2, 0xC8),
  445. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_HIGH3, 0x3B),
  446. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_HIGH4, 0xB7),
  447. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_DCC_CTRL1, 0x0C),
  448. UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_MULTI_LANE_CTRL1, 0x02),
  449. };
  450. static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = {
  451. UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x06),
  452. };
  453. #endif