phy-qcom-ufs-qmp-v3.c 6.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. */
  5. #include "phy-qcom-ufs-qmp-v3.h"
  6. #define UFS_PHY_NAME "ufs_phy_qmp_v3"
  7. static inline void ufs_qcom_phy_qmp_v3_start_serdes(struct ufs_qcom_phy *phy);
  8. static int ufs_qcom_phy_qmp_v3_is_pcs_ready(struct ufs_qcom_phy *phy_common);
  9. static int ufs_qcom_phy_qmp_v3_phy_calibrate(struct phy *generic_phy)
  10. {
  11. struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
  12. struct device *dev = ufs_qcom_phy->dev;
  13. bool is_rate_B;
  14. int err;
  15. err = reset_control_assert(ufs_qcom_phy->ufs_reset);
  16. if (err) {
  17. dev_err(dev, "Failed to assert UFS PHY reset %d\n", err);
  18. goto out;
  19. }
  20. is_rate_B = (ufs_qcom_phy->mode == PHY_MODE_UFS_HS_B) ? true : false;
  21. /*
  22. * Writing PHY calibration in this order:
  23. * 1. Write Rate-A calibration first (1-lane mode).
  24. * 2. Write 2nd lane configuration if needed.
  25. * 3. Write Rate-B calibration overrides
  26. */
  27. ufs_qcom_phy_write_tbl(ufs_qcom_phy, phy_cal_table_rate_A,
  28. ARRAY_SIZE(phy_cal_table_rate_A));
  29. if (ufs_qcom_phy->lanes_per_direction == 2)
  30. ufs_qcom_phy_write_tbl(ufs_qcom_phy,
  31. phy_cal_table_2nd_lane,
  32. ARRAY_SIZE(phy_cal_table_2nd_lane));
  33. if (is_rate_B)
  34. ufs_qcom_phy_write_tbl(ufs_qcom_phy, phy_cal_table_rate_B,
  35. ARRAY_SIZE(phy_cal_table_rate_B));
  36. /* flush buffered writes */
  37. mb();
  38. err = reset_control_deassert(ufs_qcom_phy->ufs_reset);
  39. if (err) {
  40. dev_err(dev, "Failed to deassert UFS PHY reset %d\n", err);
  41. goto out;
  42. }
  43. ufs_qcom_phy_qmp_v3_start_serdes(ufs_qcom_phy);
  44. err = ufs_qcom_phy_qmp_v3_is_pcs_ready(ufs_qcom_phy);
  45. out:
  46. return err;
  47. }
  48. static int ufs_qcom_phy_qmp_v3_init(struct phy *generic_phy)
  49. {
  50. struct ufs_qcom_phy_qmp_v3 *phy = phy_get_drvdata(generic_phy);
  51. struct ufs_qcom_phy *phy_common = &phy->common_cfg;
  52. int err;
  53. err = ufs_qcom_phy_init_clks(phy_common);
  54. if (err) {
  55. dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_clks() failed %d\n",
  56. __func__, err);
  57. goto out;
  58. }
  59. err = ufs_qcom_phy_init_vregulators(phy_common);
  60. if (err) {
  61. dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_vregulators() failed %d\n",
  62. __func__, err);
  63. goto out;
  64. }
  65. /* Optional */
  66. ufs_qcom_phy_get_reset(phy_common);
  67. out:
  68. return err;
  69. }
  70. static int ufs_qcom_phy_qmp_v3_exit(struct phy *generic_phy)
  71. {
  72. return 0;
  73. }
  74. static
  75. int ufs_qcom_phy_qmp_v3_set_mode(struct phy *generic_phy,
  76. enum phy_mode mode, int submode)
  77. {
  78. struct ufs_qcom_phy *phy_common = get_ufs_qcom_phy(generic_phy);
  79. phy_common->mode = PHY_MODE_INVALID;
  80. if (mode > 0)
  81. phy_common->mode = mode;
  82. phy_common->submode = submode;
  83. return 0;
  84. }
  85. static
  86. void ufs_qcom_phy_qmp_v3_power_control(struct ufs_qcom_phy *phy,
  87. bool power_ctrl)
  88. {
  89. if (!power_ctrl) {
  90. /* apply analog power collapse */
  91. writel_relaxed(0x0, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
  92. /*
  93. * Make sure that PHY knows its analog rail is going to be
  94. * powered OFF.
  95. */
  96. mb();
  97. } else {
  98. /* bring PHY out of analog power collapse */
  99. writel_relaxed(0x1, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
  100. /*
  101. * Before any transactions involving PHY, ensure PHY knows
  102. * that it's analog rail is powered ON.
  103. */
  104. mb();
  105. }
  106. }
  107. static inline
  108. void ufs_qcom_phy_qmp_v3_set_tx_lane_enable(struct ufs_qcom_phy *phy, u32 val)
  109. {
  110. /*
  111. * v3 PHY does not have TX_LANE_ENABLE register.
  112. * Implement this function so as not to propagate error to caller.
  113. */
  114. }
  115. static
  116. void ufs_qcom_phy_qmp_v3_ctrl_rx_linecfg(struct ufs_qcom_phy *phy, bool ctrl)
  117. {
  118. u32 temp;
  119. temp = readl_relaxed(phy->mmio + UFS_PHY_LINECFG_DISABLE);
  120. if (ctrl) /* enable RX LineCfg */
  121. temp &= ~UFS_PHY_RX_LINECFG_DISABLE_BIT;
  122. else /* disable RX LineCfg */
  123. temp |= UFS_PHY_RX_LINECFG_DISABLE_BIT;
  124. writel_relaxed(temp, phy->mmio + UFS_PHY_LINECFG_DISABLE);
  125. /* make sure that RX LineCfg config applied before we return */
  126. mb();
  127. }
  128. static inline void ufs_qcom_phy_qmp_v3_start_serdes(struct ufs_qcom_phy *phy)
  129. {
  130. u32 tmp;
  131. tmp = readl_relaxed(phy->mmio + UFS_PHY_PHY_START);
  132. tmp &= ~MASK_SERDES_START;
  133. tmp |= (1 << OFFSET_SERDES_START);
  134. writel_relaxed(tmp, phy->mmio + UFS_PHY_PHY_START);
  135. /* Ensure register value is committed */
  136. mb();
  137. }
  138. static int ufs_qcom_phy_qmp_v3_is_pcs_ready(struct ufs_qcom_phy *phy_common)
  139. {
  140. int err = 0;
  141. u32 val;
  142. err = readl_poll_timeout(phy_common->mmio + UFS_PHY_PCS_READY_STATUS,
  143. val, (val & MASK_PCS_READY), 10, 1000000);
  144. if (err) {
  145. dev_err(phy_common->dev, "%s: poll for pcs failed err = %d\n",
  146. __func__, err);
  147. goto out;
  148. }
  149. out:
  150. return err;
  151. }
  152. static void ufs_qcom_phy_qmp_v3_dbg_register_dump(struct ufs_qcom_phy *phy)
  153. {
  154. ufs_qcom_phy_dump_regs(phy, COM_BASE, COM_SIZE,
  155. "PHY QSERDES COM Registers ");
  156. ufs_qcom_phy_dump_regs(phy, PHY_BASE, PHY_SIZE,
  157. "PHY Registers ");
  158. ufs_qcom_phy_dump_regs(phy, RX_BASE(0), RX_SIZE,
  159. "PHY RX0 Registers ");
  160. ufs_qcom_phy_dump_regs(phy, TX_BASE(0), TX_SIZE,
  161. "PHY TX0 Registers ");
  162. ufs_qcom_phy_dump_regs(phy, RX_BASE(1), RX_SIZE,
  163. "PHY RX1 Registers ");
  164. ufs_qcom_phy_dump_regs(phy, TX_BASE(1), TX_SIZE,
  165. "PHY TX1 Registers ");
  166. }
  167. static const struct phy_ops ufs_qcom_phy_qmp_v3_phy_ops = {
  168. .init = ufs_qcom_phy_qmp_v3_init,
  169. .exit = ufs_qcom_phy_qmp_v3_exit,
  170. .power_on = ufs_qcom_phy_power_on,
  171. .power_off = ufs_qcom_phy_power_off,
  172. .set_mode = ufs_qcom_phy_qmp_v3_set_mode,
  173. .calibrate = ufs_qcom_phy_qmp_v3_phy_calibrate,
  174. .owner = THIS_MODULE,
  175. };
  176. static struct ufs_qcom_phy_specific_ops phy_v3_ops = {
  177. .start_serdes = ufs_qcom_phy_qmp_v3_start_serdes,
  178. .is_physical_coding_sublayer_ready = ufs_qcom_phy_qmp_v3_is_pcs_ready,
  179. .set_tx_lane_enable = ufs_qcom_phy_qmp_v3_set_tx_lane_enable,
  180. .ctrl_rx_linecfg = ufs_qcom_phy_qmp_v3_ctrl_rx_linecfg,
  181. .power_control = ufs_qcom_phy_qmp_v3_power_control,
  182. .dbg_register_dump = ufs_qcom_phy_qmp_v3_dbg_register_dump,
  183. };
  184. static int ufs_qcom_phy_qmp_v3_probe(struct platform_device *pdev)
  185. {
  186. struct device *dev = &pdev->dev;
  187. struct phy *generic_phy;
  188. struct ufs_qcom_phy_qmp_v3 *phy;
  189. int err = 0;
  190. phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
  191. if (!phy) {
  192. err = -ENOMEM;
  193. goto out;
  194. }
  195. generic_phy = ufs_qcom_phy_generic_probe(pdev, &phy->common_cfg,
  196. &ufs_qcom_phy_qmp_v3_phy_ops, &phy_v3_ops);
  197. if (!generic_phy) {
  198. dev_err(dev, "%s: ufs_qcom_phy_generic_probe() failed\n",
  199. __func__);
  200. err = -EIO;
  201. goto out;
  202. }
  203. phy_set_drvdata(generic_phy, phy);
  204. strscpy(phy->common_cfg.name, UFS_PHY_NAME,
  205. sizeof(phy->common_cfg.name));
  206. out:
  207. return err;
  208. }
  209. static const struct of_device_id ufs_qcom_phy_qmp_v3_of_match[] = {
  210. {.compatible = "qcom,ufs-phy-qmp-v3"},
  211. {},
  212. };
  213. MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qmp_v3_of_match);
  214. static struct platform_driver ufs_qcom_phy_qmp_v3_driver = {
  215. .probe = ufs_qcom_phy_qmp_v3_probe,
  216. .driver = {
  217. .of_match_table = ufs_qcom_phy_qmp_v3_of_match,
  218. .name = "ufs_qcom_phy_qmp_v3",
  219. },
  220. };
  221. module_platform_driver(ufs_qcom_phy_qmp_v3_driver);
  222. MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QMP v3");
  223. MODULE_LICENSE("GPL");