phy-qcom-qmp-pcs-ufs-v4.h 1.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (c) 2017, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef QCOM_PHY_QMP_PCS_UFS_V4_H_
  6. #define QCOM_PHY_QMP_PCS_UFS_V4_H_
  7. /* Only for QMP V4 PHY - UFS PCS registers */
  8. #define QPHY_V4_PCS_UFS_PHY_START 0x000
  9. #define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL 0x004
  10. #define QPHY_V4_PCS_UFS_SW_RESET 0x008
  11. #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
  12. #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
  13. #define QPHY_V4_PCS_UFS_PLL_CNTL 0x02c
  14. #define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
  15. #define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
  16. #define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
  17. #define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
  18. #define QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4
  19. #define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL 0x124
  20. #define QPHY_V4_PCS_UFS_LINECFG_DISABLE 0x148
  21. #define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150
  22. #define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2 0x158
  23. #define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND 0x160
  24. #define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND 0x168
  25. #define QPHY_V4_PCS_UFS_READY_STATUS 0x180
  26. #define QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8
  27. #define QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1 0x1e0
  28. #endif