riscv_pmu.c 8.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * RISC-V performance counter support.
  4. *
  5. * Copyright (C) 2021 Western Digital Corporation or its affiliates.
  6. *
  7. * This implementation is based on old RISC-V perf and ARM perf event code
  8. * which are in turn based on sparc64 and x86 code.
  9. */
  10. #include <linux/cpumask.h>
  11. #include <linux/irq.h>
  12. #include <linux/irqdesc.h>
  13. #include <linux/perf/riscv_pmu.h>
  14. #include <linux/printk.h>
  15. #include <linux/smp.h>
  16. #include <asm/sbi.h>
  17. static unsigned long csr_read_num(int csr_num)
  18. {
  19. #define switchcase_csr_read(__csr_num, __val) {\
  20. case __csr_num: \
  21. __val = csr_read(__csr_num); \
  22. break; }
  23. #define switchcase_csr_read_2(__csr_num, __val) {\
  24. switchcase_csr_read(__csr_num + 0, __val) \
  25. switchcase_csr_read(__csr_num + 1, __val)}
  26. #define switchcase_csr_read_4(__csr_num, __val) {\
  27. switchcase_csr_read_2(__csr_num + 0, __val) \
  28. switchcase_csr_read_2(__csr_num + 2, __val)}
  29. #define switchcase_csr_read_8(__csr_num, __val) {\
  30. switchcase_csr_read_4(__csr_num + 0, __val) \
  31. switchcase_csr_read_4(__csr_num + 4, __val)}
  32. #define switchcase_csr_read_16(__csr_num, __val) {\
  33. switchcase_csr_read_8(__csr_num + 0, __val) \
  34. switchcase_csr_read_8(__csr_num + 8, __val)}
  35. #define switchcase_csr_read_32(__csr_num, __val) {\
  36. switchcase_csr_read_16(__csr_num + 0, __val) \
  37. switchcase_csr_read_16(__csr_num + 16, __val)}
  38. unsigned long ret = 0;
  39. switch (csr_num) {
  40. switchcase_csr_read_32(CSR_CYCLE, ret)
  41. switchcase_csr_read_32(CSR_CYCLEH, ret)
  42. default :
  43. break;
  44. }
  45. return ret;
  46. #undef switchcase_csr_read_32
  47. #undef switchcase_csr_read_16
  48. #undef switchcase_csr_read_8
  49. #undef switchcase_csr_read_4
  50. #undef switchcase_csr_read_2
  51. #undef switchcase_csr_read
  52. }
  53. /*
  54. * Read the CSR of a corresponding counter.
  55. */
  56. unsigned long riscv_pmu_ctr_read_csr(unsigned long csr)
  57. {
  58. if (csr < CSR_CYCLE || csr > CSR_HPMCOUNTER31H ||
  59. (csr > CSR_HPMCOUNTER31 && csr < CSR_CYCLEH)) {
  60. pr_err("Invalid performance counter csr %lx\n", csr);
  61. return -EINVAL;
  62. }
  63. return csr_read_num(csr);
  64. }
  65. u64 riscv_pmu_ctr_get_width_mask(struct perf_event *event)
  66. {
  67. int cwidth;
  68. struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);
  69. struct hw_perf_event *hwc = &event->hw;
  70. if (!rvpmu->ctr_get_width)
  71. /**
  72. * If the pmu driver doesn't support counter width, set it to default
  73. * maximum allowed by the specification.
  74. */
  75. cwidth = 63;
  76. else {
  77. if (hwc->idx == -1)
  78. /* Handle init case where idx is not initialized yet */
  79. cwidth = rvpmu->ctr_get_width(0);
  80. else
  81. cwidth = rvpmu->ctr_get_width(hwc->idx);
  82. }
  83. return GENMASK_ULL(cwidth, 0);
  84. }
  85. u64 riscv_pmu_event_update(struct perf_event *event)
  86. {
  87. struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);
  88. struct hw_perf_event *hwc = &event->hw;
  89. u64 prev_raw_count, new_raw_count;
  90. unsigned long cmask;
  91. u64 oldval, delta;
  92. if (!rvpmu->ctr_read)
  93. return 0;
  94. cmask = riscv_pmu_ctr_get_width_mask(event);
  95. do {
  96. prev_raw_count = local64_read(&hwc->prev_count);
  97. new_raw_count = rvpmu->ctr_read(event);
  98. oldval = local64_cmpxchg(&hwc->prev_count, prev_raw_count,
  99. new_raw_count);
  100. } while (oldval != prev_raw_count);
  101. delta = (new_raw_count - prev_raw_count) & cmask;
  102. local64_add(delta, &event->count);
  103. local64_sub(delta, &hwc->period_left);
  104. return delta;
  105. }
  106. void riscv_pmu_stop(struct perf_event *event, int flags)
  107. {
  108. struct hw_perf_event *hwc = &event->hw;
  109. struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);
  110. WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
  111. if (!(hwc->state & PERF_HES_STOPPED)) {
  112. if (rvpmu->ctr_stop) {
  113. rvpmu->ctr_stop(event, 0);
  114. hwc->state |= PERF_HES_STOPPED;
  115. }
  116. riscv_pmu_event_update(event);
  117. hwc->state |= PERF_HES_UPTODATE;
  118. }
  119. }
  120. int riscv_pmu_event_set_period(struct perf_event *event)
  121. {
  122. struct hw_perf_event *hwc = &event->hw;
  123. s64 left = local64_read(&hwc->period_left);
  124. s64 period = hwc->sample_period;
  125. int overflow = 0;
  126. uint64_t max_period = riscv_pmu_ctr_get_width_mask(event);
  127. if (unlikely(left <= -period)) {
  128. left = period;
  129. local64_set(&hwc->period_left, left);
  130. hwc->last_period = period;
  131. overflow = 1;
  132. }
  133. if (unlikely(left <= 0)) {
  134. left += period;
  135. local64_set(&hwc->period_left, left);
  136. hwc->last_period = period;
  137. overflow = 1;
  138. }
  139. /*
  140. * Limit the maximum period to prevent the counter value
  141. * from overtaking the one we are about to program. In
  142. * effect we are reducing max_period to account for
  143. * interrupt latency (and we are being very conservative).
  144. */
  145. if (left > (max_period >> 1))
  146. left = (max_period >> 1);
  147. local64_set(&hwc->prev_count, (u64)-left);
  148. return overflow;
  149. }
  150. void riscv_pmu_start(struct perf_event *event, int flags)
  151. {
  152. struct hw_perf_event *hwc = &event->hw;
  153. struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);
  154. uint64_t max_period = riscv_pmu_ctr_get_width_mask(event);
  155. u64 init_val;
  156. if (flags & PERF_EF_RELOAD)
  157. WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
  158. hwc->state = 0;
  159. riscv_pmu_event_set_period(event);
  160. init_val = local64_read(&hwc->prev_count) & max_period;
  161. rvpmu->ctr_start(event, init_val);
  162. perf_event_update_userpage(event);
  163. }
  164. static int riscv_pmu_add(struct perf_event *event, int flags)
  165. {
  166. struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);
  167. struct cpu_hw_events *cpuc = this_cpu_ptr(rvpmu->hw_events);
  168. struct hw_perf_event *hwc = &event->hw;
  169. int idx;
  170. idx = rvpmu->ctr_get_idx(event);
  171. if (idx < 0)
  172. return idx;
  173. hwc->idx = idx;
  174. cpuc->events[idx] = event;
  175. cpuc->n_events++;
  176. hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
  177. if (flags & PERF_EF_START)
  178. riscv_pmu_start(event, PERF_EF_RELOAD);
  179. /* Propagate our changes to the userspace mapping. */
  180. perf_event_update_userpage(event);
  181. return 0;
  182. }
  183. static void riscv_pmu_del(struct perf_event *event, int flags)
  184. {
  185. struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);
  186. struct cpu_hw_events *cpuc = this_cpu_ptr(rvpmu->hw_events);
  187. struct hw_perf_event *hwc = &event->hw;
  188. riscv_pmu_stop(event, PERF_EF_UPDATE);
  189. cpuc->events[hwc->idx] = NULL;
  190. /* The firmware need to reset the counter mapping */
  191. if (rvpmu->ctr_stop)
  192. rvpmu->ctr_stop(event, RISCV_PMU_STOP_FLAG_RESET);
  193. cpuc->n_events--;
  194. if (rvpmu->ctr_clear_idx)
  195. rvpmu->ctr_clear_idx(event);
  196. perf_event_update_userpage(event);
  197. hwc->idx = -1;
  198. }
  199. static void riscv_pmu_read(struct perf_event *event)
  200. {
  201. riscv_pmu_event_update(event);
  202. }
  203. static int riscv_pmu_event_init(struct perf_event *event)
  204. {
  205. struct hw_perf_event *hwc = &event->hw;
  206. struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);
  207. int mapped_event;
  208. u64 event_config = 0;
  209. uint64_t cmask;
  210. hwc->flags = 0;
  211. mapped_event = rvpmu->event_map(event, &event_config);
  212. if (mapped_event < 0) {
  213. pr_debug("event %x:%llx not supported\n", event->attr.type,
  214. event->attr.config);
  215. return mapped_event;
  216. }
  217. /*
  218. * idx is set to -1 because the index of a general event should not be
  219. * decided until binding to some counter in pmu->add().
  220. * config will contain the information about counter CSR
  221. * the idx will contain the counter index
  222. */
  223. hwc->config = event_config;
  224. hwc->idx = -1;
  225. hwc->event_base = mapped_event;
  226. if (!is_sampling_event(event)) {
  227. /*
  228. * For non-sampling runs, limit the sample_period to half
  229. * of the counter width. That way, the new counter value
  230. * is far less likely to overtake the previous one unless
  231. * you have some serious IRQ latency issues.
  232. */
  233. cmask = riscv_pmu_ctr_get_width_mask(event);
  234. hwc->sample_period = cmask >> 1;
  235. hwc->last_period = hwc->sample_period;
  236. local64_set(&hwc->period_left, hwc->sample_period);
  237. }
  238. return 0;
  239. }
  240. struct riscv_pmu *riscv_pmu_alloc(void)
  241. {
  242. struct riscv_pmu *pmu;
  243. int cpuid, i;
  244. struct cpu_hw_events *cpuc;
  245. pmu = kzalloc(sizeof(*pmu), GFP_KERNEL);
  246. if (!pmu)
  247. goto out;
  248. pmu->hw_events = alloc_percpu_gfp(struct cpu_hw_events, GFP_KERNEL);
  249. if (!pmu->hw_events) {
  250. pr_info("failed to allocate per-cpu PMU data.\n");
  251. goto out_free_pmu;
  252. }
  253. for_each_possible_cpu(cpuid) {
  254. cpuc = per_cpu_ptr(pmu->hw_events, cpuid);
  255. cpuc->n_events = 0;
  256. for (i = 0; i < RISCV_MAX_COUNTERS; i++)
  257. cpuc->events[i] = NULL;
  258. }
  259. pmu->pmu = (struct pmu) {
  260. .event_init = riscv_pmu_event_init,
  261. .add = riscv_pmu_add,
  262. .del = riscv_pmu_del,
  263. .start = riscv_pmu_start,
  264. .stop = riscv_pmu_stop,
  265. .read = riscv_pmu_read,
  266. };
  267. return pmu;
  268. out_free_pmu:
  269. kfree(pmu);
  270. out:
  271. return NULL;
  272. }